//
// Copyright (c) 2017 NVIDIA Corporation.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// Neither the name of the NVIDIA Corporation nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//

//
// DO NOT EDIT - generated by simspec!
//

#ifndef ___ARGPIO_H_INC_
#define ___ARGPIO_H_INC_

// Register GPIO_GG_VM_00_0
#define GPIO_GG_VM_00_0                 _MK_ADDR_CONST(0x0)
#define GPIO_GG_VM_00_0_SECURE                  0x0
#define GPIO_GG_VM_00_0_DUAL                    0x0
#define GPIO_GG_VM_00_0_SCR                     GPIO_CTL0_VM_SCR_0
#define GPIO_GG_VM_00_0_WORD_COUNT                      0x1
#define GPIO_GG_VM_00_0_RESET_VAL                       _MK_MASK_CONST(0xffff)
#define GPIO_GG_VM_00_0_RESET_MASK                      _MK_MASK_CONST(0xffff)
#define GPIO_GG_VM_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_GG_VM_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_GG_VM_00_0_READ_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_GG_VM_00_0_WRITE_MASK                      _MK_MASK_CONST(0xffff)
#define GPIO_GG_VM_00_0_VM1_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_GG_VM_00_0_VM1_FIELD                       _MK_FIELD_CONST(0x3, GPIO_GG_VM_00_0_VM1_SHIFT)
#define GPIO_GG_VM_00_0_VM1_RANGE                       1:0
#define GPIO_GG_VM_00_0_VM1_WOFFSET                     0x0
#define GPIO_GG_VM_00_0_VM1_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_GG_VM_00_0_VM1_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_GG_VM_00_0_VM1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_GG_VM_00_0_VM1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_GG_VM_00_0_VM1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_GG_VM_00_0_VM1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_GG_VM_00_0_VM2_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_GG_VM_00_0_VM2_FIELD                       _MK_FIELD_CONST(0x3, GPIO_GG_VM_00_0_VM2_SHIFT)
#define GPIO_GG_VM_00_0_VM2_RANGE                       3:2
#define GPIO_GG_VM_00_0_VM2_WOFFSET                     0x0
#define GPIO_GG_VM_00_0_VM2_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_GG_VM_00_0_VM2_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_GG_VM_00_0_VM2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_GG_VM_00_0_VM2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_GG_VM_00_0_VM2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_GG_VM_00_0_VM2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_GG_VM_00_0_VM3_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_GG_VM_00_0_VM3_FIELD                       _MK_FIELD_CONST(0x3, GPIO_GG_VM_00_0_VM3_SHIFT)
#define GPIO_GG_VM_00_0_VM3_RANGE                       5:4
#define GPIO_GG_VM_00_0_VM3_WOFFSET                     0x0
#define GPIO_GG_VM_00_0_VM3_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_GG_VM_00_0_VM3_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_GG_VM_00_0_VM3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_GG_VM_00_0_VM3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_GG_VM_00_0_VM3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_GG_VM_00_0_VM3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_GG_VM_00_0_VM4_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_GG_VM_00_0_VM4_FIELD                       _MK_FIELD_CONST(0x3, GPIO_GG_VM_00_0_VM4_SHIFT)
#define GPIO_GG_VM_00_0_VM4_RANGE                       7:6
#define GPIO_GG_VM_00_0_VM4_WOFFSET                     0x0
#define GPIO_GG_VM_00_0_VM4_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_GG_VM_00_0_VM4_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_GG_VM_00_0_VM4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_GG_VM_00_0_VM4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_GG_VM_00_0_VM4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_GG_VM_00_0_VM4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_GG_VM_00_0_VM5_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_GG_VM_00_0_VM5_FIELD                       _MK_FIELD_CONST(0x3, GPIO_GG_VM_00_0_VM5_SHIFT)
#define GPIO_GG_VM_00_0_VM5_RANGE                       9:8
#define GPIO_GG_VM_00_0_VM5_WOFFSET                     0x0
#define GPIO_GG_VM_00_0_VM5_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_GG_VM_00_0_VM5_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_GG_VM_00_0_VM5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_GG_VM_00_0_VM5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_GG_VM_00_0_VM5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_GG_VM_00_0_VM5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_GG_VM_00_0_VM6_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_GG_VM_00_0_VM6_FIELD                       _MK_FIELD_CONST(0x3, GPIO_GG_VM_00_0_VM6_SHIFT)
#define GPIO_GG_VM_00_0_VM6_RANGE                       11:10
#define GPIO_GG_VM_00_0_VM6_WOFFSET                     0x0
#define GPIO_GG_VM_00_0_VM6_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_GG_VM_00_0_VM6_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_GG_VM_00_0_VM6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_GG_VM_00_0_VM6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_GG_VM_00_0_VM6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_GG_VM_00_0_VM6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_GG_VM_00_0_VM7_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_GG_VM_00_0_VM7_FIELD                       _MK_FIELD_CONST(0x3, GPIO_GG_VM_00_0_VM7_SHIFT)
#define GPIO_GG_VM_00_0_VM7_RANGE                       13:12
#define GPIO_GG_VM_00_0_VM7_WOFFSET                     0x0
#define GPIO_GG_VM_00_0_VM7_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_GG_VM_00_0_VM7_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_GG_VM_00_0_VM7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_GG_VM_00_0_VM7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_GG_VM_00_0_VM7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_GG_VM_00_0_VM7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_GG_VM_00_0_VM8_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_GG_VM_00_0_VM8_FIELD                       _MK_FIELD_CONST(0x3, GPIO_GG_VM_00_0_VM8_SHIFT)
#define GPIO_GG_VM_00_0_VM8_RANGE                       15:14
#define GPIO_GG_VM_00_0_VM8_WOFFSET                     0x0
#define GPIO_GG_VM_00_0_VM8_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_GG_VM_00_0_VM8_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_GG_VM_00_0_VM8_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_GG_VM_00_0_VM8_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_GG_VM_00_0_VM8_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_GG_VM_00_0_VM8_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_GG_SCR_00_0
#define GPIO_GG_SCR_00_0                        _MK_ADDR_CONST(0x4)
#define GPIO_GG_SCR_00_0_SECURE                         0x0
#define GPIO_GG_SCR_00_0_DUAL                   0x0
#define GPIO_GG_SCR_00_0_SCR                    0
#define GPIO_GG_SCR_00_0_WORD_COUNT                     0x1
#define GPIO_GG_SCR_00_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_RESET_MASK                     _MK_MASK_CONST(0x3fffffff)
#define GPIO_GG_SCR_00_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_READ_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_GG_SCR_00_0_WRITE_MASK                     _MK_MASK_CONST(0x3fffffff)
#define GPIO_GG_SCR_00_0_SEC_LCK_SHIFT                  _MK_SHIFT_CONST(29)
#define GPIO_GG_SCR_00_0_SEC_LCK_FIELD                  _MK_FIELD_CONST(0x1, GPIO_GG_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_GG_SCR_00_0_SEC_LCK_RANGE                  29:29
#define GPIO_GG_SCR_00_0_SEC_LCK_WOFFSET                        0x0
#define GPIO_GG_SCR_00_0_SEC_LCK_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_SEC_LCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_GG_SCR_00_0_SEC_LCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_SEC_LCK_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define GPIO_GG_SCR_00_0_SEC_WEN_SHIFT                  _MK_SHIFT_CONST(28)
#define GPIO_GG_SCR_00_0_SEC_WEN_FIELD                  _MK_FIELD_CONST(0x1, GPIO_GG_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_GG_SCR_00_0_SEC_WEN_RANGE                  28:28
#define GPIO_GG_SCR_00_0_SEC_WEN_WOFFSET                        0x0
#define GPIO_GG_SCR_00_0_SEC_WEN_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_SEC_WEN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_GG_SCR_00_0_SEC_WEN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_SEC_WEN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define GPIO_GG_SCR_00_0_SEC_REN_SHIFT                  _MK_SHIFT_CONST(27)
#define GPIO_GG_SCR_00_0_SEC_REN_FIELD                  _MK_FIELD_CONST(0x1, GPIO_GG_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_GG_SCR_00_0_SEC_REN_RANGE                  27:27
#define GPIO_GG_SCR_00_0_SEC_REN_WOFFSET                        0x0
#define GPIO_GG_SCR_00_0_SEC_REN_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_SEC_REN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_GG_SCR_00_0_SEC_REN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_SEC_REN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define GPIO_GG_SCR_00_0_SEC_OWNER_SHIFT                        _MK_SHIFT_CONST(24)
#define GPIO_GG_SCR_00_0_SEC_OWNER_FIELD                        _MK_FIELD_CONST(0x7, GPIO_GG_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_GG_SCR_00_0_SEC_OWNER_RANGE                        26:24
#define GPIO_GG_SCR_00_0_SEC_OWNER_WOFFSET                      0x0
#define GPIO_GG_SCR_00_0_SEC_OWNER_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_SEC_OWNER_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
#define GPIO_GG_SCR_00_0_SEC_OWNER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_GG_SCR_00_0_PR7_SHIFT                      _MK_SHIFT_CONST(23)
#define GPIO_GG_SCR_00_0_PR7_FIELD                      _MK_FIELD_CONST(0x1, GPIO_GG_SCR_00_0_PR7_SHIFT)
#define GPIO_GG_SCR_00_0_PR7_RANGE                      23:23
#define GPIO_GG_SCR_00_0_PR7_WOFFSET                    0x0
#define GPIO_GG_SCR_00_0_PR7_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_PR7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_GG_SCR_00_0_PR7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_PR7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_PR7_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_PR7_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_GG_SCR_00_0_PR6_SHIFT                      _MK_SHIFT_CONST(22)
#define GPIO_GG_SCR_00_0_PR6_FIELD                      _MK_FIELD_CONST(0x1, GPIO_GG_SCR_00_0_PR6_SHIFT)
#define GPIO_GG_SCR_00_0_PR6_RANGE                      22:22
#define GPIO_GG_SCR_00_0_PR6_WOFFSET                    0x0
#define GPIO_GG_SCR_00_0_PR6_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_PR6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_GG_SCR_00_0_PR6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_PR6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_PR6_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_PR6_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_GG_SCR_00_0_PR5_SHIFT                      _MK_SHIFT_CONST(21)
#define GPIO_GG_SCR_00_0_PR5_FIELD                      _MK_FIELD_CONST(0x1, GPIO_GG_SCR_00_0_PR5_SHIFT)
#define GPIO_GG_SCR_00_0_PR5_RANGE                      21:21
#define GPIO_GG_SCR_00_0_PR5_WOFFSET                    0x0
#define GPIO_GG_SCR_00_0_PR5_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_PR5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_GG_SCR_00_0_PR5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_PR5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_PR5_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_PR5_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_GG_SCR_00_0_PR4_SHIFT                      _MK_SHIFT_CONST(20)
#define GPIO_GG_SCR_00_0_PR4_FIELD                      _MK_FIELD_CONST(0x1, GPIO_GG_SCR_00_0_PR4_SHIFT)
#define GPIO_GG_SCR_00_0_PR4_RANGE                      20:20
#define GPIO_GG_SCR_00_0_PR4_WOFFSET                    0x0
#define GPIO_GG_SCR_00_0_PR4_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_PR4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_GG_SCR_00_0_PR4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_PR4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_PR4_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_PR4_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_GG_SCR_00_0_PR3_SHIFT                      _MK_SHIFT_CONST(19)
#define GPIO_GG_SCR_00_0_PR3_FIELD                      _MK_FIELD_CONST(0x1, GPIO_GG_SCR_00_0_PR3_SHIFT)
#define GPIO_GG_SCR_00_0_PR3_RANGE                      19:19
#define GPIO_GG_SCR_00_0_PR3_WOFFSET                    0x0
#define GPIO_GG_SCR_00_0_PR3_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_PR3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_GG_SCR_00_0_PR3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_PR3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_PR3_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_PR3_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_GG_SCR_00_0_PR2_SHIFT                      _MK_SHIFT_CONST(18)
#define GPIO_GG_SCR_00_0_PR2_FIELD                      _MK_FIELD_CONST(0x1, GPIO_GG_SCR_00_0_PR2_SHIFT)
#define GPIO_GG_SCR_00_0_PR2_RANGE                      18:18
#define GPIO_GG_SCR_00_0_PR2_WOFFSET                    0x0
#define GPIO_GG_SCR_00_0_PR2_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_PR2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_GG_SCR_00_0_PR2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_PR2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_PR2_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_PR2_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_GG_SCR_00_0_PR1_SHIFT                      _MK_SHIFT_CONST(17)
#define GPIO_GG_SCR_00_0_PR1_FIELD                      _MK_FIELD_CONST(0x1, GPIO_GG_SCR_00_0_PR1_SHIFT)
#define GPIO_GG_SCR_00_0_PR1_RANGE                      17:17
#define GPIO_GG_SCR_00_0_PR1_WOFFSET                    0x0
#define GPIO_GG_SCR_00_0_PR1_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_PR1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_GG_SCR_00_0_PR1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_PR1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_PR1_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_PR1_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_GG_SCR_00_0_PR0_SHIFT                      _MK_SHIFT_CONST(16)
#define GPIO_GG_SCR_00_0_PR0_FIELD                      _MK_FIELD_CONST(0x1, GPIO_GG_SCR_00_0_PR0_SHIFT)
#define GPIO_GG_SCR_00_0_PR0_RANGE                      16:16
#define GPIO_GG_SCR_00_0_PR0_WOFFSET                    0x0
#define GPIO_GG_SCR_00_0_PR0_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_PR0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_GG_SCR_00_0_PR0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_PR0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_PR0_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_PR0_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_GG_SCR_00_0_G7W_SHIFT                      _MK_SHIFT_CONST(15)
#define GPIO_GG_SCR_00_0_G7W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_GG_SCR_00_0_G7W_SHIFT)
#define GPIO_GG_SCR_00_0_G7W_RANGE                      15:15
#define GPIO_GG_SCR_00_0_G7W_WOFFSET                    0x0
#define GPIO_GG_SCR_00_0_G7W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G7W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_GG_SCR_00_0_G7W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G7W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G7W_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G7W_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_GG_SCR_00_0_G6W_SHIFT                      _MK_SHIFT_CONST(14)
#define GPIO_GG_SCR_00_0_G6W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_GG_SCR_00_0_G6W_SHIFT)
#define GPIO_GG_SCR_00_0_G6W_RANGE                      14:14
#define GPIO_GG_SCR_00_0_G6W_WOFFSET                    0x0
#define GPIO_GG_SCR_00_0_G6W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G6W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_GG_SCR_00_0_G6W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G6W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G6W_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G6W_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_GG_SCR_00_0_G5W_SHIFT                      _MK_SHIFT_CONST(13)
#define GPIO_GG_SCR_00_0_G5W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_GG_SCR_00_0_G5W_SHIFT)
#define GPIO_GG_SCR_00_0_G5W_RANGE                      13:13
#define GPIO_GG_SCR_00_0_G5W_WOFFSET                    0x0
#define GPIO_GG_SCR_00_0_G5W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G5W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_GG_SCR_00_0_G5W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G5W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G5W_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G5W_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_GG_SCR_00_0_G4W_SHIFT                      _MK_SHIFT_CONST(12)
#define GPIO_GG_SCR_00_0_G4W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_GG_SCR_00_0_G4W_SHIFT)
#define GPIO_GG_SCR_00_0_G4W_RANGE                      12:12
#define GPIO_GG_SCR_00_0_G4W_WOFFSET                    0x0
#define GPIO_GG_SCR_00_0_G4W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G4W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_GG_SCR_00_0_G4W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G4W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G4W_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G4W_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_GG_SCR_00_0_G3W_SHIFT                      _MK_SHIFT_CONST(11)
#define GPIO_GG_SCR_00_0_G3W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_GG_SCR_00_0_G3W_SHIFT)
#define GPIO_GG_SCR_00_0_G3W_RANGE                      11:11
#define GPIO_GG_SCR_00_0_G3W_WOFFSET                    0x0
#define GPIO_GG_SCR_00_0_G3W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G3W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_GG_SCR_00_0_G3W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G3W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G3W_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G3W_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_GG_SCR_00_0_G2W_SHIFT                      _MK_SHIFT_CONST(10)
#define GPIO_GG_SCR_00_0_G2W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_GG_SCR_00_0_G2W_SHIFT)
#define GPIO_GG_SCR_00_0_G2W_RANGE                      10:10
#define GPIO_GG_SCR_00_0_G2W_WOFFSET                    0x0
#define GPIO_GG_SCR_00_0_G2W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G2W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_GG_SCR_00_0_G2W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G2W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G2W_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G2W_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_GG_SCR_00_0_G1W_SHIFT                      _MK_SHIFT_CONST(9)
#define GPIO_GG_SCR_00_0_G1W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_GG_SCR_00_0_G1W_SHIFT)
#define GPIO_GG_SCR_00_0_G1W_RANGE                      9:9
#define GPIO_GG_SCR_00_0_G1W_WOFFSET                    0x0
#define GPIO_GG_SCR_00_0_G1W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G1W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_GG_SCR_00_0_G1W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G1W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G1W_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G1W_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_GG_SCR_00_0_G0W_SHIFT                      _MK_SHIFT_CONST(8)
#define GPIO_GG_SCR_00_0_G0W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_GG_SCR_00_0_G0W_SHIFT)
#define GPIO_GG_SCR_00_0_G0W_RANGE                      8:8
#define GPIO_GG_SCR_00_0_G0W_WOFFSET                    0x0
#define GPIO_GG_SCR_00_0_G0W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G0W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_GG_SCR_00_0_G0W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G0W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G0W_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G0W_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_GG_SCR_00_0_G7R_SHIFT                      _MK_SHIFT_CONST(7)
#define GPIO_GG_SCR_00_0_G7R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_GG_SCR_00_0_G7R_SHIFT)
#define GPIO_GG_SCR_00_0_G7R_RANGE                      7:7
#define GPIO_GG_SCR_00_0_G7R_WOFFSET                    0x0
#define GPIO_GG_SCR_00_0_G7R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G7R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_GG_SCR_00_0_G7R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G7R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G7R_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G7R_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_GG_SCR_00_0_G6R_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_GG_SCR_00_0_G6R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_GG_SCR_00_0_G6R_SHIFT)
#define GPIO_GG_SCR_00_0_G6R_RANGE                      6:6
#define GPIO_GG_SCR_00_0_G6R_WOFFSET                    0x0
#define GPIO_GG_SCR_00_0_G6R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G6R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_GG_SCR_00_0_G6R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G6R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G6R_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G6R_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_GG_SCR_00_0_G5R_SHIFT                      _MK_SHIFT_CONST(5)
#define GPIO_GG_SCR_00_0_G5R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_GG_SCR_00_0_G5R_SHIFT)
#define GPIO_GG_SCR_00_0_G5R_RANGE                      5:5
#define GPIO_GG_SCR_00_0_G5R_WOFFSET                    0x0
#define GPIO_GG_SCR_00_0_G5R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G5R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_GG_SCR_00_0_G5R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G5R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G5R_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G5R_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_GG_SCR_00_0_G4R_SHIFT                      _MK_SHIFT_CONST(4)
#define GPIO_GG_SCR_00_0_G4R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_GG_SCR_00_0_G4R_SHIFT)
#define GPIO_GG_SCR_00_0_G4R_RANGE                      4:4
#define GPIO_GG_SCR_00_0_G4R_WOFFSET                    0x0
#define GPIO_GG_SCR_00_0_G4R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G4R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_GG_SCR_00_0_G4R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G4R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G4R_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G4R_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_GG_SCR_00_0_G3R_SHIFT                      _MK_SHIFT_CONST(3)
#define GPIO_GG_SCR_00_0_G3R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_GG_SCR_00_0_G3R_SHIFT)
#define GPIO_GG_SCR_00_0_G3R_RANGE                      3:3
#define GPIO_GG_SCR_00_0_G3R_WOFFSET                    0x0
#define GPIO_GG_SCR_00_0_G3R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G3R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_GG_SCR_00_0_G3R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G3R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G3R_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G3R_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_GG_SCR_00_0_G2R_SHIFT                      _MK_SHIFT_CONST(2)
#define GPIO_GG_SCR_00_0_G2R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_GG_SCR_00_0_G2R_SHIFT)
#define GPIO_GG_SCR_00_0_G2R_RANGE                      2:2
#define GPIO_GG_SCR_00_0_G2R_WOFFSET                    0x0
#define GPIO_GG_SCR_00_0_G2R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G2R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_GG_SCR_00_0_G2R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G2R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G2R_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G2R_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_GG_SCR_00_0_G1R_SHIFT                      _MK_SHIFT_CONST(1)
#define GPIO_GG_SCR_00_0_G1R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_GG_SCR_00_0_G1R_SHIFT)
#define GPIO_GG_SCR_00_0_G1R_RANGE                      1:1
#define GPIO_GG_SCR_00_0_G1R_WOFFSET                    0x0
#define GPIO_GG_SCR_00_0_G1R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G1R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_GG_SCR_00_0_G1R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G1R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G1R_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G1R_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_GG_SCR_00_0_G0R_SHIFT                      _MK_SHIFT_CONST(0)
#define GPIO_GG_SCR_00_0_G0R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_GG_SCR_00_0_G0R_SHIFT)
#define GPIO_GG_SCR_00_0_G0R_RANGE                      0:0
#define GPIO_GG_SCR_00_0_G0R_WOFFSET                    0x0
#define GPIO_GG_SCR_00_0_G0R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G0R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_GG_SCR_00_0_G0R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G0R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G0R_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_00_0_G0R_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Register GPIO_GG_VM_01_0
#define GPIO_GG_VM_01_0                 _MK_ADDR_CONST(0x8)
#define GPIO_GG_VM_01_0_SECURE                  0x0
#define GPIO_GG_VM_01_0_DUAL                    0x0
#define GPIO_GG_VM_01_0_SCR                     GPIO_CTL0_VM_SCR_0
#define GPIO_GG_VM_01_0_WORD_COUNT                      0x1
#define GPIO_GG_VM_01_0_RESET_VAL                       _MK_MASK_CONST(0xffff)
#define GPIO_GG_VM_01_0_RESET_MASK                      _MK_MASK_CONST(0xffff)
#define GPIO_GG_VM_01_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_GG_VM_01_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_GG_VM_01_0_READ_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_GG_VM_01_0_WRITE_MASK                      _MK_MASK_CONST(0xffff)
#define GPIO_GG_VM_01_0_VM1_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_GG_VM_01_0_VM1_FIELD                       _MK_FIELD_CONST(0x3, GPIO_GG_VM_01_0_VM1_SHIFT)
#define GPIO_GG_VM_01_0_VM1_RANGE                       1:0
#define GPIO_GG_VM_01_0_VM1_WOFFSET                     0x0
#define GPIO_GG_VM_01_0_VM1_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_GG_VM_01_0_VM1_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_GG_VM_01_0_VM1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_GG_VM_01_0_VM1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_GG_VM_01_0_VM1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_GG_VM_01_0_VM1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_GG_VM_01_0_VM2_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_GG_VM_01_0_VM2_FIELD                       _MK_FIELD_CONST(0x3, GPIO_GG_VM_01_0_VM2_SHIFT)
#define GPIO_GG_VM_01_0_VM2_RANGE                       3:2
#define GPIO_GG_VM_01_0_VM2_WOFFSET                     0x0
#define GPIO_GG_VM_01_0_VM2_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_GG_VM_01_0_VM2_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_GG_VM_01_0_VM2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_GG_VM_01_0_VM2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_GG_VM_01_0_VM2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_GG_VM_01_0_VM2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_GG_VM_01_0_VM3_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_GG_VM_01_0_VM3_FIELD                       _MK_FIELD_CONST(0x3, GPIO_GG_VM_01_0_VM3_SHIFT)
#define GPIO_GG_VM_01_0_VM3_RANGE                       5:4
#define GPIO_GG_VM_01_0_VM3_WOFFSET                     0x0
#define GPIO_GG_VM_01_0_VM3_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_GG_VM_01_0_VM3_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_GG_VM_01_0_VM3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_GG_VM_01_0_VM3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_GG_VM_01_0_VM3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_GG_VM_01_0_VM3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_GG_VM_01_0_VM4_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_GG_VM_01_0_VM4_FIELD                       _MK_FIELD_CONST(0x3, GPIO_GG_VM_01_0_VM4_SHIFT)
#define GPIO_GG_VM_01_0_VM4_RANGE                       7:6
#define GPIO_GG_VM_01_0_VM4_WOFFSET                     0x0
#define GPIO_GG_VM_01_0_VM4_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_GG_VM_01_0_VM4_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_GG_VM_01_0_VM4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_GG_VM_01_0_VM4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_GG_VM_01_0_VM4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_GG_VM_01_0_VM4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_GG_VM_01_0_VM5_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_GG_VM_01_0_VM5_FIELD                       _MK_FIELD_CONST(0x3, GPIO_GG_VM_01_0_VM5_SHIFT)
#define GPIO_GG_VM_01_0_VM5_RANGE                       9:8
#define GPIO_GG_VM_01_0_VM5_WOFFSET                     0x0
#define GPIO_GG_VM_01_0_VM5_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_GG_VM_01_0_VM5_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_GG_VM_01_0_VM5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_GG_VM_01_0_VM5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_GG_VM_01_0_VM5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_GG_VM_01_0_VM5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_GG_VM_01_0_VM6_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_GG_VM_01_0_VM6_FIELD                       _MK_FIELD_CONST(0x3, GPIO_GG_VM_01_0_VM6_SHIFT)
#define GPIO_GG_VM_01_0_VM6_RANGE                       11:10
#define GPIO_GG_VM_01_0_VM6_WOFFSET                     0x0
#define GPIO_GG_VM_01_0_VM6_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_GG_VM_01_0_VM6_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_GG_VM_01_0_VM6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_GG_VM_01_0_VM6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_GG_VM_01_0_VM6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_GG_VM_01_0_VM6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_GG_VM_01_0_VM7_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_GG_VM_01_0_VM7_FIELD                       _MK_FIELD_CONST(0x3, GPIO_GG_VM_01_0_VM7_SHIFT)
#define GPIO_GG_VM_01_0_VM7_RANGE                       13:12
#define GPIO_GG_VM_01_0_VM7_WOFFSET                     0x0
#define GPIO_GG_VM_01_0_VM7_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_GG_VM_01_0_VM7_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_GG_VM_01_0_VM7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_GG_VM_01_0_VM7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_GG_VM_01_0_VM7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_GG_VM_01_0_VM7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_GG_VM_01_0_VM8_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_GG_VM_01_0_VM8_FIELD                       _MK_FIELD_CONST(0x3, GPIO_GG_VM_01_0_VM8_SHIFT)
#define GPIO_GG_VM_01_0_VM8_RANGE                       15:14
#define GPIO_GG_VM_01_0_VM8_WOFFSET                     0x0
#define GPIO_GG_VM_01_0_VM8_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_GG_VM_01_0_VM8_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_GG_VM_01_0_VM8_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_GG_VM_01_0_VM8_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_GG_VM_01_0_VM8_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_GG_VM_01_0_VM8_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_GG_SCR_01_0
#define GPIO_GG_SCR_01_0                        _MK_ADDR_CONST(0xc)
#define GPIO_GG_SCR_01_0_SECURE                         0x0
#define GPIO_GG_SCR_01_0_DUAL                   0x0
#define GPIO_GG_SCR_01_0_SCR                    0
#define GPIO_GG_SCR_01_0_WORD_COUNT                     0x1
#define GPIO_GG_SCR_01_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_RESET_MASK                     _MK_MASK_CONST(0x3fffffff)
#define GPIO_GG_SCR_01_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_READ_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_GG_SCR_01_0_WRITE_MASK                     _MK_MASK_CONST(0x3fffffff)
#define GPIO_GG_SCR_01_0_SEC_LCK_SHIFT                  _MK_SHIFT_CONST(29)
#define GPIO_GG_SCR_01_0_SEC_LCK_FIELD                  _MK_FIELD_CONST(0x1, GPIO_GG_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_GG_SCR_01_0_SEC_LCK_RANGE                  29:29
#define GPIO_GG_SCR_01_0_SEC_LCK_WOFFSET                        0x0
#define GPIO_GG_SCR_01_0_SEC_LCK_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_SEC_LCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_GG_SCR_01_0_SEC_LCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_SEC_LCK_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define GPIO_GG_SCR_01_0_SEC_WEN_SHIFT                  _MK_SHIFT_CONST(28)
#define GPIO_GG_SCR_01_0_SEC_WEN_FIELD                  _MK_FIELD_CONST(0x1, GPIO_GG_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_GG_SCR_01_0_SEC_WEN_RANGE                  28:28
#define GPIO_GG_SCR_01_0_SEC_WEN_WOFFSET                        0x0
#define GPIO_GG_SCR_01_0_SEC_WEN_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_SEC_WEN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_GG_SCR_01_0_SEC_WEN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_SEC_WEN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define GPIO_GG_SCR_01_0_SEC_REN_SHIFT                  _MK_SHIFT_CONST(27)
#define GPIO_GG_SCR_01_0_SEC_REN_FIELD                  _MK_FIELD_CONST(0x1, GPIO_GG_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_GG_SCR_01_0_SEC_REN_RANGE                  27:27
#define GPIO_GG_SCR_01_0_SEC_REN_WOFFSET                        0x0
#define GPIO_GG_SCR_01_0_SEC_REN_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_SEC_REN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_GG_SCR_01_0_SEC_REN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_SEC_REN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define GPIO_GG_SCR_01_0_SEC_OWNER_SHIFT                        _MK_SHIFT_CONST(24)
#define GPIO_GG_SCR_01_0_SEC_OWNER_FIELD                        _MK_FIELD_CONST(0x7, GPIO_GG_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_GG_SCR_01_0_SEC_OWNER_RANGE                        26:24
#define GPIO_GG_SCR_01_0_SEC_OWNER_WOFFSET                      0x0
#define GPIO_GG_SCR_01_0_SEC_OWNER_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_SEC_OWNER_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
#define GPIO_GG_SCR_01_0_SEC_OWNER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_GG_SCR_01_0_PR7_SHIFT                      _MK_SHIFT_CONST(23)
#define GPIO_GG_SCR_01_0_PR7_FIELD                      _MK_FIELD_CONST(0x1, GPIO_GG_SCR_01_0_PR7_SHIFT)
#define GPIO_GG_SCR_01_0_PR7_RANGE                      23:23
#define GPIO_GG_SCR_01_0_PR7_WOFFSET                    0x0
#define GPIO_GG_SCR_01_0_PR7_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_PR7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_GG_SCR_01_0_PR7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_PR7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_PR7_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_PR7_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_GG_SCR_01_0_PR6_SHIFT                      _MK_SHIFT_CONST(22)
#define GPIO_GG_SCR_01_0_PR6_FIELD                      _MK_FIELD_CONST(0x1, GPIO_GG_SCR_01_0_PR6_SHIFT)
#define GPIO_GG_SCR_01_0_PR6_RANGE                      22:22
#define GPIO_GG_SCR_01_0_PR6_WOFFSET                    0x0
#define GPIO_GG_SCR_01_0_PR6_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_PR6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_GG_SCR_01_0_PR6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_PR6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_PR6_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_PR6_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_GG_SCR_01_0_PR5_SHIFT                      _MK_SHIFT_CONST(21)
#define GPIO_GG_SCR_01_0_PR5_FIELD                      _MK_FIELD_CONST(0x1, GPIO_GG_SCR_01_0_PR5_SHIFT)
#define GPIO_GG_SCR_01_0_PR5_RANGE                      21:21
#define GPIO_GG_SCR_01_0_PR5_WOFFSET                    0x0
#define GPIO_GG_SCR_01_0_PR5_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_PR5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_GG_SCR_01_0_PR5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_PR5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_PR5_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_PR5_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_GG_SCR_01_0_PR4_SHIFT                      _MK_SHIFT_CONST(20)
#define GPIO_GG_SCR_01_0_PR4_FIELD                      _MK_FIELD_CONST(0x1, GPIO_GG_SCR_01_0_PR4_SHIFT)
#define GPIO_GG_SCR_01_0_PR4_RANGE                      20:20
#define GPIO_GG_SCR_01_0_PR4_WOFFSET                    0x0
#define GPIO_GG_SCR_01_0_PR4_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_PR4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_GG_SCR_01_0_PR4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_PR4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_PR4_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_PR4_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_GG_SCR_01_0_PR3_SHIFT                      _MK_SHIFT_CONST(19)
#define GPIO_GG_SCR_01_0_PR3_FIELD                      _MK_FIELD_CONST(0x1, GPIO_GG_SCR_01_0_PR3_SHIFT)
#define GPIO_GG_SCR_01_0_PR3_RANGE                      19:19
#define GPIO_GG_SCR_01_0_PR3_WOFFSET                    0x0
#define GPIO_GG_SCR_01_0_PR3_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_PR3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_GG_SCR_01_0_PR3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_PR3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_PR3_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_PR3_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_GG_SCR_01_0_PR2_SHIFT                      _MK_SHIFT_CONST(18)
#define GPIO_GG_SCR_01_0_PR2_FIELD                      _MK_FIELD_CONST(0x1, GPIO_GG_SCR_01_0_PR2_SHIFT)
#define GPIO_GG_SCR_01_0_PR2_RANGE                      18:18
#define GPIO_GG_SCR_01_0_PR2_WOFFSET                    0x0
#define GPIO_GG_SCR_01_0_PR2_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_PR2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_GG_SCR_01_0_PR2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_PR2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_PR2_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_PR2_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_GG_SCR_01_0_PR1_SHIFT                      _MK_SHIFT_CONST(17)
#define GPIO_GG_SCR_01_0_PR1_FIELD                      _MK_FIELD_CONST(0x1, GPIO_GG_SCR_01_0_PR1_SHIFT)
#define GPIO_GG_SCR_01_0_PR1_RANGE                      17:17
#define GPIO_GG_SCR_01_0_PR1_WOFFSET                    0x0
#define GPIO_GG_SCR_01_0_PR1_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_PR1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_GG_SCR_01_0_PR1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_PR1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_PR1_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_PR1_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_GG_SCR_01_0_PR0_SHIFT                      _MK_SHIFT_CONST(16)
#define GPIO_GG_SCR_01_0_PR0_FIELD                      _MK_FIELD_CONST(0x1, GPIO_GG_SCR_01_0_PR0_SHIFT)
#define GPIO_GG_SCR_01_0_PR0_RANGE                      16:16
#define GPIO_GG_SCR_01_0_PR0_WOFFSET                    0x0
#define GPIO_GG_SCR_01_0_PR0_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_PR0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_GG_SCR_01_0_PR0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_PR0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_PR0_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_PR0_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_GG_SCR_01_0_G7W_SHIFT                      _MK_SHIFT_CONST(15)
#define GPIO_GG_SCR_01_0_G7W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_GG_SCR_01_0_G7W_SHIFT)
#define GPIO_GG_SCR_01_0_G7W_RANGE                      15:15
#define GPIO_GG_SCR_01_0_G7W_WOFFSET                    0x0
#define GPIO_GG_SCR_01_0_G7W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G7W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_GG_SCR_01_0_G7W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G7W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G7W_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G7W_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_GG_SCR_01_0_G6W_SHIFT                      _MK_SHIFT_CONST(14)
#define GPIO_GG_SCR_01_0_G6W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_GG_SCR_01_0_G6W_SHIFT)
#define GPIO_GG_SCR_01_0_G6W_RANGE                      14:14
#define GPIO_GG_SCR_01_0_G6W_WOFFSET                    0x0
#define GPIO_GG_SCR_01_0_G6W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G6W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_GG_SCR_01_0_G6W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G6W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G6W_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G6W_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_GG_SCR_01_0_G5W_SHIFT                      _MK_SHIFT_CONST(13)
#define GPIO_GG_SCR_01_0_G5W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_GG_SCR_01_0_G5W_SHIFT)
#define GPIO_GG_SCR_01_0_G5W_RANGE                      13:13
#define GPIO_GG_SCR_01_0_G5W_WOFFSET                    0x0
#define GPIO_GG_SCR_01_0_G5W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G5W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_GG_SCR_01_0_G5W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G5W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G5W_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G5W_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_GG_SCR_01_0_G4W_SHIFT                      _MK_SHIFT_CONST(12)
#define GPIO_GG_SCR_01_0_G4W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_GG_SCR_01_0_G4W_SHIFT)
#define GPIO_GG_SCR_01_0_G4W_RANGE                      12:12
#define GPIO_GG_SCR_01_0_G4W_WOFFSET                    0x0
#define GPIO_GG_SCR_01_0_G4W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G4W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_GG_SCR_01_0_G4W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G4W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G4W_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G4W_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_GG_SCR_01_0_G3W_SHIFT                      _MK_SHIFT_CONST(11)
#define GPIO_GG_SCR_01_0_G3W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_GG_SCR_01_0_G3W_SHIFT)
#define GPIO_GG_SCR_01_0_G3W_RANGE                      11:11
#define GPIO_GG_SCR_01_0_G3W_WOFFSET                    0x0
#define GPIO_GG_SCR_01_0_G3W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G3W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_GG_SCR_01_0_G3W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G3W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G3W_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G3W_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_GG_SCR_01_0_G2W_SHIFT                      _MK_SHIFT_CONST(10)
#define GPIO_GG_SCR_01_0_G2W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_GG_SCR_01_0_G2W_SHIFT)
#define GPIO_GG_SCR_01_0_G2W_RANGE                      10:10
#define GPIO_GG_SCR_01_0_G2W_WOFFSET                    0x0
#define GPIO_GG_SCR_01_0_G2W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G2W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_GG_SCR_01_0_G2W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G2W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G2W_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G2W_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_GG_SCR_01_0_G1W_SHIFT                      _MK_SHIFT_CONST(9)
#define GPIO_GG_SCR_01_0_G1W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_GG_SCR_01_0_G1W_SHIFT)
#define GPIO_GG_SCR_01_0_G1W_RANGE                      9:9
#define GPIO_GG_SCR_01_0_G1W_WOFFSET                    0x0
#define GPIO_GG_SCR_01_0_G1W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G1W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_GG_SCR_01_0_G1W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G1W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G1W_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G1W_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_GG_SCR_01_0_G0W_SHIFT                      _MK_SHIFT_CONST(8)
#define GPIO_GG_SCR_01_0_G0W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_GG_SCR_01_0_G0W_SHIFT)
#define GPIO_GG_SCR_01_0_G0W_RANGE                      8:8
#define GPIO_GG_SCR_01_0_G0W_WOFFSET                    0x0
#define GPIO_GG_SCR_01_0_G0W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G0W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_GG_SCR_01_0_G0W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G0W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G0W_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G0W_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_GG_SCR_01_0_G7R_SHIFT                      _MK_SHIFT_CONST(7)
#define GPIO_GG_SCR_01_0_G7R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_GG_SCR_01_0_G7R_SHIFT)
#define GPIO_GG_SCR_01_0_G7R_RANGE                      7:7
#define GPIO_GG_SCR_01_0_G7R_WOFFSET                    0x0
#define GPIO_GG_SCR_01_0_G7R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G7R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_GG_SCR_01_0_G7R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G7R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G7R_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G7R_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_GG_SCR_01_0_G6R_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_GG_SCR_01_0_G6R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_GG_SCR_01_0_G6R_SHIFT)
#define GPIO_GG_SCR_01_0_G6R_RANGE                      6:6
#define GPIO_GG_SCR_01_0_G6R_WOFFSET                    0x0
#define GPIO_GG_SCR_01_0_G6R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G6R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_GG_SCR_01_0_G6R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G6R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G6R_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G6R_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_GG_SCR_01_0_G5R_SHIFT                      _MK_SHIFT_CONST(5)
#define GPIO_GG_SCR_01_0_G5R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_GG_SCR_01_0_G5R_SHIFT)
#define GPIO_GG_SCR_01_0_G5R_RANGE                      5:5
#define GPIO_GG_SCR_01_0_G5R_WOFFSET                    0x0
#define GPIO_GG_SCR_01_0_G5R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G5R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_GG_SCR_01_0_G5R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G5R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G5R_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G5R_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_GG_SCR_01_0_G4R_SHIFT                      _MK_SHIFT_CONST(4)
#define GPIO_GG_SCR_01_0_G4R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_GG_SCR_01_0_G4R_SHIFT)
#define GPIO_GG_SCR_01_0_G4R_RANGE                      4:4
#define GPIO_GG_SCR_01_0_G4R_WOFFSET                    0x0
#define GPIO_GG_SCR_01_0_G4R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G4R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_GG_SCR_01_0_G4R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G4R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G4R_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G4R_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_GG_SCR_01_0_G3R_SHIFT                      _MK_SHIFT_CONST(3)
#define GPIO_GG_SCR_01_0_G3R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_GG_SCR_01_0_G3R_SHIFT)
#define GPIO_GG_SCR_01_0_G3R_RANGE                      3:3
#define GPIO_GG_SCR_01_0_G3R_WOFFSET                    0x0
#define GPIO_GG_SCR_01_0_G3R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G3R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_GG_SCR_01_0_G3R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G3R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G3R_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G3R_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_GG_SCR_01_0_G2R_SHIFT                      _MK_SHIFT_CONST(2)
#define GPIO_GG_SCR_01_0_G2R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_GG_SCR_01_0_G2R_SHIFT)
#define GPIO_GG_SCR_01_0_G2R_RANGE                      2:2
#define GPIO_GG_SCR_01_0_G2R_WOFFSET                    0x0
#define GPIO_GG_SCR_01_0_G2R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G2R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_GG_SCR_01_0_G2R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G2R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G2R_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G2R_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_GG_SCR_01_0_G1R_SHIFT                      _MK_SHIFT_CONST(1)
#define GPIO_GG_SCR_01_0_G1R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_GG_SCR_01_0_G1R_SHIFT)
#define GPIO_GG_SCR_01_0_G1R_RANGE                      1:1
#define GPIO_GG_SCR_01_0_G1R_WOFFSET                    0x0
#define GPIO_GG_SCR_01_0_G1R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G1R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_GG_SCR_01_0_G1R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G1R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G1R_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G1R_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_GG_SCR_01_0_G0R_SHIFT                      _MK_SHIFT_CONST(0)
#define GPIO_GG_SCR_01_0_G0R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_GG_SCR_01_0_G0R_SHIFT)
#define GPIO_GG_SCR_01_0_G0R_RANGE                      0:0
#define GPIO_GG_SCR_01_0_G0R_WOFFSET                    0x0
#define GPIO_GG_SCR_01_0_G0R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G0R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_GG_SCR_01_0_G0R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G0R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G0R_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_GG_SCR_01_0_G0R_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Reserved address 0x10

// Reserved address 0x14

// Reserved address 0x18

// Reserved address 0x1c

// Reserved address 0x20

// Reserved address 0x24

// Reserved address 0x28

// Reserved address 0x2c

// Reserved address 0x30

// Reserved address 0x34

// Reserved address 0x38

// Reserved address 0x3c

// Register GPIO_CTL0_VM_SCR_0
#define GPIO_CTL0_VM_SCR_0                      _MK_ADDR_CONST(0x800)
#define GPIO_CTL0_VM_SCR_0_SECURE                       0x0
#define GPIO_CTL0_VM_SCR_0_DUAL                         0x0
#define GPIO_CTL0_VM_SCR_0_SCR                  0
#define GPIO_CTL0_VM_SCR_0_WORD_COUNT                   0x1
#define GPIO_CTL0_VM_SCR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_RESET_MASK                   _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL0_VM_SCR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_READ_MASK                    _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL0_VM_SCR_0_WRITE_MASK                   _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL0_VM_SCR_0_SEC_LCK_SHIFT                        _MK_SHIFT_CONST(29)
#define GPIO_CTL0_VM_SCR_0_SEC_LCK_FIELD                        _MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_SEC_LCK_SHIFT)
#define GPIO_CTL0_VM_SCR_0_SEC_LCK_RANGE                        29:29
#define GPIO_CTL0_VM_SCR_0_SEC_LCK_WOFFSET                      0x0
#define GPIO_CTL0_VM_SCR_0_SEC_LCK_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_SEC_LCK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_SEC_LCK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_SEC_LCK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_SEC_LCK_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_CTL0_VM_SCR_0_SEC_WEN_SHIFT                        _MK_SHIFT_CONST(28)
#define GPIO_CTL0_VM_SCR_0_SEC_WEN_FIELD                        _MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_SEC_WEN_SHIFT)
#define GPIO_CTL0_VM_SCR_0_SEC_WEN_RANGE                        28:28
#define GPIO_CTL0_VM_SCR_0_SEC_WEN_WOFFSET                      0x0
#define GPIO_CTL0_VM_SCR_0_SEC_WEN_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_SEC_WEN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_SEC_WEN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_SEC_WEN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_SEC_WEN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_CTL0_VM_SCR_0_SEC_REN_SHIFT                        _MK_SHIFT_CONST(27)
#define GPIO_CTL0_VM_SCR_0_SEC_REN_FIELD                        _MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_SEC_REN_SHIFT)
#define GPIO_CTL0_VM_SCR_0_SEC_REN_RANGE                        27:27
#define GPIO_CTL0_VM_SCR_0_SEC_REN_WOFFSET                      0x0
#define GPIO_CTL0_VM_SCR_0_SEC_REN_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_SEC_REN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_SEC_REN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_SEC_REN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_SEC_REN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_SEC_REN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_CTL0_VM_SCR_0_SEC_OWNER_SHIFT                      _MK_SHIFT_CONST(24)
#define GPIO_CTL0_VM_SCR_0_SEC_OWNER_FIELD                      _MK_FIELD_CONST(0x7, GPIO_CTL0_VM_SCR_0_SEC_OWNER_SHIFT)
#define GPIO_CTL0_VM_SCR_0_SEC_OWNER_RANGE                      26:24
#define GPIO_CTL0_VM_SCR_0_SEC_OWNER_WOFFSET                    0x0
#define GPIO_CTL0_VM_SCR_0_SEC_OWNER_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_SEC_OWNER_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
#define GPIO_CTL0_VM_SCR_0_SEC_OWNER_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_SEC_OWNER_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_CTL0_VM_SCR_0_PR7_SHIFT                    _MK_SHIFT_CONST(23)
#define GPIO_CTL0_VM_SCR_0_PR7_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_PR7_SHIFT)
#define GPIO_CTL0_VM_SCR_0_PR7_RANGE                    23:23
#define GPIO_CTL0_VM_SCR_0_PR7_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_PR7_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR7_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_PR7_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR7_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR7_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR7_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL0_VM_SCR_0_PR6_SHIFT                    _MK_SHIFT_CONST(22)
#define GPIO_CTL0_VM_SCR_0_PR6_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_PR6_SHIFT)
#define GPIO_CTL0_VM_SCR_0_PR6_RANGE                    22:22
#define GPIO_CTL0_VM_SCR_0_PR6_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_PR6_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR6_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_PR6_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR6_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR6_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL0_VM_SCR_0_PR5_SHIFT                    _MK_SHIFT_CONST(21)
#define GPIO_CTL0_VM_SCR_0_PR5_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_PR5_SHIFT)
#define GPIO_CTL0_VM_SCR_0_PR5_RANGE                    21:21
#define GPIO_CTL0_VM_SCR_0_PR5_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_PR5_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR5_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_PR5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR5_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR5_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL0_VM_SCR_0_PR4_SHIFT                    _MK_SHIFT_CONST(20)
#define GPIO_CTL0_VM_SCR_0_PR4_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_PR4_SHIFT)
#define GPIO_CTL0_VM_SCR_0_PR4_RANGE                    20:20
#define GPIO_CTL0_VM_SCR_0_PR4_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_PR4_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR4_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_PR4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR4_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR4_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL0_VM_SCR_0_PR3_SHIFT                    _MK_SHIFT_CONST(19)
#define GPIO_CTL0_VM_SCR_0_PR3_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_PR3_SHIFT)
#define GPIO_CTL0_VM_SCR_0_PR3_RANGE                    19:19
#define GPIO_CTL0_VM_SCR_0_PR3_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_PR3_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_PR3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR3_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR3_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL0_VM_SCR_0_PR2_SHIFT                    _MK_SHIFT_CONST(18)
#define GPIO_CTL0_VM_SCR_0_PR2_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_PR2_SHIFT)
#define GPIO_CTL0_VM_SCR_0_PR2_RANGE                    18:18
#define GPIO_CTL0_VM_SCR_0_PR2_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_PR2_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_PR2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR2_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR2_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL0_VM_SCR_0_PR1_SHIFT                    _MK_SHIFT_CONST(17)
#define GPIO_CTL0_VM_SCR_0_PR1_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_PR1_SHIFT)
#define GPIO_CTL0_VM_SCR_0_PR1_RANGE                    17:17
#define GPIO_CTL0_VM_SCR_0_PR1_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_PR1_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_PR1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR1_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR1_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL0_VM_SCR_0_PR0_SHIFT                    _MK_SHIFT_CONST(16)
#define GPIO_CTL0_VM_SCR_0_PR0_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_PR0_SHIFT)
#define GPIO_CTL0_VM_SCR_0_PR0_RANGE                    16:16
#define GPIO_CTL0_VM_SCR_0_PR0_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_PR0_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_PR0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR0_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR0_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL0_VM_SCR_0_G7W_SHIFT                    _MK_SHIFT_CONST(15)
#define GPIO_CTL0_VM_SCR_0_G7W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G7W_SHIFT)
#define GPIO_CTL0_VM_SCR_0_G7W_RANGE                    15:15
#define GPIO_CTL0_VM_SCR_0_G7W_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_G7W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G7W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_G7W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G7W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G7W_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G7W_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL0_VM_SCR_0_G6W_SHIFT                    _MK_SHIFT_CONST(14)
#define GPIO_CTL0_VM_SCR_0_G6W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G6W_SHIFT)
#define GPIO_CTL0_VM_SCR_0_G6W_RANGE                    14:14
#define GPIO_CTL0_VM_SCR_0_G6W_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_G6W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G6W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_G6W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G6W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G6W_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G6W_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL0_VM_SCR_0_G5W_SHIFT                    _MK_SHIFT_CONST(13)
#define GPIO_CTL0_VM_SCR_0_G5W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G5W_SHIFT)
#define GPIO_CTL0_VM_SCR_0_G5W_RANGE                    13:13
#define GPIO_CTL0_VM_SCR_0_G5W_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_G5W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G5W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_G5W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G5W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G5W_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G5W_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL0_VM_SCR_0_G4W_SHIFT                    _MK_SHIFT_CONST(12)
#define GPIO_CTL0_VM_SCR_0_G4W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G4W_SHIFT)
#define GPIO_CTL0_VM_SCR_0_G4W_RANGE                    12:12
#define GPIO_CTL0_VM_SCR_0_G4W_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_G4W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G4W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_G4W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G4W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G4W_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G4W_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL0_VM_SCR_0_G3W_SHIFT                    _MK_SHIFT_CONST(11)
#define GPIO_CTL0_VM_SCR_0_G3W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G3W_SHIFT)
#define GPIO_CTL0_VM_SCR_0_G3W_RANGE                    11:11
#define GPIO_CTL0_VM_SCR_0_G3W_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_G3W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G3W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_G3W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G3W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G3W_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G3W_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL0_VM_SCR_0_G2W_SHIFT                    _MK_SHIFT_CONST(10)
#define GPIO_CTL0_VM_SCR_0_G2W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G2W_SHIFT)
#define GPIO_CTL0_VM_SCR_0_G2W_RANGE                    10:10
#define GPIO_CTL0_VM_SCR_0_G2W_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_G2W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G2W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_G2W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G2W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G2W_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G2W_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL0_VM_SCR_0_G1W_SHIFT                    _MK_SHIFT_CONST(9)
#define GPIO_CTL0_VM_SCR_0_G1W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G1W_SHIFT)
#define GPIO_CTL0_VM_SCR_0_G1W_RANGE                    9:9
#define GPIO_CTL0_VM_SCR_0_G1W_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_G1W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G1W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_G1W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G1W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G1W_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G1W_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL0_VM_SCR_0_G0W_SHIFT                    _MK_SHIFT_CONST(8)
#define GPIO_CTL0_VM_SCR_0_G0W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G0W_SHIFT)
#define GPIO_CTL0_VM_SCR_0_G0W_RANGE                    8:8
#define GPIO_CTL0_VM_SCR_0_G0W_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_G0W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G0W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_G0W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G0W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G0W_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G0W_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL0_VM_SCR_0_G7R_SHIFT                    _MK_SHIFT_CONST(7)
#define GPIO_CTL0_VM_SCR_0_G7R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G7R_SHIFT)
#define GPIO_CTL0_VM_SCR_0_G7R_RANGE                    7:7
#define GPIO_CTL0_VM_SCR_0_G7R_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_G7R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G7R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_G7R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G7R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G7R_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G7R_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL0_VM_SCR_0_G6R_SHIFT                    _MK_SHIFT_CONST(6)
#define GPIO_CTL0_VM_SCR_0_G6R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G6R_SHIFT)
#define GPIO_CTL0_VM_SCR_0_G6R_RANGE                    6:6
#define GPIO_CTL0_VM_SCR_0_G6R_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_G6R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G6R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_G6R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G6R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G6R_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G6R_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL0_VM_SCR_0_G5R_SHIFT                    _MK_SHIFT_CONST(5)
#define GPIO_CTL0_VM_SCR_0_G5R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G5R_SHIFT)
#define GPIO_CTL0_VM_SCR_0_G5R_RANGE                    5:5
#define GPIO_CTL0_VM_SCR_0_G5R_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_G5R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G5R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_G5R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G5R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G5R_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G5R_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL0_VM_SCR_0_G4R_SHIFT                    _MK_SHIFT_CONST(4)
#define GPIO_CTL0_VM_SCR_0_G4R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G4R_SHIFT)
#define GPIO_CTL0_VM_SCR_0_G4R_RANGE                    4:4
#define GPIO_CTL0_VM_SCR_0_G4R_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_G4R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G4R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_G4R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G4R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G4R_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G4R_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL0_VM_SCR_0_G3R_SHIFT                    _MK_SHIFT_CONST(3)
#define GPIO_CTL0_VM_SCR_0_G3R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G3R_SHIFT)
#define GPIO_CTL0_VM_SCR_0_G3R_RANGE                    3:3
#define GPIO_CTL0_VM_SCR_0_G3R_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_G3R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G3R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_G3R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G3R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G3R_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G3R_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL0_VM_SCR_0_G2R_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_CTL0_VM_SCR_0_G2R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G2R_SHIFT)
#define GPIO_CTL0_VM_SCR_0_G2R_RANGE                    2:2
#define GPIO_CTL0_VM_SCR_0_G2R_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_G2R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G2R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_G2R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G2R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G2R_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G2R_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL0_VM_SCR_0_G1R_SHIFT                    _MK_SHIFT_CONST(1)
#define GPIO_CTL0_VM_SCR_0_G1R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G1R_SHIFT)
#define GPIO_CTL0_VM_SCR_0_G1R_RANGE                    1:1
#define GPIO_CTL0_VM_SCR_0_G1R_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_G1R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G1R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_G1R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G1R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G1R_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G1R_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL0_VM_SCR_0_G0R_SHIFT                    _MK_SHIFT_CONST(0)
#define GPIO_CTL0_VM_SCR_0_G0R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G0R_SHIFT)
#define GPIO_CTL0_VM_SCR_0_G0R_RANGE                    0:0
#define GPIO_CTL0_VM_SCR_0_G0R_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_G0R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G0R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_G0R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G0R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G0R_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G0R_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0                     _MK_ADDR_CONST(0x804)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SECURE                      0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_DUAL                        0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SCR                         0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_WORD_COUNT                  0x1
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_RESET_MASK                  _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_READ_MASK                   _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_WRITE_MASK                  _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SHIFT                       _MK_SHIFT_CONST(29)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_RANGE                       29:29
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_WOFFSET                     0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SHIFT                       _MK_SHIFT_CONST(28)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_RANGE                       28:28
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_WOFFSET                     0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SHIFT                       _MK_SHIFT_CONST(27)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_RANGE                       27:27
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_WOFFSET                     0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SHIFT                     _MK_SHIFT_CONST(24)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_FIELD                     _MK_FIELD_CONST(0x7, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_RANGE                     26:24
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_WOFFSET                   0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR7_SHIFT                   _MK_SHIFT_CONST(23)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR7_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR7_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR7_RANGE                   23:23
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR7_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR7_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR7_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR7_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR7_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR7_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR7_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR6_SHIFT                   _MK_SHIFT_CONST(22)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR6_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR6_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR6_RANGE                   22:22
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR6_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR6_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR6_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR6_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR6_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR6_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR6_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR5_SHIFT                   _MK_SHIFT_CONST(21)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR5_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR5_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR5_RANGE                   21:21
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR5_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR5_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR5_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR5_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR5_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR5_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR5_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR4_SHIFT                   _MK_SHIFT_CONST(20)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR4_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR4_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR4_RANGE                   20:20
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR4_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR4_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR4_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR4_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR4_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR3_SHIFT                   _MK_SHIFT_CONST(19)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR3_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR3_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR3_RANGE                   19:19
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR3_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR3_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR3_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR3_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR2_SHIFT                   _MK_SHIFT_CONST(18)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR2_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR2_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR2_RANGE                   18:18
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR2_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR2_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR2_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR2_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR1_SHIFT                   _MK_SHIFT_CONST(17)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR1_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR1_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR1_RANGE                   17:17
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR1_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR1_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR1_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR1_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR0_SHIFT                   _MK_SHIFT_CONST(16)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR0_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR0_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR0_RANGE                   16:16
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR0_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR0_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR0_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR0_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7W_SHIFT                   _MK_SHIFT_CONST(15)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7W_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7W_RANGE                   15:15
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7W_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6W_SHIFT                   _MK_SHIFT_CONST(14)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6W_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6W_RANGE                   14:14
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6W_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5W_SHIFT                   _MK_SHIFT_CONST(13)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5W_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5W_RANGE                   13:13
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5W_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4W_SHIFT                   _MK_SHIFT_CONST(12)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4W_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4W_RANGE                   12:12
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4W_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3W_SHIFT                   _MK_SHIFT_CONST(11)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3W_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3W_RANGE                   11:11
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3W_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2W_SHIFT                   _MK_SHIFT_CONST(10)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2W_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2W_RANGE                   10:10
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2W_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1W_SHIFT                   _MK_SHIFT_CONST(9)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1W_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1W_RANGE                   9:9
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1W_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0W_SHIFT                   _MK_SHIFT_CONST(8)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0W_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0W_RANGE                   8:8
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0W_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7R_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7R_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7R_RANGE                   7:7
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7R_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6R_SHIFT                   _MK_SHIFT_CONST(6)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6R_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6R_RANGE                   6:6
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6R_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5R_SHIFT                   _MK_SHIFT_CONST(5)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5R_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5R_RANGE                   5:5
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5R_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4R_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4R_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4R_RANGE                   4:4
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4R_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3R_SHIFT                   _MK_SHIFT_CONST(3)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3R_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3R_RANGE                   3:3
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3R_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2R_SHIFT                   _MK_SHIFT_CONST(2)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2R_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2R_RANGE                   2:2
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2R_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1R_SHIFT                   _MK_SHIFT_CONST(1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1R_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1R_RANGE                   1:1
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1R_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0R_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0R_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0R_RANGE                   0:0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0R_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_CTL0_INTERRUPT_STATUS_VM_0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0                 _MK_ADDR_CONST(0x808)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_SECURE                  0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_DUAL                    0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_SCR                     GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_WORD_COUNT                      0x1
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_RESET_MASK                      _MK_MASK_CONST(0xff)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_READ_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_FIELD                  _MK_FIELD_CONST(0xff, GPIO_CTL0_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_RANGE                  7:0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_WOFFSET                        0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register GPIO_CTL0_SCR_0
#define GPIO_CTL0_SCR_0                 _MK_ADDR_CONST(0x80c)
#define GPIO_CTL0_SCR_0_SECURE                  0x0
#define GPIO_CTL0_SCR_0_DUAL                    0x0
#define GPIO_CTL0_SCR_0_SCR                     0
#define GPIO_CTL0_SCR_0_WORD_COUNT                      0x1
#define GPIO_CTL0_SCR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL0_SCR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL0_SCR_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL0_SCR_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_CTL0_SCR_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_SEC_LCK_SHIFT)
#define GPIO_CTL0_SCR_0_SEC_LCK_RANGE                   29:29
#define GPIO_CTL0_SCR_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_CTL0_SCR_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL0_SCR_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_CTL0_SCR_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_SEC_WEN_SHIFT)
#define GPIO_CTL0_SCR_0_SEC_WEN_RANGE                   28:28
#define GPIO_CTL0_SCR_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_CTL0_SCR_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL0_SCR_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_CTL0_SCR_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_SEC_REN_SHIFT)
#define GPIO_CTL0_SCR_0_SEC_REN_RANGE                   27:27
#define GPIO_CTL0_SCR_0_SEC_REN_WOFFSET                 0x0
#define GPIO_CTL0_SCR_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL0_SCR_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_CTL0_SCR_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_CTL0_SCR_0_SEC_OWNER_SHIFT)
#define GPIO_CTL0_SCR_0_SEC_OWNER_RANGE                 26:24
#define GPIO_CTL0_SCR_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_CTL0_SCR_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_CTL0_SCR_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_CTL0_SCR_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_CTL0_SCR_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_PR7_SHIFT)
#define GPIO_CTL0_SCR_0_PR7_RANGE                       23:23
#define GPIO_CTL0_SCR_0_PR7_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL0_SCR_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_CTL0_SCR_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_PR6_SHIFT)
#define GPIO_CTL0_SCR_0_PR6_RANGE                       22:22
#define GPIO_CTL0_SCR_0_PR6_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL0_SCR_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_CTL0_SCR_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_PR5_SHIFT)
#define GPIO_CTL0_SCR_0_PR5_RANGE                       21:21
#define GPIO_CTL0_SCR_0_PR5_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL0_SCR_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_CTL0_SCR_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_PR4_SHIFT)
#define GPIO_CTL0_SCR_0_PR4_RANGE                       20:20
#define GPIO_CTL0_SCR_0_PR4_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL0_SCR_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_CTL0_SCR_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_PR3_SHIFT)
#define GPIO_CTL0_SCR_0_PR3_RANGE                       19:19
#define GPIO_CTL0_SCR_0_PR3_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL0_SCR_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_CTL0_SCR_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_PR2_SHIFT)
#define GPIO_CTL0_SCR_0_PR2_RANGE                       18:18
#define GPIO_CTL0_SCR_0_PR2_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL0_SCR_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_CTL0_SCR_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_PR1_SHIFT)
#define GPIO_CTL0_SCR_0_PR1_RANGE                       17:17
#define GPIO_CTL0_SCR_0_PR1_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL0_SCR_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_CTL0_SCR_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_PR0_SHIFT)
#define GPIO_CTL0_SCR_0_PR0_RANGE                       16:16
#define GPIO_CTL0_SCR_0_PR0_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL0_SCR_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_CTL0_SCR_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G7W_SHIFT)
#define GPIO_CTL0_SCR_0_G7W_RANGE                       15:15
#define GPIO_CTL0_SCR_0_G7W_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL0_SCR_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_CTL0_SCR_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G6W_SHIFT)
#define GPIO_CTL0_SCR_0_G6W_RANGE                       14:14
#define GPIO_CTL0_SCR_0_G6W_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL0_SCR_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_CTL0_SCR_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G5W_SHIFT)
#define GPIO_CTL0_SCR_0_G5W_RANGE                       13:13
#define GPIO_CTL0_SCR_0_G5W_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL0_SCR_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_CTL0_SCR_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G4W_SHIFT)
#define GPIO_CTL0_SCR_0_G4W_RANGE                       12:12
#define GPIO_CTL0_SCR_0_G4W_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL0_SCR_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_CTL0_SCR_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G3W_SHIFT)
#define GPIO_CTL0_SCR_0_G3W_RANGE                       11:11
#define GPIO_CTL0_SCR_0_G3W_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL0_SCR_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_CTL0_SCR_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G2W_SHIFT)
#define GPIO_CTL0_SCR_0_G2W_RANGE                       10:10
#define GPIO_CTL0_SCR_0_G2W_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL0_SCR_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_CTL0_SCR_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G1W_SHIFT)
#define GPIO_CTL0_SCR_0_G1W_RANGE                       9:9
#define GPIO_CTL0_SCR_0_G1W_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL0_SCR_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_CTL0_SCR_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G0W_SHIFT)
#define GPIO_CTL0_SCR_0_G0W_RANGE                       8:8
#define GPIO_CTL0_SCR_0_G0W_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL0_SCR_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_CTL0_SCR_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G7R_SHIFT)
#define GPIO_CTL0_SCR_0_G7R_RANGE                       7:7
#define GPIO_CTL0_SCR_0_G7R_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL0_SCR_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_CTL0_SCR_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G6R_SHIFT)
#define GPIO_CTL0_SCR_0_G6R_RANGE                       6:6
#define GPIO_CTL0_SCR_0_G6R_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL0_SCR_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_CTL0_SCR_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G5R_SHIFT)
#define GPIO_CTL0_SCR_0_G5R_RANGE                       5:5
#define GPIO_CTL0_SCR_0_G5R_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL0_SCR_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_CTL0_SCR_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G4R_SHIFT)
#define GPIO_CTL0_SCR_0_G4R_RANGE                       4:4
#define GPIO_CTL0_SCR_0_G4R_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL0_SCR_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_CTL0_SCR_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G3R_SHIFT)
#define GPIO_CTL0_SCR_0_G3R_RANGE                       3:3
#define GPIO_CTL0_SCR_0_G3R_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL0_SCR_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_CTL0_SCR_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G2R_SHIFT)
#define GPIO_CTL0_SCR_0_G2R_RANGE                       2:2
#define GPIO_CTL0_SCR_0_G2R_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL0_SCR_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_CTL0_SCR_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G1R_SHIFT)
#define GPIO_CTL0_SCR_0_G1R_RANGE                       1:1
#define GPIO_CTL0_SCR_0_G1R_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL0_SCR_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_CTL0_SCR_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G0R_SHIFT)
#define GPIO_CTL0_SCR_0_G0R_RANGE                       0:0
#define GPIO_CTL0_SCR_0_G0R_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_CTL0_ICG_EN_OVERRIDE_0
#define GPIO_CTL0_ICG_EN_OVERRIDE_0                     _MK_ADDR_CONST(0x810)
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_SECURE                      0x0
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_DUAL                        0x0
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_SCR                         GPIO_CTL0_SCR_0
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_WORD_COUNT                  0x1
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_FIELD                  _MK_FIELD_CONST(0x1, GPIO_CTL0_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SHIFT)
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_RANGE                  0:0
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_WOFFSET                        0x0
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register GPIO_GG_INT0_ROUTE_MAPPING_0
#define GPIO_GG_INT0_ROUTE_MAPPING_0                    _MK_ADDR_CONST(0x814)
#define GPIO_GG_INT0_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_GG_INT0_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_GG_INT0_ROUTE_MAPPING_0_SCR                        GPIO_CTL0_SCR_0
#define GPIO_GG_INT0_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_GG_INT0_ROUTE_MAPPING_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_GG_INT0_ROUTE_MAPPING_0_RESET_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_GG_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_GG_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_INT0_ROUTE_MAPPING_0_READ_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_GG_INT0_ROUTE_MAPPING_0_WRITE_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_GG_INT0_ROUTE_MAPPING_0_VAL_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_GG_INT0_ROUTE_MAPPING_0_VAL_FIELD                  _MK_FIELD_CONST(0x3, GPIO_GG_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_GG_INT0_ROUTE_MAPPING_0_VAL_RANGE                  1:0
#define GPIO_GG_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_GG_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_GG_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define GPIO_GG_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_GG_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_GG_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_GG_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register GPIO_GG_INT1_ROUTE_MAPPING_0
#define GPIO_GG_INT1_ROUTE_MAPPING_0                    _MK_ADDR_CONST(0x818)
#define GPIO_GG_INT1_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_GG_INT1_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_GG_INT1_ROUTE_MAPPING_0_SCR                        GPIO_CTL0_SCR_0
#define GPIO_GG_INT1_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_GG_INT1_ROUTE_MAPPING_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_GG_INT1_ROUTE_MAPPING_0_RESET_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_GG_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_GG_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_INT1_ROUTE_MAPPING_0_READ_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_GG_INT1_ROUTE_MAPPING_0_WRITE_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_GG_INT1_ROUTE_MAPPING_0_VAL_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_GG_INT1_ROUTE_MAPPING_0_VAL_FIELD                  _MK_FIELD_CONST(0x3, GPIO_GG_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_GG_INT1_ROUTE_MAPPING_0_VAL_RANGE                  1:0
#define GPIO_GG_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_GG_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_GG_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define GPIO_GG_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_GG_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_GG_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_GG_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register GPIO_GG_INT2_ROUTE_MAPPING_0
#define GPIO_GG_INT2_ROUTE_MAPPING_0                    _MK_ADDR_CONST(0x81c)
#define GPIO_GG_INT2_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_GG_INT2_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_GG_INT2_ROUTE_MAPPING_0_SCR                        GPIO_CTL0_SCR_0
#define GPIO_GG_INT2_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_GG_INT2_ROUTE_MAPPING_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_GG_INT2_ROUTE_MAPPING_0_RESET_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_GG_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_GG_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_INT2_ROUTE_MAPPING_0_READ_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_GG_INT2_ROUTE_MAPPING_0_WRITE_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_GG_INT2_ROUTE_MAPPING_0_VAL_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_GG_INT2_ROUTE_MAPPING_0_VAL_FIELD                  _MK_FIELD_CONST(0x3, GPIO_GG_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_GG_INT2_ROUTE_MAPPING_0_VAL_RANGE                  1:0
#define GPIO_GG_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_GG_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_GG_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define GPIO_GG_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_GG_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_GG_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_GG_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register GPIO_GG_INT3_ROUTE_MAPPING_0
#define GPIO_GG_INT3_ROUTE_MAPPING_0                    _MK_ADDR_CONST(0x820)
#define GPIO_GG_INT3_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_GG_INT3_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_GG_INT3_ROUTE_MAPPING_0_SCR                        GPIO_CTL0_SCR_0
#define GPIO_GG_INT3_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_GG_INT3_ROUTE_MAPPING_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_GG_INT3_ROUTE_MAPPING_0_RESET_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_GG_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_GG_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_INT3_ROUTE_MAPPING_0_READ_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_GG_INT3_ROUTE_MAPPING_0_WRITE_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_GG_INT3_ROUTE_MAPPING_0_VAL_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_GG_INT3_ROUTE_MAPPING_0_VAL_FIELD                  _MK_FIELD_CONST(0x3, GPIO_GG_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_GG_INT3_ROUTE_MAPPING_0_VAL_RANGE                  1:0
#define GPIO_GG_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_GG_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_GG_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define GPIO_GG_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_GG_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_GG_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_GG_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register GPIO_GG_INT4_ROUTE_MAPPING_0
#define GPIO_GG_INT4_ROUTE_MAPPING_0                    _MK_ADDR_CONST(0x824)
#define GPIO_GG_INT4_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_GG_INT4_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_GG_INT4_ROUTE_MAPPING_0_SCR                        GPIO_CTL0_SCR_0
#define GPIO_GG_INT4_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_GG_INT4_ROUTE_MAPPING_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_GG_INT4_ROUTE_MAPPING_0_RESET_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_GG_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_GG_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_INT4_ROUTE_MAPPING_0_READ_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_GG_INT4_ROUTE_MAPPING_0_WRITE_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_GG_INT4_ROUTE_MAPPING_0_VAL_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_GG_INT4_ROUTE_MAPPING_0_VAL_FIELD                  _MK_FIELD_CONST(0x3, GPIO_GG_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_GG_INT4_ROUTE_MAPPING_0_VAL_RANGE                  1:0
#define GPIO_GG_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_GG_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_GG_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define GPIO_GG_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_GG_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_GG_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_GG_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register GPIO_GG_INT5_ROUTE_MAPPING_0
#define GPIO_GG_INT5_ROUTE_MAPPING_0                    _MK_ADDR_CONST(0x828)
#define GPIO_GG_INT5_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_GG_INT5_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_GG_INT5_ROUTE_MAPPING_0_SCR                        GPIO_CTL0_SCR_0
#define GPIO_GG_INT5_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_GG_INT5_ROUTE_MAPPING_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_GG_INT5_ROUTE_MAPPING_0_RESET_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_GG_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_GG_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_INT5_ROUTE_MAPPING_0_READ_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_GG_INT5_ROUTE_MAPPING_0_WRITE_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_GG_INT5_ROUTE_MAPPING_0_VAL_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_GG_INT5_ROUTE_MAPPING_0_VAL_FIELD                  _MK_FIELD_CONST(0x3, GPIO_GG_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_GG_INT5_ROUTE_MAPPING_0_VAL_RANGE                  1:0
#define GPIO_GG_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_GG_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_GG_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define GPIO_GG_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_GG_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_GG_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_GG_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register GPIO_GG_INT6_ROUTE_MAPPING_0
#define GPIO_GG_INT6_ROUTE_MAPPING_0                    _MK_ADDR_CONST(0x82c)
#define GPIO_GG_INT6_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_GG_INT6_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_GG_INT6_ROUTE_MAPPING_0_SCR                        GPIO_CTL0_SCR_0
#define GPIO_GG_INT6_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_GG_INT6_ROUTE_MAPPING_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_GG_INT6_ROUTE_MAPPING_0_RESET_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_GG_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_GG_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_INT6_ROUTE_MAPPING_0_READ_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_GG_INT6_ROUTE_MAPPING_0_WRITE_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_GG_INT6_ROUTE_MAPPING_0_VAL_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_GG_INT6_ROUTE_MAPPING_0_VAL_FIELD                  _MK_FIELD_CONST(0x3, GPIO_GG_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_GG_INT6_ROUTE_MAPPING_0_VAL_RANGE                  1:0
#define GPIO_GG_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_GG_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_GG_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define GPIO_GG_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_GG_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_GG_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_GG_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register GPIO_GG_INT7_ROUTE_MAPPING_0
#define GPIO_GG_INT7_ROUTE_MAPPING_0                    _MK_ADDR_CONST(0x830)
#define GPIO_GG_INT7_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_GG_INT7_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_GG_INT7_ROUTE_MAPPING_0_SCR                        GPIO_CTL0_SCR_0
#define GPIO_GG_INT7_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_GG_INT7_ROUTE_MAPPING_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_GG_INT7_ROUTE_MAPPING_0_RESET_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_GG_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_GG_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_INT7_ROUTE_MAPPING_0_READ_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_GG_INT7_ROUTE_MAPPING_0_WRITE_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_GG_INT7_ROUTE_MAPPING_0_VAL_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_GG_INT7_ROUTE_MAPPING_0_VAL_FIELD                  _MK_FIELD_CONST(0x3, GPIO_GG_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_GG_INT7_ROUTE_MAPPING_0_VAL_RANGE                  1:0
#define GPIO_GG_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_GG_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_GG_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define GPIO_GG_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_GG_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_GG_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_GG_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register GPIO_CTL0_SPARE_0
#define GPIO_CTL0_SPARE_0                       _MK_ADDR_CONST(0x834)
#define GPIO_CTL0_SPARE_0_SECURE                        0x0
#define GPIO_CTL0_SPARE_0_DUAL                  0x0
#define GPIO_CTL0_SPARE_0_SCR                   0
#define GPIO_CTL0_SPARE_0_WORD_COUNT                    0x1
#define GPIO_CTL0_SPARE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SPARE_0_RESET_MASK                    _MK_MASK_CONST(0xffff)
#define GPIO_CTL0_SPARE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SPARE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SPARE_0_READ_MASK                     _MK_MASK_CONST(0xffff)
#define GPIO_CTL0_SPARE_0_WRITE_MASK                    _MK_MASK_CONST(0xffff)
#define GPIO_CTL0_SPARE_0_SPARE_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_CTL0_SPARE_0_SPARE_FIELD                   _MK_FIELD_CONST(0xffff, GPIO_CTL0_SPARE_0_SPARE_SHIFT)
#define GPIO_CTL0_SPARE_0_SPARE_RANGE                   15:0
#define GPIO_CTL0_SPARE_0_SPARE_WOFFSET                 0x0
#define GPIO_CTL0_SPARE_0_SPARE_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SPARE_0_SPARE_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define GPIO_CTL0_SPARE_0_SPARE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SPARE_0_SPARE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SPARE_0_SPARE_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL0_SPARE_0_SPARE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_V_VM_00_0
#define GPIO_V_VM_00_0                  _MK_ADDR_CONST(0x1000)
#define GPIO_V_VM_00_0_SECURE                   0x0
#define GPIO_V_VM_00_0_DUAL                     0x0
#define GPIO_V_VM_00_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_V_VM_00_0_WORD_COUNT                       0x1
#define GPIO_V_VM_00_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_V_VM_00_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_V_VM_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_V_VM_00_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_V_VM_00_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_V_VM_00_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_V_VM_00_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_00_0_VM1_SHIFT)
#define GPIO_V_VM_00_0_VM1_RANGE                        1:0
#define GPIO_V_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_V_VM_00_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_00_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_00_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_00_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_00_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_00_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_00_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_V_VM_00_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_00_0_VM2_SHIFT)
#define GPIO_V_VM_00_0_VM2_RANGE                        3:2
#define GPIO_V_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_V_VM_00_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_00_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_00_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_00_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_00_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_00_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_00_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_V_VM_00_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_00_0_VM3_SHIFT)
#define GPIO_V_VM_00_0_VM3_RANGE                        5:4
#define GPIO_V_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_V_VM_00_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_00_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_00_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_00_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_00_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_00_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_00_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_V_VM_00_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_00_0_VM4_SHIFT)
#define GPIO_V_VM_00_0_VM4_RANGE                        7:6
#define GPIO_V_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_V_VM_00_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_00_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_00_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_00_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_00_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_00_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_00_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_V_VM_00_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_00_0_VM5_SHIFT)
#define GPIO_V_VM_00_0_VM5_RANGE                        9:8
#define GPIO_V_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_V_VM_00_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_00_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_00_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_00_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_00_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_00_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_00_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_V_VM_00_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_00_0_VM6_SHIFT)
#define GPIO_V_VM_00_0_VM6_RANGE                        11:10
#define GPIO_V_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_V_VM_00_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_00_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_00_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_00_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_00_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_00_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_00_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_V_VM_00_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_00_0_VM7_SHIFT)
#define GPIO_V_VM_00_0_VM7_RANGE                        13:12
#define GPIO_V_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_V_VM_00_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_00_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_00_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_00_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_00_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_00_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_00_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_V_VM_00_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_00_0_VM8_SHIFT)
#define GPIO_V_VM_00_0_VM8_RANGE                        15:14
#define GPIO_V_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_V_VM_00_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_00_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_00_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_00_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_00_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_00_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_V_SCR_00_0
#define GPIO_V_SCR_00_0                 _MK_ADDR_CONST(0x1004)
#define GPIO_V_SCR_00_0_SECURE                  0x0
#define GPIO_V_SCR_00_0_DUAL                    0x0
#define GPIO_V_SCR_00_0_SCR                     0
#define GPIO_V_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_V_SCR_00_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_V_SCR_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_V_SCR_00_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_V_SCR_00_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_V_SCR_00_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_V_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_V_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_V_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_V_SCR_00_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_00_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_00_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_V_SCR_00_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_V_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_V_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_V_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_V_SCR_00_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_00_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_00_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_V_SCR_00_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_V_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_V_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_V_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_V_SCR_00_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_00_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_00_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_V_SCR_00_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_V_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_V_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_V_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_V_SCR_00_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_V_SCR_00_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_00_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_V_SCR_00_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_00_0_PR7_SHIFT)
#define GPIO_V_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_V_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_V_SCR_00_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_00_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_00_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_V_SCR_00_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_00_0_PR6_SHIFT)
#define GPIO_V_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_V_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_V_SCR_00_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_00_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_00_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_V_SCR_00_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_00_0_PR5_SHIFT)
#define GPIO_V_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_V_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_V_SCR_00_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_00_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_00_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_V_SCR_00_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_00_0_PR4_SHIFT)
#define GPIO_V_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_V_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_V_SCR_00_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_00_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_00_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_V_SCR_00_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_00_0_PR3_SHIFT)
#define GPIO_V_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_V_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_V_SCR_00_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_00_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_00_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_V_SCR_00_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_00_0_PR2_SHIFT)
#define GPIO_V_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_V_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_V_SCR_00_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_00_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_00_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_V_SCR_00_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_00_0_PR1_SHIFT)
#define GPIO_V_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_V_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_V_SCR_00_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_00_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_00_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_V_SCR_00_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_00_0_PR0_SHIFT)
#define GPIO_V_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_V_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_V_SCR_00_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_00_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_00_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_V_SCR_00_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_00_0_G7W_SHIFT)
#define GPIO_V_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_V_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_V_SCR_00_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_00_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_00_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_V_SCR_00_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_00_0_G6W_SHIFT)
#define GPIO_V_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_V_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_V_SCR_00_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_00_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_00_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_V_SCR_00_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_00_0_G5W_SHIFT)
#define GPIO_V_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_V_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_V_SCR_00_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_00_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_00_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_V_SCR_00_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_00_0_G4W_SHIFT)
#define GPIO_V_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_V_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_V_SCR_00_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_00_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_00_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_V_SCR_00_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_00_0_G3W_SHIFT)
#define GPIO_V_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_V_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_V_SCR_00_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_00_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_00_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_V_SCR_00_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_00_0_G2W_SHIFT)
#define GPIO_V_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_V_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_V_SCR_00_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_00_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_00_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_V_SCR_00_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_00_0_G1W_SHIFT)
#define GPIO_V_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_V_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_V_SCR_00_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_00_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_00_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_V_SCR_00_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_00_0_G0W_SHIFT)
#define GPIO_V_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_V_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_V_SCR_00_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_00_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_00_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_V_SCR_00_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_00_0_G7R_SHIFT)
#define GPIO_V_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_V_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_V_SCR_00_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_00_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_00_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_V_SCR_00_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_00_0_G6R_SHIFT)
#define GPIO_V_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_V_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_V_SCR_00_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_00_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_00_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_V_SCR_00_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_00_0_G5R_SHIFT)
#define GPIO_V_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_V_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_V_SCR_00_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_00_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_00_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_V_SCR_00_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_00_0_G4R_SHIFT)
#define GPIO_V_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_V_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_V_SCR_00_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_00_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_00_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_V_SCR_00_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_00_0_G3R_SHIFT)
#define GPIO_V_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_V_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_V_SCR_00_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_00_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_00_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_V_SCR_00_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_00_0_G2R_SHIFT)
#define GPIO_V_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_V_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_V_SCR_00_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_00_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_00_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_V_SCR_00_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_00_0_G1R_SHIFT)
#define GPIO_V_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_V_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_V_SCR_00_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_00_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_00_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_V_SCR_00_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_00_0_G0R_SHIFT)
#define GPIO_V_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_V_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_V_SCR_00_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_00_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_00_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_V_VM_01_0
#define GPIO_V_VM_01_0                  _MK_ADDR_CONST(0x1008)
#define GPIO_V_VM_01_0_SECURE                   0x0
#define GPIO_V_VM_01_0_DUAL                     0x0
#define GPIO_V_VM_01_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_V_VM_01_0_WORD_COUNT                       0x1
#define GPIO_V_VM_01_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_V_VM_01_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_V_VM_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_V_VM_01_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_V_VM_01_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_V_VM_01_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_V_VM_01_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_01_0_VM1_SHIFT)
#define GPIO_V_VM_01_0_VM1_RANGE                        1:0
#define GPIO_V_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_V_VM_01_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_01_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_01_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_01_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_01_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_01_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_01_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_V_VM_01_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_01_0_VM2_SHIFT)
#define GPIO_V_VM_01_0_VM2_RANGE                        3:2
#define GPIO_V_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_V_VM_01_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_01_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_01_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_01_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_01_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_01_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_01_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_V_VM_01_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_01_0_VM3_SHIFT)
#define GPIO_V_VM_01_0_VM3_RANGE                        5:4
#define GPIO_V_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_V_VM_01_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_01_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_01_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_01_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_01_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_01_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_01_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_V_VM_01_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_01_0_VM4_SHIFT)
#define GPIO_V_VM_01_0_VM4_RANGE                        7:6
#define GPIO_V_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_V_VM_01_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_01_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_01_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_01_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_01_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_01_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_01_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_V_VM_01_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_01_0_VM5_SHIFT)
#define GPIO_V_VM_01_0_VM5_RANGE                        9:8
#define GPIO_V_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_V_VM_01_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_01_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_01_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_01_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_01_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_01_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_01_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_V_VM_01_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_01_0_VM6_SHIFT)
#define GPIO_V_VM_01_0_VM6_RANGE                        11:10
#define GPIO_V_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_V_VM_01_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_01_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_01_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_01_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_01_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_01_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_01_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_V_VM_01_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_01_0_VM7_SHIFT)
#define GPIO_V_VM_01_0_VM7_RANGE                        13:12
#define GPIO_V_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_V_VM_01_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_01_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_01_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_01_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_01_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_01_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_01_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_V_VM_01_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_01_0_VM8_SHIFT)
#define GPIO_V_VM_01_0_VM8_RANGE                        15:14
#define GPIO_V_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_V_VM_01_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_01_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_01_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_01_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_01_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_01_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_V_SCR_01_0
#define GPIO_V_SCR_01_0                 _MK_ADDR_CONST(0x100c)
#define GPIO_V_SCR_01_0_SECURE                  0x0
#define GPIO_V_SCR_01_0_DUAL                    0x0
#define GPIO_V_SCR_01_0_SCR                     0
#define GPIO_V_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_V_SCR_01_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_V_SCR_01_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_V_SCR_01_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_V_SCR_01_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_V_SCR_01_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_V_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_V_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_V_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_V_SCR_01_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_01_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_01_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_V_SCR_01_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_V_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_V_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_V_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_V_SCR_01_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_01_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_01_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_V_SCR_01_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_V_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_V_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_V_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_V_SCR_01_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_01_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_01_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_V_SCR_01_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_V_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_V_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_V_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_V_SCR_01_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_V_SCR_01_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_01_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_V_SCR_01_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_01_0_PR7_SHIFT)
#define GPIO_V_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_V_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_V_SCR_01_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_01_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_01_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_V_SCR_01_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_01_0_PR6_SHIFT)
#define GPIO_V_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_V_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_V_SCR_01_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_01_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_01_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_V_SCR_01_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_01_0_PR5_SHIFT)
#define GPIO_V_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_V_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_V_SCR_01_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_01_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_01_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_V_SCR_01_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_01_0_PR4_SHIFT)
#define GPIO_V_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_V_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_V_SCR_01_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_01_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_01_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_V_SCR_01_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_01_0_PR3_SHIFT)
#define GPIO_V_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_V_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_V_SCR_01_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_01_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_01_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_V_SCR_01_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_01_0_PR2_SHIFT)
#define GPIO_V_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_V_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_V_SCR_01_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_01_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_01_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_V_SCR_01_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_01_0_PR1_SHIFT)
#define GPIO_V_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_V_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_V_SCR_01_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_01_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_01_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_V_SCR_01_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_01_0_PR0_SHIFT)
#define GPIO_V_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_V_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_V_SCR_01_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_01_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_01_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_V_SCR_01_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_01_0_G7W_SHIFT)
#define GPIO_V_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_V_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_V_SCR_01_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_01_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_01_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_V_SCR_01_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_01_0_G6W_SHIFT)
#define GPIO_V_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_V_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_V_SCR_01_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_01_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_01_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_V_SCR_01_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_01_0_G5W_SHIFT)
#define GPIO_V_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_V_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_V_SCR_01_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_01_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_01_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_V_SCR_01_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_01_0_G4W_SHIFT)
#define GPIO_V_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_V_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_V_SCR_01_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_01_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_01_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_V_SCR_01_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_01_0_G3W_SHIFT)
#define GPIO_V_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_V_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_V_SCR_01_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_01_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_01_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_V_SCR_01_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_01_0_G2W_SHIFT)
#define GPIO_V_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_V_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_V_SCR_01_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_01_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_01_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_V_SCR_01_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_01_0_G1W_SHIFT)
#define GPIO_V_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_V_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_V_SCR_01_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_01_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_01_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_V_SCR_01_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_01_0_G0W_SHIFT)
#define GPIO_V_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_V_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_V_SCR_01_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_01_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_01_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_V_SCR_01_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_01_0_G7R_SHIFT)
#define GPIO_V_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_V_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_V_SCR_01_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_01_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_01_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_V_SCR_01_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_01_0_G6R_SHIFT)
#define GPIO_V_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_V_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_V_SCR_01_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_01_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_01_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_V_SCR_01_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_01_0_G5R_SHIFT)
#define GPIO_V_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_V_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_V_SCR_01_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_01_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_01_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_V_SCR_01_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_01_0_G4R_SHIFT)
#define GPIO_V_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_V_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_V_SCR_01_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_01_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_01_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_V_SCR_01_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_01_0_G3R_SHIFT)
#define GPIO_V_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_V_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_V_SCR_01_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_01_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_01_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_V_SCR_01_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_01_0_G2R_SHIFT)
#define GPIO_V_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_V_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_V_SCR_01_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_01_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_01_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_V_SCR_01_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_01_0_G1R_SHIFT)
#define GPIO_V_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_V_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_V_SCR_01_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_01_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_01_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_V_SCR_01_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_01_0_G0R_SHIFT)
#define GPIO_V_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_V_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_V_SCR_01_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_01_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_01_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_V_VM_02_0
#define GPIO_V_VM_02_0                  _MK_ADDR_CONST(0x1010)
#define GPIO_V_VM_02_0_SECURE                   0x0
#define GPIO_V_VM_02_0_DUAL                     0x0
#define GPIO_V_VM_02_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_V_VM_02_0_WORD_COUNT                       0x1
#define GPIO_V_VM_02_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_V_VM_02_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_V_VM_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_V_VM_02_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_V_VM_02_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_V_VM_02_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_V_VM_02_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_02_0_VM1_SHIFT)
#define GPIO_V_VM_02_0_VM1_RANGE                        1:0
#define GPIO_V_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_V_VM_02_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_02_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_02_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_02_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_02_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_02_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_02_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_V_VM_02_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_02_0_VM2_SHIFT)
#define GPIO_V_VM_02_0_VM2_RANGE                        3:2
#define GPIO_V_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_V_VM_02_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_02_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_02_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_02_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_02_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_02_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_02_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_V_VM_02_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_02_0_VM3_SHIFT)
#define GPIO_V_VM_02_0_VM3_RANGE                        5:4
#define GPIO_V_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_V_VM_02_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_02_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_02_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_02_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_02_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_02_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_02_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_V_VM_02_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_02_0_VM4_SHIFT)
#define GPIO_V_VM_02_0_VM4_RANGE                        7:6
#define GPIO_V_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_V_VM_02_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_02_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_02_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_02_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_02_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_02_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_02_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_V_VM_02_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_02_0_VM5_SHIFT)
#define GPIO_V_VM_02_0_VM5_RANGE                        9:8
#define GPIO_V_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_V_VM_02_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_02_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_02_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_02_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_02_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_02_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_02_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_V_VM_02_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_02_0_VM6_SHIFT)
#define GPIO_V_VM_02_0_VM6_RANGE                        11:10
#define GPIO_V_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_V_VM_02_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_02_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_02_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_02_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_02_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_02_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_02_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_V_VM_02_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_02_0_VM7_SHIFT)
#define GPIO_V_VM_02_0_VM7_RANGE                        13:12
#define GPIO_V_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_V_VM_02_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_02_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_02_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_02_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_02_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_02_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_02_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_V_VM_02_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_02_0_VM8_SHIFT)
#define GPIO_V_VM_02_0_VM8_RANGE                        15:14
#define GPIO_V_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_V_VM_02_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_02_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_02_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_02_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_02_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_02_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_V_SCR_02_0
#define GPIO_V_SCR_02_0                 _MK_ADDR_CONST(0x1014)
#define GPIO_V_SCR_02_0_SECURE                  0x0
#define GPIO_V_SCR_02_0_DUAL                    0x0
#define GPIO_V_SCR_02_0_SCR                     0
#define GPIO_V_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_V_SCR_02_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_V_SCR_02_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_V_SCR_02_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_V_SCR_02_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_V_SCR_02_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_V_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_V_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_V_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_V_SCR_02_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_02_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_02_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_V_SCR_02_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_V_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_V_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_V_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_V_SCR_02_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_02_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_02_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_V_SCR_02_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_V_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_V_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_V_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_V_SCR_02_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_02_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_02_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_V_SCR_02_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_V_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_V_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_V_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_V_SCR_02_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_V_SCR_02_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_02_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_V_SCR_02_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_02_0_PR7_SHIFT)
#define GPIO_V_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_V_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_V_SCR_02_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_02_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_02_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_V_SCR_02_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_02_0_PR6_SHIFT)
#define GPIO_V_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_V_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_V_SCR_02_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_02_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_02_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_V_SCR_02_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_02_0_PR5_SHIFT)
#define GPIO_V_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_V_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_V_SCR_02_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_02_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_02_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_V_SCR_02_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_02_0_PR4_SHIFT)
#define GPIO_V_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_V_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_V_SCR_02_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_02_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_02_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_V_SCR_02_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_02_0_PR3_SHIFT)
#define GPIO_V_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_V_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_V_SCR_02_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_02_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_02_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_V_SCR_02_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_02_0_PR2_SHIFT)
#define GPIO_V_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_V_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_V_SCR_02_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_02_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_02_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_V_SCR_02_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_02_0_PR1_SHIFT)
#define GPIO_V_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_V_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_V_SCR_02_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_02_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_02_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_V_SCR_02_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_02_0_PR0_SHIFT)
#define GPIO_V_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_V_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_V_SCR_02_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_02_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_02_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_V_SCR_02_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_02_0_G7W_SHIFT)
#define GPIO_V_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_V_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_V_SCR_02_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_02_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_02_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_V_SCR_02_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_02_0_G6W_SHIFT)
#define GPIO_V_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_V_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_V_SCR_02_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_02_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_02_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_V_SCR_02_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_02_0_G5W_SHIFT)
#define GPIO_V_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_V_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_V_SCR_02_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_02_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_02_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_V_SCR_02_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_02_0_G4W_SHIFT)
#define GPIO_V_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_V_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_V_SCR_02_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_02_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_02_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_V_SCR_02_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_02_0_G3W_SHIFT)
#define GPIO_V_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_V_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_V_SCR_02_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_02_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_02_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_V_SCR_02_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_02_0_G2W_SHIFT)
#define GPIO_V_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_V_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_V_SCR_02_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_02_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_02_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_V_SCR_02_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_02_0_G1W_SHIFT)
#define GPIO_V_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_V_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_V_SCR_02_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_02_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_02_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_V_SCR_02_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_02_0_G0W_SHIFT)
#define GPIO_V_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_V_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_V_SCR_02_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_02_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_02_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_V_SCR_02_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_02_0_G7R_SHIFT)
#define GPIO_V_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_V_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_V_SCR_02_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_02_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_02_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_V_SCR_02_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_02_0_G6R_SHIFT)
#define GPIO_V_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_V_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_V_SCR_02_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_02_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_02_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_V_SCR_02_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_02_0_G5R_SHIFT)
#define GPIO_V_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_V_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_V_SCR_02_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_02_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_02_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_V_SCR_02_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_02_0_G4R_SHIFT)
#define GPIO_V_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_V_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_V_SCR_02_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_02_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_02_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_V_SCR_02_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_02_0_G3R_SHIFT)
#define GPIO_V_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_V_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_V_SCR_02_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_02_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_02_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_V_SCR_02_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_02_0_G2R_SHIFT)
#define GPIO_V_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_V_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_V_SCR_02_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_02_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_02_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_V_SCR_02_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_02_0_G1R_SHIFT)
#define GPIO_V_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_V_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_V_SCR_02_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_02_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_02_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_V_SCR_02_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_02_0_G0R_SHIFT)
#define GPIO_V_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_V_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_V_SCR_02_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_02_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_02_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_V_VM_03_0
#define GPIO_V_VM_03_0                  _MK_ADDR_CONST(0x1018)
#define GPIO_V_VM_03_0_SECURE                   0x0
#define GPIO_V_VM_03_0_DUAL                     0x0
#define GPIO_V_VM_03_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_V_VM_03_0_WORD_COUNT                       0x1
#define GPIO_V_VM_03_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_V_VM_03_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_V_VM_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_V_VM_03_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_V_VM_03_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_V_VM_03_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_V_VM_03_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_03_0_VM1_SHIFT)
#define GPIO_V_VM_03_0_VM1_RANGE                        1:0
#define GPIO_V_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_V_VM_03_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_03_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_03_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_03_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_03_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_03_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_03_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_V_VM_03_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_03_0_VM2_SHIFT)
#define GPIO_V_VM_03_0_VM2_RANGE                        3:2
#define GPIO_V_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_V_VM_03_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_03_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_03_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_03_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_03_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_03_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_03_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_V_VM_03_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_03_0_VM3_SHIFT)
#define GPIO_V_VM_03_0_VM3_RANGE                        5:4
#define GPIO_V_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_V_VM_03_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_03_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_03_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_03_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_03_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_03_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_03_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_V_VM_03_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_03_0_VM4_SHIFT)
#define GPIO_V_VM_03_0_VM4_RANGE                        7:6
#define GPIO_V_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_V_VM_03_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_03_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_03_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_03_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_03_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_03_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_03_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_V_VM_03_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_03_0_VM5_SHIFT)
#define GPIO_V_VM_03_0_VM5_RANGE                        9:8
#define GPIO_V_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_V_VM_03_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_03_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_03_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_03_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_03_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_03_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_03_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_V_VM_03_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_03_0_VM6_SHIFT)
#define GPIO_V_VM_03_0_VM6_RANGE                        11:10
#define GPIO_V_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_V_VM_03_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_03_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_03_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_03_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_03_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_03_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_03_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_V_VM_03_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_03_0_VM7_SHIFT)
#define GPIO_V_VM_03_0_VM7_RANGE                        13:12
#define GPIO_V_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_V_VM_03_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_03_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_03_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_03_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_03_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_03_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_03_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_V_VM_03_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_03_0_VM8_SHIFT)
#define GPIO_V_VM_03_0_VM8_RANGE                        15:14
#define GPIO_V_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_V_VM_03_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_03_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_03_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_03_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_03_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_03_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_V_SCR_03_0
#define GPIO_V_SCR_03_0                 _MK_ADDR_CONST(0x101c)
#define GPIO_V_SCR_03_0_SECURE                  0x0
#define GPIO_V_SCR_03_0_DUAL                    0x0
#define GPIO_V_SCR_03_0_SCR                     0
#define GPIO_V_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_V_SCR_03_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_V_SCR_03_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_V_SCR_03_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_V_SCR_03_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_V_SCR_03_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_V_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_V_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_V_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_V_SCR_03_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_03_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_03_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_V_SCR_03_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_V_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_V_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_V_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_V_SCR_03_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_03_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_03_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_V_SCR_03_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_V_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_V_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_V_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_V_SCR_03_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_03_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_03_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_V_SCR_03_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_V_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_V_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_V_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_V_SCR_03_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_V_SCR_03_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_03_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_V_SCR_03_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_03_0_PR7_SHIFT)
#define GPIO_V_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_V_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_V_SCR_03_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_03_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_03_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_V_SCR_03_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_03_0_PR6_SHIFT)
#define GPIO_V_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_V_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_V_SCR_03_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_03_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_03_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_V_SCR_03_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_03_0_PR5_SHIFT)
#define GPIO_V_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_V_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_V_SCR_03_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_03_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_03_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_V_SCR_03_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_03_0_PR4_SHIFT)
#define GPIO_V_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_V_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_V_SCR_03_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_03_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_03_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_V_SCR_03_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_03_0_PR3_SHIFT)
#define GPIO_V_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_V_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_V_SCR_03_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_03_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_03_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_V_SCR_03_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_03_0_PR2_SHIFT)
#define GPIO_V_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_V_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_V_SCR_03_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_03_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_03_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_V_SCR_03_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_03_0_PR1_SHIFT)
#define GPIO_V_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_V_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_V_SCR_03_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_03_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_03_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_V_SCR_03_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_03_0_PR0_SHIFT)
#define GPIO_V_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_V_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_V_SCR_03_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_03_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_03_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_V_SCR_03_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_03_0_G7W_SHIFT)
#define GPIO_V_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_V_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_V_SCR_03_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_03_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_03_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_V_SCR_03_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_03_0_G6W_SHIFT)
#define GPIO_V_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_V_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_V_SCR_03_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_03_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_03_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_V_SCR_03_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_03_0_G5W_SHIFT)
#define GPIO_V_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_V_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_V_SCR_03_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_03_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_03_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_V_SCR_03_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_03_0_G4W_SHIFT)
#define GPIO_V_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_V_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_V_SCR_03_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_03_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_03_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_V_SCR_03_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_03_0_G3W_SHIFT)
#define GPIO_V_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_V_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_V_SCR_03_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_03_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_03_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_V_SCR_03_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_03_0_G2W_SHIFT)
#define GPIO_V_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_V_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_V_SCR_03_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_03_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_03_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_V_SCR_03_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_03_0_G1W_SHIFT)
#define GPIO_V_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_V_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_V_SCR_03_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_03_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_03_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_V_SCR_03_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_03_0_G0W_SHIFT)
#define GPIO_V_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_V_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_V_SCR_03_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_03_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_03_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_V_SCR_03_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_03_0_G7R_SHIFT)
#define GPIO_V_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_V_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_V_SCR_03_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_03_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_03_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_V_SCR_03_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_03_0_G6R_SHIFT)
#define GPIO_V_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_V_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_V_SCR_03_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_03_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_03_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_V_SCR_03_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_03_0_G5R_SHIFT)
#define GPIO_V_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_V_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_V_SCR_03_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_03_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_03_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_V_SCR_03_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_03_0_G4R_SHIFT)
#define GPIO_V_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_V_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_V_SCR_03_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_03_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_03_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_V_SCR_03_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_03_0_G3R_SHIFT)
#define GPIO_V_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_V_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_V_SCR_03_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_03_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_03_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_V_SCR_03_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_03_0_G2R_SHIFT)
#define GPIO_V_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_V_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_V_SCR_03_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_03_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_03_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_V_SCR_03_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_03_0_G1R_SHIFT)
#define GPIO_V_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_V_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_V_SCR_03_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_03_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_03_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_V_SCR_03_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_03_0_G0R_SHIFT)
#define GPIO_V_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_V_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_V_SCR_03_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_03_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_03_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_V_VM_04_0
#define GPIO_V_VM_04_0                  _MK_ADDR_CONST(0x1020)
#define GPIO_V_VM_04_0_SECURE                   0x0
#define GPIO_V_VM_04_0_DUAL                     0x0
#define GPIO_V_VM_04_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_V_VM_04_0_WORD_COUNT                       0x1
#define GPIO_V_VM_04_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_V_VM_04_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_V_VM_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_V_VM_04_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_V_VM_04_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_V_VM_04_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_V_VM_04_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_04_0_VM1_SHIFT)
#define GPIO_V_VM_04_0_VM1_RANGE                        1:0
#define GPIO_V_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_V_VM_04_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_04_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_04_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_04_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_04_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_04_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_04_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_V_VM_04_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_04_0_VM2_SHIFT)
#define GPIO_V_VM_04_0_VM2_RANGE                        3:2
#define GPIO_V_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_V_VM_04_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_04_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_04_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_04_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_04_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_04_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_04_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_V_VM_04_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_04_0_VM3_SHIFT)
#define GPIO_V_VM_04_0_VM3_RANGE                        5:4
#define GPIO_V_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_V_VM_04_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_04_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_04_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_04_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_04_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_04_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_04_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_V_VM_04_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_04_0_VM4_SHIFT)
#define GPIO_V_VM_04_0_VM4_RANGE                        7:6
#define GPIO_V_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_V_VM_04_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_04_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_04_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_04_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_04_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_04_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_04_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_V_VM_04_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_04_0_VM5_SHIFT)
#define GPIO_V_VM_04_0_VM5_RANGE                        9:8
#define GPIO_V_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_V_VM_04_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_04_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_04_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_04_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_04_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_04_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_04_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_V_VM_04_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_04_0_VM6_SHIFT)
#define GPIO_V_VM_04_0_VM6_RANGE                        11:10
#define GPIO_V_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_V_VM_04_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_04_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_04_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_04_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_04_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_04_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_04_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_V_VM_04_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_04_0_VM7_SHIFT)
#define GPIO_V_VM_04_0_VM7_RANGE                        13:12
#define GPIO_V_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_V_VM_04_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_04_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_04_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_04_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_04_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_04_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_04_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_V_VM_04_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_04_0_VM8_SHIFT)
#define GPIO_V_VM_04_0_VM8_RANGE                        15:14
#define GPIO_V_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_V_VM_04_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_04_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_04_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_04_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_04_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_04_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_V_SCR_04_0
#define GPIO_V_SCR_04_0                 _MK_ADDR_CONST(0x1024)
#define GPIO_V_SCR_04_0_SECURE                  0x0
#define GPIO_V_SCR_04_0_DUAL                    0x0
#define GPIO_V_SCR_04_0_SCR                     0
#define GPIO_V_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_V_SCR_04_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_V_SCR_04_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_V_SCR_04_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_V_SCR_04_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_V_SCR_04_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_V_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_V_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_V_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_V_SCR_04_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_04_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_04_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_V_SCR_04_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_V_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_V_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_V_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_V_SCR_04_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_04_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_04_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_V_SCR_04_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_V_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_V_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_V_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_V_SCR_04_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_04_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_04_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_V_SCR_04_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_V_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_V_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_V_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_V_SCR_04_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_V_SCR_04_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_04_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_V_SCR_04_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_04_0_PR7_SHIFT)
#define GPIO_V_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_V_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_V_SCR_04_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_04_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_04_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_V_SCR_04_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_04_0_PR6_SHIFT)
#define GPIO_V_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_V_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_V_SCR_04_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_04_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_04_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_V_SCR_04_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_04_0_PR5_SHIFT)
#define GPIO_V_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_V_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_V_SCR_04_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_04_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_04_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_V_SCR_04_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_04_0_PR4_SHIFT)
#define GPIO_V_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_V_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_V_SCR_04_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_04_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_04_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_V_SCR_04_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_04_0_PR3_SHIFT)
#define GPIO_V_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_V_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_V_SCR_04_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_04_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_04_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_V_SCR_04_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_04_0_PR2_SHIFT)
#define GPIO_V_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_V_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_V_SCR_04_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_04_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_04_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_V_SCR_04_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_04_0_PR1_SHIFT)
#define GPIO_V_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_V_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_V_SCR_04_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_04_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_04_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_V_SCR_04_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_04_0_PR0_SHIFT)
#define GPIO_V_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_V_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_V_SCR_04_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_04_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_04_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_V_SCR_04_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_04_0_G7W_SHIFT)
#define GPIO_V_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_V_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_V_SCR_04_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_04_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_04_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_V_SCR_04_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_04_0_G6W_SHIFT)
#define GPIO_V_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_V_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_V_SCR_04_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_04_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_04_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_V_SCR_04_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_04_0_G5W_SHIFT)
#define GPIO_V_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_V_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_V_SCR_04_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_04_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_04_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_V_SCR_04_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_04_0_G4W_SHIFT)
#define GPIO_V_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_V_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_V_SCR_04_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_04_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_04_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_V_SCR_04_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_04_0_G3W_SHIFT)
#define GPIO_V_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_V_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_V_SCR_04_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_04_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_04_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_V_SCR_04_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_04_0_G2W_SHIFT)
#define GPIO_V_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_V_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_V_SCR_04_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_04_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_04_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_V_SCR_04_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_04_0_G1W_SHIFT)
#define GPIO_V_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_V_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_V_SCR_04_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_04_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_04_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_V_SCR_04_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_04_0_G0W_SHIFT)
#define GPIO_V_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_V_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_V_SCR_04_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_04_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_04_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_V_SCR_04_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_04_0_G7R_SHIFT)
#define GPIO_V_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_V_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_V_SCR_04_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_04_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_04_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_V_SCR_04_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_04_0_G6R_SHIFT)
#define GPIO_V_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_V_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_V_SCR_04_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_04_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_04_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_V_SCR_04_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_04_0_G5R_SHIFT)
#define GPIO_V_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_V_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_V_SCR_04_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_04_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_04_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_V_SCR_04_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_04_0_G4R_SHIFT)
#define GPIO_V_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_V_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_V_SCR_04_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_04_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_04_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_V_SCR_04_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_04_0_G3R_SHIFT)
#define GPIO_V_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_V_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_V_SCR_04_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_04_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_04_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_V_SCR_04_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_04_0_G2R_SHIFT)
#define GPIO_V_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_V_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_V_SCR_04_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_04_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_04_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_V_SCR_04_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_04_0_G1R_SHIFT)
#define GPIO_V_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_V_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_V_SCR_04_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_04_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_04_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_V_SCR_04_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_04_0_G0R_SHIFT)
#define GPIO_V_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_V_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_V_SCR_04_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_04_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_04_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_V_VM_05_0
#define GPIO_V_VM_05_0                  _MK_ADDR_CONST(0x1028)
#define GPIO_V_VM_05_0_SECURE                   0x0
#define GPIO_V_VM_05_0_DUAL                     0x0
#define GPIO_V_VM_05_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_V_VM_05_0_WORD_COUNT                       0x1
#define GPIO_V_VM_05_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_V_VM_05_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_V_VM_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_V_VM_05_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_V_VM_05_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_V_VM_05_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_V_VM_05_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_05_0_VM1_SHIFT)
#define GPIO_V_VM_05_0_VM1_RANGE                        1:0
#define GPIO_V_VM_05_0_VM1_WOFFSET                      0x0
#define GPIO_V_VM_05_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_05_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_05_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_05_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_05_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_05_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_05_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_V_VM_05_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_05_0_VM2_SHIFT)
#define GPIO_V_VM_05_0_VM2_RANGE                        3:2
#define GPIO_V_VM_05_0_VM2_WOFFSET                      0x0
#define GPIO_V_VM_05_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_05_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_05_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_05_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_05_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_05_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_05_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_V_VM_05_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_05_0_VM3_SHIFT)
#define GPIO_V_VM_05_0_VM3_RANGE                        5:4
#define GPIO_V_VM_05_0_VM3_WOFFSET                      0x0
#define GPIO_V_VM_05_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_05_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_05_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_05_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_05_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_05_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_05_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_V_VM_05_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_05_0_VM4_SHIFT)
#define GPIO_V_VM_05_0_VM4_RANGE                        7:6
#define GPIO_V_VM_05_0_VM4_WOFFSET                      0x0
#define GPIO_V_VM_05_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_05_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_05_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_05_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_05_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_05_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_05_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_V_VM_05_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_05_0_VM5_SHIFT)
#define GPIO_V_VM_05_0_VM5_RANGE                        9:8
#define GPIO_V_VM_05_0_VM5_WOFFSET                      0x0
#define GPIO_V_VM_05_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_05_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_05_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_05_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_05_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_05_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_05_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_V_VM_05_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_05_0_VM6_SHIFT)
#define GPIO_V_VM_05_0_VM6_RANGE                        11:10
#define GPIO_V_VM_05_0_VM6_WOFFSET                      0x0
#define GPIO_V_VM_05_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_05_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_05_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_05_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_05_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_05_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_05_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_V_VM_05_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_05_0_VM7_SHIFT)
#define GPIO_V_VM_05_0_VM7_RANGE                        13:12
#define GPIO_V_VM_05_0_VM7_WOFFSET                      0x0
#define GPIO_V_VM_05_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_05_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_05_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_05_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_05_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_05_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_05_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_V_VM_05_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_05_0_VM8_SHIFT)
#define GPIO_V_VM_05_0_VM8_RANGE                        15:14
#define GPIO_V_VM_05_0_VM8_WOFFSET                      0x0
#define GPIO_V_VM_05_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_05_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_05_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_05_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_05_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_05_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_V_SCR_05_0
#define GPIO_V_SCR_05_0                 _MK_ADDR_CONST(0x102c)
#define GPIO_V_SCR_05_0_SECURE                  0x0
#define GPIO_V_SCR_05_0_DUAL                    0x0
#define GPIO_V_SCR_05_0_SCR                     0
#define GPIO_V_SCR_05_0_WORD_COUNT                      0x1
#define GPIO_V_SCR_05_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_V_SCR_05_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_V_SCR_05_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_V_SCR_05_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_V_SCR_05_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_V_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_V_SCR_05_0_SEC_LCK_RANGE                   29:29
#define GPIO_V_SCR_05_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_V_SCR_05_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_05_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_05_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_V_SCR_05_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_V_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_V_SCR_05_0_SEC_WEN_RANGE                   28:28
#define GPIO_V_SCR_05_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_V_SCR_05_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_05_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_05_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_V_SCR_05_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_V_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_V_SCR_05_0_SEC_REN_RANGE                   27:27
#define GPIO_V_SCR_05_0_SEC_REN_WOFFSET                 0x0
#define GPIO_V_SCR_05_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_05_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_05_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_V_SCR_05_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_V_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_V_SCR_05_0_SEC_OWNER_RANGE                 26:24
#define GPIO_V_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_V_SCR_05_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_V_SCR_05_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_05_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_V_SCR_05_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_05_0_PR7_SHIFT)
#define GPIO_V_SCR_05_0_PR7_RANGE                       23:23
#define GPIO_V_SCR_05_0_PR7_WOFFSET                     0x0
#define GPIO_V_SCR_05_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_05_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_05_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_V_SCR_05_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_05_0_PR6_SHIFT)
#define GPIO_V_SCR_05_0_PR6_RANGE                       22:22
#define GPIO_V_SCR_05_0_PR6_WOFFSET                     0x0
#define GPIO_V_SCR_05_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_05_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_05_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_V_SCR_05_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_05_0_PR5_SHIFT)
#define GPIO_V_SCR_05_0_PR5_RANGE                       21:21
#define GPIO_V_SCR_05_0_PR5_WOFFSET                     0x0
#define GPIO_V_SCR_05_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_05_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_05_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_V_SCR_05_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_05_0_PR4_SHIFT)
#define GPIO_V_SCR_05_0_PR4_RANGE                       20:20
#define GPIO_V_SCR_05_0_PR4_WOFFSET                     0x0
#define GPIO_V_SCR_05_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_05_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_05_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_V_SCR_05_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_05_0_PR3_SHIFT)
#define GPIO_V_SCR_05_0_PR3_RANGE                       19:19
#define GPIO_V_SCR_05_0_PR3_WOFFSET                     0x0
#define GPIO_V_SCR_05_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_05_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_05_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_V_SCR_05_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_05_0_PR2_SHIFT)
#define GPIO_V_SCR_05_0_PR2_RANGE                       18:18
#define GPIO_V_SCR_05_0_PR2_WOFFSET                     0x0
#define GPIO_V_SCR_05_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_05_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_05_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_V_SCR_05_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_05_0_PR1_SHIFT)
#define GPIO_V_SCR_05_0_PR1_RANGE                       17:17
#define GPIO_V_SCR_05_0_PR1_WOFFSET                     0x0
#define GPIO_V_SCR_05_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_05_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_05_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_V_SCR_05_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_05_0_PR0_SHIFT)
#define GPIO_V_SCR_05_0_PR0_RANGE                       16:16
#define GPIO_V_SCR_05_0_PR0_WOFFSET                     0x0
#define GPIO_V_SCR_05_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_05_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_05_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_V_SCR_05_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_05_0_G7W_SHIFT)
#define GPIO_V_SCR_05_0_G7W_RANGE                       15:15
#define GPIO_V_SCR_05_0_G7W_WOFFSET                     0x0
#define GPIO_V_SCR_05_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_05_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_05_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_V_SCR_05_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_05_0_G6W_SHIFT)
#define GPIO_V_SCR_05_0_G6W_RANGE                       14:14
#define GPIO_V_SCR_05_0_G6W_WOFFSET                     0x0
#define GPIO_V_SCR_05_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_05_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_05_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_V_SCR_05_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_05_0_G5W_SHIFT)
#define GPIO_V_SCR_05_0_G5W_RANGE                       13:13
#define GPIO_V_SCR_05_0_G5W_WOFFSET                     0x0
#define GPIO_V_SCR_05_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_05_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_05_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_V_SCR_05_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_05_0_G4W_SHIFT)
#define GPIO_V_SCR_05_0_G4W_RANGE                       12:12
#define GPIO_V_SCR_05_0_G4W_WOFFSET                     0x0
#define GPIO_V_SCR_05_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_05_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_05_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_V_SCR_05_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_05_0_G3W_SHIFT)
#define GPIO_V_SCR_05_0_G3W_RANGE                       11:11
#define GPIO_V_SCR_05_0_G3W_WOFFSET                     0x0
#define GPIO_V_SCR_05_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_05_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_05_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_V_SCR_05_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_05_0_G2W_SHIFT)
#define GPIO_V_SCR_05_0_G2W_RANGE                       10:10
#define GPIO_V_SCR_05_0_G2W_WOFFSET                     0x0
#define GPIO_V_SCR_05_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_05_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_05_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_V_SCR_05_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_05_0_G1W_SHIFT)
#define GPIO_V_SCR_05_0_G1W_RANGE                       9:9
#define GPIO_V_SCR_05_0_G1W_WOFFSET                     0x0
#define GPIO_V_SCR_05_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_05_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_05_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_V_SCR_05_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_05_0_G0W_SHIFT)
#define GPIO_V_SCR_05_0_G0W_RANGE                       8:8
#define GPIO_V_SCR_05_0_G0W_WOFFSET                     0x0
#define GPIO_V_SCR_05_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_05_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_05_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_V_SCR_05_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_05_0_G7R_SHIFT)
#define GPIO_V_SCR_05_0_G7R_RANGE                       7:7
#define GPIO_V_SCR_05_0_G7R_WOFFSET                     0x0
#define GPIO_V_SCR_05_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_05_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_05_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_V_SCR_05_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_05_0_G6R_SHIFT)
#define GPIO_V_SCR_05_0_G6R_RANGE                       6:6
#define GPIO_V_SCR_05_0_G6R_WOFFSET                     0x0
#define GPIO_V_SCR_05_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_05_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_05_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_V_SCR_05_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_05_0_G5R_SHIFT)
#define GPIO_V_SCR_05_0_G5R_RANGE                       5:5
#define GPIO_V_SCR_05_0_G5R_WOFFSET                     0x0
#define GPIO_V_SCR_05_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_05_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_05_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_V_SCR_05_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_05_0_G4R_SHIFT)
#define GPIO_V_SCR_05_0_G4R_RANGE                       4:4
#define GPIO_V_SCR_05_0_G4R_WOFFSET                     0x0
#define GPIO_V_SCR_05_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_05_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_05_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_V_SCR_05_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_05_0_G3R_SHIFT)
#define GPIO_V_SCR_05_0_G3R_RANGE                       3:3
#define GPIO_V_SCR_05_0_G3R_WOFFSET                     0x0
#define GPIO_V_SCR_05_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_05_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_05_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_V_SCR_05_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_05_0_G2R_SHIFT)
#define GPIO_V_SCR_05_0_G2R_RANGE                       2:2
#define GPIO_V_SCR_05_0_G2R_WOFFSET                     0x0
#define GPIO_V_SCR_05_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_05_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_05_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_V_SCR_05_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_05_0_G1R_SHIFT)
#define GPIO_V_SCR_05_0_G1R_RANGE                       1:1
#define GPIO_V_SCR_05_0_G1R_WOFFSET                     0x0
#define GPIO_V_SCR_05_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_05_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_05_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_V_SCR_05_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_05_0_G0R_SHIFT)
#define GPIO_V_SCR_05_0_G0R_RANGE                       0:0
#define GPIO_V_SCR_05_0_G0R_WOFFSET                     0x0
#define GPIO_V_SCR_05_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_05_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_05_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_V_VM_06_0
#define GPIO_V_VM_06_0                  _MK_ADDR_CONST(0x1030)
#define GPIO_V_VM_06_0_SECURE                   0x0
#define GPIO_V_VM_06_0_DUAL                     0x0
#define GPIO_V_VM_06_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_V_VM_06_0_WORD_COUNT                       0x1
#define GPIO_V_VM_06_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_V_VM_06_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_V_VM_06_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_06_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_V_VM_06_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_V_VM_06_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_V_VM_06_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_V_VM_06_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_06_0_VM1_SHIFT)
#define GPIO_V_VM_06_0_VM1_RANGE                        1:0
#define GPIO_V_VM_06_0_VM1_WOFFSET                      0x0
#define GPIO_V_VM_06_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_06_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_06_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_06_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_06_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_06_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_06_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_V_VM_06_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_06_0_VM2_SHIFT)
#define GPIO_V_VM_06_0_VM2_RANGE                        3:2
#define GPIO_V_VM_06_0_VM2_WOFFSET                      0x0
#define GPIO_V_VM_06_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_06_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_06_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_06_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_06_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_06_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_06_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_V_VM_06_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_06_0_VM3_SHIFT)
#define GPIO_V_VM_06_0_VM3_RANGE                        5:4
#define GPIO_V_VM_06_0_VM3_WOFFSET                      0x0
#define GPIO_V_VM_06_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_06_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_06_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_06_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_06_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_06_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_06_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_V_VM_06_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_06_0_VM4_SHIFT)
#define GPIO_V_VM_06_0_VM4_RANGE                        7:6
#define GPIO_V_VM_06_0_VM4_WOFFSET                      0x0
#define GPIO_V_VM_06_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_06_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_06_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_06_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_06_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_06_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_06_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_V_VM_06_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_06_0_VM5_SHIFT)
#define GPIO_V_VM_06_0_VM5_RANGE                        9:8
#define GPIO_V_VM_06_0_VM5_WOFFSET                      0x0
#define GPIO_V_VM_06_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_06_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_06_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_06_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_06_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_06_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_06_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_V_VM_06_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_06_0_VM6_SHIFT)
#define GPIO_V_VM_06_0_VM6_RANGE                        11:10
#define GPIO_V_VM_06_0_VM6_WOFFSET                      0x0
#define GPIO_V_VM_06_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_06_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_06_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_06_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_06_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_06_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_06_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_V_VM_06_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_06_0_VM7_SHIFT)
#define GPIO_V_VM_06_0_VM7_RANGE                        13:12
#define GPIO_V_VM_06_0_VM7_WOFFSET                      0x0
#define GPIO_V_VM_06_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_06_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_06_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_06_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_06_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_06_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_06_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_V_VM_06_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_06_0_VM8_SHIFT)
#define GPIO_V_VM_06_0_VM8_RANGE                        15:14
#define GPIO_V_VM_06_0_VM8_WOFFSET                      0x0
#define GPIO_V_VM_06_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_06_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_06_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_06_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_06_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_06_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_V_SCR_06_0
#define GPIO_V_SCR_06_0                 _MK_ADDR_CONST(0x1034)
#define GPIO_V_SCR_06_0_SECURE                  0x0
#define GPIO_V_SCR_06_0_DUAL                    0x0
#define GPIO_V_SCR_06_0_SCR                     0
#define GPIO_V_SCR_06_0_WORD_COUNT                      0x1
#define GPIO_V_SCR_06_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_V_SCR_06_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_V_SCR_06_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_V_SCR_06_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_V_SCR_06_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_V_SCR_06_0_SEC_LCK_SHIFT)
#define GPIO_V_SCR_06_0_SEC_LCK_RANGE                   29:29
#define GPIO_V_SCR_06_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_V_SCR_06_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_06_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_06_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_V_SCR_06_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_V_SCR_06_0_SEC_WEN_SHIFT)
#define GPIO_V_SCR_06_0_SEC_WEN_RANGE                   28:28
#define GPIO_V_SCR_06_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_V_SCR_06_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_06_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_06_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_V_SCR_06_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_V_SCR_06_0_SEC_REN_SHIFT)
#define GPIO_V_SCR_06_0_SEC_REN_RANGE                   27:27
#define GPIO_V_SCR_06_0_SEC_REN_WOFFSET                 0x0
#define GPIO_V_SCR_06_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_06_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_06_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_V_SCR_06_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_V_SCR_06_0_SEC_OWNER_SHIFT)
#define GPIO_V_SCR_06_0_SEC_OWNER_RANGE                 26:24
#define GPIO_V_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_V_SCR_06_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_V_SCR_06_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_06_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_V_SCR_06_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_06_0_PR7_SHIFT)
#define GPIO_V_SCR_06_0_PR7_RANGE                       23:23
#define GPIO_V_SCR_06_0_PR7_WOFFSET                     0x0
#define GPIO_V_SCR_06_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_06_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_06_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_V_SCR_06_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_06_0_PR6_SHIFT)
#define GPIO_V_SCR_06_0_PR6_RANGE                       22:22
#define GPIO_V_SCR_06_0_PR6_WOFFSET                     0x0
#define GPIO_V_SCR_06_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_06_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_06_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_V_SCR_06_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_06_0_PR5_SHIFT)
#define GPIO_V_SCR_06_0_PR5_RANGE                       21:21
#define GPIO_V_SCR_06_0_PR5_WOFFSET                     0x0
#define GPIO_V_SCR_06_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_06_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_06_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_V_SCR_06_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_06_0_PR4_SHIFT)
#define GPIO_V_SCR_06_0_PR4_RANGE                       20:20
#define GPIO_V_SCR_06_0_PR4_WOFFSET                     0x0
#define GPIO_V_SCR_06_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_06_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_06_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_V_SCR_06_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_06_0_PR3_SHIFT)
#define GPIO_V_SCR_06_0_PR3_RANGE                       19:19
#define GPIO_V_SCR_06_0_PR3_WOFFSET                     0x0
#define GPIO_V_SCR_06_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_06_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_06_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_V_SCR_06_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_06_0_PR2_SHIFT)
#define GPIO_V_SCR_06_0_PR2_RANGE                       18:18
#define GPIO_V_SCR_06_0_PR2_WOFFSET                     0x0
#define GPIO_V_SCR_06_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_06_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_06_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_V_SCR_06_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_06_0_PR1_SHIFT)
#define GPIO_V_SCR_06_0_PR1_RANGE                       17:17
#define GPIO_V_SCR_06_0_PR1_WOFFSET                     0x0
#define GPIO_V_SCR_06_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_06_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_06_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_V_SCR_06_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_06_0_PR0_SHIFT)
#define GPIO_V_SCR_06_0_PR0_RANGE                       16:16
#define GPIO_V_SCR_06_0_PR0_WOFFSET                     0x0
#define GPIO_V_SCR_06_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_06_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_06_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_V_SCR_06_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_06_0_G7W_SHIFT)
#define GPIO_V_SCR_06_0_G7W_RANGE                       15:15
#define GPIO_V_SCR_06_0_G7W_WOFFSET                     0x0
#define GPIO_V_SCR_06_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_06_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_06_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_V_SCR_06_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_06_0_G6W_SHIFT)
#define GPIO_V_SCR_06_0_G6W_RANGE                       14:14
#define GPIO_V_SCR_06_0_G6W_WOFFSET                     0x0
#define GPIO_V_SCR_06_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_06_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_06_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_V_SCR_06_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_06_0_G5W_SHIFT)
#define GPIO_V_SCR_06_0_G5W_RANGE                       13:13
#define GPIO_V_SCR_06_0_G5W_WOFFSET                     0x0
#define GPIO_V_SCR_06_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_06_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_06_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_V_SCR_06_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_06_0_G4W_SHIFT)
#define GPIO_V_SCR_06_0_G4W_RANGE                       12:12
#define GPIO_V_SCR_06_0_G4W_WOFFSET                     0x0
#define GPIO_V_SCR_06_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_06_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_06_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_V_SCR_06_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_06_0_G3W_SHIFT)
#define GPIO_V_SCR_06_0_G3W_RANGE                       11:11
#define GPIO_V_SCR_06_0_G3W_WOFFSET                     0x0
#define GPIO_V_SCR_06_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_06_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_06_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_V_SCR_06_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_06_0_G2W_SHIFT)
#define GPIO_V_SCR_06_0_G2W_RANGE                       10:10
#define GPIO_V_SCR_06_0_G2W_WOFFSET                     0x0
#define GPIO_V_SCR_06_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_06_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_06_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_V_SCR_06_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_06_0_G1W_SHIFT)
#define GPIO_V_SCR_06_0_G1W_RANGE                       9:9
#define GPIO_V_SCR_06_0_G1W_WOFFSET                     0x0
#define GPIO_V_SCR_06_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_06_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_06_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_V_SCR_06_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_06_0_G0W_SHIFT)
#define GPIO_V_SCR_06_0_G0W_RANGE                       8:8
#define GPIO_V_SCR_06_0_G0W_WOFFSET                     0x0
#define GPIO_V_SCR_06_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_06_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_06_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_V_SCR_06_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_06_0_G7R_SHIFT)
#define GPIO_V_SCR_06_0_G7R_RANGE                       7:7
#define GPIO_V_SCR_06_0_G7R_WOFFSET                     0x0
#define GPIO_V_SCR_06_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_06_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_06_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_V_SCR_06_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_06_0_G6R_SHIFT)
#define GPIO_V_SCR_06_0_G6R_RANGE                       6:6
#define GPIO_V_SCR_06_0_G6R_WOFFSET                     0x0
#define GPIO_V_SCR_06_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_06_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_06_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_V_SCR_06_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_06_0_G5R_SHIFT)
#define GPIO_V_SCR_06_0_G5R_RANGE                       5:5
#define GPIO_V_SCR_06_0_G5R_WOFFSET                     0x0
#define GPIO_V_SCR_06_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_06_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_06_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_V_SCR_06_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_06_0_G4R_SHIFT)
#define GPIO_V_SCR_06_0_G4R_RANGE                       4:4
#define GPIO_V_SCR_06_0_G4R_WOFFSET                     0x0
#define GPIO_V_SCR_06_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_06_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_06_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_V_SCR_06_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_06_0_G3R_SHIFT)
#define GPIO_V_SCR_06_0_G3R_RANGE                       3:3
#define GPIO_V_SCR_06_0_G3R_WOFFSET                     0x0
#define GPIO_V_SCR_06_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_06_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_06_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_V_SCR_06_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_06_0_G2R_SHIFT)
#define GPIO_V_SCR_06_0_G2R_RANGE                       2:2
#define GPIO_V_SCR_06_0_G2R_WOFFSET                     0x0
#define GPIO_V_SCR_06_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_06_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_06_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_V_SCR_06_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_06_0_G1R_SHIFT)
#define GPIO_V_SCR_06_0_G1R_RANGE                       1:1
#define GPIO_V_SCR_06_0_G1R_WOFFSET                     0x0
#define GPIO_V_SCR_06_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_06_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_06_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_V_SCR_06_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_06_0_G0R_SHIFT)
#define GPIO_V_SCR_06_0_G0R_RANGE                       0:0
#define GPIO_V_SCR_06_0_G0R_WOFFSET                     0x0
#define GPIO_V_SCR_06_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_06_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_06_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_V_VM_07_0
#define GPIO_V_VM_07_0                  _MK_ADDR_CONST(0x1038)
#define GPIO_V_VM_07_0_SECURE                   0x0
#define GPIO_V_VM_07_0_DUAL                     0x0
#define GPIO_V_VM_07_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_V_VM_07_0_WORD_COUNT                       0x1
#define GPIO_V_VM_07_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_V_VM_07_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_V_VM_07_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_07_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_V_VM_07_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_V_VM_07_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_V_VM_07_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_V_VM_07_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_07_0_VM1_SHIFT)
#define GPIO_V_VM_07_0_VM1_RANGE                        1:0
#define GPIO_V_VM_07_0_VM1_WOFFSET                      0x0
#define GPIO_V_VM_07_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_07_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_07_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_07_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_07_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_07_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_07_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_V_VM_07_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_07_0_VM2_SHIFT)
#define GPIO_V_VM_07_0_VM2_RANGE                        3:2
#define GPIO_V_VM_07_0_VM2_WOFFSET                      0x0
#define GPIO_V_VM_07_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_07_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_07_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_07_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_07_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_07_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_07_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_V_VM_07_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_07_0_VM3_SHIFT)
#define GPIO_V_VM_07_0_VM3_RANGE                        5:4
#define GPIO_V_VM_07_0_VM3_WOFFSET                      0x0
#define GPIO_V_VM_07_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_07_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_07_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_07_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_07_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_07_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_07_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_V_VM_07_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_07_0_VM4_SHIFT)
#define GPIO_V_VM_07_0_VM4_RANGE                        7:6
#define GPIO_V_VM_07_0_VM4_WOFFSET                      0x0
#define GPIO_V_VM_07_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_07_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_07_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_07_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_07_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_07_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_07_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_V_VM_07_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_07_0_VM5_SHIFT)
#define GPIO_V_VM_07_0_VM5_RANGE                        9:8
#define GPIO_V_VM_07_0_VM5_WOFFSET                      0x0
#define GPIO_V_VM_07_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_07_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_07_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_07_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_07_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_07_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_07_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_V_VM_07_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_07_0_VM6_SHIFT)
#define GPIO_V_VM_07_0_VM6_RANGE                        11:10
#define GPIO_V_VM_07_0_VM6_WOFFSET                      0x0
#define GPIO_V_VM_07_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_07_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_07_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_07_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_07_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_07_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_07_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_V_VM_07_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_07_0_VM7_SHIFT)
#define GPIO_V_VM_07_0_VM7_RANGE                        13:12
#define GPIO_V_VM_07_0_VM7_WOFFSET                      0x0
#define GPIO_V_VM_07_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_07_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_07_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_07_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_07_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_07_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_V_VM_07_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_V_VM_07_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_V_VM_07_0_VM8_SHIFT)
#define GPIO_V_VM_07_0_VM8_RANGE                        15:14
#define GPIO_V_VM_07_0_VM8_WOFFSET                      0x0
#define GPIO_V_VM_07_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_V_VM_07_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_V_VM_07_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_VM_07_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_VM_07_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_VM_07_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_V_SCR_07_0
#define GPIO_V_SCR_07_0                 _MK_ADDR_CONST(0x103c)
#define GPIO_V_SCR_07_0_SECURE                  0x0
#define GPIO_V_SCR_07_0_DUAL                    0x0
#define GPIO_V_SCR_07_0_SCR                     0
#define GPIO_V_SCR_07_0_WORD_COUNT                      0x1
#define GPIO_V_SCR_07_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_V_SCR_07_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_V_SCR_07_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_V_SCR_07_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_V_SCR_07_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_V_SCR_07_0_SEC_LCK_SHIFT)
#define GPIO_V_SCR_07_0_SEC_LCK_RANGE                   29:29
#define GPIO_V_SCR_07_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_V_SCR_07_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_07_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_07_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_V_SCR_07_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_V_SCR_07_0_SEC_WEN_SHIFT)
#define GPIO_V_SCR_07_0_SEC_WEN_RANGE                   28:28
#define GPIO_V_SCR_07_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_V_SCR_07_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_07_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_07_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_V_SCR_07_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_V_SCR_07_0_SEC_REN_SHIFT)
#define GPIO_V_SCR_07_0_SEC_REN_RANGE                   27:27
#define GPIO_V_SCR_07_0_SEC_REN_WOFFSET                 0x0
#define GPIO_V_SCR_07_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_07_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_07_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_V_SCR_07_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_V_SCR_07_0_SEC_OWNER_SHIFT)
#define GPIO_V_SCR_07_0_SEC_OWNER_RANGE                 26:24
#define GPIO_V_SCR_07_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_V_SCR_07_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_V_SCR_07_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_07_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_V_SCR_07_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_07_0_PR7_SHIFT)
#define GPIO_V_SCR_07_0_PR7_RANGE                       23:23
#define GPIO_V_SCR_07_0_PR7_WOFFSET                     0x0
#define GPIO_V_SCR_07_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_07_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_07_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_V_SCR_07_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_07_0_PR6_SHIFT)
#define GPIO_V_SCR_07_0_PR6_RANGE                       22:22
#define GPIO_V_SCR_07_0_PR6_WOFFSET                     0x0
#define GPIO_V_SCR_07_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_07_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_07_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_V_SCR_07_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_07_0_PR5_SHIFT)
#define GPIO_V_SCR_07_0_PR5_RANGE                       21:21
#define GPIO_V_SCR_07_0_PR5_WOFFSET                     0x0
#define GPIO_V_SCR_07_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_07_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_07_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_V_SCR_07_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_07_0_PR4_SHIFT)
#define GPIO_V_SCR_07_0_PR4_RANGE                       20:20
#define GPIO_V_SCR_07_0_PR4_WOFFSET                     0x0
#define GPIO_V_SCR_07_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_07_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_07_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_V_SCR_07_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_07_0_PR3_SHIFT)
#define GPIO_V_SCR_07_0_PR3_RANGE                       19:19
#define GPIO_V_SCR_07_0_PR3_WOFFSET                     0x0
#define GPIO_V_SCR_07_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_07_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_07_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_V_SCR_07_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_07_0_PR2_SHIFT)
#define GPIO_V_SCR_07_0_PR2_RANGE                       18:18
#define GPIO_V_SCR_07_0_PR2_WOFFSET                     0x0
#define GPIO_V_SCR_07_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_07_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_07_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_V_SCR_07_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_07_0_PR1_SHIFT)
#define GPIO_V_SCR_07_0_PR1_RANGE                       17:17
#define GPIO_V_SCR_07_0_PR1_WOFFSET                     0x0
#define GPIO_V_SCR_07_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_07_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_07_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_V_SCR_07_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_07_0_PR0_SHIFT)
#define GPIO_V_SCR_07_0_PR0_RANGE                       16:16
#define GPIO_V_SCR_07_0_PR0_WOFFSET                     0x0
#define GPIO_V_SCR_07_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_07_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_07_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_V_SCR_07_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_07_0_G7W_SHIFT)
#define GPIO_V_SCR_07_0_G7W_RANGE                       15:15
#define GPIO_V_SCR_07_0_G7W_WOFFSET                     0x0
#define GPIO_V_SCR_07_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_07_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_07_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_V_SCR_07_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_07_0_G6W_SHIFT)
#define GPIO_V_SCR_07_0_G6W_RANGE                       14:14
#define GPIO_V_SCR_07_0_G6W_WOFFSET                     0x0
#define GPIO_V_SCR_07_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_07_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_07_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_V_SCR_07_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_07_0_G5W_SHIFT)
#define GPIO_V_SCR_07_0_G5W_RANGE                       13:13
#define GPIO_V_SCR_07_0_G5W_WOFFSET                     0x0
#define GPIO_V_SCR_07_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_07_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_07_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_V_SCR_07_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_07_0_G4W_SHIFT)
#define GPIO_V_SCR_07_0_G4W_RANGE                       12:12
#define GPIO_V_SCR_07_0_G4W_WOFFSET                     0x0
#define GPIO_V_SCR_07_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_07_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_07_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_V_SCR_07_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_07_0_G3W_SHIFT)
#define GPIO_V_SCR_07_0_G3W_RANGE                       11:11
#define GPIO_V_SCR_07_0_G3W_WOFFSET                     0x0
#define GPIO_V_SCR_07_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_07_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_07_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_V_SCR_07_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_07_0_G2W_SHIFT)
#define GPIO_V_SCR_07_0_G2W_RANGE                       10:10
#define GPIO_V_SCR_07_0_G2W_WOFFSET                     0x0
#define GPIO_V_SCR_07_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_07_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_07_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_V_SCR_07_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_07_0_G1W_SHIFT)
#define GPIO_V_SCR_07_0_G1W_RANGE                       9:9
#define GPIO_V_SCR_07_0_G1W_WOFFSET                     0x0
#define GPIO_V_SCR_07_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_07_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_07_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_V_SCR_07_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_07_0_G0W_SHIFT)
#define GPIO_V_SCR_07_0_G0W_RANGE                       8:8
#define GPIO_V_SCR_07_0_G0W_WOFFSET                     0x0
#define GPIO_V_SCR_07_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_07_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_07_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_V_SCR_07_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_07_0_G7R_SHIFT)
#define GPIO_V_SCR_07_0_G7R_RANGE                       7:7
#define GPIO_V_SCR_07_0_G7R_WOFFSET                     0x0
#define GPIO_V_SCR_07_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_07_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_07_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_V_SCR_07_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_07_0_G6R_SHIFT)
#define GPIO_V_SCR_07_0_G6R_RANGE                       6:6
#define GPIO_V_SCR_07_0_G6R_WOFFSET                     0x0
#define GPIO_V_SCR_07_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_07_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_07_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_V_SCR_07_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_07_0_G5R_SHIFT)
#define GPIO_V_SCR_07_0_G5R_RANGE                       5:5
#define GPIO_V_SCR_07_0_G5R_WOFFSET                     0x0
#define GPIO_V_SCR_07_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_07_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_07_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_V_SCR_07_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_07_0_G4R_SHIFT)
#define GPIO_V_SCR_07_0_G4R_RANGE                       4:4
#define GPIO_V_SCR_07_0_G4R_WOFFSET                     0x0
#define GPIO_V_SCR_07_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_07_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_07_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_V_SCR_07_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_07_0_G3R_SHIFT)
#define GPIO_V_SCR_07_0_G3R_RANGE                       3:3
#define GPIO_V_SCR_07_0_G3R_WOFFSET                     0x0
#define GPIO_V_SCR_07_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_07_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_07_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_V_SCR_07_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_07_0_G2R_SHIFT)
#define GPIO_V_SCR_07_0_G2R_RANGE                       2:2
#define GPIO_V_SCR_07_0_G2R_WOFFSET                     0x0
#define GPIO_V_SCR_07_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_07_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_07_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_V_SCR_07_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_07_0_G1R_SHIFT)
#define GPIO_V_SCR_07_0_G1R_RANGE                       1:1
#define GPIO_V_SCR_07_0_G1R_WOFFSET                     0x0
#define GPIO_V_SCR_07_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_07_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_V_SCR_07_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_V_SCR_07_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_SCR_07_0_G0R_SHIFT)
#define GPIO_V_SCR_07_0_G0R_RANGE                       0:0
#define GPIO_V_SCR_07_0_G0R_WOFFSET                     0x0
#define GPIO_V_SCR_07_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_SCR_07_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_SCR_07_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_W_VM_00_0
#define GPIO_W_VM_00_0                  _MK_ADDR_CONST(0x1040)
#define GPIO_W_VM_00_0_SECURE                   0x0
#define GPIO_W_VM_00_0_DUAL                     0x0
#define GPIO_W_VM_00_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_W_VM_00_0_WORD_COUNT                       0x1
#define GPIO_W_VM_00_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_W_VM_00_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_W_VM_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_W_VM_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_W_VM_00_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_W_VM_00_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_W_VM_00_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_W_VM_00_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_W_VM_00_0_VM1_SHIFT)
#define GPIO_W_VM_00_0_VM1_RANGE                        1:0
#define GPIO_W_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_W_VM_00_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_W_VM_00_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_W_VM_00_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_W_VM_00_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_W_VM_00_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_W_VM_00_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_W_VM_00_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_W_VM_00_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_W_VM_00_0_VM2_SHIFT)
#define GPIO_W_VM_00_0_VM2_RANGE                        3:2
#define GPIO_W_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_W_VM_00_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_W_VM_00_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_W_VM_00_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_W_VM_00_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_W_VM_00_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_W_VM_00_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_W_VM_00_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_W_VM_00_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_W_VM_00_0_VM3_SHIFT)
#define GPIO_W_VM_00_0_VM3_RANGE                        5:4
#define GPIO_W_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_W_VM_00_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_W_VM_00_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_W_VM_00_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_W_VM_00_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_W_VM_00_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_W_VM_00_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_W_VM_00_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_W_VM_00_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_W_VM_00_0_VM4_SHIFT)
#define GPIO_W_VM_00_0_VM4_RANGE                        7:6
#define GPIO_W_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_W_VM_00_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_W_VM_00_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_W_VM_00_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_W_VM_00_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_W_VM_00_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_W_VM_00_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_W_VM_00_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_W_VM_00_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_W_VM_00_0_VM5_SHIFT)
#define GPIO_W_VM_00_0_VM5_RANGE                        9:8
#define GPIO_W_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_W_VM_00_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_W_VM_00_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_W_VM_00_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_W_VM_00_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_W_VM_00_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_W_VM_00_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_W_VM_00_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_W_VM_00_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_W_VM_00_0_VM6_SHIFT)
#define GPIO_W_VM_00_0_VM6_RANGE                        11:10
#define GPIO_W_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_W_VM_00_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_W_VM_00_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_W_VM_00_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_W_VM_00_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_W_VM_00_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_W_VM_00_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_W_VM_00_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_W_VM_00_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_W_VM_00_0_VM7_SHIFT)
#define GPIO_W_VM_00_0_VM7_RANGE                        13:12
#define GPIO_W_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_W_VM_00_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_W_VM_00_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_W_VM_00_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_W_VM_00_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_W_VM_00_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_W_VM_00_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_W_VM_00_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_W_VM_00_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_W_VM_00_0_VM8_SHIFT)
#define GPIO_W_VM_00_0_VM8_RANGE                        15:14
#define GPIO_W_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_W_VM_00_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_W_VM_00_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_W_VM_00_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_W_VM_00_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_W_VM_00_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_W_VM_00_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_W_SCR_00_0
#define GPIO_W_SCR_00_0                 _MK_ADDR_CONST(0x1044)
#define GPIO_W_SCR_00_0_SECURE                  0x0
#define GPIO_W_SCR_00_0_DUAL                    0x0
#define GPIO_W_SCR_00_0_SCR                     0
#define GPIO_W_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_W_SCR_00_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_W_SCR_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_W_SCR_00_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_W_SCR_00_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_W_SCR_00_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_W_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_W_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_W_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_W_SCR_00_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_W_SCR_00_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_W_SCR_00_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_W_SCR_00_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_W_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_W_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_W_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_W_SCR_00_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_W_SCR_00_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_W_SCR_00_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_W_SCR_00_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_W_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_W_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_W_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_W_SCR_00_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_W_SCR_00_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_W_SCR_00_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_W_SCR_00_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_W_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_W_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_W_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_W_SCR_00_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_W_SCR_00_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_W_SCR_00_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_W_SCR_00_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_W_SCR_00_0_PR7_SHIFT)
#define GPIO_W_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_W_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_W_SCR_00_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_W_SCR_00_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_W_SCR_00_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_W_SCR_00_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_W_SCR_00_0_PR6_SHIFT)
#define GPIO_W_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_W_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_W_SCR_00_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_W_SCR_00_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_W_SCR_00_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_W_SCR_00_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_W_SCR_00_0_PR5_SHIFT)
#define GPIO_W_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_W_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_W_SCR_00_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_W_SCR_00_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_W_SCR_00_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_W_SCR_00_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_W_SCR_00_0_PR4_SHIFT)
#define GPIO_W_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_W_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_W_SCR_00_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_W_SCR_00_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_W_SCR_00_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_W_SCR_00_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_W_SCR_00_0_PR3_SHIFT)
#define GPIO_W_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_W_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_W_SCR_00_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_W_SCR_00_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_W_SCR_00_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_W_SCR_00_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_W_SCR_00_0_PR2_SHIFT)
#define GPIO_W_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_W_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_W_SCR_00_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_W_SCR_00_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_W_SCR_00_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_W_SCR_00_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_W_SCR_00_0_PR1_SHIFT)
#define GPIO_W_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_W_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_W_SCR_00_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_W_SCR_00_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_W_SCR_00_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_W_SCR_00_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_W_SCR_00_0_PR0_SHIFT)
#define GPIO_W_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_W_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_W_SCR_00_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_W_SCR_00_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_W_SCR_00_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_W_SCR_00_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_W_SCR_00_0_G7W_SHIFT)
#define GPIO_W_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_W_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_W_SCR_00_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_W_SCR_00_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_W_SCR_00_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_W_SCR_00_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_W_SCR_00_0_G6W_SHIFT)
#define GPIO_W_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_W_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_W_SCR_00_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_W_SCR_00_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_W_SCR_00_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_W_SCR_00_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_W_SCR_00_0_G5W_SHIFT)
#define GPIO_W_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_W_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_W_SCR_00_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_W_SCR_00_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_W_SCR_00_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_W_SCR_00_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_W_SCR_00_0_G4W_SHIFT)
#define GPIO_W_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_W_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_W_SCR_00_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_W_SCR_00_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_W_SCR_00_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_W_SCR_00_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_W_SCR_00_0_G3W_SHIFT)
#define GPIO_W_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_W_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_W_SCR_00_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_W_SCR_00_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_W_SCR_00_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_W_SCR_00_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_W_SCR_00_0_G2W_SHIFT)
#define GPIO_W_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_W_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_W_SCR_00_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_W_SCR_00_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_W_SCR_00_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_W_SCR_00_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_W_SCR_00_0_G1W_SHIFT)
#define GPIO_W_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_W_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_W_SCR_00_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_W_SCR_00_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_W_SCR_00_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_W_SCR_00_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_W_SCR_00_0_G0W_SHIFT)
#define GPIO_W_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_W_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_W_SCR_00_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_W_SCR_00_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_W_SCR_00_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_W_SCR_00_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_W_SCR_00_0_G7R_SHIFT)
#define GPIO_W_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_W_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_W_SCR_00_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_W_SCR_00_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_W_SCR_00_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_W_SCR_00_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_W_SCR_00_0_G6R_SHIFT)
#define GPIO_W_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_W_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_W_SCR_00_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_W_SCR_00_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_W_SCR_00_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_W_SCR_00_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_W_SCR_00_0_G5R_SHIFT)
#define GPIO_W_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_W_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_W_SCR_00_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_W_SCR_00_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_W_SCR_00_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_W_SCR_00_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_W_SCR_00_0_G4R_SHIFT)
#define GPIO_W_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_W_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_W_SCR_00_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_W_SCR_00_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_W_SCR_00_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_W_SCR_00_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_W_SCR_00_0_G3R_SHIFT)
#define GPIO_W_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_W_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_W_SCR_00_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_W_SCR_00_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_W_SCR_00_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_W_SCR_00_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_W_SCR_00_0_G2R_SHIFT)
#define GPIO_W_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_W_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_W_SCR_00_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_W_SCR_00_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_W_SCR_00_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_W_SCR_00_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_W_SCR_00_0_G1R_SHIFT)
#define GPIO_W_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_W_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_W_SCR_00_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_W_SCR_00_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_W_SCR_00_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_W_SCR_00_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_W_SCR_00_0_G0R_SHIFT)
#define GPIO_W_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_W_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_W_SCR_00_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_W_SCR_00_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_00_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_W_VM_01_0
#define GPIO_W_VM_01_0                  _MK_ADDR_CONST(0x1048)
#define GPIO_W_VM_01_0_SECURE                   0x0
#define GPIO_W_VM_01_0_DUAL                     0x0
#define GPIO_W_VM_01_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_W_VM_01_0_WORD_COUNT                       0x1
#define GPIO_W_VM_01_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_W_VM_01_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_W_VM_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_W_VM_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_W_VM_01_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_W_VM_01_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_W_VM_01_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_W_VM_01_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_W_VM_01_0_VM1_SHIFT)
#define GPIO_W_VM_01_0_VM1_RANGE                        1:0
#define GPIO_W_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_W_VM_01_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_W_VM_01_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_W_VM_01_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_W_VM_01_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_W_VM_01_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_W_VM_01_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_W_VM_01_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_W_VM_01_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_W_VM_01_0_VM2_SHIFT)
#define GPIO_W_VM_01_0_VM2_RANGE                        3:2
#define GPIO_W_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_W_VM_01_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_W_VM_01_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_W_VM_01_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_W_VM_01_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_W_VM_01_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_W_VM_01_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_W_VM_01_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_W_VM_01_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_W_VM_01_0_VM3_SHIFT)
#define GPIO_W_VM_01_0_VM3_RANGE                        5:4
#define GPIO_W_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_W_VM_01_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_W_VM_01_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_W_VM_01_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_W_VM_01_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_W_VM_01_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_W_VM_01_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_W_VM_01_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_W_VM_01_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_W_VM_01_0_VM4_SHIFT)
#define GPIO_W_VM_01_0_VM4_RANGE                        7:6
#define GPIO_W_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_W_VM_01_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_W_VM_01_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_W_VM_01_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_W_VM_01_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_W_VM_01_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_W_VM_01_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_W_VM_01_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_W_VM_01_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_W_VM_01_0_VM5_SHIFT)
#define GPIO_W_VM_01_0_VM5_RANGE                        9:8
#define GPIO_W_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_W_VM_01_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_W_VM_01_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_W_VM_01_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_W_VM_01_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_W_VM_01_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_W_VM_01_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_W_VM_01_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_W_VM_01_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_W_VM_01_0_VM6_SHIFT)
#define GPIO_W_VM_01_0_VM6_RANGE                        11:10
#define GPIO_W_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_W_VM_01_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_W_VM_01_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_W_VM_01_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_W_VM_01_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_W_VM_01_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_W_VM_01_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_W_VM_01_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_W_VM_01_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_W_VM_01_0_VM7_SHIFT)
#define GPIO_W_VM_01_0_VM7_RANGE                        13:12
#define GPIO_W_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_W_VM_01_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_W_VM_01_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_W_VM_01_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_W_VM_01_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_W_VM_01_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_W_VM_01_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_W_VM_01_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_W_VM_01_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_W_VM_01_0_VM8_SHIFT)
#define GPIO_W_VM_01_0_VM8_RANGE                        15:14
#define GPIO_W_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_W_VM_01_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_W_VM_01_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_W_VM_01_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_W_VM_01_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_W_VM_01_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_W_VM_01_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_W_SCR_01_0
#define GPIO_W_SCR_01_0                 _MK_ADDR_CONST(0x104c)
#define GPIO_W_SCR_01_0_SECURE                  0x0
#define GPIO_W_SCR_01_0_DUAL                    0x0
#define GPIO_W_SCR_01_0_SCR                     0
#define GPIO_W_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_W_SCR_01_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_W_SCR_01_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_W_SCR_01_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_W_SCR_01_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_W_SCR_01_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_W_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_W_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_W_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_W_SCR_01_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_W_SCR_01_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_W_SCR_01_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_W_SCR_01_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_W_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_W_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_W_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_W_SCR_01_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_W_SCR_01_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_W_SCR_01_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_W_SCR_01_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_W_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_W_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_W_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_W_SCR_01_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_W_SCR_01_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_W_SCR_01_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_W_SCR_01_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_W_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_W_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_W_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_W_SCR_01_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_W_SCR_01_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_W_SCR_01_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_W_SCR_01_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_W_SCR_01_0_PR7_SHIFT)
#define GPIO_W_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_W_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_W_SCR_01_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_W_SCR_01_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_W_SCR_01_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_W_SCR_01_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_W_SCR_01_0_PR6_SHIFT)
#define GPIO_W_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_W_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_W_SCR_01_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_W_SCR_01_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_W_SCR_01_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_W_SCR_01_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_W_SCR_01_0_PR5_SHIFT)
#define GPIO_W_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_W_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_W_SCR_01_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_W_SCR_01_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_W_SCR_01_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_W_SCR_01_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_W_SCR_01_0_PR4_SHIFT)
#define GPIO_W_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_W_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_W_SCR_01_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_W_SCR_01_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_W_SCR_01_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_W_SCR_01_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_W_SCR_01_0_PR3_SHIFT)
#define GPIO_W_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_W_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_W_SCR_01_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_W_SCR_01_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_W_SCR_01_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_W_SCR_01_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_W_SCR_01_0_PR2_SHIFT)
#define GPIO_W_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_W_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_W_SCR_01_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_W_SCR_01_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_W_SCR_01_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_W_SCR_01_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_W_SCR_01_0_PR1_SHIFT)
#define GPIO_W_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_W_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_W_SCR_01_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_W_SCR_01_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_W_SCR_01_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_W_SCR_01_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_W_SCR_01_0_PR0_SHIFT)
#define GPIO_W_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_W_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_W_SCR_01_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_W_SCR_01_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_W_SCR_01_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_W_SCR_01_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_W_SCR_01_0_G7W_SHIFT)
#define GPIO_W_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_W_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_W_SCR_01_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_W_SCR_01_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_W_SCR_01_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_W_SCR_01_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_W_SCR_01_0_G6W_SHIFT)
#define GPIO_W_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_W_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_W_SCR_01_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_W_SCR_01_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_W_SCR_01_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_W_SCR_01_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_W_SCR_01_0_G5W_SHIFT)
#define GPIO_W_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_W_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_W_SCR_01_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_W_SCR_01_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_W_SCR_01_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_W_SCR_01_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_W_SCR_01_0_G4W_SHIFT)
#define GPIO_W_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_W_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_W_SCR_01_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_W_SCR_01_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_W_SCR_01_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_W_SCR_01_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_W_SCR_01_0_G3W_SHIFT)
#define GPIO_W_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_W_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_W_SCR_01_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_W_SCR_01_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_W_SCR_01_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_W_SCR_01_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_W_SCR_01_0_G2W_SHIFT)
#define GPIO_W_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_W_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_W_SCR_01_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_W_SCR_01_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_W_SCR_01_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_W_SCR_01_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_W_SCR_01_0_G1W_SHIFT)
#define GPIO_W_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_W_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_W_SCR_01_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_W_SCR_01_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_W_SCR_01_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_W_SCR_01_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_W_SCR_01_0_G0W_SHIFT)
#define GPIO_W_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_W_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_W_SCR_01_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_W_SCR_01_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_W_SCR_01_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_W_SCR_01_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_W_SCR_01_0_G7R_SHIFT)
#define GPIO_W_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_W_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_W_SCR_01_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_W_SCR_01_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_W_SCR_01_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_W_SCR_01_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_W_SCR_01_0_G6R_SHIFT)
#define GPIO_W_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_W_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_W_SCR_01_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_W_SCR_01_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_W_SCR_01_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_W_SCR_01_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_W_SCR_01_0_G5R_SHIFT)
#define GPIO_W_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_W_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_W_SCR_01_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_W_SCR_01_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_W_SCR_01_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_W_SCR_01_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_W_SCR_01_0_G4R_SHIFT)
#define GPIO_W_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_W_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_W_SCR_01_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_W_SCR_01_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_W_SCR_01_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_W_SCR_01_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_W_SCR_01_0_G3R_SHIFT)
#define GPIO_W_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_W_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_W_SCR_01_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_W_SCR_01_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_W_SCR_01_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_W_SCR_01_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_W_SCR_01_0_G2R_SHIFT)
#define GPIO_W_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_W_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_W_SCR_01_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_W_SCR_01_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_W_SCR_01_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_W_SCR_01_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_W_SCR_01_0_G1R_SHIFT)
#define GPIO_W_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_W_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_W_SCR_01_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_W_SCR_01_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_W_SCR_01_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_W_SCR_01_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_W_SCR_01_0_G0R_SHIFT)
#define GPIO_W_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_W_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_W_SCR_01_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_W_SCR_01_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_W_SCR_01_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Reserved address 0x1050

// Reserved address 0x1054

// Reserved address 0x1058

// Reserved address 0x105c

// Reserved address 0x1060

// Reserved address 0x1064

// Reserved address 0x1068

// Reserved address 0x106c

// Reserved address 0x1070

// Reserved address 0x1074

// Reserved address 0x1078

// Reserved address 0x107c

// Register GPIO_A_VM_00_0
#define GPIO_A_VM_00_0                  _MK_ADDR_CONST(0x1080)
#define GPIO_A_VM_00_0_SECURE                   0x0
#define GPIO_A_VM_00_0_DUAL                     0x0
#define GPIO_A_VM_00_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_A_VM_00_0_WORD_COUNT                       0x1
#define GPIO_A_VM_00_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_00_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_00_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_00_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_A_VM_00_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_00_0_VM1_SHIFT)
#define GPIO_A_VM_00_0_VM1_RANGE                        1:0
#define GPIO_A_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_A_VM_00_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_00_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_00_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_00_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_A_VM_00_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_00_0_VM2_SHIFT)
#define GPIO_A_VM_00_0_VM2_RANGE                        3:2
#define GPIO_A_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_A_VM_00_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_00_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_00_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_00_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_A_VM_00_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_00_0_VM3_SHIFT)
#define GPIO_A_VM_00_0_VM3_RANGE                        5:4
#define GPIO_A_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_A_VM_00_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_00_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_00_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_00_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_A_VM_00_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_00_0_VM4_SHIFT)
#define GPIO_A_VM_00_0_VM4_RANGE                        7:6
#define GPIO_A_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_A_VM_00_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_00_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_00_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_00_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_A_VM_00_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_00_0_VM5_SHIFT)
#define GPIO_A_VM_00_0_VM5_RANGE                        9:8
#define GPIO_A_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_A_VM_00_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_00_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_00_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_00_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_A_VM_00_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_00_0_VM6_SHIFT)
#define GPIO_A_VM_00_0_VM6_RANGE                        11:10
#define GPIO_A_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_A_VM_00_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_00_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_00_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_00_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_A_VM_00_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_00_0_VM7_SHIFT)
#define GPIO_A_VM_00_0_VM7_RANGE                        13:12
#define GPIO_A_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_A_VM_00_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_00_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_00_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_00_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_A_VM_00_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_00_0_VM8_SHIFT)
#define GPIO_A_VM_00_0_VM8_RANGE                        15:14
#define GPIO_A_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_A_VM_00_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_00_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_00_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_A_SCR_00_0
#define GPIO_A_SCR_00_0                 _MK_ADDR_CONST(0x1084)
#define GPIO_A_SCR_00_0_SECURE                  0x0
#define GPIO_A_SCR_00_0_DUAL                    0x0
#define GPIO_A_SCR_00_0_SCR                     0
#define GPIO_A_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_A_SCR_00_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_00_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_00_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_A_SCR_00_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_A_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_A_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_A_SCR_00_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_00_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_A_SCR_00_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_A_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_A_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_A_SCR_00_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_00_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_A_SCR_00_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_A_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_A_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_A_SCR_00_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_00_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_A_SCR_00_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_A_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_A_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_A_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_A_SCR_00_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_A_SCR_00_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_00_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_A_SCR_00_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_PR7_SHIFT)
#define GPIO_A_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_A_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_00_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_A_SCR_00_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_PR6_SHIFT)
#define GPIO_A_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_A_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_00_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_A_SCR_00_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_PR5_SHIFT)
#define GPIO_A_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_A_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_00_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_A_SCR_00_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_PR4_SHIFT)
#define GPIO_A_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_A_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_00_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_A_SCR_00_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_PR3_SHIFT)
#define GPIO_A_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_A_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_00_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_A_SCR_00_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_PR2_SHIFT)
#define GPIO_A_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_A_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_00_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_A_SCR_00_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_PR1_SHIFT)
#define GPIO_A_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_A_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_00_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_A_SCR_00_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_PR0_SHIFT)
#define GPIO_A_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_A_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_00_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_A_SCR_00_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G7W_SHIFT)
#define GPIO_A_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_A_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_00_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_A_SCR_00_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G6W_SHIFT)
#define GPIO_A_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_A_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_00_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_A_SCR_00_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G5W_SHIFT)
#define GPIO_A_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_A_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_00_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_A_SCR_00_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G4W_SHIFT)
#define GPIO_A_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_A_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_00_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_A_SCR_00_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G3W_SHIFT)
#define GPIO_A_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_A_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_00_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_A_SCR_00_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G2W_SHIFT)
#define GPIO_A_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_A_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_00_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_A_SCR_00_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G1W_SHIFT)
#define GPIO_A_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_A_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_00_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_A_SCR_00_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G0W_SHIFT)
#define GPIO_A_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_A_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_00_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_A_SCR_00_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G7R_SHIFT)
#define GPIO_A_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_A_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_00_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_A_SCR_00_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G6R_SHIFT)
#define GPIO_A_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_A_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_00_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_A_SCR_00_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G5R_SHIFT)
#define GPIO_A_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_A_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_00_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_A_SCR_00_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G4R_SHIFT)
#define GPIO_A_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_A_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_00_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_A_SCR_00_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G3R_SHIFT)
#define GPIO_A_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_A_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_00_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_A_SCR_00_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G2R_SHIFT)
#define GPIO_A_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_A_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_00_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_A_SCR_00_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G1R_SHIFT)
#define GPIO_A_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_A_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_00_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_A_SCR_00_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G0R_SHIFT)
#define GPIO_A_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_A_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_A_VM_01_0
#define GPIO_A_VM_01_0                  _MK_ADDR_CONST(0x1088)
#define GPIO_A_VM_01_0_SECURE                   0x0
#define GPIO_A_VM_01_0_DUAL                     0x0
#define GPIO_A_VM_01_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_A_VM_01_0_WORD_COUNT                       0x1
#define GPIO_A_VM_01_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_01_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_01_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_01_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_A_VM_01_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_01_0_VM1_SHIFT)
#define GPIO_A_VM_01_0_VM1_RANGE                        1:0
#define GPIO_A_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_A_VM_01_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_01_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_01_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_01_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_A_VM_01_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_01_0_VM2_SHIFT)
#define GPIO_A_VM_01_0_VM2_RANGE                        3:2
#define GPIO_A_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_A_VM_01_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_01_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_01_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_01_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_A_VM_01_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_01_0_VM3_SHIFT)
#define GPIO_A_VM_01_0_VM3_RANGE                        5:4
#define GPIO_A_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_A_VM_01_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_01_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_01_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_01_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_A_VM_01_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_01_0_VM4_SHIFT)
#define GPIO_A_VM_01_0_VM4_RANGE                        7:6
#define GPIO_A_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_A_VM_01_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_01_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_01_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_01_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_A_VM_01_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_01_0_VM5_SHIFT)
#define GPIO_A_VM_01_0_VM5_RANGE                        9:8
#define GPIO_A_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_A_VM_01_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_01_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_01_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_01_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_A_VM_01_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_01_0_VM6_SHIFT)
#define GPIO_A_VM_01_0_VM6_RANGE                        11:10
#define GPIO_A_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_A_VM_01_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_01_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_01_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_01_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_A_VM_01_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_01_0_VM7_SHIFT)
#define GPIO_A_VM_01_0_VM7_RANGE                        13:12
#define GPIO_A_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_A_VM_01_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_01_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_01_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_01_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_A_VM_01_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_01_0_VM8_SHIFT)
#define GPIO_A_VM_01_0_VM8_RANGE                        15:14
#define GPIO_A_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_A_VM_01_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_01_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_01_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_A_SCR_01_0
#define GPIO_A_SCR_01_0                 _MK_ADDR_CONST(0x108c)
#define GPIO_A_SCR_01_0_SECURE                  0x0
#define GPIO_A_SCR_01_0_DUAL                    0x0
#define GPIO_A_SCR_01_0_SCR                     0
#define GPIO_A_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_A_SCR_01_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_01_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_01_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_01_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_A_SCR_01_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_A_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_A_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_A_SCR_01_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_01_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_A_SCR_01_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_A_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_A_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_A_SCR_01_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_01_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_A_SCR_01_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_A_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_A_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_A_SCR_01_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_01_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_A_SCR_01_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_A_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_A_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_A_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_A_SCR_01_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_A_SCR_01_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_01_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_A_SCR_01_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_PR7_SHIFT)
#define GPIO_A_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_A_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_01_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_A_SCR_01_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_PR6_SHIFT)
#define GPIO_A_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_A_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_01_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_A_SCR_01_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_PR5_SHIFT)
#define GPIO_A_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_A_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_01_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_A_SCR_01_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_PR4_SHIFT)
#define GPIO_A_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_A_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_01_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_A_SCR_01_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_PR3_SHIFT)
#define GPIO_A_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_A_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_01_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_A_SCR_01_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_PR2_SHIFT)
#define GPIO_A_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_A_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_01_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_A_SCR_01_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_PR1_SHIFT)
#define GPIO_A_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_A_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_01_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_A_SCR_01_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_PR0_SHIFT)
#define GPIO_A_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_A_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_01_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_A_SCR_01_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G7W_SHIFT)
#define GPIO_A_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_A_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_01_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_A_SCR_01_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G6W_SHIFT)
#define GPIO_A_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_A_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_01_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_A_SCR_01_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G5W_SHIFT)
#define GPIO_A_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_A_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_01_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_A_SCR_01_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G4W_SHIFT)
#define GPIO_A_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_A_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_01_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_A_SCR_01_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G3W_SHIFT)
#define GPIO_A_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_A_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_01_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_A_SCR_01_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G2W_SHIFT)
#define GPIO_A_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_A_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_01_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_A_SCR_01_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G1W_SHIFT)
#define GPIO_A_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_A_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_01_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_A_SCR_01_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G0W_SHIFT)
#define GPIO_A_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_A_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_01_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_A_SCR_01_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G7R_SHIFT)
#define GPIO_A_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_A_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_01_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_A_SCR_01_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G6R_SHIFT)
#define GPIO_A_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_A_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_01_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_A_SCR_01_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G5R_SHIFT)
#define GPIO_A_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_A_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_01_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_A_SCR_01_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G4R_SHIFT)
#define GPIO_A_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_A_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_01_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_A_SCR_01_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G3R_SHIFT)
#define GPIO_A_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_A_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_01_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_A_SCR_01_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G2R_SHIFT)
#define GPIO_A_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_A_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_01_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_A_SCR_01_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G1R_SHIFT)
#define GPIO_A_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_A_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_01_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_A_SCR_01_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G0R_SHIFT)
#define GPIO_A_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_A_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_A_VM_02_0
#define GPIO_A_VM_02_0                  _MK_ADDR_CONST(0x1090)
#define GPIO_A_VM_02_0_SECURE                   0x0
#define GPIO_A_VM_02_0_DUAL                     0x0
#define GPIO_A_VM_02_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_A_VM_02_0_WORD_COUNT                       0x1
#define GPIO_A_VM_02_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_02_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_02_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_02_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_A_VM_02_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_02_0_VM1_SHIFT)
#define GPIO_A_VM_02_0_VM1_RANGE                        1:0
#define GPIO_A_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_A_VM_02_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_02_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_02_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_02_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_A_VM_02_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_02_0_VM2_SHIFT)
#define GPIO_A_VM_02_0_VM2_RANGE                        3:2
#define GPIO_A_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_A_VM_02_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_02_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_02_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_02_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_A_VM_02_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_02_0_VM3_SHIFT)
#define GPIO_A_VM_02_0_VM3_RANGE                        5:4
#define GPIO_A_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_A_VM_02_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_02_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_02_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_02_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_A_VM_02_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_02_0_VM4_SHIFT)
#define GPIO_A_VM_02_0_VM4_RANGE                        7:6
#define GPIO_A_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_A_VM_02_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_02_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_02_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_02_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_A_VM_02_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_02_0_VM5_SHIFT)
#define GPIO_A_VM_02_0_VM5_RANGE                        9:8
#define GPIO_A_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_A_VM_02_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_02_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_02_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_02_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_A_VM_02_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_02_0_VM6_SHIFT)
#define GPIO_A_VM_02_0_VM6_RANGE                        11:10
#define GPIO_A_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_A_VM_02_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_02_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_02_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_02_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_A_VM_02_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_02_0_VM7_SHIFT)
#define GPIO_A_VM_02_0_VM7_RANGE                        13:12
#define GPIO_A_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_A_VM_02_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_02_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_02_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_02_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_A_VM_02_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_02_0_VM8_SHIFT)
#define GPIO_A_VM_02_0_VM8_RANGE                        15:14
#define GPIO_A_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_A_VM_02_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_02_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_02_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_A_SCR_02_0
#define GPIO_A_SCR_02_0                 _MK_ADDR_CONST(0x1094)
#define GPIO_A_SCR_02_0_SECURE                  0x0
#define GPIO_A_SCR_02_0_DUAL                    0x0
#define GPIO_A_SCR_02_0_SCR                     0
#define GPIO_A_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_A_SCR_02_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_02_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_02_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_02_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_A_SCR_02_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_A_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_A_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_A_SCR_02_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_02_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_A_SCR_02_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_A_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_A_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_A_SCR_02_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_02_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_A_SCR_02_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_A_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_A_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_A_SCR_02_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_02_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_A_SCR_02_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_A_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_A_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_A_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_A_SCR_02_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_A_SCR_02_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_02_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_A_SCR_02_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_PR7_SHIFT)
#define GPIO_A_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_A_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_02_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_A_SCR_02_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_PR6_SHIFT)
#define GPIO_A_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_A_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_02_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_A_SCR_02_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_PR5_SHIFT)
#define GPIO_A_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_A_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_02_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_A_SCR_02_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_PR4_SHIFT)
#define GPIO_A_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_A_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_02_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_A_SCR_02_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_PR3_SHIFT)
#define GPIO_A_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_A_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_02_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_A_SCR_02_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_PR2_SHIFT)
#define GPIO_A_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_A_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_02_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_A_SCR_02_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_PR1_SHIFT)
#define GPIO_A_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_A_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_02_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_A_SCR_02_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_PR0_SHIFT)
#define GPIO_A_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_A_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_02_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_A_SCR_02_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G7W_SHIFT)
#define GPIO_A_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_A_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_02_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_A_SCR_02_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G6W_SHIFT)
#define GPIO_A_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_A_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_02_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_A_SCR_02_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G5W_SHIFT)
#define GPIO_A_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_A_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_02_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_A_SCR_02_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G4W_SHIFT)
#define GPIO_A_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_A_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_02_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_A_SCR_02_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G3W_SHIFT)
#define GPIO_A_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_A_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_02_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_A_SCR_02_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G2W_SHIFT)
#define GPIO_A_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_A_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_02_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_A_SCR_02_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G1W_SHIFT)
#define GPIO_A_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_A_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_02_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_A_SCR_02_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G0W_SHIFT)
#define GPIO_A_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_A_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_02_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_A_SCR_02_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G7R_SHIFT)
#define GPIO_A_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_A_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_02_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_A_SCR_02_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G6R_SHIFT)
#define GPIO_A_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_A_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_02_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_A_SCR_02_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G5R_SHIFT)
#define GPIO_A_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_A_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_02_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_A_SCR_02_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G4R_SHIFT)
#define GPIO_A_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_A_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_02_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_A_SCR_02_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G3R_SHIFT)
#define GPIO_A_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_A_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_02_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_A_SCR_02_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G2R_SHIFT)
#define GPIO_A_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_A_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_02_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_A_SCR_02_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G1R_SHIFT)
#define GPIO_A_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_A_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_02_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_A_SCR_02_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G0R_SHIFT)
#define GPIO_A_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_A_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_A_VM_03_0
#define GPIO_A_VM_03_0                  _MK_ADDR_CONST(0x1098)
#define GPIO_A_VM_03_0_SECURE                   0x0
#define GPIO_A_VM_03_0_DUAL                     0x0
#define GPIO_A_VM_03_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_A_VM_03_0_WORD_COUNT                       0x1
#define GPIO_A_VM_03_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_03_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_03_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_03_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_A_VM_03_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_03_0_VM1_SHIFT)
#define GPIO_A_VM_03_0_VM1_RANGE                        1:0
#define GPIO_A_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_A_VM_03_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_03_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_03_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_03_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_A_VM_03_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_03_0_VM2_SHIFT)
#define GPIO_A_VM_03_0_VM2_RANGE                        3:2
#define GPIO_A_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_A_VM_03_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_03_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_03_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_03_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_A_VM_03_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_03_0_VM3_SHIFT)
#define GPIO_A_VM_03_0_VM3_RANGE                        5:4
#define GPIO_A_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_A_VM_03_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_03_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_03_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_03_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_A_VM_03_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_03_0_VM4_SHIFT)
#define GPIO_A_VM_03_0_VM4_RANGE                        7:6
#define GPIO_A_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_A_VM_03_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_03_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_03_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_03_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_A_VM_03_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_03_0_VM5_SHIFT)
#define GPIO_A_VM_03_0_VM5_RANGE                        9:8
#define GPIO_A_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_A_VM_03_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_03_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_03_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_03_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_A_VM_03_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_03_0_VM6_SHIFT)
#define GPIO_A_VM_03_0_VM6_RANGE                        11:10
#define GPIO_A_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_A_VM_03_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_03_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_03_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_03_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_A_VM_03_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_03_0_VM7_SHIFT)
#define GPIO_A_VM_03_0_VM7_RANGE                        13:12
#define GPIO_A_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_A_VM_03_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_03_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_03_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_03_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_A_VM_03_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_03_0_VM8_SHIFT)
#define GPIO_A_VM_03_0_VM8_RANGE                        15:14
#define GPIO_A_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_A_VM_03_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_03_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_03_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_A_SCR_03_0
#define GPIO_A_SCR_03_0                 _MK_ADDR_CONST(0x109c)
#define GPIO_A_SCR_03_0_SECURE                  0x0
#define GPIO_A_SCR_03_0_DUAL                    0x0
#define GPIO_A_SCR_03_0_SCR                     0
#define GPIO_A_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_A_SCR_03_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_03_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_03_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_03_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_A_SCR_03_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_A_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_A_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_A_SCR_03_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_03_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_A_SCR_03_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_A_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_A_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_A_SCR_03_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_03_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_A_SCR_03_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_A_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_A_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_A_SCR_03_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_03_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_A_SCR_03_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_A_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_A_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_A_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_A_SCR_03_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_A_SCR_03_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_03_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_A_SCR_03_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_PR7_SHIFT)
#define GPIO_A_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_A_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_03_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_A_SCR_03_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_PR6_SHIFT)
#define GPIO_A_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_A_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_03_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_A_SCR_03_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_PR5_SHIFT)
#define GPIO_A_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_A_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_03_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_A_SCR_03_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_PR4_SHIFT)
#define GPIO_A_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_A_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_03_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_A_SCR_03_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_PR3_SHIFT)
#define GPIO_A_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_A_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_03_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_A_SCR_03_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_PR2_SHIFT)
#define GPIO_A_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_A_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_03_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_A_SCR_03_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_PR1_SHIFT)
#define GPIO_A_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_A_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_03_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_A_SCR_03_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_PR0_SHIFT)
#define GPIO_A_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_A_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_03_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_A_SCR_03_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G7W_SHIFT)
#define GPIO_A_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_A_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_03_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_A_SCR_03_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G6W_SHIFT)
#define GPIO_A_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_A_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_03_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_A_SCR_03_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G5W_SHIFT)
#define GPIO_A_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_A_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_03_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_A_SCR_03_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G4W_SHIFT)
#define GPIO_A_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_A_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_03_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_A_SCR_03_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G3W_SHIFT)
#define GPIO_A_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_A_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_03_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_A_SCR_03_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G2W_SHIFT)
#define GPIO_A_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_A_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_03_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_A_SCR_03_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G1W_SHIFT)
#define GPIO_A_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_A_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_03_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_A_SCR_03_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G0W_SHIFT)
#define GPIO_A_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_A_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_03_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_A_SCR_03_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G7R_SHIFT)
#define GPIO_A_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_A_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_03_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_A_SCR_03_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G6R_SHIFT)
#define GPIO_A_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_A_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_03_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_A_SCR_03_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G5R_SHIFT)
#define GPIO_A_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_A_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_03_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_A_SCR_03_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G4R_SHIFT)
#define GPIO_A_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_A_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_03_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_A_SCR_03_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G3R_SHIFT)
#define GPIO_A_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_A_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_03_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_A_SCR_03_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G2R_SHIFT)
#define GPIO_A_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_A_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_03_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_A_SCR_03_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G1R_SHIFT)
#define GPIO_A_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_A_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_03_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_A_SCR_03_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G0R_SHIFT)
#define GPIO_A_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_A_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_A_VM_04_0
#define GPIO_A_VM_04_0                  _MK_ADDR_CONST(0x10a0)
#define GPIO_A_VM_04_0_SECURE                   0x0
#define GPIO_A_VM_04_0_DUAL                     0x0
#define GPIO_A_VM_04_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_A_VM_04_0_WORD_COUNT                       0x1
#define GPIO_A_VM_04_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_04_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_04_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_04_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_A_VM_04_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_04_0_VM1_SHIFT)
#define GPIO_A_VM_04_0_VM1_RANGE                        1:0
#define GPIO_A_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_A_VM_04_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_04_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_04_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_04_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_A_VM_04_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_04_0_VM2_SHIFT)
#define GPIO_A_VM_04_0_VM2_RANGE                        3:2
#define GPIO_A_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_A_VM_04_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_04_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_04_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_04_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_A_VM_04_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_04_0_VM3_SHIFT)
#define GPIO_A_VM_04_0_VM3_RANGE                        5:4
#define GPIO_A_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_A_VM_04_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_04_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_04_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_04_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_A_VM_04_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_04_0_VM4_SHIFT)
#define GPIO_A_VM_04_0_VM4_RANGE                        7:6
#define GPIO_A_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_A_VM_04_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_04_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_04_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_04_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_A_VM_04_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_04_0_VM5_SHIFT)
#define GPIO_A_VM_04_0_VM5_RANGE                        9:8
#define GPIO_A_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_A_VM_04_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_04_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_04_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_04_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_A_VM_04_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_04_0_VM6_SHIFT)
#define GPIO_A_VM_04_0_VM6_RANGE                        11:10
#define GPIO_A_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_A_VM_04_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_04_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_04_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_04_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_A_VM_04_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_04_0_VM7_SHIFT)
#define GPIO_A_VM_04_0_VM7_RANGE                        13:12
#define GPIO_A_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_A_VM_04_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_04_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_04_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_04_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_A_VM_04_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_04_0_VM8_SHIFT)
#define GPIO_A_VM_04_0_VM8_RANGE                        15:14
#define GPIO_A_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_A_VM_04_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_04_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_04_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_A_SCR_04_0
#define GPIO_A_SCR_04_0                 _MK_ADDR_CONST(0x10a4)
#define GPIO_A_SCR_04_0_SECURE                  0x0
#define GPIO_A_SCR_04_0_DUAL                    0x0
#define GPIO_A_SCR_04_0_SCR                     0
#define GPIO_A_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_A_SCR_04_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_04_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_04_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_04_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_A_SCR_04_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_A_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_A_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_A_SCR_04_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_04_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_A_SCR_04_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_A_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_A_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_A_SCR_04_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_04_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_A_SCR_04_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_A_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_A_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_A_SCR_04_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_04_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_A_SCR_04_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_A_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_A_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_A_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_A_SCR_04_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_A_SCR_04_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_04_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_A_SCR_04_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_PR7_SHIFT)
#define GPIO_A_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_A_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_04_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_A_SCR_04_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_PR6_SHIFT)
#define GPIO_A_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_A_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_04_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_A_SCR_04_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_PR5_SHIFT)
#define GPIO_A_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_A_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_04_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_A_SCR_04_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_PR4_SHIFT)
#define GPIO_A_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_A_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_04_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_A_SCR_04_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_PR3_SHIFT)
#define GPIO_A_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_A_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_04_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_A_SCR_04_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_PR2_SHIFT)
#define GPIO_A_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_A_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_04_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_A_SCR_04_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_PR1_SHIFT)
#define GPIO_A_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_A_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_04_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_A_SCR_04_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_PR0_SHIFT)
#define GPIO_A_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_A_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_04_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_A_SCR_04_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G7W_SHIFT)
#define GPIO_A_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_A_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_04_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_A_SCR_04_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G6W_SHIFT)
#define GPIO_A_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_A_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_04_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_A_SCR_04_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G5W_SHIFT)
#define GPIO_A_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_A_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_04_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_A_SCR_04_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G4W_SHIFT)
#define GPIO_A_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_A_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_04_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_A_SCR_04_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G3W_SHIFT)
#define GPIO_A_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_A_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_04_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_A_SCR_04_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G2W_SHIFT)
#define GPIO_A_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_A_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_04_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_A_SCR_04_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G1W_SHIFT)
#define GPIO_A_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_A_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_04_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_A_SCR_04_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G0W_SHIFT)
#define GPIO_A_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_A_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_04_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_A_SCR_04_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G7R_SHIFT)
#define GPIO_A_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_A_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_04_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_A_SCR_04_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G6R_SHIFT)
#define GPIO_A_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_A_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_04_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_A_SCR_04_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G5R_SHIFT)
#define GPIO_A_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_A_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_04_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_A_SCR_04_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G4R_SHIFT)
#define GPIO_A_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_A_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_04_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_A_SCR_04_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G3R_SHIFT)
#define GPIO_A_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_A_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_04_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_A_SCR_04_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G2R_SHIFT)
#define GPIO_A_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_A_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_04_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_A_SCR_04_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G1R_SHIFT)
#define GPIO_A_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_A_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_04_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_A_SCR_04_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G0R_SHIFT)
#define GPIO_A_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_A_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_A_VM_05_0
#define GPIO_A_VM_05_0                  _MK_ADDR_CONST(0x10a8)
#define GPIO_A_VM_05_0_SECURE                   0x0
#define GPIO_A_VM_05_0_DUAL                     0x0
#define GPIO_A_VM_05_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_A_VM_05_0_WORD_COUNT                       0x1
#define GPIO_A_VM_05_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_05_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_05_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_05_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_A_VM_05_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_05_0_VM1_SHIFT)
#define GPIO_A_VM_05_0_VM1_RANGE                        1:0
#define GPIO_A_VM_05_0_VM1_WOFFSET                      0x0
#define GPIO_A_VM_05_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_05_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_05_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_05_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_A_VM_05_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_05_0_VM2_SHIFT)
#define GPIO_A_VM_05_0_VM2_RANGE                        3:2
#define GPIO_A_VM_05_0_VM2_WOFFSET                      0x0
#define GPIO_A_VM_05_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_05_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_05_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_05_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_A_VM_05_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_05_0_VM3_SHIFT)
#define GPIO_A_VM_05_0_VM3_RANGE                        5:4
#define GPIO_A_VM_05_0_VM3_WOFFSET                      0x0
#define GPIO_A_VM_05_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_05_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_05_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_05_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_A_VM_05_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_05_0_VM4_SHIFT)
#define GPIO_A_VM_05_0_VM4_RANGE                        7:6
#define GPIO_A_VM_05_0_VM4_WOFFSET                      0x0
#define GPIO_A_VM_05_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_05_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_05_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_05_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_A_VM_05_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_05_0_VM5_SHIFT)
#define GPIO_A_VM_05_0_VM5_RANGE                        9:8
#define GPIO_A_VM_05_0_VM5_WOFFSET                      0x0
#define GPIO_A_VM_05_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_05_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_05_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_05_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_A_VM_05_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_05_0_VM6_SHIFT)
#define GPIO_A_VM_05_0_VM6_RANGE                        11:10
#define GPIO_A_VM_05_0_VM6_WOFFSET                      0x0
#define GPIO_A_VM_05_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_05_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_05_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_05_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_A_VM_05_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_05_0_VM7_SHIFT)
#define GPIO_A_VM_05_0_VM7_RANGE                        13:12
#define GPIO_A_VM_05_0_VM7_WOFFSET                      0x0
#define GPIO_A_VM_05_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_05_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_05_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_05_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_A_VM_05_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_05_0_VM8_SHIFT)
#define GPIO_A_VM_05_0_VM8_RANGE                        15:14
#define GPIO_A_VM_05_0_VM8_WOFFSET                      0x0
#define GPIO_A_VM_05_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_05_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_05_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_A_SCR_05_0
#define GPIO_A_SCR_05_0                 _MK_ADDR_CONST(0x10ac)
#define GPIO_A_SCR_05_0_SECURE                  0x0
#define GPIO_A_SCR_05_0_DUAL                    0x0
#define GPIO_A_SCR_05_0_SCR                     0
#define GPIO_A_SCR_05_0_WORD_COUNT                      0x1
#define GPIO_A_SCR_05_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_05_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_05_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_05_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_A_SCR_05_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_A_SCR_05_0_SEC_LCK_RANGE                   29:29
#define GPIO_A_SCR_05_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_A_SCR_05_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_05_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_A_SCR_05_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_A_SCR_05_0_SEC_WEN_RANGE                   28:28
#define GPIO_A_SCR_05_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_A_SCR_05_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_05_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_A_SCR_05_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_A_SCR_05_0_SEC_REN_RANGE                   27:27
#define GPIO_A_SCR_05_0_SEC_REN_WOFFSET                 0x0
#define GPIO_A_SCR_05_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_05_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_A_SCR_05_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_A_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_A_SCR_05_0_SEC_OWNER_RANGE                 26:24
#define GPIO_A_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_A_SCR_05_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_A_SCR_05_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_05_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_A_SCR_05_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_PR7_SHIFT)
#define GPIO_A_SCR_05_0_PR7_RANGE                       23:23
#define GPIO_A_SCR_05_0_PR7_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_05_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_A_SCR_05_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_PR6_SHIFT)
#define GPIO_A_SCR_05_0_PR6_RANGE                       22:22
#define GPIO_A_SCR_05_0_PR6_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_05_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_A_SCR_05_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_PR5_SHIFT)
#define GPIO_A_SCR_05_0_PR5_RANGE                       21:21
#define GPIO_A_SCR_05_0_PR5_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_05_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_A_SCR_05_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_PR4_SHIFT)
#define GPIO_A_SCR_05_0_PR4_RANGE                       20:20
#define GPIO_A_SCR_05_0_PR4_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_05_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_A_SCR_05_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_PR3_SHIFT)
#define GPIO_A_SCR_05_0_PR3_RANGE                       19:19
#define GPIO_A_SCR_05_0_PR3_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_05_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_A_SCR_05_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_PR2_SHIFT)
#define GPIO_A_SCR_05_0_PR2_RANGE                       18:18
#define GPIO_A_SCR_05_0_PR2_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_05_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_A_SCR_05_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_PR1_SHIFT)
#define GPIO_A_SCR_05_0_PR1_RANGE                       17:17
#define GPIO_A_SCR_05_0_PR1_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_05_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_A_SCR_05_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_PR0_SHIFT)
#define GPIO_A_SCR_05_0_PR0_RANGE                       16:16
#define GPIO_A_SCR_05_0_PR0_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_05_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_A_SCR_05_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G7W_SHIFT)
#define GPIO_A_SCR_05_0_G7W_RANGE                       15:15
#define GPIO_A_SCR_05_0_G7W_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_05_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_A_SCR_05_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G6W_SHIFT)
#define GPIO_A_SCR_05_0_G6W_RANGE                       14:14
#define GPIO_A_SCR_05_0_G6W_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_05_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_A_SCR_05_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G5W_SHIFT)
#define GPIO_A_SCR_05_0_G5W_RANGE                       13:13
#define GPIO_A_SCR_05_0_G5W_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_05_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_A_SCR_05_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G4W_SHIFT)
#define GPIO_A_SCR_05_0_G4W_RANGE                       12:12
#define GPIO_A_SCR_05_0_G4W_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_05_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_A_SCR_05_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G3W_SHIFT)
#define GPIO_A_SCR_05_0_G3W_RANGE                       11:11
#define GPIO_A_SCR_05_0_G3W_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_05_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_A_SCR_05_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G2W_SHIFT)
#define GPIO_A_SCR_05_0_G2W_RANGE                       10:10
#define GPIO_A_SCR_05_0_G2W_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_05_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_A_SCR_05_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G1W_SHIFT)
#define GPIO_A_SCR_05_0_G1W_RANGE                       9:9
#define GPIO_A_SCR_05_0_G1W_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_05_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_A_SCR_05_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G0W_SHIFT)
#define GPIO_A_SCR_05_0_G0W_RANGE                       8:8
#define GPIO_A_SCR_05_0_G0W_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_05_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_A_SCR_05_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G7R_SHIFT)
#define GPIO_A_SCR_05_0_G7R_RANGE                       7:7
#define GPIO_A_SCR_05_0_G7R_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_05_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_A_SCR_05_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G6R_SHIFT)
#define GPIO_A_SCR_05_0_G6R_RANGE                       6:6
#define GPIO_A_SCR_05_0_G6R_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_05_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_A_SCR_05_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G5R_SHIFT)
#define GPIO_A_SCR_05_0_G5R_RANGE                       5:5
#define GPIO_A_SCR_05_0_G5R_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_05_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_A_SCR_05_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G4R_SHIFT)
#define GPIO_A_SCR_05_0_G4R_RANGE                       4:4
#define GPIO_A_SCR_05_0_G4R_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_05_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_A_SCR_05_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G3R_SHIFT)
#define GPIO_A_SCR_05_0_G3R_RANGE                       3:3
#define GPIO_A_SCR_05_0_G3R_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_05_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_A_SCR_05_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G2R_SHIFT)
#define GPIO_A_SCR_05_0_G2R_RANGE                       2:2
#define GPIO_A_SCR_05_0_G2R_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_05_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_A_SCR_05_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G1R_SHIFT)
#define GPIO_A_SCR_05_0_G1R_RANGE                       1:1
#define GPIO_A_SCR_05_0_G1R_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_05_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_A_SCR_05_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G0R_SHIFT)
#define GPIO_A_SCR_05_0_G0R_RANGE                       0:0
#define GPIO_A_SCR_05_0_G0R_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_A_VM_06_0
#define GPIO_A_VM_06_0                  _MK_ADDR_CONST(0x10b0)
#define GPIO_A_VM_06_0_SECURE                   0x0
#define GPIO_A_VM_06_0_DUAL                     0x0
#define GPIO_A_VM_06_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_A_VM_06_0_WORD_COUNT                       0x1
#define GPIO_A_VM_06_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_06_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_06_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_06_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_06_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_A_VM_06_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_06_0_VM1_SHIFT)
#define GPIO_A_VM_06_0_VM1_RANGE                        1:0
#define GPIO_A_VM_06_0_VM1_WOFFSET                      0x0
#define GPIO_A_VM_06_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_06_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_06_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_06_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_A_VM_06_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_06_0_VM2_SHIFT)
#define GPIO_A_VM_06_0_VM2_RANGE                        3:2
#define GPIO_A_VM_06_0_VM2_WOFFSET                      0x0
#define GPIO_A_VM_06_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_06_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_06_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_06_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_A_VM_06_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_06_0_VM3_SHIFT)
#define GPIO_A_VM_06_0_VM3_RANGE                        5:4
#define GPIO_A_VM_06_0_VM3_WOFFSET                      0x0
#define GPIO_A_VM_06_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_06_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_06_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_06_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_A_VM_06_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_06_0_VM4_SHIFT)
#define GPIO_A_VM_06_0_VM4_RANGE                        7:6
#define GPIO_A_VM_06_0_VM4_WOFFSET                      0x0
#define GPIO_A_VM_06_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_06_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_06_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_06_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_A_VM_06_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_06_0_VM5_SHIFT)
#define GPIO_A_VM_06_0_VM5_RANGE                        9:8
#define GPIO_A_VM_06_0_VM5_WOFFSET                      0x0
#define GPIO_A_VM_06_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_06_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_06_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_06_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_A_VM_06_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_06_0_VM6_SHIFT)
#define GPIO_A_VM_06_0_VM6_RANGE                        11:10
#define GPIO_A_VM_06_0_VM6_WOFFSET                      0x0
#define GPIO_A_VM_06_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_06_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_06_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_06_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_A_VM_06_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_06_0_VM7_SHIFT)
#define GPIO_A_VM_06_0_VM7_RANGE                        13:12
#define GPIO_A_VM_06_0_VM7_WOFFSET                      0x0
#define GPIO_A_VM_06_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_06_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_06_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_06_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_A_VM_06_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_06_0_VM8_SHIFT)
#define GPIO_A_VM_06_0_VM8_RANGE                        15:14
#define GPIO_A_VM_06_0_VM8_WOFFSET                      0x0
#define GPIO_A_VM_06_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_06_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_06_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_A_SCR_06_0
#define GPIO_A_SCR_06_0                 _MK_ADDR_CONST(0x10b4)
#define GPIO_A_SCR_06_0_SECURE                  0x0
#define GPIO_A_SCR_06_0_DUAL                    0x0
#define GPIO_A_SCR_06_0_SCR                     0
#define GPIO_A_SCR_06_0_WORD_COUNT                      0x1
#define GPIO_A_SCR_06_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_06_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_06_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_06_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_A_SCR_06_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_SEC_LCK_SHIFT)
#define GPIO_A_SCR_06_0_SEC_LCK_RANGE                   29:29
#define GPIO_A_SCR_06_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_A_SCR_06_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_06_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_A_SCR_06_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_SEC_WEN_SHIFT)
#define GPIO_A_SCR_06_0_SEC_WEN_RANGE                   28:28
#define GPIO_A_SCR_06_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_A_SCR_06_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_06_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_A_SCR_06_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_SEC_REN_SHIFT)
#define GPIO_A_SCR_06_0_SEC_REN_RANGE                   27:27
#define GPIO_A_SCR_06_0_SEC_REN_WOFFSET                 0x0
#define GPIO_A_SCR_06_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_06_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_A_SCR_06_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_A_SCR_06_0_SEC_OWNER_SHIFT)
#define GPIO_A_SCR_06_0_SEC_OWNER_RANGE                 26:24
#define GPIO_A_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_A_SCR_06_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_A_SCR_06_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_06_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_A_SCR_06_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_PR7_SHIFT)
#define GPIO_A_SCR_06_0_PR7_RANGE                       23:23
#define GPIO_A_SCR_06_0_PR7_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_06_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_A_SCR_06_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_PR6_SHIFT)
#define GPIO_A_SCR_06_0_PR6_RANGE                       22:22
#define GPIO_A_SCR_06_0_PR6_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_06_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_A_SCR_06_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_PR5_SHIFT)
#define GPIO_A_SCR_06_0_PR5_RANGE                       21:21
#define GPIO_A_SCR_06_0_PR5_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_06_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_A_SCR_06_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_PR4_SHIFT)
#define GPIO_A_SCR_06_0_PR4_RANGE                       20:20
#define GPIO_A_SCR_06_0_PR4_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_06_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_A_SCR_06_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_PR3_SHIFT)
#define GPIO_A_SCR_06_0_PR3_RANGE                       19:19
#define GPIO_A_SCR_06_0_PR3_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_06_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_A_SCR_06_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_PR2_SHIFT)
#define GPIO_A_SCR_06_0_PR2_RANGE                       18:18
#define GPIO_A_SCR_06_0_PR2_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_06_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_A_SCR_06_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_PR1_SHIFT)
#define GPIO_A_SCR_06_0_PR1_RANGE                       17:17
#define GPIO_A_SCR_06_0_PR1_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_06_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_A_SCR_06_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_PR0_SHIFT)
#define GPIO_A_SCR_06_0_PR0_RANGE                       16:16
#define GPIO_A_SCR_06_0_PR0_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_06_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_A_SCR_06_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G7W_SHIFT)
#define GPIO_A_SCR_06_0_G7W_RANGE                       15:15
#define GPIO_A_SCR_06_0_G7W_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_06_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_A_SCR_06_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G6W_SHIFT)
#define GPIO_A_SCR_06_0_G6W_RANGE                       14:14
#define GPIO_A_SCR_06_0_G6W_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_06_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_A_SCR_06_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G5W_SHIFT)
#define GPIO_A_SCR_06_0_G5W_RANGE                       13:13
#define GPIO_A_SCR_06_0_G5W_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_06_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_A_SCR_06_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G4W_SHIFT)
#define GPIO_A_SCR_06_0_G4W_RANGE                       12:12
#define GPIO_A_SCR_06_0_G4W_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_06_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_A_SCR_06_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G3W_SHIFT)
#define GPIO_A_SCR_06_0_G3W_RANGE                       11:11
#define GPIO_A_SCR_06_0_G3W_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_06_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_A_SCR_06_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G2W_SHIFT)
#define GPIO_A_SCR_06_0_G2W_RANGE                       10:10
#define GPIO_A_SCR_06_0_G2W_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_06_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_A_SCR_06_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G1W_SHIFT)
#define GPIO_A_SCR_06_0_G1W_RANGE                       9:9
#define GPIO_A_SCR_06_0_G1W_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_06_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_A_SCR_06_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G0W_SHIFT)
#define GPIO_A_SCR_06_0_G0W_RANGE                       8:8
#define GPIO_A_SCR_06_0_G0W_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_06_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_A_SCR_06_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G7R_SHIFT)
#define GPIO_A_SCR_06_0_G7R_RANGE                       7:7
#define GPIO_A_SCR_06_0_G7R_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_06_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_A_SCR_06_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G6R_SHIFT)
#define GPIO_A_SCR_06_0_G6R_RANGE                       6:6
#define GPIO_A_SCR_06_0_G6R_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_06_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_A_SCR_06_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G5R_SHIFT)
#define GPIO_A_SCR_06_0_G5R_RANGE                       5:5
#define GPIO_A_SCR_06_0_G5R_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_06_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_A_SCR_06_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G4R_SHIFT)
#define GPIO_A_SCR_06_0_G4R_RANGE                       4:4
#define GPIO_A_SCR_06_0_G4R_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_06_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_A_SCR_06_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G3R_SHIFT)
#define GPIO_A_SCR_06_0_G3R_RANGE                       3:3
#define GPIO_A_SCR_06_0_G3R_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_06_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_A_SCR_06_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G2R_SHIFT)
#define GPIO_A_SCR_06_0_G2R_RANGE                       2:2
#define GPIO_A_SCR_06_0_G2R_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_06_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_A_SCR_06_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G1R_SHIFT)
#define GPIO_A_SCR_06_0_G1R_RANGE                       1:1
#define GPIO_A_SCR_06_0_G1R_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_06_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_A_SCR_06_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G0R_SHIFT)
#define GPIO_A_SCR_06_0_G0R_RANGE                       0:0
#define GPIO_A_SCR_06_0_G0R_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_A_VM_07_0
#define GPIO_A_VM_07_0                  _MK_ADDR_CONST(0x10b8)
#define GPIO_A_VM_07_0_SECURE                   0x0
#define GPIO_A_VM_07_0_DUAL                     0x0
#define GPIO_A_VM_07_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_A_VM_07_0_WORD_COUNT                       0x1
#define GPIO_A_VM_07_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_07_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_07_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_07_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_VM_07_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_07_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_A_VM_07_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_A_VM_07_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_07_0_VM1_SHIFT)
#define GPIO_A_VM_07_0_VM1_RANGE                        1:0
#define GPIO_A_VM_07_0_VM1_WOFFSET                      0x0
#define GPIO_A_VM_07_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_07_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_07_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_07_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_07_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_07_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_07_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_A_VM_07_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_07_0_VM2_SHIFT)
#define GPIO_A_VM_07_0_VM2_RANGE                        3:2
#define GPIO_A_VM_07_0_VM2_WOFFSET                      0x0
#define GPIO_A_VM_07_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_07_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_07_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_07_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_07_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_07_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_07_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_A_VM_07_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_07_0_VM3_SHIFT)
#define GPIO_A_VM_07_0_VM3_RANGE                        5:4
#define GPIO_A_VM_07_0_VM3_WOFFSET                      0x0
#define GPIO_A_VM_07_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_07_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_07_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_07_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_07_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_07_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_07_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_A_VM_07_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_07_0_VM4_SHIFT)
#define GPIO_A_VM_07_0_VM4_RANGE                        7:6
#define GPIO_A_VM_07_0_VM4_WOFFSET                      0x0
#define GPIO_A_VM_07_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_07_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_07_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_07_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_07_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_07_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_07_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_A_VM_07_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_07_0_VM5_SHIFT)
#define GPIO_A_VM_07_0_VM5_RANGE                        9:8
#define GPIO_A_VM_07_0_VM5_WOFFSET                      0x0
#define GPIO_A_VM_07_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_07_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_07_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_07_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_07_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_07_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_07_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_A_VM_07_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_07_0_VM6_SHIFT)
#define GPIO_A_VM_07_0_VM6_RANGE                        11:10
#define GPIO_A_VM_07_0_VM6_WOFFSET                      0x0
#define GPIO_A_VM_07_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_07_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_07_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_07_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_07_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_07_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_07_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_A_VM_07_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_07_0_VM7_SHIFT)
#define GPIO_A_VM_07_0_VM7_RANGE                        13:12
#define GPIO_A_VM_07_0_VM7_WOFFSET                      0x0
#define GPIO_A_VM_07_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_07_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_07_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_07_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_07_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_07_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_A_VM_07_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_A_VM_07_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_A_VM_07_0_VM8_SHIFT)
#define GPIO_A_VM_07_0_VM8_RANGE                        15:14
#define GPIO_A_VM_07_0_VM8_WOFFSET                      0x0
#define GPIO_A_VM_07_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_A_VM_07_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_A_VM_07_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_VM_07_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_VM_07_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_VM_07_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_A_SCR_07_0
#define GPIO_A_SCR_07_0                 _MK_ADDR_CONST(0x10bc)
#define GPIO_A_SCR_07_0_SECURE                  0x0
#define GPIO_A_SCR_07_0_DUAL                    0x0
#define GPIO_A_SCR_07_0_SCR                     0
#define GPIO_A_SCR_07_0_WORD_COUNT                      0x1
#define GPIO_A_SCR_07_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_07_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_07_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_07_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_A_SCR_07_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_SEC_LCK_SHIFT)
#define GPIO_A_SCR_07_0_SEC_LCK_RANGE                   29:29
#define GPIO_A_SCR_07_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_A_SCR_07_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_07_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_07_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_A_SCR_07_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_SEC_WEN_SHIFT)
#define GPIO_A_SCR_07_0_SEC_WEN_RANGE                   28:28
#define GPIO_A_SCR_07_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_A_SCR_07_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_07_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_07_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_A_SCR_07_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_SEC_REN_SHIFT)
#define GPIO_A_SCR_07_0_SEC_REN_RANGE                   27:27
#define GPIO_A_SCR_07_0_SEC_REN_WOFFSET                 0x0
#define GPIO_A_SCR_07_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_07_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_07_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_A_SCR_07_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_A_SCR_07_0_SEC_OWNER_SHIFT)
#define GPIO_A_SCR_07_0_SEC_OWNER_RANGE                 26:24
#define GPIO_A_SCR_07_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_A_SCR_07_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_A_SCR_07_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_07_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_A_SCR_07_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_PR7_SHIFT)
#define GPIO_A_SCR_07_0_PR7_RANGE                       23:23
#define GPIO_A_SCR_07_0_PR7_WOFFSET                     0x0
#define GPIO_A_SCR_07_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_07_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_07_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_A_SCR_07_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_PR6_SHIFT)
#define GPIO_A_SCR_07_0_PR6_RANGE                       22:22
#define GPIO_A_SCR_07_0_PR6_WOFFSET                     0x0
#define GPIO_A_SCR_07_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_07_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_07_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_A_SCR_07_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_PR5_SHIFT)
#define GPIO_A_SCR_07_0_PR5_RANGE                       21:21
#define GPIO_A_SCR_07_0_PR5_WOFFSET                     0x0
#define GPIO_A_SCR_07_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_07_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_07_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_A_SCR_07_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_PR4_SHIFT)
#define GPIO_A_SCR_07_0_PR4_RANGE                       20:20
#define GPIO_A_SCR_07_0_PR4_WOFFSET                     0x0
#define GPIO_A_SCR_07_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_07_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_07_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_A_SCR_07_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_PR3_SHIFT)
#define GPIO_A_SCR_07_0_PR3_RANGE                       19:19
#define GPIO_A_SCR_07_0_PR3_WOFFSET                     0x0
#define GPIO_A_SCR_07_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_07_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_07_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_A_SCR_07_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_PR2_SHIFT)
#define GPIO_A_SCR_07_0_PR2_RANGE                       18:18
#define GPIO_A_SCR_07_0_PR2_WOFFSET                     0x0
#define GPIO_A_SCR_07_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_07_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_07_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_A_SCR_07_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_PR1_SHIFT)
#define GPIO_A_SCR_07_0_PR1_RANGE                       17:17
#define GPIO_A_SCR_07_0_PR1_WOFFSET                     0x0
#define GPIO_A_SCR_07_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_07_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_07_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_A_SCR_07_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_PR0_SHIFT)
#define GPIO_A_SCR_07_0_PR0_RANGE                       16:16
#define GPIO_A_SCR_07_0_PR0_WOFFSET                     0x0
#define GPIO_A_SCR_07_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_07_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_07_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_A_SCR_07_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_G7W_SHIFT)
#define GPIO_A_SCR_07_0_G7W_RANGE                       15:15
#define GPIO_A_SCR_07_0_G7W_WOFFSET                     0x0
#define GPIO_A_SCR_07_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_07_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_07_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_A_SCR_07_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_G6W_SHIFT)
#define GPIO_A_SCR_07_0_G6W_RANGE                       14:14
#define GPIO_A_SCR_07_0_G6W_WOFFSET                     0x0
#define GPIO_A_SCR_07_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_07_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_07_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_A_SCR_07_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_G5W_SHIFT)
#define GPIO_A_SCR_07_0_G5W_RANGE                       13:13
#define GPIO_A_SCR_07_0_G5W_WOFFSET                     0x0
#define GPIO_A_SCR_07_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_07_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_07_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_A_SCR_07_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_G4W_SHIFT)
#define GPIO_A_SCR_07_0_G4W_RANGE                       12:12
#define GPIO_A_SCR_07_0_G4W_WOFFSET                     0x0
#define GPIO_A_SCR_07_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_07_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_07_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_A_SCR_07_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_G3W_SHIFT)
#define GPIO_A_SCR_07_0_G3W_RANGE                       11:11
#define GPIO_A_SCR_07_0_G3W_WOFFSET                     0x0
#define GPIO_A_SCR_07_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_07_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_07_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_A_SCR_07_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_G2W_SHIFT)
#define GPIO_A_SCR_07_0_G2W_RANGE                       10:10
#define GPIO_A_SCR_07_0_G2W_WOFFSET                     0x0
#define GPIO_A_SCR_07_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_07_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_07_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_A_SCR_07_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_G1W_SHIFT)
#define GPIO_A_SCR_07_0_G1W_RANGE                       9:9
#define GPIO_A_SCR_07_0_G1W_WOFFSET                     0x0
#define GPIO_A_SCR_07_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_07_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_07_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_A_SCR_07_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_G0W_SHIFT)
#define GPIO_A_SCR_07_0_G0W_RANGE                       8:8
#define GPIO_A_SCR_07_0_G0W_WOFFSET                     0x0
#define GPIO_A_SCR_07_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_07_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_07_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_A_SCR_07_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_G7R_SHIFT)
#define GPIO_A_SCR_07_0_G7R_RANGE                       7:7
#define GPIO_A_SCR_07_0_G7R_WOFFSET                     0x0
#define GPIO_A_SCR_07_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_07_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_07_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_A_SCR_07_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_G6R_SHIFT)
#define GPIO_A_SCR_07_0_G6R_RANGE                       6:6
#define GPIO_A_SCR_07_0_G6R_WOFFSET                     0x0
#define GPIO_A_SCR_07_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_07_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_07_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_A_SCR_07_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_G5R_SHIFT)
#define GPIO_A_SCR_07_0_G5R_RANGE                       5:5
#define GPIO_A_SCR_07_0_G5R_WOFFSET                     0x0
#define GPIO_A_SCR_07_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_07_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_07_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_A_SCR_07_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_G4R_SHIFT)
#define GPIO_A_SCR_07_0_G4R_RANGE                       4:4
#define GPIO_A_SCR_07_0_G4R_WOFFSET                     0x0
#define GPIO_A_SCR_07_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_07_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_07_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_A_SCR_07_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_G3R_SHIFT)
#define GPIO_A_SCR_07_0_G3R_RANGE                       3:3
#define GPIO_A_SCR_07_0_G3R_WOFFSET                     0x0
#define GPIO_A_SCR_07_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_07_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_07_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_A_SCR_07_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_G2R_SHIFT)
#define GPIO_A_SCR_07_0_G2R_RANGE                       2:2
#define GPIO_A_SCR_07_0_G2R_WOFFSET                     0x0
#define GPIO_A_SCR_07_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_07_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_07_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_A_SCR_07_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_G1R_SHIFT)
#define GPIO_A_SCR_07_0_G1R_RANGE                       1:1
#define GPIO_A_SCR_07_0_G1R_WOFFSET                     0x0
#define GPIO_A_SCR_07_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_07_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_A_SCR_07_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_A_SCR_07_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_G0R_SHIFT)
#define GPIO_A_SCR_07_0_G0R_RANGE                       0:0
#define GPIO_A_SCR_07_0_G0R_WOFFSET                     0x0
#define GPIO_A_SCR_07_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_SCR_07_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_CTL1_VM_SCR_0
#define GPIO_CTL1_VM_SCR_0                      _MK_ADDR_CONST(0x1800)
#define GPIO_CTL1_VM_SCR_0_SECURE                       0x0
#define GPIO_CTL1_VM_SCR_0_DUAL                         0x0
#define GPIO_CTL1_VM_SCR_0_SCR                  0
#define GPIO_CTL1_VM_SCR_0_WORD_COUNT                   0x1
#define GPIO_CTL1_VM_SCR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_RESET_MASK                   _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL1_VM_SCR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_READ_MASK                    _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL1_VM_SCR_0_WRITE_MASK                   _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL1_VM_SCR_0_SEC_LCK_SHIFT                        _MK_SHIFT_CONST(29)
#define GPIO_CTL1_VM_SCR_0_SEC_LCK_FIELD                        _MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_SEC_LCK_SHIFT)
#define GPIO_CTL1_VM_SCR_0_SEC_LCK_RANGE                        29:29
#define GPIO_CTL1_VM_SCR_0_SEC_LCK_WOFFSET                      0x0
#define GPIO_CTL1_VM_SCR_0_SEC_LCK_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_SEC_LCK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_SEC_LCK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_SEC_LCK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_SEC_LCK_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_CTL1_VM_SCR_0_SEC_WEN_SHIFT                        _MK_SHIFT_CONST(28)
#define GPIO_CTL1_VM_SCR_0_SEC_WEN_FIELD                        _MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_SEC_WEN_SHIFT)
#define GPIO_CTL1_VM_SCR_0_SEC_WEN_RANGE                        28:28
#define GPIO_CTL1_VM_SCR_0_SEC_WEN_WOFFSET                      0x0
#define GPIO_CTL1_VM_SCR_0_SEC_WEN_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_SEC_WEN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_SEC_WEN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_SEC_WEN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_SEC_WEN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_CTL1_VM_SCR_0_SEC_REN_SHIFT                        _MK_SHIFT_CONST(27)
#define GPIO_CTL1_VM_SCR_0_SEC_REN_FIELD                        _MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_SEC_REN_SHIFT)
#define GPIO_CTL1_VM_SCR_0_SEC_REN_RANGE                        27:27
#define GPIO_CTL1_VM_SCR_0_SEC_REN_WOFFSET                      0x0
#define GPIO_CTL1_VM_SCR_0_SEC_REN_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_SEC_REN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_SEC_REN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_SEC_REN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_SEC_REN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_SEC_REN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_CTL1_VM_SCR_0_SEC_OWNER_SHIFT                      _MK_SHIFT_CONST(24)
#define GPIO_CTL1_VM_SCR_0_SEC_OWNER_FIELD                      _MK_FIELD_CONST(0x7, GPIO_CTL1_VM_SCR_0_SEC_OWNER_SHIFT)
#define GPIO_CTL1_VM_SCR_0_SEC_OWNER_RANGE                      26:24
#define GPIO_CTL1_VM_SCR_0_SEC_OWNER_WOFFSET                    0x0
#define GPIO_CTL1_VM_SCR_0_SEC_OWNER_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_SEC_OWNER_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
#define GPIO_CTL1_VM_SCR_0_SEC_OWNER_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_SEC_OWNER_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_CTL1_VM_SCR_0_PR7_SHIFT                    _MK_SHIFT_CONST(23)
#define GPIO_CTL1_VM_SCR_0_PR7_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_PR7_SHIFT)
#define GPIO_CTL1_VM_SCR_0_PR7_RANGE                    23:23
#define GPIO_CTL1_VM_SCR_0_PR7_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_PR7_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR7_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_PR7_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR7_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR7_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR7_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL1_VM_SCR_0_PR6_SHIFT                    _MK_SHIFT_CONST(22)
#define GPIO_CTL1_VM_SCR_0_PR6_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_PR6_SHIFT)
#define GPIO_CTL1_VM_SCR_0_PR6_RANGE                    22:22
#define GPIO_CTL1_VM_SCR_0_PR6_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_PR6_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR6_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_PR6_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR6_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR6_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL1_VM_SCR_0_PR5_SHIFT                    _MK_SHIFT_CONST(21)
#define GPIO_CTL1_VM_SCR_0_PR5_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_PR5_SHIFT)
#define GPIO_CTL1_VM_SCR_0_PR5_RANGE                    21:21
#define GPIO_CTL1_VM_SCR_0_PR5_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_PR5_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR5_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_PR5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR5_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR5_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL1_VM_SCR_0_PR4_SHIFT                    _MK_SHIFT_CONST(20)
#define GPIO_CTL1_VM_SCR_0_PR4_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_PR4_SHIFT)
#define GPIO_CTL1_VM_SCR_0_PR4_RANGE                    20:20
#define GPIO_CTL1_VM_SCR_0_PR4_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_PR4_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR4_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_PR4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR4_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR4_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL1_VM_SCR_0_PR3_SHIFT                    _MK_SHIFT_CONST(19)
#define GPIO_CTL1_VM_SCR_0_PR3_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_PR3_SHIFT)
#define GPIO_CTL1_VM_SCR_0_PR3_RANGE                    19:19
#define GPIO_CTL1_VM_SCR_0_PR3_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_PR3_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_PR3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR3_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR3_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL1_VM_SCR_0_PR2_SHIFT                    _MK_SHIFT_CONST(18)
#define GPIO_CTL1_VM_SCR_0_PR2_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_PR2_SHIFT)
#define GPIO_CTL1_VM_SCR_0_PR2_RANGE                    18:18
#define GPIO_CTL1_VM_SCR_0_PR2_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_PR2_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_PR2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR2_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR2_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL1_VM_SCR_0_PR1_SHIFT                    _MK_SHIFT_CONST(17)
#define GPIO_CTL1_VM_SCR_0_PR1_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_PR1_SHIFT)
#define GPIO_CTL1_VM_SCR_0_PR1_RANGE                    17:17
#define GPIO_CTL1_VM_SCR_0_PR1_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_PR1_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_PR1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR1_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR1_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL1_VM_SCR_0_PR0_SHIFT                    _MK_SHIFT_CONST(16)
#define GPIO_CTL1_VM_SCR_0_PR0_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_PR0_SHIFT)
#define GPIO_CTL1_VM_SCR_0_PR0_RANGE                    16:16
#define GPIO_CTL1_VM_SCR_0_PR0_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_PR0_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_PR0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR0_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR0_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL1_VM_SCR_0_G7W_SHIFT                    _MK_SHIFT_CONST(15)
#define GPIO_CTL1_VM_SCR_0_G7W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G7W_SHIFT)
#define GPIO_CTL1_VM_SCR_0_G7W_RANGE                    15:15
#define GPIO_CTL1_VM_SCR_0_G7W_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_G7W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G7W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_G7W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G7W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G7W_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G7W_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL1_VM_SCR_0_G6W_SHIFT                    _MK_SHIFT_CONST(14)
#define GPIO_CTL1_VM_SCR_0_G6W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G6W_SHIFT)
#define GPIO_CTL1_VM_SCR_0_G6W_RANGE                    14:14
#define GPIO_CTL1_VM_SCR_0_G6W_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_G6W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G6W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_G6W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G6W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G6W_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G6W_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL1_VM_SCR_0_G5W_SHIFT                    _MK_SHIFT_CONST(13)
#define GPIO_CTL1_VM_SCR_0_G5W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G5W_SHIFT)
#define GPIO_CTL1_VM_SCR_0_G5W_RANGE                    13:13
#define GPIO_CTL1_VM_SCR_0_G5W_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_G5W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G5W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_G5W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G5W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G5W_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G5W_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL1_VM_SCR_0_G4W_SHIFT                    _MK_SHIFT_CONST(12)
#define GPIO_CTL1_VM_SCR_0_G4W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G4W_SHIFT)
#define GPIO_CTL1_VM_SCR_0_G4W_RANGE                    12:12
#define GPIO_CTL1_VM_SCR_0_G4W_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_G4W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G4W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_G4W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G4W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G4W_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G4W_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL1_VM_SCR_0_G3W_SHIFT                    _MK_SHIFT_CONST(11)
#define GPIO_CTL1_VM_SCR_0_G3W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G3W_SHIFT)
#define GPIO_CTL1_VM_SCR_0_G3W_RANGE                    11:11
#define GPIO_CTL1_VM_SCR_0_G3W_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_G3W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G3W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_G3W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G3W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G3W_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G3W_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL1_VM_SCR_0_G2W_SHIFT                    _MK_SHIFT_CONST(10)
#define GPIO_CTL1_VM_SCR_0_G2W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G2W_SHIFT)
#define GPIO_CTL1_VM_SCR_0_G2W_RANGE                    10:10
#define GPIO_CTL1_VM_SCR_0_G2W_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_G2W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G2W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_G2W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G2W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G2W_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G2W_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL1_VM_SCR_0_G1W_SHIFT                    _MK_SHIFT_CONST(9)
#define GPIO_CTL1_VM_SCR_0_G1W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G1W_SHIFT)
#define GPIO_CTL1_VM_SCR_0_G1W_RANGE                    9:9
#define GPIO_CTL1_VM_SCR_0_G1W_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_G1W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G1W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_G1W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G1W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G1W_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G1W_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL1_VM_SCR_0_G0W_SHIFT                    _MK_SHIFT_CONST(8)
#define GPIO_CTL1_VM_SCR_0_G0W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G0W_SHIFT)
#define GPIO_CTL1_VM_SCR_0_G0W_RANGE                    8:8
#define GPIO_CTL1_VM_SCR_0_G0W_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_G0W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G0W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_G0W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G0W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G0W_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G0W_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL1_VM_SCR_0_G7R_SHIFT                    _MK_SHIFT_CONST(7)
#define GPIO_CTL1_VM_SCR_0_G7R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G7R_SHIFT)
#define GPIO_CTL1_VM_SCR_0_G7R_RANGE                    7:7
#define GPIO_CTL1_VM_SCR_0_G7R_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_G7R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G7R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_G7R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G7R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G7R_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G7R_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL1_VM_SCR_0_G6R_SHIFT                    _MK_SHIFT_CONST(6)
#define GPIO_CTL1_VM_SCR_0_G6R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G6R_SHIFT)
#define GPIO_CTL1_VM_SCR_0_G6R_RANGE                    6:6
#define GPIO_CTL1_VM_SCR_0_G6R_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_G6R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G6R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_G6R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G6R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G6R_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G6R_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL1_VM_SCR_0_G5R_SHIFT                    _MK_SHIFT_CONST(5)
#define GPIO_CTL1_VM_SCR_0_G5R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G5R_SHIFT)
#define GPIO_CTL1_VM_SCR_0_G5R_RANGE                    5:5
#define GPIO_CTL1_VM_SCR_0_G5R_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_G5R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G5R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_G5R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G5R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G5R_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G5R_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL1_VM_SCR_0_G4R_SHIFT                    _MK_SHIFT_CONST(4)
#define GPIO_CTL1_VM_SCR_0_G4R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G4R_SHIFT)
#define GPIO_CTL1_VM_SCR_0_G4R_RANGE                    4:4
#define GPIO_CTL1_VM_SCR_0_G4R_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_G4R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G4R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_G4R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G4R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G4R_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G4R_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL1_VM_SCR_0_G3R_SHIFT                    _MK_SHIFT_CONST(3)
#define GPIO_CTL1_VM_SCR_0_G3R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G3R_SHIFT)
#define GPIO_CTL1_VM_SCR_0_G3R_RANGE                    3:3
#define GPIO_CTL1_VM_SCR_0_G3R_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_G3R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G3R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_G3R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G3R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G3R_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G3R_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL1_VM_SCR_0_G2R_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_CTL1_VM_SCR_0_G2R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G2R_SHIFT)
#define GPIO_CTL1_VM_SCR_0_G2R_RANGE                    2:2
#define GPIO_CTL1_VM_SCR_0_G2R_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_G2R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G2R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_G2R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G2R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G2R_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G2R_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL1_VM_SCR_0_G1R_SHIFT                    _MK_SHIFT_CONST(1)
#define GPIO_CTL1_VM_SCR_0_G1R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G1R_SHIFT)
#define GPIO_CTL1_VM_SCR_0_G1R_RANGE                    1:1
#define GPIO_CTL1_VM_SCR_0_G1R_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_G1R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G1R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_G1R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G1R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G1R_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G1R_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL1_VM_SCR_0_G0R_SHIFT                    _MK_SHIFT_CONST(0)
#define GPIO_CTL1_VM_SCR_0_G0R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G0R_SHIFT)
#define GPIO_CTL1_VM_SCR_0_G0R_RANGE                    0:0
#define GPIO_CTL1_VM_SCR_0_G0R_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_G0R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G0R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_G0R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G0R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G0R_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G0R_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0                     _MK_ADDR_CONST(0x1804)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SECURE                      0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_DUAL                        0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SCR                         0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_WORD_COUNT                  0x1
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_RESET_MASK                  _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_READ_MASK                   _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_WRITE_MASK                  _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SHIFT                       _MK_SHIFT_CONST(29)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_RANGE                       29:29
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_WOFFSET                     0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SHIFT                       _MK_SHIFT_CONST(28)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_RANGE                       28:28
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_WOFFSET                     0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SHIFT                       _MK_SHIFT_CONST(27)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_RANGE                       27:27
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_WOFFSET                     0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SHIFT                     _MK_SHIFT_CONST(24)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_FIELD                     _MK_FIELD_CONST(0x7, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_RANGE                     26:24
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_WOFFSET                   0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR7_SHIFT                   _MK_SHIFT_CONST(23)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR7_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR7_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR7_RANGE                   23:23
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR7_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR7_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR7_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR7_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR7_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR7_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR7_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR6_SHIFT                   _MK_SHIFT_CONST(22)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR6_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR6_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR6_RANGE                   22:22
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR6_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR6_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR6_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR6_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR6_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR6_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR6_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR5_SHIFT                   _MK_SHIFT_CONST(21)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR5_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR5_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR5_RANGE                   21:21
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR5_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR5_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR5_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR5_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR5_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR5_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR5_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR4_SHIFT                   _MK_SHIFT_CONST(20)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR4_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR4_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR4_RANGE                   20:20
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR4_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR4_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR4_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR4_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR4_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR3_SHIFT                   _MK_SHIFT_CONST(19)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR3_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR3_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR3_RANGE                   19:19
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR3_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR3_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR3_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR3_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR2_SHIFT                   _MK_SHIFT_CONST(18)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR2_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR2_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR2_RANGE                   18:18
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR2_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR2_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR2_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR2_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR1_SHIFT                   _MK_SHIFT_CONST(17)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR1_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR1_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR1_RANGE                   17:17
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR1_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR1_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR1_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR1_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR0_SHIFT                   _MK_SHIFT_CONST(16)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR0_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR0_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR0_RANGE                   16:16
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR0_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR0_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR0_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR0_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7W_SHIFT                   _MK_SHIFT_CONST(15)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7W_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7W_RANGE                   15:15
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7W_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6W_SHIFT                   _MK_SHIFT_CONST(14)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6W_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6W_RANGE                   14:14
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6W_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5W_SHIFT                   _MK_SHIFT_CONST(13)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5W_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5W_RANGE                   13:13
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5W_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4W_SHIFT                   _MK_SHIFT_CONST(12)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4W_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4W_RANGE                   12:12
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4W_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3W_SHIFT                   _MK_SHIFT_CONST(11)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3W_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3W_RANGE                   11:11
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3W_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2W_SHIFT                   _MK_SHIFT_CONST(10)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2W_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2W_RANGE                   10:10
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2W_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1W_SHIFT                   _MK_SHIFT_CONST(9)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1W_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1W_RANGE                   9:9
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1W_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0W_SHIFT                   _MK_SHIFT_CONST(8)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0W_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0W_RANGE                   8:8
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0W_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7R_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7R_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7R_RANGE                   7:7
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7R_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6R_SHIFT                   _MK_SHIFT_CONST(6)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6R_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6R_RANGE                   6:6
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6R_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5R_SHIFT                   _MK_SHIFT_CONST(5)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5R_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5R_RANGE                   5:5
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5R_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4R_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4R_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4R_RANGE                   4:4
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4R_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3R_SHIFT                   _MK_SHIFT_CONST(3)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3R_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3R_RANGE                   3:3
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3R_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2R_SHIFT                   _MK_SHIFT_CONST(2)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2R_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2R_RANGE                   2:2
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2R_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1R_SHIFT                   _MK_SHIFT_CONST(1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1R_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1R_RANGE                   1:1
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1R_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0R_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0R_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0R_RANGE                   0:0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0R_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_CTL1_INTERRUPT_STATUS_VM_0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0                 _MK_ADDR_CONST(0x1808)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_SECURE                  0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_DUAL                    0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_SCR                     GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_WORD_COUNT                      0x1
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_RESET_MASK                      _MK_MASK_CONST(0xff)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_READ_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_FIELD                  _MK_FIELD_CONST(0xff, GPIO_CTL1_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_RANGE                  7:0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_WOFFSET                        0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register GPIO_CTL1_SCR_0
#define GPIO_CTL1_SCR_0                 _MK_ADDR_CONST(0x180c)
#define GPIO_CTL1_SCR_0_SECURE                  0x0
#define GPIO_CTL1_SCR_0_DUAL                    0x0
#define GPIO_CTL1_SCR_0_SCR                     0
#define GPIO_CTL1_SCR_0_WORD_COUNT                      0x1
#define GPIO_CTL1_SCR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL1_SCR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL1_SCR_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL1_SCR_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_CTL1_SCR_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_SEC_LCK_SHIFT)
#define GPIO_CTL1_SCR_0_SEC_LCK_RANGE                   29:29
#define GPIO_CTL1_SCR_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_CTL1_SCR_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL1_SCR_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_CTL1_SCR_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_SEC_WEN_SHIFT)
#define GPIO_CTL1_SCR_0_SEC_WEN_RANGE                   28:28
#define GPIO_CTL1_SCR_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_CTL1_SCR_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL1_SCR_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_CTL1_SCR_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_SEC_REN_SHIFT)
#define GPIO_CTL1_SCR_0_SEC_REN_RANGE                   27:27
#define GPIO_CTL1_SCR_0_SEC_REN_WOFFSET                 0x0
#define GPIO_CTL1_SCR_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL1_SCR_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_CTL1_SCR_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_CTL1_SCR_0_SEC_OWNER_SHIFT)
#define GPIO_CTL1_SCR_0_SEC_OWNER_RANGE                 26:24
#define GPIO_CTL1_SCR_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_CTL1_SCR_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_CTL1_SCR_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_CTL1_SCR_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_CTL1_SCR_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_PR7_SHIFT)
#define GPIO_CTL1_SCR_0_PR7_RANGE                       23:23
#define GPIO_CTL1_SCR_0_PR7_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL1_SCR_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_CTL1_SCR_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_PR6_SHIFT)
#define GPIO_CTL1_SCR_0_PR6_RANGE                       22:22
#define GPIO_CTL1_SCR_0_PR6_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL1_SCR_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_CTL1_SCR_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_PR5_SHIFT)
#define GPIO_CTL1_SCR_0_PR5_RANGE                       21:21
#define GPIO_CTL1_SCR_0_PR5_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL1_SCR_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_CTL1_SCR_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_PR4_SHIFT)
#define GPIO_CTL1_SCR_0_PR4_RANGE                       20:20
#define GPIO_CTL1_SCR_0_PR4_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL1_SCR_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_CTL1_SCR_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_PR3_SHIFT)
#define GPIO_CTL1_SCR_0_PR3_RANGE                       19:19
#define GPIO_CTL1_SCR_0_PR3_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL1_SCR_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_CTL1_SCR_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_PR2_SHIFT)
#define GPIO_CTL1_SCR_0_PR2_RANGE                       18:18
#define GPIO_CTL1_SCR_0_PR2_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL1_SCR_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_CTL1_SCR_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_PR1_SHIFT)
#define GPIO_CTL1_SCR_0_PR1_RANGE                       17:17
#define GPIO_CTL1_SCR_0_PR1_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL1_SCR_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_CTL1_SCR_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_PR0_SHIFT)
#define GPIO_CTL1_SCR_0_PR0_RANGE                       16:16
#define GPIO_CTL1_SCR_0_PR0_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL1_SCR_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_CTL1_SCR_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G7W_SHIFT)
#define GPIO_CTL1_SCR_0_G7W_RANGE                       15:15
#define GPIO_CTL1_SCR_0_G7W_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL1_SCR_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_CTL1_SCR_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G6W_SHIFT)
#define GPIO_CTL1_SCR_0_G6W_RANGE                       14:14
#define GPIO_CTL1_SCR_0_G6W_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL1_SCR_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_CTL1_SCR_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G5W_SHIFT)
#define GPIO_CTL1_SCR_0_G5W_RANGE                       13:13
#define GPIO_CTL1_SCR_0_G5W_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL1_SCR_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_CTL1_SCR_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G4W_SHIFT)
#define GPIO_CTL1_SCR_0_G4W_RANGE                       12:12
#define GPIO_CTL1_SCR_0_G4W_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL1_SCR_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_CTL1_SCR_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G3W_SHIFT)
#define GPIO_CTL1_SCR_0_G3W_RANGE                       11:11
#define GPIO_CTL1_SCR_0_G3W_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL1_SCR_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_CTL1_SCR_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G2W_SHIFT)
#define GPIO_CTL1_SCR_0_G2W_RANGE                       10:10
#define GPIO_CTL1_SCR_0_G2W_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL1_SCR_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_CTL1_SCR_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G1W_SHIFT)
#define GPIO_CTL1_SCR_0_G1W_RANGE                       9:9
#define GPIO_CTL1_SCR_0_G1W_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL1_SCR_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_CTL1_SCR_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G0W_SHIFT)
#define GPIO_CTL1_SCR_0_G0W_RANGE                       8:8
#define GPIO_CTL1_SCR_0_G0W_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL1_SCR_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_CTL1_SCR_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G7R_SHIFT)
#define GPIO_CTL1_SCR_0_G7R_RANGE                       7:7
#define GPIO_CTL1_SCR_0_G7R_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL1_SCR_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_CTL1_SCR_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G6R_SHIFT)
#define GPIO_CTL1_SCR_0_G6R_RANGE                       6:6
#define GPIO_CTL1_SCR_0_G6R_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL1_SCR_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_CTL1_SCR_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G5R_SHIFT)
#define GPIO_CTL1_SCR_0_G5R_RANGE                       5:5
#define GPIO_CTL1_SCR_0_G5R_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL1_SCR_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_CTL1_SCR_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G4R_SHIFT)
#define GPIO_CTL1_SCR_0_G4R_RANGE                       4:4
#define GPIO_CTL1_SCR_0_G4R_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL1_SCR_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_CTL1_SCR_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G3R_SHIFT)
#define GPIO_CTL1_SCR_0_G3R_RANGE                       3:3
#define GPIO_CTL1_SCR_0_G3R_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL1_SCR_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_CTL1_SCR_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G2R_SHIFT)
#define GPIO_CTL1_SCR_0_G2R_RANGE                       2:2
#define GPIO_CTL1_SCR_0_G2R_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL1_SCR_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_CTL1_SCR_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G1R_SHIFT)
#define GPIO_CTL1_SCR_0_G1R_RANGE                       1:1
#define GPIO_CTL1_SCR_0_G1R_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL1_SCR_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_CTL1_SCR_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G0R_SHIFT)
#define GPIO_CTL1_SCR_0_G0R_RANGE                       0:0
#define GPIO_CTL1_SCR_0_G0R_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_CTL1_ICG_EN_OVERRIDE_0
#define GPIO_CTL1_ICG_EN_OVERRIDE_0                     _MK_ADDR_CONST(0x1810)
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_SECURE                      0x0
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_DUAL                        0x0
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_SCR                         GPIO_CTL1_SCR_0
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_WORD_COUNT                  0x1
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_FIELD                  _MK_FIELD_CONST(0x1, GPIO_CTL1_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SHIFT)
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_RANGE                  0:0
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_WOFFSET                        0x0
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register GPIO_V_INT0_ROUTE_MAPPING_0
#define GPIO_V_INT0_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x1814)
#define GPIO_V_INT0_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_V_INT0_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_V_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
#define GPIO_V_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_V_INT0_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_V_INT0_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_V_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_V_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_INT0_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_V_INT0_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_V_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_V_INT0_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_V_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_V_INT0_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_V_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_V_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_V_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_V_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_V_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_V_INT1_ROUTE_MAPPING_0
#define GPIO_V_INT1_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x1818)
#define GPIO_V_INT1_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_V_INT1_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_V_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
#define GPIO_V_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_V_INT1_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_V_INT1_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_V_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_V_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_INT1_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_V_INT1_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_V_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_V_INT1_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_V_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_V_INT1_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_V_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_V_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_V_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_V_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_V_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_V_INT2_ROUTE_MAPPING_0
#define GPIO_V_INT2_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x181c)
#define GPIO_V_INT2_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_V_INT2_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_V_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
#define GPIO_V_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_V_INT2_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_V_INT2_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_V_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_V_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_INT2_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_V_INT2_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_V_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_V_INT2_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_V_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_V_INT2_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_V_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_V_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_V_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_V_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_V_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_V_INT3_ROUTE_MAPPING_0
#define GPIO_V_INT3_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x1820)
#define GPIO_V_INT3_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_V_INT3_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_V_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
#define GPIO_V_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_V_INT3_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_V_INT3_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_V_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_V_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_INT3_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_V_INT3_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_V_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_V_INT3_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_V_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_V_INT3_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_V_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_V_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_V_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_V_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_V_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_V_INT4_ROUTE_MAPPING_0
#define GPIO_V_INT4_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x1824)
#define GPIO_V_INT4_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_V_INT4_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_V_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
#define GPIO_V_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_V_INT4_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_V_INT4_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_V_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_V_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_INT4_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_V_INT4_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_V_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_V_INT4_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_V_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_V_INT4_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_V_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_V_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_V_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_V_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_V_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_V_INT5_ROUTE_MAPPING_0
#define GPIO_V_INT5_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x1828)
#define GPIO_V_INT5_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_V_INT5_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_V_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
#define GPIO_V_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_V_INT5_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_V_INT5_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_V_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_V_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_INT5_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_V_INT5_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_V_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_V_INT5_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_V_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_V_INT5_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_V_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_V_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_V_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_V_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_V_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_V_INT6_ROUTE_MAPPING_0
#define GPIO_V_INT6_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x182c)
#define GPIO_V_INT6_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_V_INT6_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_V_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
#define GPIO_V_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_V_INT6_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_V_INT6_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_V_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_V_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_INT6_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_V_INT6_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_V_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_V_INT6_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_V_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_V_INT6_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_V_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_V_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_V_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_V_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_V_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_V_INT7_ROUTE_MAPPING_0
#define GPIO_V_INT7_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x1830)
#define GPIO_V_INT7_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_V_INT7_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_V_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
#define GPIO_V_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_V_INT7_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_V_INT7_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_V_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_V_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_INT7_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_V_INT7_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_V_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_V_INT7_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_V_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_V_INT7_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_V_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_V_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_V_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_V_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_V_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_W_INT0_ROUTE_MAPPING_0
#define GPIO_W_INT0_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x1834)
#define GPIO_W_INT0_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_W_INT0_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_W_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
#define GPIO_W_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_W_INT0_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_W_INT0_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_W_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_W_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_INT0_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x3)
#define GPIO_W_INT0_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_W_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_W_INT0_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x3, GPIO_W_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_W_INT0_ROUTE_MAPPING_0_VAL_RANGE                   1:0
#define GPIO_W_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_W_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_W_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define GPIO_W_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_W_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_W_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_W_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_W_INT1_ROUTE_MAPPING_0
#define GPIO_W_INT1_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x1838)
#define GPIO_W_INT1_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_W_INT1_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_W_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
#define GPIO_W_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_W_INT1_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_W_INT1_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_W_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_W_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_INT1_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x3)
#define GPIO_W_INT1_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_W_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_W_INT1_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x3, GPIO_W_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_W_INT1_ROUTE_MAPPING_0_VAL_RANGE                   1:0
#define GPIO_W_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_W_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_W_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define GPIO_W_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_W_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_W_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_W_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_W_INT2_ROUTE_MAPPING_0
#define GPIO_W_INT2_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x183c)
#define GPIO_W_INT2_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_W_INT2_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_W_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
#define GPIO_W_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_W_INT2_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_W_INT2_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_W_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_W_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_INT2_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x3)
#define GPIO_W_INT2_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_W_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_W_INT2_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x3, GPIO_W_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_W_INT2_ROUTE_MAPPING_0_VAL_RANGE                   1:0
#define GPIO_W_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_W_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_W_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define GPIO_W_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_W_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_W_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_W_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_W_INT3_ROUTE_MAPPING_0
#define GPIO_W_INT3_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x1840)
#define GPIO_W_INT3_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_W_INT3_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_W_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
#define GPIO_W_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_W_INT3_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_W_INT3_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_W_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_W_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_INT3_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x3)
#define GPIO_W_INT3_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_W_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_W_INT3_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x3, GPIO_W_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_W_INT3_ROUTE_MAPPING_0_VAL_RANGE                   1:0
#define GPIO_W_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_W_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_W_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define GPIO_W_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_W_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_W_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_W_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_W_INT4_ROUTE_MAPPING_0
#define GPIO_W_INT4_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x1844)
#define GPIO_W_INT4_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_W_INT4_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_W_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
#define GPIO_W_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_W_INT4_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_W_INT4_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_W_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_W_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_INT4_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x3)
#define GPIO_W_INT4_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_W_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_W_INT4_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x3, GPIO_W_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_W_INT4_ROUTE_MAPPING_0_VAL_RANGE                   1:0
#define GPIO_W_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_W_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_W_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define GPIO_W_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_W_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_W_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_W_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_W_INT5_ROUTE_MAPPING_0
#define GPIO_W_INT5_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x1848)
#define GPIO_W_INT5_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_W_INT5_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_W_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
#define GPIO_W_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_W_INT5_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_W_INT5_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_W_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_W_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_INT5_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x3)
#define GPIO_W_INT5_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_W_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_W_INT5_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x3, GPIO_W_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_W_INT5_ROUTE_MAPPING_0_VAL_RANGE                   1:0
#define GPIO_W_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_W_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_W_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define GPIO_W_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_W_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_W_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_W_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_W_INT6_ROUTE_MAPPING_0
#define GPIO_W_INT6_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x184c)
#define GPIO_W_INT6_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_W_INT6_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_W_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
#define GPIO_W_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_W_INT6_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_W_INT6_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_W_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_W_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_INT6_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x3)
#define GPIO_W_INT6_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_W_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_W_INT6_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x3, GPIO_W_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_W_INT6_ROUTE_MAPPING_0_VAL_RANGE                   1:0
#define GPIO_W_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_W_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_W_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define GPIO_W_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_W_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_W_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_W_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_W_INT7_ROUTE_MAPPING_0
#define GPIO_W_INT7_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x1850)
#define GPIO_W_INT7_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_W_INT7_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_W_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
#define GPIO_W_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_W_INT7_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_W_INT7_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_W_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_W_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_INT7_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x3)
#define GPIO_W_INT7_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_W_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_W_INT7_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x3, GPIO_W_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_W_INT7_ROUTE_MAPPING_0_VAL_RANGE                   1:0
#define GPIO_W_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_W_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_W_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define GPIO_W_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_W_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_W_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_W_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_A_INT0_ROUTE_MAPPING_0
#define GPIO_A_INT0_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x1854)
#define GPIO_A_INT0_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_A_INT0_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_A_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
#define GPIO_A_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_A_INT0_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_A_INT0_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_A_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_A_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_INT0_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_A_INT0_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_A_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_A_INT0_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_A_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_A_INT0_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_A_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_A_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_A_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_A_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_A_INT1_ROUTE_MAPPING_0
#define GPIO_A_INT1_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x1858)
#define GPIO_A_INT1_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_A_INT1_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_A_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
#define GPIO_A_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_A_INT1_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_A_INT1_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_A_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_A_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_INT1_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_A_INT1_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_A_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_A_INT1_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_A_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_A_INT1_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_A_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_A_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_A_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_A_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_A_INT2_ROUTE_MAPPING_0
#define GPIO_A_INT2_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x185c)
#define GPIO_A_INT2_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_A_INT2_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_A_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
#define GPIO_A_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_A_INT2_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_A_INT2_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_A_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_A_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_INT2_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_A_INT2_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_A_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_A_INT2_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_A_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_A_INT2_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_A_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_A_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_A_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_A_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_A_INT3_ROUTE_MAPPING_0
#define GPIO_A_INT3_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x1860)
#define GPIO_A_INT3_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_A_INT3_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_A_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
#define GPIO_A_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_A_INT3_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_A_INT3_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_A_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_A_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_INT3_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_A_INT3_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_A_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_A_INT3_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_A_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_A_INT3_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_A_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_A_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_A_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_A_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_A_INT4_ROUTE_MAPPING_0
#define GPIO_A_INT4_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x1864)
#define GPIO_A_INT4_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_A_INT4_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_A_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
#define GPIO_A_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_A_INT4_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_A_INT4_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_A_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_A_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_INT4_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_A_INT4_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_A_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_A_INT4_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_A_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_A_INT4_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_A_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_A_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_A_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_A_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_A_INT5_ROUTE_MAPPING_0
#define GPIO_A_INT5_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x1868)
#define GPIO_A_INT5_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_A_INT5_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_A_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
#define GPIO_A_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_A_INT5_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_A_INT5_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_A_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_A_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_INT5_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_A_INT5_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_A_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_A_INT5_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_A_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_A_INT5_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_A_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_A_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_A_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_A_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_A_INT6_ROUTE_MAPPING_0
#define GPIO_A_INT6_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x186c)
#define GPIO_A_INT6_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_A_INT6_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_A_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
#define GPIO_A_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_A_INT6_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_A_INT6_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_A_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_A_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_INT6_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_A_INT6_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_A_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_A_INT6_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_A_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_A_INT6_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_A_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_A_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_A_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_A_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_A_INT7_ROUTE_MAPPING_0
#define GPIO_A_INT7_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x1870)
#define GPIO_A_INT7_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_A_INT7_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_A_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
#define GPIO_A_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_A_INT7_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_A_INT7_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_A_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_A_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_INT7_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_A_INT7_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_A_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_A_INT7_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_A_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_A_INT7_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_A_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_A_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_A_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_A_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_CTL1_SPARE_0
#define GPIO_CTL1_SPARE_0                       _MK_ADDR_CONST(0x1874)
#define GPIO_CTL1_SPARE_0_SECURE                        0x0
#define GPIO_CTL1_SPARE_0_DUAL                  0x0
#define GPIO_CTL1_SPARE_0_SCR                   0
#define GPIO_CTL1_SPARE_0_WORD_COUNT                    0x1
#define GPIO_CTL1_SPARE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SPARE_0_RESET_MASK                    _MK_MASK_CONST(0xffff)
#define GPIO_CTL1_SPARE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SPARE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SPARE_0_READ_MASK                     _MK_MASK_CONST(0xffff)
#define GPIO_CTL1_SPARE_0_WRITE_MASK                    _MK_MASK_CONST(0xffff)
#define GPIO_CTL1_SPARE_0_SPARE_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_CTL1_SPARE_0_SPARE_FIELD                   _MK_FIELD_CONST(0xffff, GPIO_CTL1_SPARE_0_SPARE_SHIFT)
#define GPIO_CTL1_SPARE_0_SPARE_RANGE                   15:0
#define GPIO_CTL1_SPARE_0_SPARE_WOFFSET                 0x0
#define GPIO_CTL1_SPARE_0_SPARE_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SPARE_0_SPARE_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define GPIO_CTL1_SPARE_0_SPARE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SPARE_0_SPARE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SPARE_0_SPARE_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL1_SPARE_0_SPARE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_X_VM_00_0
#define GPIO_X_VM_00_0                  _MK_ADDR_CONST(0x2000)
#define GPIO_X_VM_00_0_SECURE                   0x0
#define GPIO_X_VM_00_0_DUAL                     0x0
#define GPIO_X_VM_00_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_X_VM_00_0_WORD_COUNT                       0x1
#define GPIO_X_VM_00_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_00_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_00_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_00_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_X_VM_00_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_00_0_VM1_SHIFT)
#define GPIO_X_VM_00_0_VM1_RANGE                        1:0
#define GPIO_X_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_X_VM_00_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_00_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_00_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_00_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_X_VM_00_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_00_0_VM2_SHIFT)
#define GPIO_X_VM_00_0_VM2_RANGE                        3:2
#define GPIO_X_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_X_VM_00_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_00_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_00_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_00_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_X_VM_00_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_00_0_VM3_SHIFT)
#define GPIO_X_VM_00_0_VM3_RANGE                        5:4
#define GPIO_X_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_X_VM_00_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_00_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_00_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_00_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_X_VM_00_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_00_0_VM4_SHIFT)
#define GPIO_X_VM_00_0_VM4_RANGE                        7:6
#define GPIO_X_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_X_VM_00_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_00_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_00_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_00_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_X_VM_00_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_00_0_VM5_SHIFT)
#define GPIO_X_VM_00_0_VM5_RANGE                        9:8
#define GPIO_X_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_X_VM_00_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_00_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_00_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_00_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_X_VM_00_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_00_0_VM6_SHIFT)
#define GPIO_X_VM_00_0_VM6_RANGE                        11:10
#define GPIO_X_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_X_VM_00_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_00_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_00_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_00_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_X_VM_00_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_00_0_VM7_SHIFT)
#define GPIO_X_VM_00_0_VM7_RANGE                        13:12
#define GPIO_X_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_X_VM_00_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_00_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_00_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_00_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_X_VM_00_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_00_0_VM8_SHIFT)
#define GPIO_X_VM_00_0_VM8_RANGE                        15:14
#define GPIO_X_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_X_VM_00_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_00_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_00_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_X_SCR_00_0
#define GPIO_X_SCR_00_0                 _MK_ADDR_CONST(0x2004)
#define GPIO_X_SCR_00_0_SECURE                  0x0
#define GPIO_X_SCR_00_0_DUAL                    0x0
#define GPIO_X_SCR_00_0_SCR                     0
#define GPIO_X_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_X_SCR_00_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_00_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_00_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_X_SCR_00_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_X_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_X_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_X_SCR_00_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_00_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_X_SCR_00_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_X_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_X_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_X_SCR_00_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_00_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_X_SCR_00_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_X_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_X_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_X_SCR_00_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_00_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_X_SCR_00_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_X_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_X_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_X_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_X_SCR_00_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_X_SCR_00_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_00_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_X_SCR_00_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_PR7_SHIFT)
#define GPIO_X_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_X_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_00_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_X_SCR_00_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_PR6_SHIFT)
#define GPIO_X_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_X_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_00_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_X_SCR_00_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_PR5_SHIFT)
#define GPIO_X_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_X_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_00_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_X_SCR_00_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_PR4_SHIFT)
#define GPIO_X_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_X_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_00_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_X_SCR_00_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_PR3_SHIFT)
#define GPIO_X_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_X_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_00_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_X_SCR_00_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_PR2_SHIFT)
#define GPIO_X_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_X_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_00_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_X_SCR_00_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_PR1_SHIFT)
#define GPIO_X_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_X_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_00_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_X_SCR_00_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_PR0_SHIFT)
#define GPIO_X_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_X_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_00_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_X_SCR_00_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G7W_SHIFT)
#define GPIO_X_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_X_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_00_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_X_SCR_00_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G6W_SHIFT)
#define GPIO_X_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_X_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_00_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_X_SCR_00_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G5W_SHIFT)
#define GPIO_X_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_X_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_00_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_X_SCR_00_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G4W_SHIFT)
#define GPIO_X_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_X_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_00_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_X_SCR_00_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G3W_SHIFT)
#define GPIO_X_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_X_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_00_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_X_SCR_00_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G2W_SHIFT)
#define GPIO_X_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_X_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_00_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_X_SCR_00_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G1W_SHIFT)
#define GPIO_X_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_X_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_00_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_X_SCR_00_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G0W_SHIFT)
#define GPIO_X_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_X_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_00_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_X_SCR_00_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G7R_SHIFT)
#define GPIO_X_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_X_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_00_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_X_SCR_00_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G6R_SHIFT)
#define GPIO_X_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_X_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_00_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_X_SCR_00_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G5R_SHIFT)
#define GPIO_X_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_X_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_00_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_X_SCR_00_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G4R_SHIFT)
#define GPIO_X_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_X_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_00_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_X_SCR_00_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G3R_SHIFT)
#define GPIO_X_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_X_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_00_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_X_SCR_00_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G2R_SHIFT)
#define GPIO_X_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_X_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_00_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_X_SCR_00_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G1R_SHIFT)
#define GPIO_X_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_X_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_00_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_X_SCR_00_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G0R_SHIFT)
#define GPIO_X_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_X_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_X_VM_01_0
#define GPIO_X_VM_01_0                  _MK_ADDR_CONST(0x2008)
#define GPIO_X_VM_01_0_SECURE                   0x0
#define GPIO_X_VM_01_0_DUAL                     0x0
#define GPIO_X_VM_01_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_X_VM_01_0_WORD_COUNT                       0x1
#define GPIO_X_VM_01_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_01_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_01_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_01_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_X_VM_01_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_01_0_VM1_SHIFT)
#define GPIO_X_VM_01_0_VM1_RANGE                        1:0
#define GPIO_X_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_X_VM_01_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_01_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_01_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_01_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_X_VM_01_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_01_0_VM2_SHIFT)
#define GPIO_X_VM_01_0_VM2_RANGE                        3:2
#define GPIO_X_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_X_VM_01_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_01_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_01_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_01_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_X_VM_01_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_01_0_VM3_SHIFT)
#define GPIO_X_VM_01_0_VM3_RANGE                        5:4
#define GPIO_X_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_X_VM_01_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_01_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_01_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_01_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_X_VM_01_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_01_0_VM4_SHIFT)
#define GPIO_X_VM_01_0_VM4_RANGE                        7:6
#define GPIO_X_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_X_VM_01_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_01_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_01_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_01_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_X_VM_01_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_01_0_VM5_SHIFT)
#define GPIO_X_VM_01_0_VM5_RANGE                        9:8
#define GPIO_X_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_X_VM_01_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_01_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_01_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_01_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_X_VM_01_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_01_0_VM6_SHIFT)
#define GPIO_X_VM_01_0_VM6_RANGE                        11:10
#define GPIO_X_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_X_VM_01_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_01_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_01_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_01_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_X_VM_01_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_01_0_VM7_SHIFT)
#define GPIO_X_VM_01_0_VM7_RANGE                        13:12
#define GPIO_X_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_X_VM_01_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_01_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_01_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_01_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_X_VM_01_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_01_0_VM8_SHIFT)
#define GPIO_X_VM_01_0_VM8_RANGE                        15:14
#define GPIO_X_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_X_VM_01_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_01_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_01_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_X_SCR_01_0
#define GPIO_X_SCR_01_0                 _MK_ADDR_CONST(0x200c)
#define GPIO_X_SCR_01_0_SECURE                  0x0
#define GPIO_X_SCR_01_0_DUAL                    0x0
#define GPIO_X_SCR_01_0_SCR                     0
#define GPIO_X_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_X_SCR_01_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_01_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_01_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_01_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_X_SCR_01_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_X_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_X_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_X_SCR_01_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_01_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_X_SCR_01_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_X_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_X_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_X_SCR_01_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_01_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_X_SCR_01_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_X_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_X_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_X_SCR_01_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_01_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_X_SCR_01_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_X_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_X_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_X_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_X_SCR_01_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_X_SCR_01_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_01_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_X_SCR_01_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_PR7_SHIFT)
#define GPIO_X_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_X_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_01_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_X_SCR_01_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_PR6_SHIFT)
#define GPIO_X_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_X_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_01_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_X_SCR_01_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_PR5_SHIFT)
#define GPIO_X_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_X_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_01_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_X_SCR_01_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_PR4_SHIFT)
#define GPIO_X_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_X_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_01_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_X_SCR_01_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_PR3_SHIFT)
#define GPIO_X_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_X_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_01_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_X_SCR_01_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_PR2_SHIFT)
#define GPIO_X_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_X_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_01_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_X_SCR_01_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_PR1_SHIFT)
#define GPIO_X_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_X_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_01_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_X_SCR_01_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_PR0_SHIFT)
#define GPIO_X_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_X_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_01_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_X_SCR_01_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G7W_SHIFT)
#define GPIO_X_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_X_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_01_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_X_SCR_01_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G6W_SHIFT)
#define GPIO_X_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_X_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_01_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_X_SCR_01_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G5W_SHIFT)
#define GPIO_X_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_X_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_01_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_X_SCR_01_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G4W_SHIFT)
#define GPIO_X_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_X_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_01_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_X_SCR_01_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G3W_SHIFT)
#define GPIO_X_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_X_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_01_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_X_SCR_01_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G2W_SHIFT)
#define GPIO_X_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_X_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_01_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_X_SCR_01_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G1W_SHIFT)
#define GPIO_X_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_X_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_01_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_X_SCR_01_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G0W_SHIFT)
#define GPIO_X_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_X_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_01_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_X_SCR_01_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G7R_SHIFT)
#define GPIO_X_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_X_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_01_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_X_SCR_01_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G6R_SHIFT)
#define GPIO_X_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_X_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_01_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_X_SCR_01_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G5R_SHIFT)
#define GPIO_X_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_X_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_01_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_X_SCR_01_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G4R_SHIFT)
#define GPIO_X_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_X_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_01_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_X_SCR_01_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G3R_SHIFT)
#define GPIO_X_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_X_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_01_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_X_SCR_01_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G2R_SHIFT)
#define GPIO_X_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_X_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_01_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_X_SCR_01_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G1R_SHIFT)
#define GPIO_X_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_X_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_01_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_X_SCR_01_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G0R_SHIFT)
#define GPIO_X_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_X_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_X_VM_02_0
#define GPIO_X_VM_02_0                  _MK_ADDR_CONST(0x2010)
#define GPIO_X_VM_02_0_SECURE                   0x0
#define GPIO_X_VM_02_0_DUAL                     0x0
#define GPIO_X_VM_02_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_X_VM_02_0_WORD_COUNT                       0x1
#define GPIO_X_VM_02_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_02_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_02_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_02_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_X_VM_02_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_02_0_VM1_SHIFT)
#define GPIO_X_VM_02_0_VM1_RANGE                        1:0
#define GPIO_X_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_X_VM_02_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_02_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_02_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_02_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_X_VM_02_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_02_0_VM2_SHIFT)
#define GPIO_X_VM_02_0_VM2_RANGE                        3:2
#define GPIO_X_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_X_VM_02_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_02_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_02_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_02_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_X_VM_02_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_02_0_VM3_SHIFT)
#define GPIO_X_VM_02_0_VM3_RANGE                        5:4
#define GPIO_X_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_X_VM_02_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_02_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_02_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_02_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_X_VM_02_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_02_0_VM4_SHIFT)
#define GPIO_X_VM_02_0_VM4_RANGE                        7:6
#define GPIO_X_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_X_VM_02_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_02_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_02_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_02_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_X_VM_02_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_02_0_VM5_SHIFT)
#define GPIO_X_VM_02_0_VM5_RANGE                        9:8
#define GPIO_X_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_X_VM_02_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_02_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_02_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_02_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_X_VM_02_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_02_0_VM6_SHIFT)
#define GPIO_X_VM_02_0_VM6_RANGE                        11:10
#define GPIO_X_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_X_VM_02_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_02_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_02_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_02_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_X_VM_02_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_02_0_VM7_SHIFT)
#define GPIO_X_VM_02_0_VM7_RANGE                        13:12
#define GPIO_X_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_X_VM_02_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_02_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_02_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_02_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_X_VM_02_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_02_0_VM8_SHIFT)
#define GPIO_X_VM_02_0_VM8_RANGE                        15:14
#define GPIO_X_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_X_VM_02_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_02_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_02_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_X_SCR_02_0
#define GPIO_X_SCR_02_0                 _MK_ADDR_CONST(0x2014)
#define GPIO_X_SCR_02_0_SECURE                  0x0
#define GPIO_X_SCR_02_0_DUAL                    0x0
#define GPIO_X_SCR_02_0_SCR                     0
#define GPIO_X_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_X_SCR_02_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_02_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_02_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_02_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_X_SCR_02_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_X_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_X_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_X_SCR_02_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_02_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_X_SCR_02_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_X_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_X_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_X_SCR_02_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_02_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_X_SCR_02_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_X_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_X_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_X_SCR_02_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_02_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_X_SCR_02_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_X_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_X_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_X_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_X_SCR_02_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_X_SCR_02_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_02_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_X_SCR_02_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_PR7_SHIFT)
#define GPIO_X_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_X_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_02_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_X_SCR_02_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_PR6_SHIFT)
#define GPIO_X_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_X_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_02_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_X_SCR_02_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_PR5_SHIFT)
#define GPIO_X_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_X_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_02_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_X_SCR_02_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_PR4_SHIFT)
#define GPIO_X_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_X_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_02_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_X_SCR_02_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_PR3_SHIFT)
#define GPIO_X_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_X_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_02_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_X_SCR_02_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_PR2_SHIFT)
#define GPIO_X_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_X_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_02_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_X_SCR_02_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_PR1_SHIFT)
#define GPIO_X_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_X_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_02_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_X_SCR_02_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_PR0_SHIFT)
#define GPIO_X_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_X_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_02_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_X_SCR_02_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G7W_SHIFT)
#define GPIO_X_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_X_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_02_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_X_SCR_02_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G6W_SHIFT)
#define GPIO_X_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_X_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_02_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_X_SCR_02_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G5W_SHIFT)
#define GPIO_X_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_X_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_02_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_X_SCR_02_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G4W_SHIFT)
#define GPIO_X_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_X_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_02_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_X_SCR_02_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G3W_SHIFT)
#define GPIO_X_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_X_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_02_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_X_SCR_02_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G2W_SHIFT)
#define GPIO_X_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_X_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_02_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_X_SCR_02_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G1W_SHIFT)
#define GPIO_X_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_X_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_02_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_X_SCR_02_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G0W_SHIFT)
#define GPIO_X_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_X_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_02_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_X_SCR_02_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G7R_SHIFT)
#define GPIO_X_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_X_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_02_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_X_SCR_02_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G6R_SHIFT)
#define GPIO_X_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_X_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_02_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_X_SCR_02_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G5R_SHIFT)
#define GPIO_X_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_X_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_02_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_X_SCR_02_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G4R_SHIFT)
#define GPIO_X_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_X_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_02_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_X_SCR_02_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G3R_SHIFT)
#define GPIO_X_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_X_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_02_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_X_SCR_02_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G2R_SHIFT)
#define GPIO_X_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_X_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_02_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_X_SCR_02_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G1R_SHIFT)
#define GPIO_X_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_X_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_02_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_X_SCR_02_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G0R_SHIFT)
#define GPIO_X_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_X_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_X_VM_03_0
#define GPIO_X_VM_03_0                  _MK_ADDR_CONST(0x2018)
#define GPIO_X_VM_03_0_SECURE                   0x0
#define GPIO_X_VM_03_0_DUAL                     0x0
#define GPIO_X_VM_03_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_X_VM_03_0_WORD_COUNT                       0x1
#define GPIO_X_VM_03_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_03_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_03_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_03_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_X_VM_03_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_03_0_VM1_SHIFT)
#define GPIO_X_VM_03_0_VM1_RANGE                        1:0
#define GPIO_X_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_X_VM_03_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_03_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_03_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_03_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_X_VM_03_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_03_0_VM2_SHIFT)
#define GPIO_X_VM_03_0_VM2_RANGE                        3:2
#define GPIO_X_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_X_VM_03_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_03_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_03_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_03_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_X_VM_03_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_03_0_VM3_SHIFT)
#define GPIO_X_VM_03_0_VM3_RANGE                        5:4
#define GPIO_X_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_X_VM_03_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_03_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_03_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_03_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_X_VM_03_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_03_0_VM4_SHIFT)
#define GPIO_X_VM_03_0_VM4_RANGE                        7:6
#define GPIO_X_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_X_VM_03_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_03_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_03_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_03_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_X_VM_03_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_03_0_VM5_SHIFT)
#define GPIO_X_VM_03_0_VM5_RANGE                        9:8
#define GPIO_X_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_X_VM_03_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_03_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_03_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_03_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_X_VM_03_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_03_0_VM6_SHIFT)
#define GPIO_X_VM_03_0_VM6_RANGE                        11:10
#define GPIO_X_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_X_VM_03_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_03_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_03_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_03_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_X_VM_03_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_03_0_VM7_SHIFT)
#define GPIO_X_VM_03_0_VM7_RANGE                        13:12
#define GPIO_X_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_X_VM_03_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_03_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_03_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_03_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_X_VM_03_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_03_0_VM8_SHIFT)
#define GPIO_X_VM_03_0_VM8_RANGE                        15:14
#define GPIO_X_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_X_VM_03_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_03_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_03_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_X_SCR_03_0
#define GPIO_X_SCR_03_0                 _MK_ADDR_CONST(0x201c)
#define GPIO_X_SCR_03_0_SECURE                  0x0
#define GPIO_X_SCR_03_0_DUAL                    0x0
#define GPIO_X_SCR_03_0_SCR                     0
#define GPIO_X_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_X_SCR_03_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_03_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_03_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_03_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_X_SCR_03_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_X_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_X_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_X_SCR_03_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_03_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_X_SCR_03_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_X_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_X_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_X_SCR_03_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_03_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_X_SCR_03_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_X_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_X_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_X_SCR_03_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_03_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_X_SCR_03_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_X_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_X_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_X_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_X_SCR_03_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_X_SCR_03_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_03_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_X_SCR_03_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_PR7_SHIFT)
#define GPIO_X_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_X_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_03_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_X_SCR_03_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_PR6_SHIFT)
#define GPIO_X_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_X_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_03_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_X_SCR_03_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_PR5_SHIFT)
#define GPIO_X_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_X_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_03_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_X_SCR_03_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_PR4_SHIFT)
#define GPIO_X_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_X_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_03_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_X_SCR_03_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_PR3_SHIFT)
#define GPIO_X_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_X_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_03_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_X_SCR_03_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_PR2_SHIFT)
#define GPIO_X_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_X_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_03_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_X_SCR_03_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_PR1_SHIFT)
#define GPIO_X_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_X_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_03_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_X_SCR_03_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_PR0_SHIFT)
#define GPIO_X_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_X_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_03_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_X_SCR_03_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G7W_SHIFT)
#define GPIO_X_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_X_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_03_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_X_SCR_03_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G6W_SHIFT)
#define GPIO_X_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_X_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_03_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_X_SCR_03_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G5W_SHIFT)
#define GPIO_X_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_X_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_03_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_X_SCR_03_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G4W_SHIFT)
#define GPIO_X_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_X_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_03_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_X_SCR_03_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G3W_SHIFT)
#define GPIO_X_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_X_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_03_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_X_SCR_03_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G2W_SHIFT)
#define GPIO_X_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_X_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_03_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_X_SCR_03_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G1W_SHIFT)
#define GPIO_X_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_X_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_03_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_X_SCR_03_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G0W_SHIFT)
#define GPIO_X_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_X_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_03_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_X_SCR_03_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G7R_SHIFT)
#define GPIO_X_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_X_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_03_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_X_SCR_03_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G6R_SHIFT)
#define GPIO_X_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_X_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_03_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_X_SCR_03_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G5R_SHIFT)
#define GPIO_X_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_X_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_03_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_X_SCR_03_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G4R_SHIFT)
#define GPIO_X_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_X_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_03_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_X_SCR_03_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G3R_SHIFT)
#define GPIO_X_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_X_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_03_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_X_SCR_03_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G2R_SHIFT)
#define GPIO_X_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_X_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_03_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_X_SCR_03_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G1R_SHIFT)
#define GPIO_X_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_X_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_03_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_X_SCR_03_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G0R_SHIFT)
#define GPIO_X_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_X_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_X_VM_04_0
#define GPIO_X_VM_04_0                  _MK_ADDR_CONST(0x2020)
#define GPIO_X_VM_04_0_SECURE                   0x0
#define GPIO_X_VM_04_0_DUAL                     0x0
#define GPIO_X_VM_04_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_X_VM_04_0_WORD_COUNT                       0x1
#define GPIO_X_VM_04_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_04_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_04_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_04_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_X_VM_04_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_04_0_VM1_SHIFT)
#define GPIO_X_VM_04_0_VM1_RANGE                        1:0
#define GPIO_X_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_X_VM_04_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_04_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_04_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_04_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_X_VM_04_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_04_0_VM2_SHIFT)
#define GPIO_X_VM_04_0_VM2_RANGE                        3:2
#define GPIO_X_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_X_VM_04_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_04_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_04_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_04_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_X_VM_04_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_04_0_VM3_SHIFT)
#define GPIO_X_VM_04_0_VM3_RANGE                        5:4
#define GPIO_X_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_X_VM_04_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_04_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_04_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_04_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_X_VM_04_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_04_0_VM4_SHIFT)
#define GPIO_X_VM_04_0_VM4_RANGE                        7:6
#define GPIO_X_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_X_VM_04_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_04_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_04_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_04_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_X_VM_04_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_04_0_VM5_SHIFT)
#define GPIO_X_VM_04_0_VM5_RANGE                        9:8
#define GPIO_X_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_X_VM_04_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_04_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_04_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_04_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_X_VM_04_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_04_0_VM6_SHIFT)
#define GPIO_X_VM_04_0_VM6_RANGE                        11:10
#define GPIO_X_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_X_VM_04_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_04_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_04_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_04_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_X_VM_04_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_04_0_VM7_SHIFT)
#define GPIO_X_VM_04_0_VM7_RANGE                        13:12
#define GPIO_X_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_X_VM_04_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_04_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_04_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_04_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_X_VM_04_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_04_0_VM8_SHIFT)
#define GPIO_X_VM_04_0_VM8_RANGE                        15:14
#define GPIO_X_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_X_VM_04_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_04_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_04_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_X_SCR_04_0
#define GPIO_X_SCR_04_0                 _MK_ADDR_CONST(0x2024)
#define GPIO_X_SCR_04_0_SECURE                  0x0
#define GPIO_X_SCR_04_0_DUAL                    0x0
#define GPIO_X_SCR_04_0_SCR                     0
#define GPIO_X_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_X_SCR_04_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_04_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_04_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_04_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_X_SCR_04_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_X_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_X_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_X_SCR_04_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_04_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_X_SCR_04_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_X_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_X_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_X_SCR_04_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_04_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_X_SCR_04_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_X_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_X_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_X_SCR_04_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_04_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_X_SCR_04_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_X_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_X_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_X_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_X_SCR_04_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_X_SCR_04_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_04_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_X_SCR_04_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_PR7_SHIFT)
#define GPIO_X_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_X_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_04_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_X_SCR_04_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_PR6_SHIFT)
#define GPIO_X_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_X_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_04_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_X_SCR_04_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_PR5_SHIFT)
#define GPIO_X_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_X_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_04_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_X_SCR_04_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_PR4_SHIFT)
#define GPIO_X_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_X_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_04_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_X_SCR_04_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_PR3_SHIFT)
#define GPIO_X_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_X_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_04_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_X_SCR_04_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_PR2_SHIFT)
#define GPIO_X_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_X_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_04_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_X_SCR_04_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_PR1_SHIFT)
#define GPIO_X_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_X_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_04_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_X_SCR_04_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_PR0_SHIFT)
#define GPIO_X_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_X_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_04_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_X_SCR_04_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G7W_SHIFT)
#define GPIO_X_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_X_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_04_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_X_SCR_04_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G6W_SHIFT)
#define GPIO_X_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_X_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_04_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_X_SCR_04_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G5W_SHIFT)
#define GPIO_X_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_X_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_04_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_X_SCR_04_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G4W_SHIFT)
#define GPIO_X_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_X_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_04_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_X_SCR_04_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G3W_SHIFT)
#define GPIO_X_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_X_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_04_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_X_SCR_04_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G2W_SHIFT)
#define GPIO_X_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_X_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_04_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_X_SCR_04_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G1W_SHIFT)
#define GPIO_X_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_X_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_04_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_X_SCR_04_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G0W_SHIFT)
#define GPIO_X_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_X_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_04_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_X_SCR_04_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G7R_SHIFT)
#define GPIO_X_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_X_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_04_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_X_SCR_04_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G6R_SHIFT)
#define GPIO_X_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_X_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_04_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_X_SCR_04_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G5R_SHIFT)
#define GPIO_X_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_X_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_04_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_X_SCR_04_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G4R_SHIFT)
#define GPIO_X_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_X_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_04_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_X_SCR_04_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G3R_SHIFT)
#define GPIO_X_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_X_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_04_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_X_SCR_04_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G2R_SHIFT)
#define GPIO_X_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_X_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_04_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_X_SCR_04_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G1R_SHIFT)
#define GPIO_X_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_X_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_04_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_X_SCR_04_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G0R_SHIFT)
#define GPIO_X_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_X_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_X_VM_05_0
#define GPIO_X_VM_05_0                  _MK_ADDR_CONST(0x2028)
#define GPIO_X_VM_05_0_SECURE                   0x0
#define GPIO_X_VM_05_0_DUAL                     0x0
#define GPIO_X_VM_05_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_X_VM_05_0_WORD_COUNT                       0x1
#define GPIO_X_VM_05_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_05_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_05_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_05_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_X_VM_05_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_05_0_VM1_SHIFT)
#define GPIO_X_VM_05_0_VM1_RANGE                        1:0
#define GPIO_X_VM_05_0_VM1_WOFFSET                      0x0
#define GPIO_X_VM_05_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_05_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_05_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_05_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_X_VM_05_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_05_0_VM2_SHIFT)
#define GPIO_X_VM_05_0_VM2_RANGE                        3:2
#define GPIO_X_VM_05_0_VM2_WOFFSET                      0x0
#define GPIO_X_VM_05_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_05_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_05_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_05_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_X_VM_05_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_05_0_VM3_SHIFT)
#define GPIO_X_VM_05_0_VM3_RANGE                        5:4
#define GPIO_X_VM_05_0_VM3_WOFFSET                      0x0
#define GPIO_X_VM_05_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_05_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_05_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_05_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_X_VM_05_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_05_0_VM4_SHIFT)
#define GPIO_X_VM_05_0_VM4_RANGE                        7:6
#define GPIO_X_VM_05_0_VM4_WOFFSET                      0x0
#define GPIO_X_VM_05_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_05_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_05_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_05_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_X_VM_05_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_05_0_VM5_SHIFT)
#define GPIO_X_VM_05_0_VM5_RANGE                        9:8
#define GPIO_X_VM_05_0_VM5_WOFFSET                      0x0
#define GPIO_X_VM_05_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_05_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_05_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_05_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_X_VM_05_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_05_0_VM6_SHIFT)
#define GPIO_X_VM_05_0_VM6_RANGE                        11:10
#define GPIO_X_VM_05_0_VM6_WOFFSET                      0x0
#define GPIO_X_VM_05_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_05_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_05_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_05_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_X_VM_05_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_05_0_VM7_SHIFT)
#define GPIO_X_VM_05_0_VM7_RANGE                        13:12
#define GPIO_X_VM_05_0_VM7_WOFFSET                      0x0
#define GPIO_X_VM_05_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_05_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_05_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_05_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_X_VM_05_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_05_0_VM8_SHIFT)
#define GPIO_X_VM_05_0_VM8_RANGE                        15:14
#define GPIO_X_VM_05_0_VM8_WOFFSET                      0x0
#define GPIO_X_VM_05_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_05_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_05_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_X_SCR_05_0
#define GPIO_X_SCR_05_0                 _MK_ADDR_CONST(0x202c)
#define GPIO_X_SCR_05_0_SECURE                  0x0
#define GPIO_X_SCR_05_0_DUAL                    0x0
#define GPIO_X_SCR_05_0_SCR                     0
#define GPIO_X_SCR_05_0_WORD_COUNT                      0x1
#define GPIO_X_SCR_05_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_05_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_05_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_05_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_X_SCR_05_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_X_SCR_05_0_SEC_LCK_RANGE                   29:29
#define GPIO_X_SCR_05_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_X_SCR_05_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_05_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_X_SCR_05_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_X_SCR_05_0_SEC_WEN_RANGE                   28:28
#define GPIO_X_SCR_05_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_X_SCR_05_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_05_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_X_SCR_05_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_X_SCR_05_0_SEC_REN_RANGE                   27:27
#define GPIO_X_SCR_05_0_SEC_REN_WOFFSET                 0x0
#define GPIO_X_SCR_05_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_05_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_X_SCR_05_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_X_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_X_SCR_05_0_SEC_OWNER_RANGE                 26:24
#define GPIO_X_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_X_SCR_05_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_X_SCR_05_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_05_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_X_SCR_05_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_PR7_SHIFT)
#define GPIO_X_SCR_05_0_PR7_RANGE                       23:23
#define GPIO_X_SCR_05_0_PR7_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_05_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_X_SCR_05_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_PR6_SHIFT)
#define GPIO_X_SCR_05_0_PR6_RANGE                       22:22
#define GPIO_X_SCR_05_0_PR6_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_05_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_X_SCR_05_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_PR5_SHIFT)
#define GPIO_X_SCR_05_0_PR5_RANGE                       21:21
#define GPIO_X_SCR_05_0_PR5_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_05_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_X_SCR_05_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_PR4_SHIFT)
#define GPIO_X_SCR_05_0_PR4_RANGE                       20:20
#define GPIO_X_SCR_05_0_PR4_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_05_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_X_SCR_05_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_PR3_SHIFT)
#define GPIO_X_SCR_05_0_PR3_RANGE                       19:19
#define GPIO_X_SCR_05_0_PR3_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_05_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_X_SCR_05_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_PR2_SHIFT)
#define GPIO_X_SCR_05_0_PR2_RANGE                       18:18
#define GPIO_X_SCR_05_0_PR2_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_05_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_X_SCR_05_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_PR1_SHIFT)
#define GPIO_X_SCR_05_0_PR1_RANGE                       17:17
#define GPIO_X_SCR_05_0_PR1_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_05_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_X_SCR_05_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_PR0_SHIFT)
#define GPIO_X_SCR_05_0_PR0_RANGE                       16:16
#define GPIO_X_SCR_05_0_PR0_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_05_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_X_SCR_05_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G7W_SHIFT)
#define GPIO_X_SCR_05_0_G7W_RANGE                       15:15
#define GPIO_X_SCR_05_0_G7W_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_05_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_X_SCR_05_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G6W_SHIFT)
#define GPIO_X_SCR_05_0_G6W_RANGE                       14:14
#define GPIO_X_SCR_05_0_G6W_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_05_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_X_SCR_05_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G5W_SHIFT)
#define GPIO_X_SCR_05_0_G5W_RANGE                       13:13
#define GPIO_X_SCR_05_0_G5W_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_05_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_X_SCR_05_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G4W_SHIFT)
#define GPIO_X_SCR_05_0_G4W_RANGE                       12:12
#define GPIO_X_SCR_05_0_G4W_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_05_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_X_SCR_05_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G3W_SHIFT)
#define GPIO_X_SCR_05_0_G3W_RANGE                       11:11
#define GPIO_X_SCR_05_0_G3W_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_05_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_X_SCR_05_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G2W_SHIFT)
#define GPIO_X_SCR_05_0_G2W_RANGE                       10:10
#define GPIO_X_SCR_05_0_G2W_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_05_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_X_SCR_05_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G1W_SHIFT)
#define GPIO_X_SCR_05_0_G1W_RANGE                       9:9
#define GPIO_X_SCR_05_0_G1W_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_05_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_X_SCR_05_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G0W_SHIFT)
#define GPIO_X_SCR_05_0_G0W_RANGE                       8:8
#define GPIO_X_SCR_05_0_G0W_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_05_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_X_SCR_05_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G7R_SHIFT)
#define GPIO_X_SCR_05_0_G7R_RANGE                       7:7
#define GPIO_X_SCR_05_0_G7R_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_05_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_X_SCR_05_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G6R_SHIFT)
#define GPIO_X_SCR_05_0_G6R_RANGE                       6:6
#define GPIO_X_SCR_05_0_G6R_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_05_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_X_SCR_05_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G5R_SHIFT)
#define GPIO_X_SCR_05_0_G5R_RANGE                       5:5
#define GPIO_X_SCR_05_0_G5R_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_05_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_X_SCR_05_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G4R_SHIFT)
#define GPIO_X_SCR_05_0_G4R_RANGE                       4:4
#define GPIO_X_SCR_05_0_G4R_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_05_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_X_SCR_05_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G3R_SHIFT)
#define GPIO_X_SCR_05_0_G3R_RANGE                       3:3
#define GPIO_X_SCR_05_0_G3R_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_05_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_X_SCR_05_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G2R_SHIFT)
#define GPIO_X_SCR_05_0_G2R_RANGE                       2:2
#define GPIO_X_SCR_05_0_G2R_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_05_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_X_SCR_05_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G1R_SHIFT)
#define GPIO_X_SCR_05_0_G1R_RANGE                       1:1
#define GPIO_X_SCR_05_0_G1R_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_05_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_X_SCR_05_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G0R_SHIFT)
#define GPIO_X_SCR_05_0_G0R_RANGE                       0:0
#define GPIO_X_SCR_05_0_G0R_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_X_VM_06_0
#define GPIO_X_VM_06_0                  _MK_ADDR_CONST(0x2030)
#define GPIO_X_VM_06_0_SECURE                   0x0
#define GPIO_X_VM_06_0_DUAL                     0x0
#define GPIO_X_VM_06_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_X_VM_06_0_WORD_COUNT                       0x1
#define GPIO_X_VM_06_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_06_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_06_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_06_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_06_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_X_VM_06_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_06_0_VM1_SHIFT)
#define GPIO_X_VM_06_0_VM1_RANGE                        1:0
#define GPIO_X_VM_06_0_VM1_WOFFSET                      0x0
#define GPIO_X_VM_06_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_06_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_06_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_06_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_X_VM_06_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_06_0_VM2_SHIFT)
#define GPIO_X_VM_06_0_VM2_RANGE                        3:2
#define GPIO_X_VM_06_0_VM2_WOFFSET                      0x0
#define GPIO_X_VM_06_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_06_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_06_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_06_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_X_VM_06_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_06_0_VM3_SHIFT)
#define GPIO_X_VM_06_0_VM3_RANGE                        5:4
#define GPIO_X_VM_06_0_VM3_WOFFSET                      0x0
#define GPIO_X_VM_06_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_06_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_06_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_06_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_X_VM_06_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_06_0_VM4_SHIFT)
#define GPIO_X_VM_06_0_VM4_RANGE                        7:6
#define GPIO_X_VM_06_0_VM4_WOFFSET                      0x0
#define GPIO_X_VM_06_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_06_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_06_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_06_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_X_VM_06_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_06_0_VM5_SHIFT)
#define GPIO_X_VM_06_0_VM5_RANGE                        9:8
#define GPIO_X_VM_06_0_VM5_WOFFSET                      0x0
#define GPIO_X_VM_06_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_06_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_06_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_06_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_X_VM_06_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_06_0_VM6_SHIFT)
#define GPIO_X_VM_06_0_VM6_RANGE                        11:10
#define GPIO_X_VM_06_0_VM6_WOFFSET                      0x0
#define GPIO_X_VM_06_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_06_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_06_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_06_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_X_VM_06_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_06_0_VM7_SHIFT)
#define GPIO_X_VM_06_0_VM7_RANGE                        13:12
#define GPIO_X_VM_06_0_VM7_WOFFSET                      0x0
#define GPIO_X_VM_06_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_06_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_06_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_06_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_X_VM_06_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_06_0_VM8_SHIFT)
#define GPIO_X_VM_06_0_VM8_RANGE                        15:14
#define GPIO_X_VM_06_0_VM8_WOFFSET                      0x0
#define GPIO_X_VM_06_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_06_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_06_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_X_SCR_06_0
#define GPIO_X_SCR_06_0                 _MK_ADDR_CONST(0x2034)
#define GPIO_X_SCR_06_0_SECURE                  0x0
#define GPIO_X_SCR_06_0_DUAL                    0x0
#define GPIO_X_SCR_06_0_SCR                     0
#define GPIO_X_SCR_06_0_WORD_COUNT                      0x1
#define GPIO_X_SCR_06_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_06_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_06_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_06_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_X_SCR_06_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_SEC_LCK_SHIFT)
#define GPIO_X_SCR_06_0_SEC_LCK_RANGE                   29:29
#define GPIO_X_SCR_06_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_X_SCR_06_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_06_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_X_SCR_06_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_SEC_WEN_SHIFT)
#define GPIO_X_SCR_06_0_SEC_WEN_RANGE                   28:28
#define GPIO_X_SCR_06_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_X_SCR_06_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_06_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_X_SCR_06_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_SEC_REN_SHIFT)
#define GPIO_X_SCR_06_0_SEC_REN_RANGE                   27:27
#define GPIO_X_SCR_06_0_SEC_REN_WOFFSET                 0x0
#define GPIO_X_SCR_06_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_06_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_X_SCR_06_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_X_SCR_06_0_SEC_OWNER_SHIFT)
#define GPIO_X_SCR_06_0_SEC_OWNER_RANGE                 26:24
#define GPIO_X_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_X_SCR_06_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_X_SCR_06_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_06_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_X_SCR_06_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_PR7_SHIFT)
#define GPIO_X_SCR_06_0_PR7_RANGE                       23:23
#define GPIO_X_SCR_06_0_PR7_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_06_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_X_SCR_06_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_PR6_SHIFT)
#define GPIO_X_SCR_06_0_PR6_RANGE                       22:22
#define GPIO_X_SCR_06_0_PR6_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_06_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_X_SCR_06_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_PR5_SHIFT)
#define GPIO_X_SCR_06_0_PR5_RANGE                       21:21
#define GPIO_X_SCR_06_0_PR5_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_06_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_X_SCR_06_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_PR4_SHIFT)
#define GPIO_X_SCR_06_0_PR4_RANGE                       20:20
#define GPIO_X_SCR_06_0_PR4_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_06_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_X_SCR_06_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_PR3_SHIFT)
#define GPIO_X_SCR_06_0_PR3_RANGE                       19:19
#define GPIO_X_SCR_06_0_PR3_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_06_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_X_SCR_06_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_PR2_SHIFT)
#define GPIO_X_SCR_06_0_PR2_RANGE                       18:18
#define GPIO_X_SCR_06_0_PR2_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_06_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_X_SCR_06_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_PR1_SHIFT)
#define GPIO_X_SCR_06_0_PR1_RANGE                       17:17
#define GPIO_X_SCR_06_0_PR1_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_06_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_X_SCR_06_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_PR0_SHIFT)
#define GPIO_X_SCR_06_0_PR0_RANGE                       16:16
#define GPIO_X_SCR_06_0_PR0_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_06_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_X_SCR_06_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G7W_SHIFT)
#define GPIO_X_SCR_06_0_G7W_RANGE                       15:15
#define GPIO_X_SCR_06_0_G7W_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_06_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_X_SCR_06_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G6W_SHIFT)
#define GPIO_X_SCR_06_0_G6W_RANGE                       14:14
#define GPIO_X_SCR_06_0_G6W_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_06_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_X_SCR_06_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G5W_SHIFT)
#define GPIO_X_SCR_06_0_G5W_RANGE                       13:13
#define GPIO_X_SCR_06_0_G5W_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_06_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_X_SCR_06_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G4W_SHIFT)
#define GPIO_X_SCR_06_0_G4W_RANGE                       12:12
#define GPIO_X_SCR_06_0_G4W_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_06_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_X_SCR_06_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G3W_SHIFT)
#define GPIO_X_SCR_06_0_G3W_RANGE                       11:11
#define GPIO_X_SCR_06_0_G3W_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_06_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_X_SCR_06_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G2W_SHIFT)
#define GPIO_X_SCR_06_0_G2W_RANGE                       10:10
#define GPIO_X_SCR_06_0_G2W_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_06_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_X_SCR_06_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G1W_SHIFT)
#define GPIO_X_SCR_06_0_G1W_RANGE                       9:9
#define GPIO_X_SCR_06_0_G1W_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_06_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_X_SCR_06_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G0W_SHIFT)
#define GPIO_X_SCR_06_0_G0W_RANGE                       8:8
#define GPIO_X_SCR_06_0_G0W_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_06_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_X_SCR_06_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G7R_SHIFT)
#define GPIO_X_SCR_06_0_G7R_RANGE                       7:7
#define GPIO_X_SCR_06_0_G7R_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_06_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_X_SCR_06_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G6R_SHIFT)
#define GPIO_X_SCR_06_0_G6R_RANGE                       6:6
#define GPIO_X_SCR_06_0_G6R_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_06_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_X_SCR_06_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G5R_SHIFT)
#define GPIO_X_SCR_06_0_G5R_RANGE                       5:5
#define GPIO_X_SCR_06_0_G5R_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_06_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_X_SCR_06_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G4R_SHIFT)
#define GPIO_X_SCR_06_0_G4R_RANGE                       4:4
#define GPIO_X_SCR_06_0_G4R_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_06_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_X_SCR_06_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G3R_SHIFT)
#define GPIO_X_SCR_06_0_G3R_RANGE                       3:3
#define GPIO_X_SCR_06_0_G3R_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_06_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_X_SCR_06_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G2R_SHIFT)
#define GPIO_X_SCR_06_0_G2R_RANGE                       2:2
#define GPIO_X_SCR_06_0_G2R_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_06_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_X_SCR_06_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G1R_SHIFT)
#define GPIO_X_SCR_06_0_G1R_RANGE                       1:1
#define GPIO_X_SCR_06_0_G1R_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_06_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_X_SCR_06_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G0R_SHIFT)
#define GPIO_X_SCR_06_0_G0R_RANGE                       0:0
#define GPIO_X_SCR_06_0_G0R_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_X_VM_07_0
#define GPIO_X_VM_07_0                  _MK_ADDR_CONST(0x2038)
#define GPIO_X_VM_07_0_SECURE                   0x0
#define GPIO_X_VM_07_0_DUAL                     0x0
#define GPIO_X_VM_07_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_X_VM_07_0_WORD_COUNT                       0x1
#define GPIO_X_VM_07_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_07_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_07_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_07_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_X_VM_07_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_X_VM_07_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_07_0_VM1_SHIFT)
#define GPIO_X_VM_07_0_VM1_RANGE                        1:0
#define GPIO_X_VM_07_0_VM1_WOFFSET                      0x0
#define GPIO_X_VM_07_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_07_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_07_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_07_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_X_VM_07_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_07_0_VM2_SHIFT)
#define GPIO_X_VM_07_0_VM2_RANGE                        3:2
#define GPIO_X_VM_07_0_VM2_WOFFSET                      0x0
#define GPIO_X_VM_07_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_07_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_07_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_07_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_X_VM_07_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_07_0_VM3_SHIFT)
#define GPIO_X_VM_07_0_VM3_RANGE                        5:4
#define GPIO_X_VM_07_0_VM3_WOFFSET                      0x0
#define GPIO_X_VM_07_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_07_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_07_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_07_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_X_VM_07_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_07_0_VM4_SHIFT)
#define GPIO_X_VM_07_0_VM4_RANGE                        7:6
#define GPIO_X_VM_07_0_VM4_WOFFSET                      0x0
#define GPIO_X_VM_07_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_07_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_07_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_07_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_X_VM_07_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_07_0_VM5_SHIFT)
#define GPIO_X_VM_07_0_VM5_RANGE                        9:8
#define GPIO_X_VM_07_0_VM5_WOFFSET                      0x0
#define GPIO_X_VM_07_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_07_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_07_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_07_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_X_VM_07_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_07_0_VM6_SHIFT)
#define GPIO_X_VM_07_0_VM6_RANGE                        11:10
#define GPIO_X_VM_07_0_VM6_WOFFSET                      0x0
#define GPIO_X_VM_07_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_07_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_07_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_07_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_X_VM_07_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_07_0_VM7_SHIFT)
#define GPIO_X_VM_07_0_VM7_RANGE                        13:12
#define GPIO_X_VM_07_0_VM7_WOFFSET                      0x0
#define GPIO_X_VM_07_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_07_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_07_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_X_VM_07_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_X_VM_07_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_X_VM_07_0_VM8_SHIFT)
#define GPIO_X_VM_07_0_VM8_RANGE                        15:14
#define GPIO_X_VM_07_0_VM8_WOFFSET                      0x0
#define GPIO_X_VM_07_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_X_VM_07_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_X_VM_07_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_X_SCR_07_0
#define GPIO_X_SCR_07_0                 _MK_ADDR_CONST(0x203c)
#define GPIO_X_SCR_07_0_SECURE                  0x0
#define GPIO_X_SCR_07_0_DUAL                    0x0
#define GPIO_X_SCR_07_0_SCR                     0
#define GPIO_X_SCR_07_0_WORD_COUNT                      0x1
#define GPIO_X_SCR_07_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_07_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_07_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_07_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_X_SCR_07_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_SEC_LCK_SHIFT)
#define GPIO_X_SCR_07_0_SEC_LCK_RANGE                   29:29
#define GPIO_X_SCR_07_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_X_SCR_07_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_07_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_X_SCR_07_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_SEC_WEN_SHIFT)
#define GPIO_X_SCR_07_0_SEC_WEN_RANGE                   28:28
#define GPIO_X_SCR_07_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_X_SCR_07_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_07_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_X_SCR_07_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_SEC_REN_SHIFT)
#define GPIO_X_SCR_07_0_SEC_REN_RANGE                   27:27
#define GPIO_X_SCR_07_0_SEC_REN_WOFFSET                 0x0
#define GPIO_X_SCR_07_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_07_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_X_SCR_07_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_X_SCR_07_0_SEC_OWNER_SHIFT)
#define GPIO_X_SCR_07_0_SEC_OWNER_RANGE                 26:24
#define GPIO_X_SCR_07_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_X_SCR_07_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_X_SCR_07_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_07_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_X_SCR_07_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_PR7_SHIFT)
#define GPIO_X_SCR_07_0_PR7_RANGE                       23:23
#define GPIO_X_SCR_07_0_PR7_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_07_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_X_SCR_07_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_PR6_SHIFT)
#define GPIO_X_SCR_07_0_PR6_RANGE                       22:22
#define GPIO_X_SCR_07_0_PR6_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_07_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_X_SCR_07_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_PR5_SHIFT)
#define GPIO_X_SCR_07_0_PR5_RANGE                       21:21
#define GPIO_X_SCR_07_0_PR5_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_07_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_X_SCR_07_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_PR4_SHIFT)
#define GPIO_X_SCR_07_0_PR4_RANGE                       20:20
#define GPIO_X_SCR_07_0_PR4_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_07_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_X_SCR_07_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_PR3_SHIFT)
#define GPIO_X_SCR_07_0_PR3_RANGE                       19:19
#define GPIO_X_SCR_07_0_PR3_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_07_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_X_SCR_07_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_PR2_SHIFT)
#define GPIO_X_SCR_07_0_PR2_RANGE                       18:18
#define GPIO_X_SCR_07_0_PR2_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_07_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_X_SCR_07_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_PR1_SHIFT)
#define GPIO_X_SCR_07_0_PR1_RANGE                       17:17
#define GPIO_X_SCR_07_0_PR1_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_07_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_X_SCR_07_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_PR0_SHIFT)
#define GPIO_X_SCR_07_0_PR0_RANGE                       16:16
#define GPIO_X_SCR_07_0_PR0_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_07_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_X_SCR_07_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G7W_SHIFT)
#define GPIO_X_SCR_07_0_G7W_RANGE                       15:15
#define GPIO_X_SCR_07_0_G7W_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_07_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_X_SCR_07_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G6W_SHIFT)
#define GPIO_X_SCR_07_0_G6W_RANGE                       14:14
#define GPIO_X_SCR_07_0_G6W_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_07_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_X_SCR_07_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G5W_SHIFT)
#define GPIO_X_SCR_07_0_G5W_RANGE                       13:13
#define GPIO_X_SCR_07_0_G5W_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_07_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_X_SCR_07_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G4W_SHIFT)
#define GPIO_X_SCR_07_0_G4W_RANGE                       12:12
#define GPIO_X_SCR_07_0_G4W_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_07_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_X_SCR_07_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G3W_SHIFT)
#define GPIO_X_SCR_07_0_G3W_RANGE                       11:11
#define GPIO_X_SCR_07_0_G3W_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_07_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_X_SCR_07_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G2W_SHIFT)
#define GPIO_X_SCR_07_0_G2W_RANGE                       10:10
#define GPIO_X_SCR_07_0_G2W_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_07_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_X_SCR_07_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G1W_SHIFT)
#define GPIO_X_SCR_07_0_G1W_RANGE                       9:9
#define GPIO_X_SCR_07_0_G1W_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_07_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_X_SCR_07_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G0W_SHIFT)
#define GPIO_X_SCR_07_0_G0W_RANGE                       8:8
#define GPIO_X_SCR_07_0_G0W_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_07_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_X_SCR_07_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G7R_SHIFT)
#define GPIO_X_SCR_07_0_G7R_RANGE                       7:7
#define GPIO_X_SCR_07_0_G7R_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_07_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_X_SCR_07_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G6R_SHIFT)
#define GPIO_X_SCR_07_0_G6R_RANGE                       6:6
#define GPIO_X_SCR_07_0_G6R_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_07_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_X_SCR_07_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G5R_SHIFT)
#define GPIO_X_SCR_07_0_G5R_RANGE                       5:5
#define GPIO_X_SCR_07_0_G5R_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_07_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_X_SCR_07_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G4R_SHIFT)
#define GPIO_X_SCR_07_0_G4R_RANGE                       4:4
#define GPIO_X_SCR_07_0_G4R_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_07_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_X_SCR_07_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G3R_SHIFT)
#define GPIO_X_SCR_07_0_G3R_RANGE                       3:3
#define GPIO_X_SCR_07_0_G3R_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_07_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_X_SCR_07_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G2R_SHIFT)
#define GPIO_X_SCR_07_0_G2R_RANGE                       2:2
#define GPIO_X_SCR_07_0_G2R_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_07_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_X_SCR_07_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G1R_SHIFT)
#define GPIO_X_SCR_07_0_G1R_RANGE                       1:1
#define GPIO_X_SCR_07_0_G1R_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_X_SCR_07_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_X_SCR_07_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G0R_SHIFT)
#define GPIO_X_SCR_07_0_G0R_RANGE                       0:0
#define GPIO_X_SCR_07_0_G0R_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_Y_VM_00_0
#define GPIO_Y_VM_00_0                  _MK_ADDR_CONST(0x2040)
#define GPIO_Y_VM_00_0_SECURE                   0x0
#define GPIO_Y_VM_00_0_DUAL                     0x0
#define GPIO_Y_VM_00_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_Y_VM_00_0_WORD_COUNT                       0x1
#define GPIO_Y_VM_00_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_00_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_00_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_00_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Y_VM_00_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_00_0_VM1_SHIFT)
#define GPIO_Y_VM_00_0_VM1_RANGE                        1:0
#define GPIO_Y_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_Y_VM_00_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_00_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_00_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_00_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_Y_VM_00_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_00_0_VM2_SHIFT)
#define GPIO_Y_VM_00_0_VM2_RANGE                        3:2
#define GPIO_Y_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_Y_VM_00_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_00_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_00_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_00_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_Y_VM_00_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_00_0_VM3_SHIFT)
#define GPIO_Y_VM_00_0_VM3_RANGE                        5:4
#define GPIO_Y_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_Y_VM_00_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_00_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_00_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_00_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_Y_VM_00_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_00_0_VM4_SHIFT)
#define GPIO_Y_VM_00_0_VM4_RANGE                        7:6
#define GPIO_Y_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_Y_VM_00_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_00_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_00_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_00_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_Y_VM_00_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_00_0_VM5_SHIFT)
#define GPIO_Y_VM_00_0_VM5_RANGE                        9:8
#define GPIO_Y_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_Y_VM_00_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_00_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_00_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_00_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_Y_VM_00_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_00_0_VM6_SHIFT)
#define GPIO_Y_VM_00_0_VM6_RANGE                        11:10
#define GPIO_Y_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_Y_VM_00_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_00_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_00_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_00_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_Y_VM_00_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_00_0_VM7_SHIFT)
#define GPIO_Y_VM_00_0_VM7_RANGE                        13:12
#define GPIO_Y_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_Y_VM_00_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_00_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_00_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_00_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_Y_VM_00_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_00_0_VM8_SHIFT)
#define GPIO_Y_VM_00_0_VM8_RANGE                        15:14
#define GPIO_Y_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_Y_VM_00_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_00_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_00_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_Y_SCR_00_0
#define GPIO_Y_SCR_00_0                 _MK_ADDR_CONST(0x2044)
#define GPIO_Y_SCR_00_0_SECURE                  0x0
#define GPIO_Y_SCR_00_0_DUAL                    0x0
#define GPIO_Y_SCR_00_0_SCR                     0
#define GPIO_Y_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_Y_SCR_00_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_00_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_00_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_Y_SCR_00_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_Y_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_Y_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Y_SCR_00_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_00_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_Y_SCR_00_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_Y_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_Y_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Y_SCR_00_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_00_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_Y_SCR_00_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_Y_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_Y_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Y_SCR_00_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_00_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_Y_SCR_00_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_Y_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_Y_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Y_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Y_SCR_00_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_Y_SCR_00_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_00_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_Y_SCR_00_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_PR7_SHIFT)
#define GPIO_Y_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_Y_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_00_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_Y_SCR_00_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_PR6_SHIFT)
#define GPIO_Y_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_Y_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_00_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_Y_SCR_00_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_PR5_SHIFT)
#define GPIO_Y_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_Y_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_00_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_Y_SCR_00_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_PR4_SHIFT)
#define GPIO_Y_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_Y_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_00_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_Y_SCR_00_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_PR3_SHIFT)
#define GPIO_Y_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_Y_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_00_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_Y_SCR_00_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_PR2_SHIFT)
#define GPIO_Y_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_Y_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_00_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_Y_SCR_00_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_PR1_SHIFT)
#define GPIO_Y_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_Y_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_00_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_Y_SCR_00_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_PR0_SHIFT)
#define GPIO_Y_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_Y_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_00_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_Y_SCR_00_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G7W_SHIFT)
#define GPIO_Y_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_Y_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_00_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_Y_SCR_00_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G6W_SHIFT)
#define GPIO_Y_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_Y_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_00_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_Y_SCR_00_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G5W_SHIFT)
#define GPIO_Y_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_Y_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_00_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_Y_SCR_00_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G4W_SHIFT)
#define GPIO_Y_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_Y_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_00_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_Y_SCR_00_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G3W_SHIFT)
#define GPIO_Y_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_Y_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_00_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_Y_SCR_00_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G2W_SHIFT)
#define GPIO_Y_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_Y_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_00_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_Y_SCR_00_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G1W_SHIFT)
#define GPIO_Y_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_Y_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_00_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_Y_SCR_00_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G0W_SHIFT)
#define GPIO_Y_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_Y_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_00_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_Y_SCR_00_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G7R_SHIFT)
#define GPIO_Y_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_Y_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_00_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_Y_SCR_00_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G6R_SHIFT)
#define GPIO_Y_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_Y_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_00_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Y_SCR_00_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G5R_SHIFT)
#define GPIO_Y_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_Y_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_00_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_Y_SCR_00_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G4R_SHIFT)
#define GPIO_Y_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_Y_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_00_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_Y_SCR_00_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G3R_SHIFT)
#define GPIO_Y_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_Y_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_00_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_Y_SCR_00_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G2R_SHIFT)
#define GPIO_Y_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_Y_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_00_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_Y_SCR_00_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G1R_SHIFT)
#define GPIO_Y_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_Y_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_00_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Y_SCR_00_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G0R_SHIFT)
#define GPIO_Y_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_Y_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_Y_VM_01_0
#define GPIO_Y_VM_01_0                  _MK_ADDR_CONST(0x2048)
#define GPIO_Y_VM_01_0_SECURE                   0x0
#define GPIO_Y_VM_01_0_DUAL                     0x0
#define GPIO_Y_VM_01_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_Y_VM_01_0_WORD_COUNT                       0x1
#define GPIO_Y_VM_01_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_01_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_01_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_01_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Y_VM_01_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_01_0_VM1_SHIFT)
#define GPIO_Y_VM_01_0_VM1_RANGE                        1:0
#define GPIO_Y_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_Y_VM_01_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_01_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_01_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_01_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_Y_VM_01_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_01_0_VM2_SHIFT)
#define GPIO_Y_VM_01_0_VM2_RANGE                        3:2
#define GPIO_Y_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_Y_VM_01_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_01_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_01_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_01_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_Y_VM_01_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_01_0_VM3_SHIFT)
#define GPIO_Y_VM_01_0_VM3_RANGE                        5:4
#define GPIO_Y_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_Y_VM_01_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_01_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_01_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_01_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_Y_VM_01_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_01_0_VM4_SHIFT)
#define GPIO_Y_VM_01_0_VM4_RANGE                        7:6
#define GPIO_Y_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_Y_VM_01_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_01_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_01_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_01_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_Y_VM_01_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_01_0_VM5_SHIFT)
#define GPIO_Y_VM_01_0_VM5_RANGE                        9:8
#define GPIO_Y_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_Y_VM_01_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_01_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_01_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_01_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_Y_VM_01_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_01_0_VM6_SHIFT)
#define GPIO_Y_VM_01_0_VM6_RANGE                        11:10
#define GPIO_Y_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_Y_VM_01_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_01_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_01_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_01_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_Y_VM_01_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_01_0_VM7_SHIFT)
#define GPIO_Y_VM_01_0_VM7_RANGE                        13:12
#define GPIO_Y_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_Y_VM_01_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_01_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_01_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_01_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_Y_VM_01_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_01_0_VM8_SHIFT)
#define GPIO_Y_VM_01_0_VM8_RANGE                        15:14
#define GPIO_Y_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_Y_VM_01_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_01_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_01_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_Y_SCR_01_0
#define GPIO_Y_SCR_01_0                 _MK_ADDR_CONST(0x204c)
#define GPIO_Y_SCR_01_0_SECURE                  0x0
#define GPIO_Y_SCR_01_0_DUAL                    0x0
#define GPIO_Y_SCR_01_0_SCR                     0
#define GPIO_Y_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_Y_SCR_01_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_01_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_01_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_01_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_Y_SCR_01_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_Y_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_Y_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Y_SCR_01_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_01_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_Y_SCR_01_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_Y_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_Y_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Y_SCR_01_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_01_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_Y_SCR_01_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_Y_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_Y_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Y_SCR_01_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_01_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_Y_SCR_01_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_Y_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_Y_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Y_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Y_SCR_01_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_Y_SCR_01_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_01_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_Y_SCR_01_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_PR7_SHIFT)
#define GPIO_Y_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_Y_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_01_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_Y_SCR_01_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_PR6_SHIFT)
#define GPIO_Y_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_Y_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_01_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_Y_SCR_01_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_PR5_SHIFT)
#define GPIO_Y_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_Y_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_01_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_Y_SCR_01_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_PR4_SHIFT)
#define GPIO_Y_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_Y_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_01_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_Y_SCR_01_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_PR3_SHIFT)
#define GPIO_Y_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_Y_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_01_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_Y_SCR_01_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_PR2_SHIFT)
#define GPIO_Y_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_Y_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_01_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_Y_SCR_01_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_PR1_SHIFT)
#define GPIO_Y_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_Y_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_01_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_Y_SCR_01_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_PR0_SHIFT)
#define GPIO_Y_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_Y_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_01_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_Y_SCR_01_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G7W_SHIFT)
#define GPIO_Y_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_Y_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_01_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_Y_SCR_01_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G6W_SHIFT)
#define GPIO_Y_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_Y_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_01_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_Y_SCR_01_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G5W_SHIFT)
#define GPIO_Y_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_Y_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_01_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_Y_SCR_01_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G4W_SHIFT)
#define GPIO_Y_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_Y_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_01_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_Y_SCR_01_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G3W_SHIFT)
#define GPIO_Y_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_Y_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_01_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_Y_SCR_01_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G2W_SHIFT)
#define GPIO_Y_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_Y_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_01_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_Y_SCR_01_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G1W_SHIFT)
#define GPIO_Y_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_Y_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_01_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_Y_SCR_01_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G0W_SHIFT)
#define GPIO_Y_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_Y_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_01_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_Y_SCR_01_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G7R_SHIFT)
#define GPIO_Y_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_Y_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_01_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_Y_SCR_01_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G6R_SHIFT)
#define GPIO_Y_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_Y_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_01_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Y_SCR_01_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G5R_SHIFT)
#define GPIO_Y_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_Y_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_01_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_Y_SCR_01_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G4R_SHIFT)
#define GPIO_Y_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_Y_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_01_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_Y_SCR_01_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G3R_SHIFT)
#define GPIO_Y_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_Y_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_01_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_Y_SCR_01_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G2R_SHIFT)
#define GPIO_Y_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_Y_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_01_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_Y_SCR_01_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G1R_SHIFT)
#define GPIO_Y_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_Y_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_01_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Y_SCR_01_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G0R_SHIFT)
#define GPIO_Y_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_Y_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_Y_VM_02_0
#define GPIO_Y_VM_02_0                  _MK_ADDR_CONST(0x2050)
#define GPIO_Y_VM_02_0_SECURE                   0x0
#define GPIO_Y_VM_02_0_DUAL                     0x0
#define GPIO_Y_VM_02_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_Y_VM_02_0_WORD_COUNT                       0x1
#define GPIO_Y_VM_02_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_02_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_02_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_02_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Y_VM_02_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_02_0_VM1_SHIFT)
#define GPIO_Y_VM_02_0_VM1_RANGE                        1:0
#define GPIO_Y_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_Y_VM_02_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_02_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_02_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_02_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_Y_VM_02_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_02_0_VM2_SHIFT)
#define GPIO_Y_VM_02_0_VM2_RANGE                        3:2
#define GPIO_Y_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_Y_VM_02_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_02_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_02_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_02_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_Y_VM_02_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_02_0_VM3_SHIFT)
#define GPIO_Y_VM_02_0_VM3_RANGE                        5:4
#define GPIO_Y_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_Y_VM_02_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_02_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_02_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_02_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_Y_VM_02_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_02_0_VM4_SHIFT)
#define GPIO_Y_VM_02_0_VM4_RANGE                        7:6
#define GPIO_Y_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_Y_VM_02_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_02_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_02_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_02_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_Y_VM_02_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_02_0_VM5_SHIFT)
#define GPIO_Y_VM_02_0_VM5_RANGE                        9:8
#define GPIO_Y_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_Y_VM_02_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_02_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_02_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_02_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_Y_VM_02_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_02_0_VM6_SHIFT)
#define GPIO_Y_VM_02_0_VM6_RANGE                        11:10
#define GPIO_Y_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_Y_VM_02_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_02_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_02_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_02_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_Y_VM_02_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_02_0_VM7_SHIFT)
#define GPIO_Y_VM_02_0_VM7_RANGE                        13:12
#define GPIO_Y_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_Y_VM_02_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_02_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_02_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_02_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_Y_VM_02_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_02_0_VM8_SHIFT)
#define GPIO_Y_VM_02_0_VM8_RANGE                        15:14
#define GPIO_Y_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_Y_VM_02_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_02_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_02_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_Y_SCR_02_0
#define GPIO_Y_SCR_02_0                 _MK_ADDR_CONST(0x2054)
#define GPIO_Y_SCR_02_0_SECURE                  0x0
#define GPIO_Y_SCR_02_0_DUAL                    0x0
#define GPIO_Y_SCR_02_0_SCR                     0
#define GPIO_Y_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_Y_SCR_02_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_02_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_02_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_02_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_Y_SCR_02_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_Y_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_Y_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Y_SCR_02_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_02_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_Y_SCR_02_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_Y_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_Y_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Y_SCR_02_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_02_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_Y_SCR_02_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_Y_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_Y_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Y_SCR_02_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_02_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_Y_SCR_02_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_Y_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_Y_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Y_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Y_SCR_02_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_Y_SCR_02_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_02_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_Y_SCR_02_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_PR7_SHIFT)
#define GPIO_Y_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_Y_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_02_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_Y_SCR_02_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_PR6_SHIFT)
#define GPIO_Y_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_Y_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_02_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_Y_SCR_02_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_PR5_SHIFT)
#define GPIO_Y_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_Y_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_02_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_Y_SCR_02_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_PR4_SHIFT)
#define GPIO_Y_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_Y_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_02_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_Y_SCR_02_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_PR3_SHIFT)
#define GPIO_Y_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_Y_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_02_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_Y_SCR_02_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_PR2_SHIFT)
#define GPIO_Y_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_Y_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_02_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_Y_SCR_02_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_PR1_SHIFT)
#define GPIO_Y_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_Y_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_02_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_Y_SCR_02_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_PR0_SHIFT)
#define GPIO_Y_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_Y_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_02_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_Y_SCR_02_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G7W_SHIFT)
#define GPIO_Y_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_Y_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_02_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_Y_SCR_02_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G6W_SHIFT)
#define GPIO_Y_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_Y_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_02_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_Y_SCR_02_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G5W_SHIFT)
#define GPIO_Y_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_Y_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_02_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_Y_SCR_02_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G4W_SHIFT)
#define GPIO_Y_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_Y_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_02_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_Y_SCR_02_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G3W_SHIFT)
#define GPIO_Y_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_Y_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_02_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_Y_SCR_02_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G2W_SHIFT)
#define GPIO_Y_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_Y_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_02_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_Y_SCR_02_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G1W_SHIFT)
#define GPIO_Y_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_Y_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_02_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_Y_SCR_02_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G0W_SHIFT)
#define GPIO_Y_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_Y_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_02_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_Y_SCR_02_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G7R_SHIFT)
#define GPIO_Y_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_Y_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_02_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_Y_SCR_02_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G6R_SHIFT)
#define GPIO_Y_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_Y_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_02_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Y_SCR_02_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G5R_SHIFT)
#define GPIO_Y_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_Y_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_02_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_Y_SCR_02_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G4R_SHIFT)
#define GPIO_Y_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_Y_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_02_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_Y_SCR_02_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G3R_SHIFT)
#define GPIO_Y_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_Y_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_02_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_Y_SCR_02_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G2R_SHIFT)
#define GPIO_Y_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_Y_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_02_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_Y_SCR_02_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G1R_SHIFT)
#define GPIO_Y_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_Y_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_02_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Y_SCR_02_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G0R_SHIFT)
#define GPIO_Y_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_Y_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_Y_VM_03_0
#define GPIO_Y_VM_03_0                  _MK_ADDR_CONST(0x2058)
#define GPIO_Y_VM_03_0_SECURE                   0x0
#define GPIO_Y_VM_03_0_DUAL                     0x0
#define GPIO_Y_VM_03_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_Y_VM_03_0_WORD_COUNT                       0x1
#define GPIO_Y_VM_03_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_03_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_03_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_03_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Y_VM_03_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_03_0_VM1_SHIFT)
#define GPIO_Y_VM_03_0_VM1_RANGE                        1:0
#define GPIO_Y_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_Y_VM_03_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_03_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_03_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_03_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_Y_VM_03_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_03_0_VM2_SHIFT)
#define GPIO_Y_VM_03_0_VM2_RANGE                        3:2
#define GPIO_Y_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_Y_VM_03_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_03_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_03_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_03_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_Y_VM_03_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_03_0_VM3_SHIFT)
#define GPIO_Y_VM_03_0_VM3_RANGE                        5:4
#define GPIO_Y_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_Y_VM_03_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_03_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_03_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_03_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_Y_VM_03_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_03_0_VM4_SHIFT)
#define GPIO_Y_VM_03_0_VM4_RANGE                        7:6
#define GPIO_Y_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_Y_VM_03_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_03_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_03_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_03_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_Y_VM_03_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_03_0_VM5_SHIFT)
#define GPIO_Y_VM_03_0_VM5_RANGE                        9:8
#define GPIO_Y_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_Y_VM_03_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_03_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_03_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_03_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_Y_VM_03_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_03_0_VM6_SHIFT)
#define GPIO_Y_VM_03_0_VM6_RANGE                        11:10
#define GPIO_Y_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_Y_VM_03_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_03_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_03_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_03_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_Y_VM_03_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_03_0_VM7_SHIFT)
#define GPIO_Y_VM_03_0_VM7_RANGE                        13:12
#define GPIO_Y_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_Y_VM_03_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_03_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_03_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_03_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_Y_VM_03_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_03_0_VM8_SHIFT)
#define GPIO_Y_VM_03_0_VM8_RANGE                        15:14
#define GPIO_Y_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_Y_VM_03_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_03_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_03_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_Y_SCR_03_0
#define GPIO_Y_SCR_03_0                 _MK_ADDR_CONST(0x205c)
#define GPIO_Y_SCR_03_0_SECURE                  0x0
#define GPIO_Y_SCR_03_0_DUAL                    0x0
#define GPIO_Y_SCR_03_0_SCR                     0
#define GPIO_Y_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_Y_SCR_03_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_03_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_03_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_03_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_Y_SCR_03_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_Y_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_Y_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Y_SCR_03_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_03_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_Y_SCR_03_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_Y_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_Y_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Y_SCR_03_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_03_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_Y_SCR_03_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_Y_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_Y_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Y_SCR_03_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_03_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_Y_SCR_03_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_Y_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_Y_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Y_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Y_SCR_03_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_Y_SCR_03_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_03_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_Y_SCR_03_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_PR7_SHIFT)
#define GPIO_Y_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_Y_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_03_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_Y_SCR_03_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_PR6_SHIFT)
#define GPIO_Y_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_Y_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_03_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_Y_SCR_03_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_PR5_SHIFT)
#define GPIO_Y_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_Y_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_03_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_Y_SCR_03_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_PR4_SHIFT)
#define GPIO_Y_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_Y_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_03_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_Y_SCR_03_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_PR3_SHIFT)
#define GPIO_Y_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_Y_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_03_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_Y_SCR_03_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_PR2_SHIFT)
#define GPIO_Y_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_Y_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_03_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_Y_SCR_03_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_PR1_SHIFT)
#define GPIO_Y_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_Y_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_03_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_Y_SCR_03_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_PR0_SHIFT)
#define GPIO_Y_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_Y_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_03_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_Y_SCR_03_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G7W_SHIFT)
#define GPIO_Y_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_Y_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_03_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_Y_SCR_03_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G6W_SHIFT)
#define GPIO_Y_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_Y_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_03_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_Y_SCR_03_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G5W_SHIFT)
#define GPIO_Y_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_Y_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_03_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_Y_SCR_03_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G4W_SHIFT)
#define GPIO_Y_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_Y_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_03_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_Y_SCR_03_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G3W_SHIFT)
#define GPIO_Y_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_Y_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_03_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_Y_SCR_03_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G2W_SHIFT)
#define GPIO_Y_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_Y_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_03_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_Y_SCR_03_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G1W_SHIFT)
#define GPIO_Y_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_Y_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_03_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_Y_SCR_03_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G0W_SHIFT)
#define GPIO_Y_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_Y_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_03_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_Y_SCR_03_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G7R_SHIFT)
#define GPIO_Y_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_Y_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_03_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_Y_SCR_03_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G6R_SHIFT)
#define GPIO_Y_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_Y_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_03_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Y_SCR_03_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G5R_SHIFT)
#define GPIO_Y_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_Y_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_03_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_Y_SCR_03_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G4R_SHIFT)
#define GPIO_Y_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_Y_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_03_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_Y_SCR_03_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G3R_SHIFT)
#define GPIO_Y_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_Y_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_03_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_Y_SCR_03_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G2R_SHIFT)
#define GPIO_Y_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_Y_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_03_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_Y_SCR_03_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G1R_SHIFT)
#define GPIO_Y_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_Y_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_03_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Y_SCR_03_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G0R_SHIFT)
#define GPIO_Y_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_Y_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_Y_VM_04_0
#define GPIO_Y_VM_04_0                  _MK_ADDR_CONST(0x2060)
#define GPIO_Y_VM_04_0_SECURE                   0x0
#define GPIO_Y_VM_04_0_DUAL                     0x0
#define GPIO_Y_VM_04_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_Y_VM_04_0_WORD_COUNT                       0x1
#define GPIO_Y_VM_04_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_04_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_04_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_04_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Y_VM_04_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_04_0_VM1_SHIFT)
#define GPIO_Y_VM_04_0_VM1_RANGE                        1:0
#define GPIO_Y_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_Y_VM_04_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_04_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_04_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_04_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_Y_VM_04_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_04_0_VM2_SHIFT)
#define GPIO_Y_VM_04_0_VM2_RANGE                        3:2
#define GPIO_Y_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_Y_VM_04_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_04_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_04_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_04_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_Y_VM_04_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_04_0_VM3_SHIFT)
#define GPIO_Y_VM_04_0_VM3_RANGE                        5:4
#define GPIO_Y_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_Y_VM_04_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_04_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_04_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_04_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_Y_VM_04_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_04_0_VM4_SHIFT)
#define GPIO_Y_VM_04_0_VM4_RANGE                        7:6
#define GPIO_Y_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_Y_VM_04_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_04_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_04_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_04_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_Y_VM_04_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_04_0_VM5_SHIFT)
#define GPIO_Y_VM_04_0_VM5_RANGE                        9:8
#define GPIO_Y_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_Y_VM_04_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_04_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_04_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_04_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_Y_VM_04_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_04_0_VM6_SHIFT)
#define GPIO_Y_VM_04_0_VM6_RANGE                        11:10
#define GPIO_Y_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_Y_VM_04_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_04_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_04_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_04_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_Y_VM_04_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_04_0_VM7_SHIFT)
#define GPIO_Y_VM_04_0_VM7_RANGE                        13:12
#define GPIO_Y_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_Y_VM_04_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_04_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_04_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_04_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_Y_VM_04_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_04_0_VM8_SHIFT)
#define GPIO_Y_VM_04_0_VM8_RANGE                        15:14
#define GPIO_Y_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_Y_VM_04_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_04_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_04_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_Y_SCR_04_0
#define GPIO_Y_SCR_04_0                 _MK_ADDR_CONST(0x2064)
#define GPIO_Y_SCR_04_0_SECURE                  0x0
#define GPIO_Y_SCR_04_0_DUAL                    0x0
#define GPIO_Y_SCR_04_0_SCR                     0
#define GPIO_Y_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_Y_SCR_04_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_04_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_04_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_04_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_Y_SCR_04_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_Y_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_Y_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Y_SCR_04_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_04_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_Y_SCR_04_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_Y_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_Y_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Y_SCR_04_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_04_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_Y_SCR_04_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_Y_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_Y_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Y_SCR_04_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_04_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_Y_SCR_04_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_Y_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_Y_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Y_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Y_SCR_04_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_Y_SCR_04_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_04_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_Y_SCR_04_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_PR7_SHIFT)
#define GPIO_Y_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_Y_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_04_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_Y_SCR_04_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_PR6_SHIFT)
#define GPIO_Y_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_Y_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_04_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_Y_SCR_04_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_PR5_SHIFT)
#define GPIO_Y_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_Y_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_04_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_Y_SCR_04_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_PR4_SHIFT)
#define GPIO_Y_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_Y_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_04_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_Y_SCR_04_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_PR3_SHIFT)
#define GPIO_Y_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_Y_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_04_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_Y_SCR_04_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_PR2_SHIFT)
#define GPIO_Y_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_Y_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_04_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_Y_SCR_04_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_PR1_SHIFT)
#define GPIO_Y_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_Y_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_04_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_Y_SCR_04_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_PR0_SHIFT)
#define GPIO_Y_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_Y_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_04_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_Y_SCR_04_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G7W_SHIFT)
#define GPIO_Y_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_Y_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_04_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_Y_SCR_04_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G6W_SHIFT)
#define GPIO_Y_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_Y_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_04_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_Y_SCR_04_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G5W_SHIFT)
#define GPIO_Y_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_Y_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_04_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_Y_SCR_04_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G4W_SHIFT)
#define GPIO_Y_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_Y_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_04_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_Y_SCR_04_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G3W_SHIFT)
#define GPIO_Y_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_Y_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_04_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_Y_SCR_04_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G2W_SHIFT)
#define GPIO_Y_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_Y_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_04_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_Y_SCR_04_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G1W_SHIFT)
#define GPIO_Y_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_Y_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_04_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_Y_SCR_04_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G0W_SHIFT)
#define GPIO_Y_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_Y_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_04_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_Y_SCR_04_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G7R_SHIFT)
#define GPIO_Y_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_Y_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_04_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_Y_SCR_04_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G6R_SHIFT)
#define GPIO_Y_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_Y_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_04_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Y_SCR_04_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G5R_SHIFT)
#define GPIO_Y_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_Y_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_04_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_Y_SCR_04_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G4R_SHIFT)
#define GPIO_Y_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_Y_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_04_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_Y_SCR_04_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G3R_SHIFT)
#define GPIO_Y_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_Y_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_04_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_Y_SCR_04_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G2R_SHIFT)
#define GPIO_Y_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_Y_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_04_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_Y_SCR_04_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G1R_SHIFT)
#define GPIO_Y_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_Y_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_04_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Y_SCR_04_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G0R_SHIFT)
#define GPIO_Y_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_Y_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_Y_VM_05_0
#define GPIO_Y_VM_05_0                  _MK_ADDR_CONST(0x2068)
#define GPIO_Y_VM_05_0_SECURE                   0x0
#define GPIO_Y_VM_05_0_DUAL                     0x0
#define GPIO_Y_VM_05_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_Y_VM_05_0_WORD_COUNT                       0x1
#define GPIO_Y_VM_05_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_05_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_05_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_05_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Y_VM_05_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_05_0_VM1_SHIFT)
#define GPIO_Y_VM_05_0_VM1_RANGE                        1:0
#define GPIO_Y_VM_05_0_VM1_WOFFSET                      0x0
#define GPIO_Y_VM_05_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_05_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_05_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_05_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_Y_VM_05_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_05_0_VM2_SHIFT)
#define GPIO_Y_VM_05_0_VM2_RANGE                        3:2
#define GPIO_Y_VM_05_0_VM2_WOFFSET                      0x0
#define GPIO_Y_VM_05_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_05_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_05_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_05_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_Y_VM_05_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_05_0_VM3_SHIFT)
#define GPIO_Y_VM_05_0_VM3_RANGE                        5:4
#define GPIO_Y_VM_05_0_VM3_WOFFSET                      0x0
#define GPIO_Y_VM_05_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_05_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_05_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_05_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_Y_VM_05_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_05_0_VM4_SHIFT)
#define GPIO_Y_VM_05_0_VM4_RANGE                        7:6
#define GPIO_Y_VM_05_0_VM4_WOFFSET                      0x0
#define GPIO_Y_VM_05_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_05_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_05_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_05_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_Y_VM_05_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_05_0_VM5_SHIFT)
#define GPIO_Y_VM_05_0_VM5_RANGE                        9:8
#define GPIO_Y_VM_05_0_VM5_WOFFSET                      0x0
#define GPIO_Y_VM_05_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_05_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_05_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_05_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_Y_VM_05_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_05_0_VM6_SHIFT)
#define GPIO_Y_VM_05_0_VM6_RANGE                        11:10
#define GPIO_Y_VM_05_0_VM6_WOFFSET                      0x0
#define GPIO_Y_VM_05_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_05_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_05_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_05_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_Y_VM_05_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_05_0_VM7_SHIFT)
#define GPIO_Y_VM_05_0_VM7_RANGE                        13:12
#define GPIO_Y_VM_05_0_VM7_WOFFSET                      0x0
#define GPIO_Y_VM_05_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_05_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_05_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_05_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_Y_VM_05_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_05_0_VM8_SHIFT)
#define GPIO_Y_VM_05_0_VM8_RANGE                        15:14
#define GPIO_Y_VM_05_0_VM8_WOFFSET                      0x0
#define GPIO_Y_VM_05_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_05_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_05_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_Y_SCR_05_0
#define GPIO_Y_SCR_05_0                 _MK_ADDR_CONST(0x206c)
#define GPIO_Y_SCR_05_0_SECURE                  0x0
#define GPIO_Y_SCR_05_0_DUAL                    0x0
#define GPIO_Y_SCR_05_0_SCR                     0
#define GPIO_Y_SCR_05_0_WORD_COUNT                      0x1
#define GPIO_Y_SCR_05_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_05_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_05_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_05_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_Y_SCR_05_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_Y_SCR_05_0_SEC_LCK_RANGE                   29:29
#define GPIO_Y_SCR_05_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Y_SCR_05_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_05_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_Y_SCR_05_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_Y_SCR_05_0_SEC_WEN_RANGE                   28:28
#define GPIO_Y_SCR_05_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Y_SCR_05_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_05_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_Y_SCR_05_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_Y_SCR_05_0_SEC_REN_RANGE                   27:27
#define GPIO_Y_SCR_05_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Y_SCR_05_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_05_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_Y_SCR_05_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_Y_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_Y_SCR_05_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Y_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Y_SCR_05_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_Y_SCR_05_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_05_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_Y_SCR_05_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_PR7_SHIFT)
#define GPIO_Y_SCR_05_0_PR7_RANGE                       23:23
#define GPIO_Y_SCR_05_0_PR7_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_05_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_Y_SCR_05_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_PR6_SHIFT)
#define GPIO_Y_SCR_05_0_PR6_RANGE                       22:22
#define GPIO_Y_SCR_05_0_PR6_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_05_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_Y_SCR_05_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_PR5_SHIFT)
#define GPIO_Y_SCR_05_0_PR5_RANGE                       21:21
#define GPIO_Y_SCR_05_0_PR5_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_05_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_Y_SCR_05_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_PR4_SHIFT)
#define GPIO_Y_SCR_05_0_PR4_RANGE                       20:20
#define GPIO_Y_SCR_05_0_PR4_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_05_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_Y_SCR_05_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_PR3_SHIFT)
#define GPIO_Y_SCR_05_0_PR3_RANGE                       19:19
#define GPIO_Y_SCR_05_0_PR3_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_05_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_Y_SCR_05_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_PR2_SHIFT)
#define GPIO_Y_SCR_05_0_PR2_RANGE                       18:18
#define GPIO_Y_SCR_05_0_PR2_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_05_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_Y_SCR_05_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_PR1_SHIFT)
#define GPIO_Y_SCR_05_0_PR1_RANGE                       17:17
#define GPIO_Y_SCR_05_0_PR1_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_05_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_Y_SCR_05_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_PR0_SHIFT)
#define GPIO_Y_SCR_05_0_PR0_RANGE                       16:16
#define GPIO_Y_SCR_05_0_PR0_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_05_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_Y_SCR_05_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G7W_SHIFT)
#define GPIO_Y_SCR_05_0_G7W_RANGE                       15:15
#define GPIO_Y_SCR_05_0_G7W_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_05_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_Y_SCR_05_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G6W_SHIFT)
#define GPIO_Y_SCR_05_0_G6W_RANGE                       14:14
#define GPIO_Y_SCR_05_0_G6W_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_05_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_Y_SCR_05_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G5W_SHIFT)
#define GPIO_Y_SCR_05_0_G5W_RANGE                       13:13
#define GPIO_Y_SCR_05_0_G5W_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_05_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_Y_SCR_05_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G4W_SHIFT)
#define GPIO_Y_SCR_05_0_G4W_RANGE                       12:12
#define GPIO_Y_SCR_05_0_G4W_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_05_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_Y_SCR_05_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G3W_SHIFT)
#define GPIO_Y_SCR_05_0_G3W_RANGE                       11:11
#define GPIO_Y_SCR_05_0_G3W_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_05_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_Y_SCR_05_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G2W_SHIFT)
#define GPIO_Y_SCR_05_0_G2W_RANGE                       10:10
#define GPIO_Y_SCR_05_0_G2W_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_05_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_Y_SCR_05_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G1W_SHIFT)
#define GPIO_Y_SCR_05_0_G1W_RANGE                       9:9
#define GPIO_Y_SCR_05_0_G1W_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_05_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_Y_SCR_05_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G0W_SHIFT)
#define GPIO_Y_SCR_05_0_G0W_RANGE                       8:8
#define GPIO_Y_SCR_05_0_G0W_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_05_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_Y_SCR_05_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G7R_SHIFT)
#define GPIO_Y_SCR_05_0_G7R_RANGE                       7:7
#define GPIO_Y_SCR_05_0_G7R_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_05_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_Y_SCR_05_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G6R_SHIFT)
#define GPIO_Y_SCR_05_0_G6R_RANGE                       6:6
#define GPIO_Y_SCR_05_0_G6R_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_05_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Y_SCR_05_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G5R_SHIFT)
#define GPIO_Y_SCR_05_0_G5R_RANGE                       5:5
#define GPIO_Y_SCR_05_0_G5R_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_05_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_Y_SCR_05_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G4R_SHIFT)
#define GPIO_Y_SCR_05_0_G4R_RANGE                       4:4
#define GPIO_Y_SCR_05_0_G4R_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_05_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_Y_SCR_05_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G3R_SHIFT)
#define GPIO_Y_SCR_05_0_G3R_RANGE                       3:3
#define GPIO_Y_SCR_05_0_G3R_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_05_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_Y_SCR_05_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G2R_SHIFT)
#define GPIO_Y_SCR_05_0_G2R_RANGE                       2:2
#define GPIO_Y_SCR_05_0_G2R_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_05_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_Y_SCR_05_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G1R_SHIFT)
#define GPIO_Y_SCR_05_0_G1R_RANGE                       1:1
#define GPIO_Y_SCR_05_0_G1R_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_05_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Y_SCR_05_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G0R_SHIFT)
#define GPIO_Y_SCR_05_0_G0R_RANGE                       0:0
#define GPIO_Y_SCR_05_0_G0R_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_Y_VM_06_0
#define GPIO_Y_VM_06_0                  _MK_ADDR_CONST(0x2070)
#define GPIO_Y_VM_06_0_SECURE                   0x0
#define GPIO_Y_VM_06_0_DUAL                     0x0
#define GPIO_Y_VM_06_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_Y_VM_06_0_WORD_COUNT                       0x1
#define GPIO_Y_VM_06_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_06_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_06_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_06_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_06_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Y_VM_06_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_06_0_VM1_SHIFT)
#define GPIO_Y_VM_06_0_VM1_RANGE                        1:0
#define GPIO_Y_VM_06_0_VM1_WOFFSET                      0x0
#define GPIO_Y_VM_06_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_06_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_06_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_06_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_Y_VM_06_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_06_0_VM2_SHIFT)
#define GPIO_Y_VM_06_0_VM2_RANGE                        3:2
#define GPIO_Y_VM_06_0_VM2_WOFFSET                      0x0
#define GPIO_Y_VM_06_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_06_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_06_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_06_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_Y_VM_06_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_06_0_VM3_SHIFT)
#define GPIO_Y_VM_06_0_VM3_RANGE                        5:4
#define GPIO_Y_VM_06_0_VM3_WOFFSET                      0x0
#define GPIO_Y_VM_06_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_06_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_06_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_06_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_Y_VM_06_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_06_0_VM4_SHIFT)
#define GPIO_Y_VM_06_0_VM4_RANGE                        7:6
#define GPIO_Y_VM_06_0_VM4_WOFFSET                      0x0
#define GPIO_Y_VM_06_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_06_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_06_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_06_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_Y_VM_06_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_06_0_VM5_SHIFT)
#define GPIO_Y_VM_06_0_VM5_RANGE                        9:8
#define GPIO_Y_VM_06_0_VM5_WOFFSET                      0x0
#define GPIO_Y_VM_06_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_06_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_06_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_06_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_Y_VM_06_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_06_0_VM6_SHIFT)
#define GPIO_Y_VM_06_0_VM6_RANGE                        11:10
#define GPIO_Y_VM_06_0_VM6_WOFFSET                      0x0
#define GPIO_Y_VM_06_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_06_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_06_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_06_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_Y_VM_06_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_06_0_VM7_SHIFT)
#define GPIO_Y_VM_06_0_VM7_RANGE                        13:12
#define GPIO_Y_VM_06_0_VM7_WOFFSET                      0x0
#define GPIO_Y_VM_06_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_06_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_06_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_06_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_Y_VM_06_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_06_0_VM8_SHIFT)
#define GPIO_Y_VM_06_0_VM8_RANGE                        15:14
#define GPIO_Y_VM_06_0_VM8_WOFFSET                      0x0
#define GPIO_Y_VM_06_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_06_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_06_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_Y_SCR_06_0
#define GPIO_Y_SCR_06_0                 _MK_ADDR_CONST(0x2074)
#define GPIO_Y_SCR_06_0_SECURE                  0x0
#define GPIO_Y_SCR_06_0_DUAL                    0x0
#define GPIO_Y_SCR_06_0_SCR                     0
#define GPIO_Y_SCR_06_0_WORD_COUNT                      0x1
#define GPIO_Y_SCR_06_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_06_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_06_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_06_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_Y_SCR_06_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_SEC_LCK_SHIFT)
#define GPIO_Y_SCR_06_0_SEC_LCK_RANGE                   29:29
#define GPIO_Y_SCR_06_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Y_SCR_06_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_06_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_Y_SCR_06_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_SEC_WEN_SHIFT)
#define GPIO_Y_SCR_06_0_SEC_WEN_RANGE                   28:28
#define GPIO_Y_SCR_06_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Y_SCR_06_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_06_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_Y_SCR_06_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_SEC_REN_SHIFT)
#define GPIO_Y_SCR_06_0_SEC_REN_RANGE                   27:27
#define GPIO_Y_SCR_06_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Y_SCR_06_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_06_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_Y_SCR_06_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_Y_SCR_06_0_SEC_OWNER_SHIFT)
#define GPIO_Y_SCR_06_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Y_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Y_SCR_06_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_Y_SCR_06_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_06_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_Y_SCR_06_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_PR7_SHIFT)
#define GPIO_Y_SCR_06_0_PR7_RANGE                       23:23
#define GPIO_Y_SCR_06_0_PR7_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_06_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_Y_SCR_06_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_PR6_SHIFT)
#define GPIO_Y_SCR_06_0_PR6_RANGE                       22:22
#define GPIO_Y_SCR_06_0_PR6_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_06_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_Y_SCR_06_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_PR5_SHIFT)
#define GPIO_Y_SCR_06_0_PR5_RANGE                       21:21
#define GPIO_Y_SCR_06_0_PR5_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_06_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_Y_SCR_06_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_PR4_SHIFT)
#define GPIO_Y_SCR_06_0_PR4_RANGE                       20:20
#define GPIO_Y_SCR_06_0_PR4_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_06_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_Y_SCR_06_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_PR3_SHIFT)
#define GPIO_Y_SCR_06_0_PR3_RANGE                       19:19
#define GPIO_Y_SCR_06_0_PR3_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_06_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_Y_SCR_06_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_PR2_SHIFT)
#define GPIO_Y_SCR_06_0_PR2_RANGE                       18:18
#define GPIO_Y_SCR_06_0_PR2_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_06_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_Y_SCR_06_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_PR1_SHIFT)
#define GPIO_Y_SCR_06_0_PR1_RANGE                       17:17
#define GPIO_Y_SCR_06_0_PR1_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_06_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_Y_SCR_06_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_PR0_SHIFT)
#define GPIO_Y_SCR_06_0_PR0_RANGE                       16:16
#define GPIO_Y_SCR_06_0_PR0_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_06_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_Y_SCR_06_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G7W_SHIFT)
#define GPIO_Y_SCR_06_0_G7W_RANGE                       15:15
#define GPIO_Y_SCR_06_0_G7W_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_06_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_Y_SCR_06_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G6W_SHIFT)
#define GPIO_Y_SCR_06_0_G6W_RANGE                       14:14
#define GPIO_Y_SCR_06_0_G6W_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_06_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_Y_SCR_06_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G5W_SHIFT)
#define GPIO_Y_SCR_06_0_G5W_RANGE                       13:13
#define GPIO_Y_SCR_06_0_G5W_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_06_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_Y_SCR_06_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G4W_SHIFT)
#define GPIO_Y_SCR_06_0_G4W_RANGE                       12:12
#define GPIO_Y_SCR_06_0_G4W_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_06_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_Y_SCR_06_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G3W_SHIFT)
#define GPIO_Y_SCR_06_0_G3W_RANGE                       11:11
#define GPIO_Y_SCR_06_0_G3W_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_06_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_Y_SCR_06_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G2W_SHIFT)
#define GPIO_Y_SCR_06_0_G2W_RANGE                       10:10
#define GPIO_Y_SCR_06_0_G2W_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_06_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_Y_SCR_06_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G1W_SHIFT)
#define GPIO_Y_SCR_06_0_G1W_RANGE                       9:9
#define GPIO_Y_SCR_06_0_G1W_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_06_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_Y_SCR_06_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G0W_SHIFT)
#define GPIO_Y_SCR_06_0_G0W_RANGE                       8:8
#define GPIO_Y_SCR_06_0_G0W_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_06_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_Y_SCR_06_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G7R_SHIFT)
#define GPIO_Y_SCR_06_0_G7R_RANGE                       7:7
#define GPIO_Y_SCR_06_0_G7R_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_06_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_Y_SCR_06_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G6R_SHIFT)
#define GPIO_Y_SCR_06_0_G6R_RANGE                       6:6
#define GPIO_Y_SCR_06_0_G6R_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_06_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Y_SCR_06_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G5R_SHIFT)
#define GPIO_Y_SCR_06_0_G5R_RANGE                       5:5
#define GPIO_Y_SCR_06_0_G5R_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_06_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_Y_SCR_06_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G4R_SHIFT)
#define GPIO_Y_SCR_06_0_G4R_RANGE                       4:4
#define GPIO_Y_SCR_06_0_G4R_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_06_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_Y_SCR_06_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G3R_SHIFT)
#define GPIO_Y_SCR_06_0_G3R_RANGE                       3:3
#define GPIO_Y_SCR_06_0_G3R_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_06_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_Y_SCR_06_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G2R_SHIFT)
#define GPIO_Y_SCR_06_0_G2R_RANGE                       2:2
#define GPIO_Y_SCR_06_0_G2R_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_06_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_Y_SCR_06_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G1R_SHIFT)
#define GPIO_Y_SCR_06_0_G1R_RANGE                       1:1
#define GPIO_Y_SCR_06_0_G1R_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_06_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Y_SCR_06_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G0R_SHIFT)
#define GPIO_Y_SCR_06_0_G0R_RANGE                       0:0
#define GPIO_Y_SCR_06_0_G0R_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_Y_VM_07_0
#define GPIO_Y_VM_07_0                  _MK_ADDR_CONST(0x2078)
#define GPIO_Y_VM_07_0_SECURE                   0x0
#define GPIO_Y_VM_07_0_DUAL                     0x0
#define GPIO_Y_VM_07_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_Y_VM_07_0_WORD_COUNT                       0x1
#define GPIO_Y_VM_07_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_07_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_07_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_07_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_07_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_07_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_07_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Y_VM_07_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_07_0_VM1_SHIFT)
#define GPIO_Y_VM_07_0_VM1_RANGE                        1:0
#define GPIO_Y_VM_07_0_VM1_WOFFSET                      0x0
#define GPIO_Y_VM_07_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_07_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_07_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_07_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_07_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_07_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_07_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_Y_VM_07_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_07_0_VM2_SHIFT)
#define GPIO_Y_VM_07_0_VM2_RANGE                        3:2
#define GPIO_Y_VM_07_0_VM2_WOFFSET                      0x0
#define GPIO_Y_VM_07_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_07_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_07_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_07_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_07_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_07_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_07_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_Y_VM_07_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_07_0_VM3_SHIFT)
#define GPIO_Y_VM_07_0_VM3_RANGE                        5:4
#define GPIO_Y_VM_07_0_VM3_WOFFSET                      0x0
#define GPIO_Y_VM_07_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_07_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_07_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_07_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_07_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_07_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_07_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_Y_VM_07_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_07_0_VM4_SHIFT)
#define GPIO_Y_VM_07_0_VM4_RANGE                        7:6
#define GPIO_Y_VM_07_0_VM4_WOFFSET                      0x0
#define GPIO_Y_VM_07_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_07_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_07_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_07_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_07_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_07_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_07_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_Y_VM_07_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_07_0_VM5_SHIFT)
#define GPIO_Y_VM_07_0_VM5_RANGE                        9:8
#define GPIO_Y_VM_07_0_VM5_WOFFSET                      0x0
#define GPIO_Y_VM_07_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_07_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_07_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_07_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_07_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_07_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_07_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_Y_VM_07_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_07_0_VM6_SHIFT)
#define GPIO_Y_VM_07_0_VM6_RANGE                        11:10
#define GPIO_Y_VM_07_0_VM6_WOFFSET                      0x0
#define GPIO_Y_VM_07_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_07_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_07_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_07_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_07_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_07_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_07_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_Y_VM_07_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_07_0_VM7_SHIFT)
#define GPIO_Y_VM_07_0_VM7_RANGE                        13:12
#define GPIO_Y_VM_07_0_VM7_WOFFSET                      0x0
#define GPIO_Y_VM_07_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_07_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_07_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_07_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_07_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_07_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Y_VM_07_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_Y_VM_07_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Y_VM_07_0_VM8_SHIFT)
#define GPIO_Y_VM_07_0_VM8_RANGE                        15:14
#define GPIO_Y_VM_07_0_VM8_WOFFSET                      0x0
#define GPIO_Y_VM_07_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_07_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Y_VM_07_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_07_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_07_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_VM_07_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_Y_SCR_07_0
#define GPIO_Y_SCR_07_0                 _MK_ADDR_CONST(0x207c)
#define GPIO_Y_SCR_07_0_SECURE                  0x0
#define GPIO_Y_SCR_07_0_DUAL                    0x0
#define GPIO_Y_SCR_07_0_SCR                     0
#define GPIO_Y_SCR_07_0_WORD_COUNT                      0x1
#define GPIO_Y_SCR_07_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_07_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_07_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_07_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_Y_SCR_07_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_SEC_LCK_SHIFT)
#define GPIO_Y_SCR_07_0_SEC_LCK_RANGE                   29:29
#define GPIO_Y_SCR_07_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Y_SCR_07_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_07_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_07_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_Y_SCR_07_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_SEC_WEN_SHIFT)
#define GPIO_Y_SCR_07_0_SEC_WEN_RANGE                   28:28
#define GPIO_Y_SCR_07_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Y_SCR_07_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_07_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_07_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_Y_SCR_07_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_SEC_REN_SHIFT)
#define GPIO_Y_SCR_07_0_SEC_REN_RANGE                   27:27
#define GPIO_Y_SCR_07_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Y_SCR_07_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_07_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_07_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_Y_SCR_07_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_Y_SCR_07_0_SEC_OWNER_SHIFT)
#define GPIO_Y_SCR_07_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Y_SCR_07_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Y_SCR_07_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_Y_SCR_07_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_07_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_Y_SCR_07_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_PR7_SHIFT)
#define GPIO_Y_SCR_07_0_PR7_RANGE                       23:23
#define GPIO_Y_SCR_07_0_PR7_WOFFSET                     0x0
#define GPIO_Y_SCR_07_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_07_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_07_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_Y_SCR_07_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_PR6_SHIFT)
#define GPIO_Y_SCR_07_0_PR6_RANGE                       22:22
#define GPIO_Y_SCR_07_0_PR6_WOFFSET                     0x0
#define GPIO_Y_SCR_07_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_07_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_07_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_Y_SCR_07_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_PR5_SHIFT)
#define GPIO_Y_SCR_07_0_PR5_RANGE                       21:21
#define GPIO_Y_SCR_07_0_PR5_WOFFSET                     0x0
#define GPIO_Y_SCR_07_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_07_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_07_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_Y_SCR_07_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_PR4_SHIFT)
#define GPIO_Y_SCR_07_0_PR4_RANGE                       20:20
#define GPIO_Y_SCR_07_0_PR4_WOFFSET                     0x0
#define GPIO_Y_SCR_07_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_07_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_07_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_Y_SCR_07_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_PR3_SHIFT)
#define GPIO_Y_SCR_07_0_PR3_RANGE                       19:19
#define GPIO_Y_SCR_07_0_PR3_WOFFSET                     0x0
#define GPIO_Y_SCR_07_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_07_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_07_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_Y_SCR_07_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_PR2_SHIFT)
#define GPIO_Y_SCR_07_0_PR2_RANGE                       18:18
#define GPIO_Y_SCR_07_0_PR2_WOFFSET                     0x0
#define GPIO_Y_SCR_07_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_07_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_07_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_Y_SCR_07_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_PR1_SHIFT)
#define GPIO_Y_SCR_07_0_PR1_RANGE                       17:17
#define GPIO_Y_SCR_07_0_PR1_WOFFSET                     0x0
#define GPIO_Y_SCR_07_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_07_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_07_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_Y_SCR_07_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_PR0_SHIFT)
#define GPIO_Y_SCR_07_0_PR0_RANGE                       16:16
#define GPIO_Y_SCR_07_0_PR0_WOFFSET                     0x0
#define GPIO_Y_SCR_07_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_07_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_07_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_Y_SCR_07_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_G7W_SHIFT)
#define GPIO_Y_SCR_07_0_G7W_RANGE                       15:15
#define GPIO_Y_SCR_07_0_G7W_WOFFSET                     0x0
#define GPIO_Y_SCR_07_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_07_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_07_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_Y_SCR_07_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_G6W_SHIFT)
#define GPIO_Y_SCR_07_0_G6W_RANGE                       14:14
#define GPIO_Y_SCR_07_0_G6W_WOFFSET                     0x0
#define GPIO_Y_SCR_07_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_07_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_07_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_Y_SCR_07_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_G5W_SHIFT)
#define GPIO_Y_SCR_07_0_G5W_RANGE                       13:13
#define GPIO_Y_SCR_07_0_G5W_WOFFSET                     0x0
#define GPIO_Y_SCR_07_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_07_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_07_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_Y_SCR_07_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_G4W_SHIFT)
#define GPIO_Y_SCR_07_0_G4W_RANGE                       12:12
#define GPIO_Y_SCR_07_0_G4W_WOFFSET                     0x0
#define GPIO_Y_SCR_07_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_07_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_07_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_Y_SCR_07_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_G3W_SHIFT)
#define GPIO_Y_SCR_07_0_G3W_RANGE                       11:11
#define GPIO_Y_SCR_07_0_G3W_WOFFSET                     0x0
#define GPIO_Y_SCR_07_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_07_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_07_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_Y_SCR_07_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_G2W_SHIFT)
#define GPIO_Y_SCR_07_0_G2W_RANGE                       10:10
#define GPIO_Y_SCR_07_0_G2W_WOFFSET                     0x0
#define GPIO_Y_SCR_07_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_07_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_07_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_Y_SCR_07_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_G1W_SHIFT)
#define GPIO_Y_SCR_07_0_G1W_RANGE                       9:9
#define GPIO_Y_SCR_07_0_G1W_WOFFSET                     0x0
#define GPIO_Y_SCR_07_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_07_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_07_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_Y_SCR_07_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_G0W_SHIFT)
#define GPIO_Y_SCR_07_0_G0W_RANGE                       8:8
#define GPIO_Y_SCR_07_0_G0W_WOFFSET                     0x0
#define GPIO_Y_SCR_07_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_07_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_07_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_Y_SCR_07_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_G7R_SHIFT)
#define GPIO_Y_SCR_07_0_G7R_RANGE                       7:7
#define GPIO_Y_SCR_07_0_G7R_WOFFSET                     0x0
#define GPIO_Y_SCR_07_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_07_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_07_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_Y_SCR_07_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_G6R_SHIFT)
#define GPIO_Y_SCR_07_0_G6R_RANGE                       6:6
#define GPIO_Y_SCR_07_0_G6R_WOFFSET                     0x0
#define GPIO_Y_SCR_07_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_07_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_07_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Y_SCR_07_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_G5R_SHIFT)
#define GPIO_Y_SCR_07_0_G5R_RANGE                       5:5
#define GPIO_Y_SCR_07_0_G5R_WOFFSET                     0x0
#define GPIO_Y_SCR_07_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_07_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_07_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_Y_SCR_07_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_G4R_SHIFT)
#define GPIO_Y_SCR_07_0_G4R_RANGE                       4:4
#define GPIO_Y_SCR_07_0_G4R_WOFFSET                     0x0
#define GPIO_Y_SCR_07_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_07_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_07_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_Y_SCR_07_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_G3R_SHIFT)
#define GPIO_Y_SCR_07_0_G3R_RANGE                       3:3
#define GPIO_Y_SCR_07_0_G3R_WOFFSET                     0x0
#define GPIO_Y_SCR_07_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_07_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_07_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_Y_SCR_07_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_G2R_SHIFT)
#define GPIO_Y_SCR_07_0_G2R_RANGE                       2:2
#define GPIO_Y_SCR_07_0_G2R_WOFFSET                     0x0
#define GPIO_Y_SCR_07_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_07_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_07_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_Y_SCR_07_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_G1R_SHIFT)
#define GPIO_Y_SCR_07_0_G1R_RANGE                       1:1
#define GPIO_Y_SCR_07_0_G1R_WOFFSET                     0x0
#define GPIO_Y_SCR_07_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_07_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_07_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Y_SCR_07_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_G0R_SHIFT)
#define GPIO_Y_SCR_07_0_G0R_RANGE                       0:0
#define GPIO_Y_SCR_07_0_G0R_WOFFSET                     0x0
#define GPIO_Y_SCR_07_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_07_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_Z_VM_00_0
#define GPIO_Z_VM_00_0                  _MK_ADDR_CONST(0x2080)
#define GPIO_Z_VM_00_0_SECURE                   0x0
#define GPIO_Z_VM_00_0_DUAL                     0x0
#define GPIO_Z_VM_00_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_Z_VM_00_0_WORD_COUNT                       0x1
#define GPIO_Z_VM_00_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_00_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_00_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_00_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_00_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Z_VM_00_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_00_0_VM1_SHIFT)
#define GPIO_Z_VM_00_0_VM1_RANGE                        1:0
#define GPIO_Z_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_Z_VM_00_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_00_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_00_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_00_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_00_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_00_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_00_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_Z_VM_00_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_00_0_VM2_SHIFT)
#define GPIO_Z_VM_00_0_VM2_RANGE                        3:2
#define GPIO_Z_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_Z_VM_00_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_00_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_00_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_00_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_00_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_00_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_00_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_Z_VM_00_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_00_0_VM3_SHIFT)
#define GPIO_Z_VM_00_0_VM3_RANGE                        5:4
#define GPIO_Z_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_Z_VM_00_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_00_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_00_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_00_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_00_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_00_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_00_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_Z_VM_00_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_00_0_VM4_SHIFT)
#define GPIO_Z_VM_00_0_VM4_RANGE                        7:6
#define GPIO_Z_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_Z_VM_00_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_00_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_00_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_00_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_00_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_00_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_00_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_Z_VM_00_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_00_0_VM5_SHIFT)
#define GPIO_Z_VM_00_0_VM5_RANGE                        9:8
#define GPIO_Z_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_Z_VM_00_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_00_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_00_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_00_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_00_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_00_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_00_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_Z_VM_00_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_00_0_VM6_SHIFT)
#define GPIO_Z_VM_00_0_VM6_RANGE                        11:10
#define GPIO_Z_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_Z_VM_00_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_00_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_00_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_00_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_00_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_00_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_00_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_Z_VM_00_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_00_0_VM7_SHIFT)
#define GPIO_Z_VM_00_0_VM7_RANGE                        13:12
#define GPIO_Z_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_Z_VM_00_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_00_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_00_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_00_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_00_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_00_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_00_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_Z_VM_00_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_00_0_VM8_SHIFT)
#define GPIO_Z_VM_00_0_VM8_RANGE                        15:14
#define GPIO_Z_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_Z_VM_00_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_00_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_00_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_00_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_00_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_00_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_Z_SCR_00_0
#define GPIO_Z_SCR_00_0                 _MK_ADDR_CONST(0x2084)
#define GPIO_Z_SCR_00_0_SECURE                  0x0
#define GPIO_Z_SCR_00_0_DUAL                    0x0
#define GPIO_Z_SCR_00_0_SCR                     0
#define GPIO_Z_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_Z_SCR_00_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Z_SCR_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_Z_SCR_00_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Z_SCR_00_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_Z_SCR_00_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_Z_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_Z_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Z_SCR_00_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_00_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_00_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_Z_SCR_00_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_Z_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_Z_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Z_SCR_00_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_00_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_00_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_Z_SCR_00_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_Z_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_Z_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Z_SCR_00_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_00_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_00_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_Z_SCR_00_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_Z_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_Z_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Z_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Z_SCR_00_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_Z_SCR_00_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_00_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_Z_SCR_00_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_PR7_SHIFT)
#define GPIO_Z_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_Z_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_Z_SCR_00_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_00_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_00_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_Z_SCR_00_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_PR6_SHIFT)
#define GPIO_Z_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_Z_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_Z_SCR_00_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_00_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_00_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_Z_SCR_00_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_PR5_SHIFT)
#define GPIO_Z_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_Z_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_Z_SCR_00_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_00_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_00_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_Z_SCR_00_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_PR4_SHIFT)
#define GPIO_Z_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_Z_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_Z_SCR_00_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_00_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_00_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_Z_SCR_00_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_PR3_SHIFT)
#define GPIO_Z_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_Z_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_Z_SCR_00_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_00_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_00_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_Z_SCR_00_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_PR2_SHIFT)
#define GPIO_Z_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_Z_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_Z_SCR_00_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_00_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_00_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_Z_SCR_00_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_PR1_SHIFT)
#define GPIO_Z_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_Z_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_Z_SCR_00_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_00_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_00_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_Z_SCR_00_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_PR0_SHIFT)
#define GPIO_Z_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_Z_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_Z_SCR_00_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_00_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_00_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_Z_SCR_00_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_G7W_SHIFT)
#define GPIO_Z_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_Z_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_Z_SCR_00_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_00_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_00_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_Z_SCR_00_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_G6W_SHIFT)
#define GPIO_Z_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_Z_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_Z_SCR_00_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_00_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_00_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_Z_SCR_00_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_G5W_SHIFT)
#define GPIO_Z_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_Z_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_Z_SCR_00_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_00_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_00_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_Z_SCR_00_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_G4W_SHIFT)
#define GPIO_Z_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_Z_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_Z_SCR_00_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_00_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_00_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_Z_SCR_00_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_G3W_SHIFT)
#define GPIO_Z_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_Z_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_Z_SCR_00_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_00_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_00_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_Z_SCR_00_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_G2W_SHIFT)
#define GPIO_Z_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_Z_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_Z_SCR_00_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_00_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_00_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_Z_SCR_00_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_G1W_SHIFT)
#define GPIO_Z_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_Z_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_Z_SCR_00_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_00_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_00_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_Z_SCR_00_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_G0W_SHIFT)
#define GPIO_Z_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_Z_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_Z_SCR_00_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_00_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_00_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_Z_SCR_00_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_G7R_SHIFT)
#define GPIO_Z_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_Z_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_Z_SCR_00_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_00_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_00_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_Z_SCR_00_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_G6R_SHIFT)
#define GPIO_Z_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_Z_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_Z_SCR_00_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_00_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_00_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Z_SCR_00_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_G5R_SHIFT)
#define GPIO_Z_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_Z_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_Z_SCR_00_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_00_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_00_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_Z_SCR_00_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_G4R_SHIFT)
#define GPIO_Z_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_Z_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_Z_SCR_00_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_00_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_00_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_Z_SCR_00_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_G3R_SHIFT)
#define GPIO_Z_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_Z_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_Z_SCR_00_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_00_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_00_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_Z_SCR_00_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_G2R_SHIFT)
#define GPIO_Z_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_Z_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_Z_SCR_00_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_00_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_00_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_Z_SCR_00_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_G1R_SHIFT)
#define GPIO_Z_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_Z_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_Z_SCR_00_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_00_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_00_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Z_SCR_00_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_G0R_SHIFT)
#define GPIO_Z_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_Z_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_Z_SCR_00_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_00_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_Z_VM_01_0
#define GPIO_Z_VM_01_0                  _MK_ADDR_CONST(0x2088)
#define GPIO_Z_VM_01_0_SECURE                   0x0
#define GPIO_Z_VM_01_0_DUAL                     0x0
#define GPIO_Z_VM_01_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_Z_VM_01_0_WORD_COUNT                       0x1
#define GPIO_Z_VM_01_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_01_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_01_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_01_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_01_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Z_VM_01_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_01_0_VM1_SHIFT)
#define GPIO_Z_VM_01_0_VM1_RANGE                        1:0
#define GPIO_Z_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_Z_VM_01_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_01_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_01_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_01_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_01_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_01_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_01_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_Z_VM_01_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_01_0_VM2_SHIFT)
#define GPIO_Z_VM_01_0_VM2_RANGE                        3:2
#define GPIO_Z_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_Z_VM_01_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_01_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_01_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_01_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_01_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_01_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_01_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_Z_VM_01_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_01_0_VM3_SHIFT)
#define GPIO_Z_VM_01_0_VM3_RANGE                        5:4
#define GPIO_Z_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_Z_VM_01_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_01_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_01_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_01_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_01_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_01_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_01_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_Z_VM_01_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_01_0_VM4_SHIFT)
#define GPIO_Z_VM_01_0_VM4_RANGE                        7:6
#define GPIO_Z_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_Z_VM_01_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_01_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_01_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_01_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_01_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_01_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_01_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_Z_VM_01_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_01_0_VM5_SHIFT)
#define GPIO_Z_VM_01_0_VM5_RANGE                        9:8
#define GPIO_Z_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_Z_VM_01_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_01_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_01_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_01_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_01_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_01_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_01_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_Z_VM_01_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_01_0_VM6_SHIFT)
#define GPIO_Z_VM_01_0_VM6_RANGE                        11:10
#define GPIO_Z_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_Z_VM_01_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_01_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_01_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_01_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_01_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_01_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_01_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_Z_VM_01_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_01_0_VM7_SHIFT)
#define GPIO_Z_VM_01_0_VM7_RANGE                        13:12
#define GPIO_Z_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_Z_VM_01_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_01_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_01_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_01_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_01_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_01_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_01_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_Z_VM_01_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_01_0_VM8_SHIFT)
#define GPIO_Z_VM_01_0_VM8_RANGE                        15:14
#define GPIO_Z_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_Z_VM_01_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_01_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_01_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_01_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_01_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_01_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_Z_SCR_01_0
#define GPIO_Z_SCR_01_0                 _MK_ADDR_CONST(0x208c)
#define GPIO_Z_SCR_01_0_SECURE                  0x0
#define GPIO_Z_SCR_01_0_DUAL                    0x0
#define GPIO_Z_SCR_01_0_SCR                     0
#define GPIO_Z_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_Z_SCR_01_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Z_SCR_01_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_Z_SCR_01_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Z_SCR_01_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_Z_SCR_01_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_Z_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_Z_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Z_SCR_01_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_01_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_01_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_Z_SCR_01_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_Z_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_Z_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Z_SCR_01_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_01_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_01_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_Z_SCR_01_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_Z_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_Z_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Z_SCR_01_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_01_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_01_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_Z_SCR_01_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_Z_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_Z_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Z_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Z_SCR_01_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_Z_SCR_01_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_01_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_Z_SCR_01_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_PR7_SHIFT)
#define GPIO_Z_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_Z_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_Z_SCR_01_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_01_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_01_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_Z_SCR_01_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_PR6_SHIFT)
#define GPIO_Z_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_Z_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_Z_SCR_01_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_01_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_01_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_Z_SCR_01_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_PR5_SHIFT)
#define GPIO_Z_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_Z_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_Z_SCR_01_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_01_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_01_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_Z_SCR_01_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_PR4_SHIFT)
#define GPIO_Z_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_Z_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_Z_SCR_01_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_01_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_01_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_Z_SCR_01_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_PR3_SHIFT)
#define GPIO_Z_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_Z_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_Z_SCR_01_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_01_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_01_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_Z_SCR_01_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_PR2_SHIFT)
#define GPIO_Z_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_Z_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_Z_SCR_01_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_01_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_01_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_Z_SCR_01_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_PR1_SHIFT)
#define GPIO_Z_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_Z_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_Z_SCR_01_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_01_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_01_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_Z_SCR_01_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_PR0_SHIFT)
#define GPIO_Z_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_Z_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_Z_SCR_01_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_01_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_01_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_Z_SCR_01_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_G7W_SHIFT)
#define GPIO_Z_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_Z_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_Z_SCR_01_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_01_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_01_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_Z_SCR_01_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_G6W_SHIFT)
#define GPIO_Z_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_Z_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_Z_SCR_01_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_01_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_01_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_Z_SCR_01_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_G5W_SHIFT)
#define GPIO_Z_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_Z_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_Z_SCR_01_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_01_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_01_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_Z_SCR_01_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_G4W_SHIFT)
#define GPIO_Z_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_Z_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_Z_SCR_01_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_01_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_01_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_Z_SCR_01_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_G3W_SHIFT)
#define GPIO_Z_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_Z_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_Z_SCR_01_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_01_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_01_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_Z_SCR_01_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_G2W_SHIFT)
#define GPIO_Z_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_Z_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_Z_SCR_01_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_01_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_01_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_Z_SCR_01_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_G1W_SHIFT)
#define GPIO_Z_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_Z_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_Z_SCR_01_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_01_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_01_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_Z_SCR_01_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_G0W_SHIFT)
#define GPIO_Z_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_Z_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_Z_SCR_01_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_01_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_01_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_Z_SCR_01_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_G7R_SHIFT)
#define GPIO_Z_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_Z_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_Z_SCR_01_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_01_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_01_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_Z_SCR_01_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_G6R_SHIFT)
#define GPIO_Z_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_Z_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_Z_SCR_01_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_01_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_01_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Z_SCR_01_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_G5R_SHIFT)
#define GPIO_Z_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_Z_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_Z_SCR_01_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_01_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_01_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_Z_SCR_01_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_G4R_SHIFT)
#define GPIO_Z_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_Z_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_Z_SCR_01_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_01_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_01_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_Z_SCR_01_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_G3R_SHIFT)
#define GPIO_Z_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_Z_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_Z_SCR_01_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_01_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_01_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_Z_SCR_01_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_G2R_SHIFT)
#define GPIO_Z_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_Z_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_Z_SCR_01_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_01_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_01_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_Z_SCR_01_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_G1R_SHIFT)
#define GPIO_Z_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_Z_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_Z_SCR_01_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_01_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_01_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Z_SCR_01_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_G0R_SHIFT)
#define GPIO_Z_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_Z_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_Z_SCR_01_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_01_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_Z_VM_02_0
#define GPIO_Z_VM_02_0                  _MK_ADDR_CONST(0x2090)
#define GPIO_Z_VM_02_0_SECURE                   0x0
#define GPIO_Z_VM_02_0_DUAL                     0x0
#define GPIO_Z_VM_02_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_Z_VM_02_0_WORD_COUNT                       0x1
#define GPIO_Z_VM_02_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_02_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_02_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_02_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_02_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Z_VM_02_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_02_0_VM1_SHIFT)
#define GPIO_Z_VM_02_0_VM1_RANGE                        1:0
#define GPIO_Z_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_Z_VM_02_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_02_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_02_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_02_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_02_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_02_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_02_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_Z_VM_02_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_02_0_VM2_SHIFT)
#define GPIO_Z_VM_02_0_VM2_RANGE                        3:2
#define GPIO_Z_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_Z_VM_02_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_02_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_02_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_02_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_02_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_02_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_02_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_Z_VM_02_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_02_0_VM3_SHIFT)
#define GPIO_Z_VM_02_0_VM3_RANGE                        5:4
#define GPIO_Z_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_Z_VM_02_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_02_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_02_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_02_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_02_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_02_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_02_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_Z_VM_02_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_02_0_VM4_SHIFT)
#define GPIO_Z_VM_02_0_VM4_RANGE                        7:6
#define GPIO_Z_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_Z_VM_02_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_02_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_02_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_02_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_02_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_02_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_02_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_Z_VM_02_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_02_0_VM5_SHIFT)
#define GPIO_Z_VM_02_0_VM5_RANGE                        9:8
#define GPIO_Z_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_Z_VM_02_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_02_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_02_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_02_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_02_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_02_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_02_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_Z_VM_02_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_02_0_VM6_SHIFT)
#define GPIO_Z_VM_02_0_VM6_RANGE                        11:10
#define GPIO_Z_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_Z_VM_02_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_02_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_02_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_02_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_02_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_02_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_02_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_Z_VM_02_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_02_0_VM7_SHIFT)
#define GPIO_Z_VM_02_0_VM7_RANGE                        13:12
#define GPIO_Z_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_Z_VM_02_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_02_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_02_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_02_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_02_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_02_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_02_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_Z_VM_02_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_02_0_VM8_SHIFT)
#define GPIO_Z_VM_02_0_VM8_RANGE                        15:14
#define GPIO_Z_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_Z_VM_02_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_02_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_02_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_02_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_02_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_02_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_Z_SCR_02_0
#define GPIO_Z_SCR_02_0                 _MK_ADDR_CONST(0x2094)
#define GPIO_Z_SCR_02_0_SECURE                  0x0
#define GPIO_Z_SCR_02_0_DUAL                    0x0
#define GPIO_Z_SCR_02_0_SCR                     0
#define GPIO_Z_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_Z_SCR_02_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Z_SCR_02_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_Z_SCR_02_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Z_SCR_02_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_Z_SCR_02_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_Z_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_Z_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Z_SCR_02_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_02_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_02_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_Z_SCR_02_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_Z_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_Z_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Z_SCR_02_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_02_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_02_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_Z_SCR_02_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_Z_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_Z_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Z_SCR_02_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_02_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_02_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_Z_SCR_02_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_Z_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_Z_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Z_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Z_SCR_02_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_Z_SCR_02_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_02_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_Z_SCR_02_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_PR7_SHIFT)
#define GPIO_Z_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_Z_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_Z_SCR_02_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_02_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_02_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_Z_SCR_02_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_PR6_SHIFT)
#define GPIO_Z_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_Z_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_Z_SCR_02_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_02_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_02_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_Z_SCR_02_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_PR5_SHIFT)
#define GPIO_Z_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_Z_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_Z_SCR_02_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_02_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_02_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_Z_SCR_02_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_PR4_SHIFT)
#define GPIO_Z_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_Z_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_Z_SCR_02_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_02_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_02_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_Z_SCR_02_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_PR3_SHIFT)
#define GPIO_Z_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_Z_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_Z_SCR_02_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_02_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_02_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_Z_SCR_02_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_PR2_SHIFT)
#define GPIO_Z_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_Z_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_Z_SCR_02_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_02_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_02_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_Z_SCR_02_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_PR1_SHIFT)
#define GPIO_Z_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_Z_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_Z_SCR_02_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_02_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_02_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_Z_SCR_02_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_PR0_SHIFT)
#define GPIO_Z_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_Z_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_Z_SCR_02_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_02_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_02_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_Z_SCR_02_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_G7W_SHIFT)
#define GPIO_Z_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_Z_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_Z_SCR_02_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_02_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_02_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_Z_SCR_02_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_G6W_SHIFT)
#define GPIO_Z_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_Z_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_Z_SCR_02_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_02_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_02_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_Z_SCR_02_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_G5W_SHIFT)
#define GPIO_Z_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_Z_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_Z_SCR_02_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_02_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_02_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_Z_SCR_02_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_G4W_SHIFT)
#define GPIO_Z_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_Z_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_Z_SCR_02_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_02_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_02_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_Z_SCR_02_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_G3W_SHIFT)
#define GPIO_Z_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_Z_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_Z_SCR_02_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_02_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_02_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_Z_SCR_02_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_G2W_SHIFT)
#define GPIO_Z_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_Z_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_Z_SCR_02_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_02_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_02_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_Z_SCR_02_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_G1W_SHIFT)
#define GPIO_Z_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_Z_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_Z_SCR_02_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_02_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_02_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_Z_SCR_02_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_G0W_SHIFT)
#define GPIO_Z_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_Z_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_Z_SCR_02_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_02_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_02_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_Z_SCR_02_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_G7R_SHIFT)
#define GPIO_Z_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_Z_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_Z_SCR_02_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_02_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_02_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_Z_SCR_02_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_G6R_SHIFT)
#define GPIO_Z_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_Z_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_Z_SCR_02_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_02_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_02_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Z_SCR_02_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_G5R_SHIFT)
#define GPIO_Z_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_Z_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_Z_SCR_02_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_02_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_02_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_Z_SCR_02_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_G4R_SHIFT)
#define GPIO_Z_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_Z_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_Z_SCR_02_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_02_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_02_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_Z_SCR_02_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_G3R_SHIFT)
#define GPIO_Z_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_Z_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_Z_SCR_02_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_02_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_02_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_Z_SCR_02_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_G2R_SHIFT)
#define GPIO_Z_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_Z_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_Z_SCR_02_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_02_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_02_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_Z_SCR_02_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_G1R_SHIFT)
#define GPIO_Z_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_Z_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_Z_SCR_02_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_02_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_02_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Z_SCR_02_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_G0R_SHIFT)
#define GPIO_Z_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_Z_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_Z_SCR_02_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_02_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_Z_VM_03_0
#define GPIO_Z_VM_03_0                  _MK_ADDR_CONST(0x2098)
#define GPIO_Z_VM_03_0_SECURE                   0x0
#define GPIO_Z_VM_03_0_DUAL                     0x0
#define GPIO_Z_VM_03_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_Z_VM_03_0_WORD_COUNT                       0x1
#define GPIO_Z_VM_03_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_03_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_03_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_03_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_03_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Z_VM_03_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_03_0_VM1_SHIFT)
#define GPIO_Z_VM_03_0_VM1_RANGE                        1:0
#define GPIO_Z_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_Z_VM_03_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_03_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_03_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_03_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_03_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_03_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_03_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_Z_VM_03_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_03_0_VM2_SHIFT)
#define GPIO_Z_VM_03_0_VM2_RANGE                        3:2
#define GPIO_Z_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_Z_VM_03_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_03_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_03_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_03_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_03_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_03_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_03_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_Z_VM_03_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_03_0_VM3_SHIFT)
#define GPIO_Z_VM_03_0_VM3_RANGE                        5:4
#define GPIO_Z_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_Z_VM_03_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_03_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_03_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_03_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_03_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_03_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_03_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_Z_VM_03_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_03_0_VM4_SHIFT)
#define GPIO_Z_VM_03_0_VM4_RANGE                        7:6
#define GPIO_Z_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_Z_VM_03_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_03_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_03_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_03_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_03_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_03_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_03_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_Z_VM_03_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_03_0_VM5_SHIFT)
#define GPIO_Z_VM_03_0_VM5_RANGE                        9:8
#define GPIO_Z_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_Z_VM_03_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_03_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_03_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_03_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_03_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_03_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_03_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_Z_VM_03_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_03_0_VM6_SHIFT)
#define GPIO_Z_VM_03_0_VM6_RANGE                        11:10
#define GPIO_Z_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_Z_VM_03_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_03_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_03_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_03_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_03_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_03_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_03_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_Z_VM_03_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_03_0_VM7_SHIFT)
#define GPIO_Z_VM_03_0_VM7_RANGE                        13:12
#define GPIO_Z_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_Z_VM_03_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_03_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_03_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_03_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_03_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_03_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_03_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_Z_VM_03_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_03_0_VM8_SHIFT)
#define GPIO_Z_VM_03_0_VM8_RANGE                        15:14
#define GPIO_Z_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_Z_VM_03_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_03_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_03_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_03_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_03_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_03_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_Z_SCR_03_0
#define GPIO_Z_SCR_03_0                 _MK_ADDR_CONST(0x209c)
#define GPIO_Z_SCR_03_0_SECURE                  0x0
#define GPIO_Z_SCR_03_0_DUAL                    0x0
#define GPIO_Z_SCR_03_0_SCR                     0
#define GPIO_Z_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_Z_SCR_03_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Z_SCR_03_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_Z_SCR_03_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Z_SCR_03_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_Z_SCR_03_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_Z_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_Z_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Z_SCR_03_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_03_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_03_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_Z_SCR_03_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_Z_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_Z_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Z_SCR_03_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_03_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_03_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_Z_SCR_03_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_Z_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_Z_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Z_SCR_03_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_03_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_03_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_Z_SCR_03_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_Z_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_Z_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Z_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Z_SCR_03_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_Z_SCR_03_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_03_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_Z_SCR_03_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_PR7_SHIFT)
#define GPIO_Z_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_Z_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_Z_SCR_03_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_03_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_03_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_Z_SCR_03_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_PR6_SHIFT)
#define GPIO_Z_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_Z_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_Z_SCR_03_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_03_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_03_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_Z_SCR_03_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_PR5_SHIFT)
#define GPIO_Z_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_Z_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_Z_SCR_03_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_03_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_03_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_Z_SCR_03_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_PR4_SHIFT)
#define GPIO_Z_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_Z_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_Z_SCR_03_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_03_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_03_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_Z_SCR_03_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_PR3_SHIFT)
#define GPIO_Z_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_Z_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_Z_SCR_03_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_03_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_03_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_Z_SCR_03_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_PR2_SHIFT)
#define GPIO_Z_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_Z_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_Z_SCR_03_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_03_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_03_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_Z_SCR_03_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_PR1_SHIFT)
#define GPIO_Z_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_Z_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_Z_SCR_03_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_03_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_03_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_Z_SCR_03_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_PR0_SHIFT)
#define GPIO_Z_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_Z_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_Z_SCR_03_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_03_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_03_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_Z_SCR_03_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_G7W_SHIFT)
#define GPIO_Z_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_Z_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_Z_SCR_03_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_03_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_03_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_Z_SCR_03_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_G6W_SHIFT)
#define GPIO_Z_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_Z_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_Z_SCR_03_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_03_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_03_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_Z_SCR_03_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_G5W_SHIFT)
#define GPIO_Z_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_Z_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_Z_SCR_03_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_03_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_03_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_Z_SCR_03_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_G4W_SHIFT)
#define GPIO_Z_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_Z_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_Z_SCR_03_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_03_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_03_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_Z_SCR_03_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_G3W_SHIFT)
#define GPIO_Z_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_Z_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_Z_SCR_03_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_03_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_03_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_Z_SCR_03_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_G2W_SHIFT)
#define GPIO_Z_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_Z_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_Z_SCR_03_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_03_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_03_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_Z_SCR_03_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_G1W_SHIFT)
#define GPIO_Z_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_Z_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_Z_SCR_03_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_03_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_03_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_Z_SCR_03_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_G0W_SHIFT)
#define GPIO_Z_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_Z_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_Z_SCR_03_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_03_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_03_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_Z_SCR_03_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_G7R_SHIFT)
#define GPIO_Z_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_Z_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_Z_SCR_03_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_03_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_03_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_Z_SCR_03_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_G6R_SHIFT)
#define GPIO_Z_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_Z_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_Z_SCR_03_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_03_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_03_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Z_SCR_03_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_G5R_SHIFT)
#define GPIO_Z_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_Z_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_Z_SCR_03_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_03_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_03_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_Z_SCR_03_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_G4R_SHIFT)
#define GPIO_Z_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_Z_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_Z_SCR_03_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_03_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_03_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_Z_SCR_03_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_G3R_SHIFT)
#define GPIO_Z_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_Z_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_Z_SCR_03_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_03_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_03_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_Z_SCR_03_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_G2R_SHIFT)
#define GPIO_Z_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_Z_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_Z_SCR_03_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_03_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_03_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_Z_SCR_03_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_G1R_SHIFT)
#define GPIO_Z_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_Z_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_Z_SCR_03_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_03_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_03_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Z_SCR_03_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_G0R_SHIFT)
#define GPIO_Z_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_Z_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_Z_SCR_03_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_03_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_Z_VM_04_0
#define GPIO_Z_VM_04_0                  _MK_ADDR_CONST(0x20a0)
#define GPIO_Z_VM_04_0_SECURE                   0x0
#define GPIO_Z_VM_04_0_DUAL                     0x0
#define GPIO_Z_VM_04_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_Z_VM_04_0_WORD_COUNT                       0x1
#define GPIO_Z_VM_04_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_04_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_04_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_04_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_04_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Z_VM_04_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_04_0_VM1_SHIFT)
#define GPIO_Z_VM_04_0_VM1_RANGE                        1:0
#define GPIO_Z_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_Z_VM_04_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_04_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_04_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_04_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_04_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_04_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_04_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_Z_VM_04_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_04_0_VM2_SHIFT)
#define GPIO_Z_VM_04_0_VM2_RANGE                        3:2
#define GPIO_Z_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_Z_VM_04_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_04_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_04_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_04_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_04_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_04_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_04_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_Z_VM_04_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_04_0_VM3_SHIFT)
#define GPIO_Z_VM_04_0_VM3_RANGE                        5:4
#define GPIO_Z_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_Z_VM_04_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_04_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_04_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_04_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_04_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_04_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_04_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_Z_VM_04_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_04_0_VM4_SHIFT)
#define GPIO_Z_VM_04_0_VM4_RANGE                        7:6
#define GPIO_Z_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_Z_VM_04_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_04_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_04_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_04_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_04_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_04_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_04_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_Z_VM_04_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_04_0_VM5_SHIFT)
#define GPIO_Z_VM_04_0_VM5_RANGE                        9:8
#define GPIO_Z_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_Z_VM_04_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_04_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_04_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_04_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_04_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_04_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_04_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_Z_VM_04_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_04_0_VM6_SHIFT)
#define GPIO_Z_VM_04_0_VM6_RANGE                        11:10
#define GPIO_Z_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_Z_VM_04_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_04_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_04_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_04_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_04_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_04_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_04_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_Z_VM_04_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_04_0_VM7_SHIFT)
#define GPIO_Z_VM_04_0_VM7_RANGE                        13:12
#define GPIO_Z_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_Z_VM_04_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_04_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_04_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_04_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_04_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_04_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_04_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_Z_VM_04_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_04_0_VM8_SHIFT)
#define GPIO_Z_VM_04_0_VM8_RANGE                        15:14
#define GPIO_Z_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_Z_VM_04_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_04_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_04_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_04_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_04_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_04_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_Z_SCR_04_0
#define GPIO_Z_SCR_04_0                 _MK_ADDR_CONST(0x20a4)
#define GPIO_Z_SCR_04_0_SECURE                  0x0
#define GPIO_Z_SCR_04_0_DUAL                    0x0
#define GPIO_Z_SCR_04_0_SCR                     0
#define GPIO_Z_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_Z_SCR_04_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Z_SCR_04_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_Z_SCR_04_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Z_SCR_04_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_Z_SCR_04_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_Z_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_Z_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Z_SCR_04_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_04_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_04_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_Z_SCR_04_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_Z_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_Z_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Z_SCR_04_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_04_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_04_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_Z_SCR_04_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_Z_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_Z_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Z_SCR_04_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_04_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_04_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_Z_SCR_04_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_Z_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_Z_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Z_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Z_SCR_04_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_Z_SCR_04_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_04_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_Z_SCR_04_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_PR7_SHIFT)
#define GPIO_Z_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_Z_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_Z_SCR_04_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_04_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_04_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_Z_SCR_04_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_PR6_SHIFT)
#define GPIO_Z_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_Z_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_Z_SCR_04_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_04_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_04_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_Z_SCR_04_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_PR5_SHIFT)
#define GPIO_Z_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_Z_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_Z_SCR_04_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_04_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_04_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_Z_SCR_04_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_PR4_SHIFT)
#define GPIO_Z_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_Z_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_Z_SCR_04_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_04_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_04_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_Z_SCR_04_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_PR3_SHIFT)
#define GPIO_Z_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_Z_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_Z_SCR_04_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_04_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_04_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_Z_SCR_04_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_PR2_SHIFT)
#define GPIO_Z_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_Z_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_Z_SCR_04_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_04_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_04_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_Z_SCR_04_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_PR1_SHIFT)
#define GPIO_Z_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_Z_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_Z_SCR_04_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_04_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_04_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_Z_SCR_04_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_PR0_SHIFT)
#define GPIO_Z_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_Z_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_Z_SCR_04_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_04_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_04_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_Z_SCR_04_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_G7W_SHIFT)
#define GPIO_Z_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_Z_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_Z_SCR_04_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_04_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_04_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_Z_SCR_04_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_G6W_SHIFT)
#define GPIO_Z_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_Z_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_Z_SCR_04_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_04_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_04_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_Z_SCR_04_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_G5W_SHIFT)
#define GPIO_Z_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_Z_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_Z_SCR_04_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_04_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_04_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_Z_SCR_04_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_G4W_SHIFT)
#define GPIO_Z_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_Z_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_Z_SCR_04_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_04_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_04_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_Z_SCR_04_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_G3W_SHIFT)
#define GPIO_Z_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_Z_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_Z_SCR_04_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_04_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_04_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_Z_SCR_04_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_G2W_SHIFT)
#define GPIO_Z_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_Z_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_Z_SCR_04_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_04_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_04_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_Z_SCR_04_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_G1W_SHIFT)
#define GPIO_Z_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_Z_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_Z_SCR_04_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_04_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_04_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_Z_SCR_04_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_G0W_SHIFT)
#define GPIO_Z_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_Z_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_Z_SCR_04_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_04_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_04_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_Z_SCR_04_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_G7R_SHIFT)
#define GPIO_Z_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_Z_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_Z_SCR_04_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_04_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_04_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_Z_SCR_04_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_G6R_SHIFT)
#define GPIO_Z_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_Z_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_Z_SCR_04_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_04_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_04_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Z_SCR_04_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_G5R_SHIFT)
#define GPIO_Z_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_Z_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_Z_SCR_04_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_04_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_04_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_Z_SCR_04_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_G4R_SHIFT)
#define GPIO_Z_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_Z_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_Z_SCR_04_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_04_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_04_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_Z_SCR_04_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_G3R_SHIFT)
#define GPIO_Z_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_Z_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_Z_SCR_04_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_04_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_04_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_Z_SCR_04_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_G2R_SHIFT)
#define GPIO_Z_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_Z_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_Z_SCR_04_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_04_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_04_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_Z_SCR_04_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_G1R_SHIFT)
#define GPIO_Z_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_Z_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_Z_SCR_04_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_04_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_04_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Z_SCR_04_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_G0R_SHIFT)
#define GPIO_Z_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_Z_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_Z_SCR_04_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_04_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_Z_VM_05_0
#define GPIO_Z_VM_05_0                  _MK_ADDR_CONST(0x20a8)
#define GPIO_Z_VM_05_0_SECURE                   0x0
#define GPIO_Z_VM_05_0_DUAL                     0x0
#define GPIO_Z_VM_05_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_Z_VM_05_0_WORD_COUNT                       0x1
#define GPIO_Z_VM_05_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_05_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_05_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_05_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_05_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Z_VM_05_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_05_0_VM1_SHIFT)
#define GPIO_Z_VM_05_0_VM1_RANGE                        1:0
#define GPIO_Z_VM_05_0_VM1_WOFFSET                      0x0
#define GPIO_Z_VM_05_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_05_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_05_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_05_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_05_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_05_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_05_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_Z_VM_05_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_05_0_VM2_SHIFT)
#define GPIO_Z_VM_05_0_VM2_RANGE                        3:2
#define GPIO_Z_VM_05_0_VM2_WOFFSET                      0x0
#define GPIO_Z_VM_05_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_05_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_05_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_05_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_05_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_05_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_05_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_Z_VM_05_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_05_0_VM3_SHIFT)
#define GPIO_Z_VM_05_0_VM3_RANGE                        5:4
#define GPIO_Z_VM_05_0_VM3_WOFFSET                      0x0
#define GPIO_Z_VM_05_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_05_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_05_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_05_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_05_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_05_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_05_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_Z_VM_05_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_05_0_VM4_SHIFT)
#define GPIO_Z_VM_05_0_VM4_RANGE                        7:6
#define GPIO_Z_VM_05_0_VM4_WOFFSET                      0x0
#define GPIO_Z_VM_05_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_05_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_05_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_05_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_05_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_05_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_05_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_Z_VM_05_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_05_0_VM5_SHIFT)
#define GPIO_Z_VM_05_0_VM5_RANGE                        9:8
#define GPIO_Z_VM_05_0_VM5_WOFFSET                      0x0
#define GPIO_Z_VM_05_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_05_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_05_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_05_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_05_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_05_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_05_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_Z_VM_05_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_05_0_VM6_SHIFT)
#define GPIO_Z_VM_05_0_VM6_RANGE                        11:10
#define GPIO_Z_VM_05_0_VM6_WOFFSET                      0x0
#define GPIO_Z_VM_05_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_05_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_05_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_05_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_05_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_05_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_05_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_Z_VM_05_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_05_0_VM7_SHIFT)
#define GPIO_Z_VM_05_0_VM7_RANGE                        13:12
#define GPIO_Z_VM_05_0_VM7_WOFFSET                      0x0
#define GPIO_Z_VM_05_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_05_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_05_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_05_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_05_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_05_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_05_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_Z_VM_05_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_05_0_VM8_SHIFT)
#define GPIO_Z_VM_05_0_VM8_RANGE                        15:14
#define GPIO_Z_VM_05_0_VM8_WOFFSET                      0x0
#define GPIO_Z_VM_05_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_05_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_05_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_05_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_05_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_05_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_Z_SCR_05_0
#define GPIO_Z_SCR_05_0                 _MK_ADDR_CONST(0x20ac)
#define GPIO_Z_SCR_05_0_SECURE                  0x0
#define GPIO_Z_SCR_05_0_DUAL                    0x0
#define GPIO_Z_SCR_05_0_SCR                     0
#define GPIO_Z_SCR_05_0_WORD_COUNT                      0x1
#define GPIO_Z_SCR_05_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Z_SCR_05_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_Z_SCR_05_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Z_SCR_05_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_Z_SCR_05_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_Z_SCR_05_0_SEC_LCK_RANGE                   29:29
#define GPIO_Z_SCR_05_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Z_SCR_05_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_05_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_05_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_Z_SCR_05_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_Z_SCR_05_0_SEC_WEN_RANGE                   28:28
#define GPIO_Z_SCR_05_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Z_SCR_05_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_05_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_05_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_Z_SCR_05_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_Z_SCR_05_0_SEC_REN_RANGE                   27:27
#define GPIO_Z_SCR_05_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Z_SCR_05_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_05_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_05_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_Z_SCR_05_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_Z_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_Z_SCR_05_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Z_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Z_SCR_05_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_Z_SCR_05_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_05_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_Z_SCR_05_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_PR7_SHIFT)
#define GPIO_Z_SCR_05_0_PR7_RANGE                       23:23
#define GPIO_Z_SCR_05_0_PR7_WOFFSET                     0x0
#define GPIO_Z_SCR_05_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_05_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_05_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_Z_SCR_05_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_PR6_SHIFT)
#define GPIO_Z_SCR_05_0_PR6_RANGE                       22:22
#define GPIO_Z_SCR_05_0_PR6_WOFFSET                     0x0
#define GPIO_Z_SCR_05_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_05_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_05_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_Z_SCR_05_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_PR5_SHIFT)
#define GPIO_Z_SCR_05_0_PR5_RANGE                       21:21
#define GPIO_Z_SCR_05_0_PR5_WOFFSET                     0x0
#define GPIO_Z_SCR_05_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_05_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_05_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_Z_SCR_05_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_PR4_SHIFT)
#define GPIO_Z_SCR_05_0_PR4_RANGE                       20:20
#define GPIO_Z_SCR_05_0_PR4_WOFFSET                     0x0
#define GPIO_Z_SCR_05_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_05_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_05_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_Z_SCR_05_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_PR3_SHIFT)
#define GPIO_Z_SCR_05_0_PR3_RANGE                       19:19
#define GPIO_Z_SCR_05_0_PR3_WOFFSET                     0x0
#define GPIO_Z_SCR_05_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_05_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_05_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_Z_SCR_05_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_PR2_SHIFT)
#define GPIO_Z_SCR_05_0_PR2_RANGE                       18:18
#define GPIO_Z_SCR_05_0_PR2_WOFFSET                     0x0
#define GPIO_Z_SCR_05_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_05_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_05_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_Z_SCR_05_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_PR1_SHIFT)
#define GPIO_Z_SCR_05_0_PR1_RANGE                       17:17
#define GPIO_Z_SCR_05_0_PR1_WOFFSET                     0x0
#define GPIO_Z_SCR_05_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_05_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_05_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_Z_SCR_05_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_PR0_SHIFT)
#define GPIO_Z_SCR_05_0_PR0_RANGE                       16:16
#define GPIO_Z_SCR_05_0_PR0_WOFFSET                     0x0
#define GPIO_Z_SCR_05_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_05_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_05_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_Z_SCR_05_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_G7W_SHIFT)
#define GPIO_Z_SCR_05_0_G7W_RANGE                       15:15
#define GPIO_Z_SCR_05_0_G7W_WOFFSET                     0x0
#define GPIO_Z_SCR_05_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_05_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_05_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_Z_SCR_05_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_G6W_SHIFT)
#define GPIO_Z_SCR_05_0_G6W_RANGE                       14:14
#define GPIO_Z_SCR_05_0_G6W_WOFFSET                     0x0
#define GPIO_Z_SCR_05_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_05_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_05_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_Z_SCR_05_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_G5W_SHIFT)
#define GPIO_Z_SCR_05_0_G5W_RANGE                       13:13
#define GPIO_Z_SCR_05_0_G5W_WOFFSET                     0x0
#define GPIO_Z_SCR_05_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_05_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_05_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_Z_SCR_05_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_G4W_SHIFT)
#define GPIO_Z_SCR_05_0_G4W_RANGE                       12:12
#define GPIO_Z_SCR_05_0_G4W_WOFFSET                     0x0
#define GPIO_Z_SCR_05_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_05_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_05_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_Z_SCR_05_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_G3W_SHIFT)
#define GPIO_Z_SCR_05_0_G3W_RANGE                       11:11
#define GPIO_Z_SCR_05_0_G3W_WOFFSET                     0x0
#define GPIO_Z_SCR_05_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_05_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_05_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_Z_SCR_05_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_G2W_SHIFT)
#define GPIO_Z_SCR_05_0_G2W_RANGE                       10:10
#define GPIO_Z_SCR_05_0_G2W_WOFFSET                     0x0
#define GPIO_Z_SCR_05_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_05_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_05_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_Z_SCR_05_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_G1W_SHIFT)
#define GPIO_Z_SCR_05_0_G1W_RANGE                       9:9
#define GPIO_Z_SCR_05_0_G1W_WOFFSET                     0x0
#define GPIO_Z_SCR_05_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_05_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_05_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_Z_SCR_05_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_G0W_SHIFT)
#define GPIO_Z_SCR_05_0_G0W_RANGE                       8:8
#define GPIO_Z_SCR_05_0_G0W_WOFFSET                     0x0
#define GPIO_Z_SCR_05_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_05_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_05_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_Z_SCR_05_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_G7R_SHIFT)
#define GPIO_Z_SCR_05_0_G7R_RANGE                       7:7
#define GPIO_Z_SCR_05_0_G7R_WOFFSET                     0x0
#define GPIO_Z_SCR_05_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_05_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_05_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_Z_SCR_05_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_G6R_SHIFT)
#define GPIO_Z_SCR_05_0_G6R_RANGE                       6:6
#define GPIO_Z_SCR_05_0_G6R_WOFFSET                     0x0
#define GPIO_Z_SCR_05_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_05_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_05_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Z_SCR_05_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_G5R_SHIFT)
#define GPIO_Z_SCR_05_0_G5R_RANGE                       5:5
#define GPIO_Z_SCR_05_0_G5R_WOFFSET                     0x0
#define GPIO_Z_SCR_05_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_05_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_05_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_Z_SCR_05_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_G4R_SHIFT)
#define GPIO_Z_SCR_05_0_G4R_RANGE                       4:4
#define GPIO_Z_SCR_05_0_G4R_WOFFSET                     0x0
#define GPIO_Z_SCR_05_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_05_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_05_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_Z_SCR_05_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_G3R_SHIFT)
#define GPIO_Z_SCR_05_0_G3R_RANGE                       3:3
#define GPIO_Z_SCR_05_0_G3R_WOFFSET                     0x0
#define GPIO_Z_SCR_05_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_05_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_05_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_Z_SCR_05_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_G2R_SHIFT)
#define GPIO_Z_SCR_05_0_G2R_RANGE                       2:2
#define GPIO_Z_SCR_05_0_G2R_WOFFSET                     0x0
#define GPIO_Z_SCR_05_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_05_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_05_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_Z_SCR_05_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_G1R_SHIFT)
#define GPIO_Z_SCR_05_0_G1R_RANGE                       1:1
#define GPIO_Z_SCR_05_0_G1R_WOFFSET                     0x0
#define GPIO_Z_SCR_05_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_05_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_05_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Z_SCR_05_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_G0R_SHIFT)
#define GPIO_Z_SCR_05_0_G0R_RANGE                       0:0
#define GPIO_Z_SCR_05_0_G0R_WOFFSET                     0x0
#define GPIO_Z_SCR_05_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_05_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_Z_VM_06_0
#define GPIO_Z_VM_06_0                  _MK_ADDR_CONST(0x20b0)
#define GPIO_Z_VM_06_0_SECURE                   0x0
#define GPIO_Z_VM_06_0_DUAL                     0x0
#define GPIO_Z_VM_06_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_Z_VM_06_0_WORD_COUNT                       0x1
#define GPIO_Z_VM_06_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_06_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_06_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_06_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_06_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_06_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_06_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Z_VM_06_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_06_0_VM1_SHIFT)
#define GPIO_Z_VM_06_0_VM1_RANGE                        1:0
#define GPIO_Z_VM_06_0_VM1_WOFFSET                      0x0
#define GPIO_Z_VM_06_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_06_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_06_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_06_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_06_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_06_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_06_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_Z_VM_06_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_06_0_VM2_SHIFT)
#define GPIO_Z_VM_06_0_VM2_RANGE                        3:2
#define GPIO_Z_VM_06_0_VM2_WOFFSET                      0x0
#define GPIO_Z_VM_06_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_06_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_06_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_06_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_06_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_06_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_06_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_Z_VM_06_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_06_0_VM3_SHIFT)
#define GPIO_Z_VM_06_0_VM3_RANGE                        5:4
#define GPIO_Z_VM_06_0_VM3_WOFFSET                      0x0
#define GPIO_Z_VM_06_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_06_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_06_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_06_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_06_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_06_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_06_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_Z_VM_06_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_06_0_VM4_SHIFT)
#define GPIO_Z_VM_06_0_VM4_RANGE                        7:6
#define GPIO_Z_VM_06_0_VM4_WOFFSET                      0x0
#define GPIO_Z_VM_06_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_06_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_06_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_06_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_06_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_06_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_06_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_Z_VM_06_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_06_0_VM5_SHIFT)
#define GPIO_Z_VM_06_0_VM5_RANGE                        9:8
#define GPIO_Z_VM_06_0_VM5_WOFFSET                      0x0
#define GPIO_Z_VM_06_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_06_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_06_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_06_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_06_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_06_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_06_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_Z_VM_06_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_06_0_VM6_SHIFT)
#define GPIO_Z_VM_06_0_VM6_RANGE                        11:10
#define GPIO_Z_VM_06_0_VM6_WOFFSET                      0x0
#define GPIO_Z_VM_06_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_06_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_06_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_06_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_06_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_06_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_06_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_Z_VM_06_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_06_0_VM7_SHIFT)
#define GPIO_Z_VM_06_0_VM7_RANGE                        13:12
#define GPIO_Z_VM_06_0_VM7_WOFFSET                      0x0
#define GPIO_Z_VM_06_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_06_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_06_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_06_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_06_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_06_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_06_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_Z_VM_06_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_06_0_VM8_SHIFT)
#define GPIO_Z_VM_06_0_VM8_RANGE                        15:14
#define GPIO_Z_VM_06_0_VM8_WOFFSET                      0x0
#define GPIO_Z_VM_06_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_06_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_06_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_06_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_06_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_06_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_Z_SCR_06_0
#define GPIO_Z_SCR_06_0                 _MK_ADDR_CONST(0x20b4)
#define GPIO_Z_SCR_06_0_SECURE                  0x0
#define GPIO_Z_SCR_06_0_DUAL                    0x0
#define GPIO_Z_SCR_06_0_SCR                     0
#define GPIO_Z_SCR_06_0_WORD_COUNT                      0x1
#define GPIO_Z_SCR_06_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Z_SCR_06_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_Z_SCR_06_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Z_SCR_06_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_Z_SCR_06_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_SEC_LCK_SHIFT)
#define GPIO_Z_SCR_06_0_SEC_LCK_RANGE                   29:29
#define GPIO_Z_SCR_06_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Z_SCR_06_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_06_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_06_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_Z_SCR_06_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_SEC_WEN_SHIFT)
#define GPIO_Z_SCR_06_0_SEC_WEN_RANGE                   28:28
#define GPIO_Z_SCR_06_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Z_SCR_06_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_06_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_06_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_Z_SCR_06_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_SEC_REN_SHIFT)
#define GPIO_Z_SCR_06_0_SEC_REN_RANGE                   27:27
#define GPIO_Z_SCR_06_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Z_SCR_06_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_06_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_06_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_Z_SCR_06_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_Z_SCR_06_0_SEC_OWNER_SHIFT)
#define GPIO_Z_SCR_06_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Z_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Z_SCR_06_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_Z_SCR_06_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_06_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_Z_SCR_06_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_PR7_SHIFT)
#define GPIO_Z_SCR_06_0_PR7_RANGE                       23:23
#define GPIO_Z_SCR_06_0_PR7_WOFFSET                     0x0
#define GPIO_Z_SCR_06_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_06_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_06_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_Z_SCR_06_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_PR6_SHIFT)
#define GPIO_Z_SCR_06_0_PR6_RANGE                       22:22
#define GPIO_Z_SCR_06_0_PR6_WOFFSET                     0x0
#define GPIO_Z_SCR_06_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_06_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_06_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_Z_SCR_06_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_PR5_SHIFT)
#define GPIO_Z_SCR_06_0_PR5_RANGE                       21:21
#define GPIO_Z_SCR_06_0_PR5_WOFFSET                     0x0
#define GPIO_Z_SCR_06_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_06_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_06_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_Z_SCR_06_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_PR4_SHIFT)
#define GPIO_Z_SCR_06_0_PR4_RANGE                       20:20
#define GPIO_Z_SCR_06_0_PR4_WOFFSET                     0x0
#define GPIO_Z_SCR_06_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_06_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_06_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_Z_SCR_06_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_PR3_SHIFT)
#define GPIO_Z_SCR_06_0_PR3_RANGE                       19:19
#define GPIO_Z_SCR_06_0_PR3_WOFFSET                     0x0
#define GPIO_Z_SCR_06_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_06_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_06_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_Z_SCR_06_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_PR2_SHIFT)
#define GPIO_Z_SCR_06_0_PR2_RANGE                       18:18
#define GPIO_Z_SCR_06_0_PR2_WOFFSET                     0x0
#define GPIO_Z_SCR_06_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_06_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_06_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_Z_SCR_06_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_PR1_SHIFT)
#define GPIO_Z_SCR_06_0_PR1_RANGE                       17:17
#define GPIO_Z_SCR_06_0_PR1_WOFFSET                     0x0
#define GPIO_Z_SCR_06_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_06_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_06_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_Z_SCR_06_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_PR0_SHIFT)
#define GPIO_Z_SCR_06_0_PR0_RANGE                       16:16
#define GPIO_Z_SCR_06_0_PR0_WOFFSET                     0x0
#define GPIO_Z_SCR_06_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_06_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_06_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_Z_SCR_06_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_G7W_SHIFT)
#define GPIO_Z_SCR_06_0_G7W_RANGE                       15:15
#define GPIO_Z_SCR_06_0_G7W_WOFFSET                     0x0
#define GPIO_Z_SCR_06_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_06_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_06_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_Z_SCR_06_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_G6W_SHIFT)
#define GPIO_Z_SCR_06_0_G6W_RANGE                       14:14
#define GPIO_Z_SCR_06_0_G6W_WOFFSET                     0x0
#define GPIO_Z_SCR_06_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_06_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_06_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_Z_SCR_06_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_G5W_SHIFT)
#define GPIO_Z_SCR_06_0_G5W_RANGE                       13:13
#define GPIO_Z_SCR_06_0_G5W_WOFFSET                     0x0
#define GPIO_Z_SCR_06_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_06_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_06_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_Z_SCR_06_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_G4W_SHIFT)
#define GPIO_Z_SCR_06_0_G4W_RANGE                       12:12
#define GPIO_Z_SCR_06_0_G4W_WOFFSET                     0x0
#define GPIO_Z_SCR_06_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_06_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_06_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_Z_SCR_06_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_G3W_SHIFT)
#define GPIO_Z_SCR_06_0_G3W_RANGE                       11:11
#define GPIO_Z_SCR_06_0_G3W_WOFFSET                     0x0
#define GPIO_Z_SCR_06_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_06_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_06_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_Z_SCR_06_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_G2W_SHIFT)
#define GPIO_Z_SCR_06_0_G2W_RANGE                       10:10
#define GPIO_Z_SCR_06_0_G2W_WOFFSET                     0x0
#define GPIO_Z_SCR_06_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_06_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_06_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_Z_SCR_06_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_G1W_SHIFT)
#define GPIO_Z_SCR_06_0_G1W_RANGE                       9:9
#define GPIO_Z_SCR_06_0_G1W_WOFFSET                     0x0
#define GPIO_Z_SCR_06_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_06_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_06_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_Z_SCR_06_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_G0W_SHIFT)
#define GPIO_Z_SCR_06_0_G0W_RANGE                       8:8
#define GPIO_Z_SCR_06_0_G0W_WOFFSET                     0x0
#define GPIO_Z_SCR_06_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_06_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_06_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_Z_SCR_06_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_G7R_SHIFT)
#define GPIO_Z_SCR_06_0_G7R_RANGE                       7:7
#define GPIO_Z_SCR_06_0_G7R_WOFFSET                     0x0
#define GPIO_Z_SCR_06_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_06_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_06_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_Z_SCR_06_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_G6R_SHIFT)
#define GPIO_Z_SCR_06_0_G6R_RANGE                       6:6
#define GPIO_Z_SCR_06_0_G6R_WOFFSET                     0x0
#define GPIO_Z_SCR_06_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_06_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_06_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Z_SCR_06_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_G5R_SHIFT)
#define GPIO_Z_SCR_06_0_G5R_RANGE                       5:5
#define GPIO_Z_SCR_06_0_G5R_WOFFSET                     0x0
#define GPIO_Z_SCR_06_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_06_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_06_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_Z_SCR_06_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_G4R_SHIFT)
#define GPIO_Z_SCR_06_0_G4R_RANGE                       4:4
#define GPIO_Z_SCR_06_0_G4R_WOFFSET                     0x0
#define GPIO_Z_SCR_06_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_06_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_06_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_Z_SCR_06_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_G3R_SHIFT)
#define GPIO_Z_SCR_06_0_G3R_RANGE                       3:3
#define GPIO_Z_SCR_06_0_G3R_WOFFSET                     0x0
#define GPIO_Z_SCR_06_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_06_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_06_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_Z_SCR_06_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_G2R_SHIFT)
#define GPIO_Z_SCR_06_0_G2R_RANGE                       2:2
#define GPIO_Z_SCR_06_0_G2R_WOFFSET                     0x0
#define GPIO_Z_SCR_06_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_06_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_06_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_Z_SCR_06_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_G1R_SHIFT)
#define GPIO_Z_SCR_06_0_G1R_RANGE                       1:1
#define GPIO_Z_SCR_06_0_G1R_WOFFSET                     0x0
#define GPIO_Z_SCR_06_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_06_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_06_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Z_SCR_06_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_G0R_SHIFT)
#define GPIO_Z_SCR_06_0_G0R_RANGE                       0:0
#define GPIO_Z_SCR_06_0_G0R_WOFFSET                     0x0
#define GPIO_Z_SCR_06_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_06_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_Z_VM_07_0
#define GPIO_Z_VM_07_0                  _MK_ADDR_CONST(0x20b8)
#define GPIO_Z_VM_07_0_SECURE                   0x0
#define GPIO_Z_VM_07_0_DUAL                     0x0
#define GPIO_Z_VM_07_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_Z_VM_07_0_WORD_COUNT                       0x1
#define GPIO_Z_VM_07_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_07_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_07_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_07_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_07_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_07_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_07_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Z_VM_07_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_07_0_VM1_SHIFT)
#define GPIO_Z_VM_07_0_VM1_RANGE                        1:0
#define GPIO_Z_VM_07_0_VM1_WOFFSET                      0x0
#define GPIO_Z_VM_07_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_07_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_07_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_07_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_07_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_07_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_07_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_Z_VM_07_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_07_0_VM2_SHIFT)
#define GPIO_Z_VM_07_0_VM2_RANGE                        3:2
#define GPIO_Z_VM_07_0_VM2_WOFFSET                      0x0
#define GPIO_Z_VM_07_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_07_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_07_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_07_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_07_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_07_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_07_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_Z_VM_07_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_07_0_VM3_SHIFT)
#define GPIO_Z_VM_07_0_VM3_RANGE                        5:4
#define GPIO_Z_VM_07_0_VM3_WOFFSET                      0x0
#define GPIO_Z_VM_07_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_07_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_07_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_07_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_07_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_07_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_07_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_Z_VM_07_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_07_0_VM4_SHIFT)
#define GPIO_Z_VM_07_0_VM4_RANGE                        7:6
#define GPIO_Z_VM_07_0_VM4_WOFFSET                      0x0
#define GPIO_Z_VM_07_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_07_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_07_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_07_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_07_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_07_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_07_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_Z_VM_07_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_07_0_VM5_SHIFT)
#define GPIO_Z_VM_07_0_VM5_RANGE                        9:8
#define GPIO_Z_VM_07_0_VM5_WOFFSET                      0x0
#define GPIO_Z_VM_07_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_07_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_07_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_07_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_07_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_07_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_07_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_Z_VM_07_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_07_0_VM6_SHIFT)
#define GPIO_Z_VM_07_0_VM6_RANGE                        11:10
#define GPIO_Z_VM_07_0_VM6_WOFFSET                      0x0
#define GPIO_Z_VM_07_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_07_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_07_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_07_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_07_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_07_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_07_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_Z_VM_07_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_07_0_VM7_SHIFT)
#define GPIO_Z_VM_07_0_VM7_RANGE                        13:12
#define GPIO_Z_VM_07_0_VM7_WOFFSET                      0x0
#define GPIO_Z_VM_07_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_07_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_07_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_07_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_07_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_07_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Z_VM_07_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_Z_VM_07_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Z_VM_07_0_VM8_SHIFT)
#define GPIO_Z_VM_07_0_VM8_RANGE                        15:14
#define GPIO_Z_VM_07_0_VM8_WOFFSET                      0x0
#define GPIO_Z_VM_07_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_07_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Z_VM_07_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_07_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_07_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_VM_07_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_Z_SCR_07_0
#define GPIO_Z_SCR_07_0                 _MK_ADDR_CONST(0x20bc)
#define GPIO_Z_SCR_07_0_SECURE                  0x0
#define GPIO_Z_SCR_07_0_DUAL                    0x0
#define GPIO_Z_SCR_07_0_SCR                     0
#define GPIO_Z_SCR_07_0_WORD_COUNT                      0x1
#define GPIO_Z_SCR_07_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Z_SCR_07_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_Z_SCR_07_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Z_SCR_07_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_Z_SCR_07_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_SEC_LCK_SHIFT)
#define GPIO_Z_SCR_07_0_SEC_LCK_RANGE                   29:29
#define GPIO_Z_SCR_07_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Z_SCR_07_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_07_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_07_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_Z_SCR_07_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_SEC_WEN_SHIFT)
#define GPIO_Z_SCR_07_0_SEC_WEN_RANGE                   28:28
#define GPIO_Z_SCR_07_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Z_SCR_07_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_07_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_07_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_Z_SCR_07_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_SEC_REN_SHIFT)
#define GPIO_Z_SCR_07_0_SEC_REN_RANGE                   27:27
#define GPIO_Z_SCR_07_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Z_SCR_07_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_07_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_07_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_Z_SCR_07_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_Z_SCR_07_0_SEC_OWNER_SHIFT)
#define GPIO_Z_SCR_07_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Z_SCR_07_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Z_SCR_07_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_Z_SCR_07_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_07_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_Z_SCR_07_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_PR7_SHIFT)
#define GPIO_Z_SCR_07_0_PR7_RANGE                       23:23
#define GPIO_Z_SCR_07_0_PR7_WOFFSET                     0x0
#define GPIO_Z_SCR_07_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_07_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_07_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_Z_SCR_07_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_PR6_SHIFT)
#define GPIO_Z_SCR_07_0_PR6_RANGE                       22:22
#define GPIO_Z_SCR_07_0_PR6_WOFFSET                     0x0
#define GPIO_Z_SCR_07_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_07_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_07_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_Z_SCR_07_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_PR5_SHIFT)
#define GPIO_Z_SCR_07_0_PR5_RANGE                       21:21
#define GPIO_Z_SCR_07_0_PR5_WOFFSET                     0x0
#define GPIO_Z_SCR_07_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_07_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_07_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_Z_SCR_07_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_PR4_SHIFT)
#define GPIO_Z_SCR_07_0_PR4_RANGE                       20:20
#define GPIO_Z_SCR_07_0_PR4_WOFFSET                     0x0
#define GPIO_Z_SCR_07_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_07_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_07_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_Z_SCR_07_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_PR3_SHIFT)
#define GPIO_Z_SCR_07_0_PR3_RANGE                       19:19
#define GPIO_Z_SCR_07_0_PR3_WOFFSET                     0x0
#define GPIO_Z_SCR_07_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_07_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_07_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_Z_SCR_07_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_PR2_SHIFT)
#define GPIO_Z_SCR_07_0_PR2_RANGE                       18:18
#define GPIO_Z_SCR_07_0_PR2_WOFFSET                     0x0
#define GPIO_Z_SCR_07_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_07_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_07_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_Z_SCR_07_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_PR1_SHIFT)
#define GPIO_Z_SCR_07_0_PR1_RANGE                       17:17
#define GPIO_Z_SCR_07_0_PR1_WOFFSET                     0x0
#define GPIO_Z_SCR_07_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_07_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_07_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_Z_SCR_07_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_PR0_SHIFT)
#define GPIO_Z_SCR_07_0_PR0_RANGE                       16:16
#define GPIO_Z_SCR_07_0_PR0_WOFFSET                     0x0
#define GPIO_Z_SCR_07_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_07_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_07_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_Z_SCR_07_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_G7W_SHIFT)
#define GPIO_Z_SCR_07_0_G7W_RANGE                       15:15
#define GPIO_Z_SCR_07_0_G7W_WOFFSET                     0x0
#define GPIO_Z_SCR_07_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_07_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_07_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_Z_SCR_07_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_G6W_SHIFT)
#define GPIO_Z_SCR_07_0_G6W_RANGE                       14:14
#define GPIO_Z_SCR_07_0_G6W_WOFFSET                     0x0
#define GPIO_Z_SCR_07_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_07_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_07_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_Z_SCR_07_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_G5W_SHIFT)
#define GPIO_Z_SCR_07_0_G5W_RANGE                       13:13
#define GPIO_Z_SCR_07_0_G5W_WOFFSET                     0x0
#define GPIO_Z_SCR_07_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_07_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_07_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_Z_SCR_07_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_G4W_SHIFT)
#define GPIO_Z_SCR_07_0_G4W_RANGE                       12:12
#define GPIO_Z_SCR_07_0_G4W_WOFFSET                     0x0
#define GPIO_Z_SCR_07_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_07_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_07_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_Z_SCR_07_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_G3W_SHIFT)
#define GPIO_Z_SCR_07_0_G3W_RANGE                       11:11
#define GPIO_Z_SCR_07_0_G3W_WOFFSET                     0x0
#define GPIO_Z_SCR_07_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_07_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_07_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_Z_SCR_07_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_G2W_SHIFT)
#define GPIO_Z_SCR_07_0_G2W_RANGE                       10:10
#define GPIO_Z_SCR_07_0_G2W_WOFFSET                     0x0
#define GPIO_Z_SCR_07_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_07_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_07_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_Z_SCR_07_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_G1W_SHIFT)
#define GPIO_Z_SCR_07_0_G1W_RANGE                       9:9
#define GPIO_Z_SCR_07_0_G1W_WOFFSET                     0x0
#define GPIO_Z_SCR_07_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_07_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_07_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_Z_SCR_07_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_G0W_SHIFT)
#define GPIO_Z_SCR_07_0_G0W_RANGE                       8:8
#define GPIO_Z_SCR_07_0_G0W_WOFFSET                     0x0
#define GPIO_Z_SCR_07_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_07_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_07_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_Z_SCR_07_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_G7R_SHIFT)
#define GPIO_Z_SCR_07_0_G7R_RANGE                       7:7
#define GPIO_Z_SCR_07_0_G7R_WOFFSET                     0x0
#define GPIO_Z_SCR_07_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_07_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_07_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_Z_SCR_07_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_G6R_SHIFT)
#define GPIO_Z_SCR_07_0_G6R_RANGE                       6:6
#define GPIO_Z_SCR_07_0_G6R_WOFFSET                     0x0
#define GPIO_Z_SCR_07_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_07_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_07_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Z_SCR_07_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_G5R_SHIFT)
#define GPIO_Z_SCR_07_0_G5R_RANGE                       5:5
#define GPIO_Z_SCR_07_0_G5R_WOFFSET                     0x0
#define GPIO_Z_SCR_07_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_07_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_07_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_Z_SCR_07_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_G4R_SHIFT)
#define GPIO_Z_SCR_07_0_G4R_RANGE                       4:4
#define GPIO_Z_SCR_07_0_G4R_WOFFSET                     0x0
#define GPIO_Z_SCR_07_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_07_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_07_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_Z_SCR_07_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_G3R_SHIFT)
#define GPIO_Z_SCR_07_0_G3R_RANGE                       3:3
#define GPIO_Z_SCR_07_0_G3R_WOFFSET                     0x0
#define GPIO_Z_SCR_07_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_07_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_07_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_Z_SCR_07_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_G2R_SHIFT)
#define GPIO_Z_SCR_07_0_G2R_RANGE                       2:2
#define GPIO_Z_SCR_07_0_G2R_WOFFSET                     0x0
#define GPIO_Z_SCR_07_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_07_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_07_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_Z_SCR_07_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_G1R_SHIFT)
#define GPIO_Z_SCR_07_0_G1R_RANGE                       1:1
#define GPIO_Z_SCR_07_0_G1R_WOFFSET                     0x0
#define GPIO_Z_SCR_07_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_07_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_07_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Z_SCR_07_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_G0R_SHIFT)
#define GPIO_Z_SCR_07_0_G0R_RANGE                       0:0
#define GPIO_Z_SCR_07_0_G0R_WOFFSET                     0x0
#define GPIO_Z_SCR_07_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_07_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_M_VM_00_0
#define GPIO_M_VM_00_0                  _MK_ADDR_CONST(0x20c0)
#define GPIO_M_VM_00_0_SECURE                   0x0
#define GPIO_M_VM_00_0_DUAL                     0x0
#define GPIO_M_VM_00_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_M_VM_00_0_WORD_COUNT                       0x1
#define GPIO_M_VM_00_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_00_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_00_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_00_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_M_VM_00_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_00_0_VM1_SHIFT)
#define GPIO_M_VM_00_0_VM1_RANGE                        1:0
#define GPIO_M_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_M_VM_00_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_00_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_00_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_00_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_M_VM_00_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_00_0_VM2_SHIFT)
#define GPIO_M_VM_00_0_VM2_RANGE                        3:2
#define GPIO_M_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_M_VM_00_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_00_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_00_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_00_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_M_VM_00_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_00_0_VM3_SHIFT)
#define GPIO_M_VM_00_0_VM3_RANGE                        5:4
#define GPIO_M_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_M_VM_00_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_00_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_00_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_00_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_M_VM_00_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_00_0_VM4_SHIFT)
#define GPIO_M_VM_00_0_VM4_RANGE                        7:6
#define GPIO_M_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_M_VM_00_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_00_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_00_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_00_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_M_VM_00_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_00_0_VM5_SHIFT)
#define GPIO_M_VM_00_0_VM5_RANGE                        9:8
#define GPIO_M_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_M_VM_00_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_00_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_00_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_00_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_M_VM_00_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_00_0_VM6_SHIFT)
#define GPIO_M_VM_00_0_VM6_RANGE                        11:10
#define GPIO_M_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_M_VM_00_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_00_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_00_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_00_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_M_VM_00_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_00_0_VM7_SHIFT)
#define GPIO_M_VM_00_0_VM7_RANGE                        13:12
#define GPIO_M_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_M_VM_00_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_00_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_00_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_00_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_M_VM_00_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_00_0_VM8_SHIFT)
#define GPIO_M_VM_00_0_VM8_RANGE                        15:14
#define GPIO_M_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_M_VM_00_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_00_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_00_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_M_SCR_00_0
#define GPIO_M_SCR_00_0                 _MK_ADDR_CONST(0x20c4)
#define GPIO_M_SCR_00_0_SECURE                  0x0
#define GPIO_M_SCR_00_0_DUAL                    0x0
#define GPIO_M_SCR_00_0_SCR                     0
#define GPIO_M_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_M_SCR_00_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_00_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_00_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_M_SCR_00_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_M_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_M_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_M_SCR_00_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_00_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_M_SCR_00_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_M_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_M_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_M_SCR_00_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_00_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_M_SCR_00_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_M_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_M_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_M_SCR_00_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_00_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_M_SCR_00_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_M_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_M_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_M_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_M_SCR_00_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_M_SCR_00_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_00_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_M_SCR_00_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_PR7_SHIFT)
#define GPIO_M_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_M_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_00_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_M_SCR_00_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_PR6_SHIFT)
#define GPIO_M_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_M_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_00_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_M_SCR_00_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_PR5_SHIFT)
#define GPIO_M_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_M_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_00_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_M_SCR_00_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_PR4_SHIFT)
#define GPIO_M_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_M_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_00_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_M_SCR_00_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_PR3_SHIFT)
#define GPIO_M_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_M_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_00_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_M_SCR_00_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_PR2_SHIFT)
#define GPIO_M_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_M_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_00_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_M_SCR_00_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_PR1_SHIFT)
#define GPIO_M_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_M_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_00_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_M_SCR_00_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_PR0_SHIFT)
#define GPIO_M_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_M_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_00_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_M_SCR_00_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G7W_SHIFT)
#define GPIO_M_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_M_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_00_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_M_SCR_00_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G6W_SHIFT)
#define GPIO_M_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_M_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_00_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_M_SCR_00_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G5W_SHIFT)
#define GPIO_M_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_M_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_00_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_M_SCR_00_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G4W_SHIFT)
#define GPIO_M_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_M_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_00_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_M_SCR_00_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G3W_SHIFT)
#define GPIO_M_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_M_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_00_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_M_SCR_00_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G2W_SHIFT)
#define GPIO_M_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_M_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_00_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_M_SCR_00_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G1W_SHIFT)
#define GPIO_M_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_M_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_00_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_M_SCR_00_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G0W_SHIFT)
#define GPIO_M_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_M_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_00_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_M_SCR_00_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G7R_SHIFT)
#define GPIO_M_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_M_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_00_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_M_SCR_00_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G6R_SHIFT)
#define GPIO_M_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_M_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_00_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_M_SCR_00_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G5R_SHIFT)
#define GPIO_M_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_M_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_00_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_M_SCR_00_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G4R_SHIFT)
#define GPIO_M_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_M_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_00_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_M_SCR_00_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G3R_SHIFT)
#define GPIO_M_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_M_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_00_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_M_SCR_00_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G2R_SHIFT)
#define GPIO_M_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_M_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_00_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_M_SCR_00_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G1R_SHIFT)
#define GPIO_M_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_M_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_00_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_M_SCR_00_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G0R_SHIFT)
#define GPIO_M_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_M_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_M_VM_01_0
#define GPIO_M_VM_01_0                  _MK_ADDR_CONST(0x20c8)
#define GPIO_M_VM_01_0_SECURE                   0x0
#define GPIO_M_VM_01_0_DUAL                     0x0
#define GPIO_M_VM_01_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_M_VM_01_0_WORD_COUNT                       0x1
#define GPIO_M_VM_01_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_01_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_01_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_01_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_M_VM_01_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_01_0_VM1_SHIFT)
#define GPIO_M_VM_01_0_VM1_RANGE                        1:0
#define GPIO_M_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_M_VM_01_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_01_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_01_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_01_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_M_VM_01_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_01_0_VM2_SHIFT)
#define GPIO_M_VM_01_0_VM2_RANGE                        3:2
#define GPIO_M_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_M_VM_01_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_01_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_01_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_01_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_M_VM_01_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_01_0_VM3_SHIFT)
#define GPIO_M_VM_01_0_VM3_RANGE                        5:4
#define GPIO_M_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_M_VM_01_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_01_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_01_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_01_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_M_VM_01_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_01_0_VM4_SHIFT)
#define GPIO_M_VM_01_0_VM4_RANGE                        7:6
#define GPIO_M_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_M_VM_01_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_01_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_01_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_01_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_M_VM_01_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_01_0_VM5_SHIFT)
#define GPIO_M_VM_01_0_VM5_RANGE                        9:8
#define GPIO_M_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_M_VM_01_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_01_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_01_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_01_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_M_VM_01_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_01_0_VM6_SHIFT)
#define GPIO_M_VM_01_0_VM6_RANGE                        11:10
#define GPIO_M_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_M_VM_01_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_01_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_01_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_01_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_M_VM_01_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_01_0_VM7_SHIFT)
#define GPIO_M_VM_01_0_VM7_RANGE                        13:12
#define GPIO_M_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_M_VM_01_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_01_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_01_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_01_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_M_VM_01_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_01_0_VM8_SHIFT)
#define GPIO_M_VM_01_0_VM8_RANGE                        15:14
#define GPIO_M_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_M_VM_01_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_01_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_01_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_M_SCR_01_0
#define GPIO_M_SCR_01_0                 _MK_ADDR_CONST(0x20cc)
#define GPIO_M_SCR_01_0_SECURE                  0x0
#define GPIO_M_SCR_01_0_DUAL                    0x0
#define GPIO_M_SCR_01_0_SCR                     0
#define GPIO_M_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_M_SCR_01_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_01_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_01_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_01_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_M_SCR_01_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_M_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_M_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_M_SCR_01_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_01_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_M_SCR_01_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_M_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_M_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_M_SCR_01_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_01_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_M_SCR_01_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_M_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_M_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_M_SCR_01_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_01_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_M_SCR_01_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_M_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_M_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_M_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_M_SCR_01_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_M_SCR_01_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_01_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_M_SCR_01_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_PR7_SHIFT)
#define GPIO_M_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_M_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_01_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_M_SCR_01_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_PR6_SHIFT)
#define GPIO_M_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_M_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_01_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_M_SCR_01_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_PR5_SHIFT)
#define GPIO_M_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_M_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_01_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_M_SCR_01_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_PR4_SHIFT)
#define GPIO_M_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_M_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_01_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_M_SCR_01_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_PR3_SHIFT)
#define GPIO_M_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_M_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_01_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_M_SCR_01_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_PR2_SHIFT)
#define GPIO_M_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_M_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_01_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_M_SCR_01_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_PR1_SHIFT)
#define GPIO_M_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_M_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_01_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_M_SCR_01_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_PR0_SHIFT)
#define GPIO_M_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_M_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_01_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_M_SCR_01_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G7W_SHIFT)
#define GPIO_M_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_M_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_01_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_M_SCR_01_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G6W_SHIFT)
#define GPIO_M_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_M_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_01_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_M_SCR_01_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G5W_SHIFT)
#define GPIO_M_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_M_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_01_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_M_SCR_01_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G4W_SHIFT)
#define GPIO_M_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_M_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_01_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_M_SCR_01_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G3W_SHIFT)
#define GPIO_M_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_M_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_01_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_M_SCR_01_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G2W_SHIFT)
#define GPIO_M_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_M_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_01_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_M_SCR_01_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G1W_SHIFT)
#define GPIO_M_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_M_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_01_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_M_SCR_01_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G0W_SHIFT)
#define GPIO_M_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_M_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_01_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_M_SCR_01_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G7R_SHIFT)
#define GPIO_M_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_M_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_01_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_M_SCR_01_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G6R_SHIFT)
#define GPIO_M_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_M_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_01_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_M_SCR_01_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G5R_SHIFT)
#define GPIO_M_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_M_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_01_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_M_SCR_01_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G4R_SHIFT)
#define GPIO_M_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_M_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_01_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_M_SCR_01_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G3R_SHIFT)
#define GPIO_M_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_M_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_01_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_M_SCR_01_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G2R_SHIFT)
#define GPIO_M_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_M_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_01_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_M_SCR_01_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G1R_SHIFT)
#define GPIO_M_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_M_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_01_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_M_SCR_01_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G0R_SHIFT)
#define GPIO_M_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_M_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_M_VM_02_0
#define GPIO_M_VM_02_0                  _MK_ADDR_CONST(0x20d0)
#define GPIO_M_VM_02_0_SECURE                   0x0
#define GPIO_M_VM_02_0_DUAL                     0x0
#define GPIO_M_VM_02_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_M_VM_02_0_WORD_COUNT                       0x1
#define GPIO_M_VM_02_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_02_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_02_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_02_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_M_VM_02_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_02_0_VM1_SHIFT)
#define GPIO_M_VM_02_0_VM1_RANGE                        1:0
#define GPIO_M_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_M_VM_02_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_02_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_02_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_02_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_M_VM_02_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_02_0_VM2_SHIFT)
#define GPIO_M_VM_02_0_VM2_RANGE                        3:2
#define GPIO_M_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_M_VM_02_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_02_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_02_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_02_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_M_VM_02_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_02_0_VM3_SHIFT)
#define GPIO_M_VM_02_0_VM3_RANGE                        5:4
#define GPIO_M_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_M_VM_02_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_02_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_02_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_02_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_M_VM_02_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_02_0_VM4_SHIFT)
#define GPIO_M_VM_02_0_VM4_RANGE                        7:6
#define GPIO_M_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_M_VM_02_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_02_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_02_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_02_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_M_VM_02_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_02_0_VM5_SHIFT)
#define GPIO_M_VM_02_0_VM5_RANGE                        9:8
#define GPIO_M_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_M_VM_02_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_02_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_02_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_02_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_M_VM_02_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_02_0_VM6_SHIFT)
#define GPIO_M_VM_02_0_VM6_RANGE                        11:10
#define GPIO_M_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_M_VM_02_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_02_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_02_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_02_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_M_VM_02_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_02_0_VM7_SHIFT)
#define GPIO_M_VM_02_0_VM7_RANGE                        13:12
#define GPIO_M_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_M_VM_02_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_02_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_02_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_02_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_M_VM_02_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_02_0_VM8_SHIFT)
#define GPIO_M_VM_02_0_VM8_RANGE                        15:14
#define GPIO_M_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_M_VM_02_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_02_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_02_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_M_SCR_02_0
#define GPIO_M_SCR_02_0                 _MK_ADDR_CONST(0x20d4)
#define GPIO_M_SCR_02_0_SECURE                  0x0
#define GPIO_M_SCR_02_0_DUAL                    0x0
#define GPIO_M_SCR_02_0_SCR                     0
#define GPIO_M_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_M_SCR_02_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_02_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_02_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_02_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_M_SCR_02_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_M_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_M_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_M_SCR_02_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_02_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_M_SCR_02_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_M_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_M_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_M_SCR_02_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_02_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_M_SCR_02_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_M_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_M_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_M_SCR_02_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_02_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_M_SCR_02_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_M_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_M_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_M_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_M_SCR_02_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_M_SCR_02_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_02_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_M_SCR_02_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_PR7_SHIFT)
#define GPIO_M_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_M_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_02_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_M_SCR_02_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_PR6_SHIFT)
#define GPIO_M_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_M_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_02_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_M_SCR_02_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_PR5_SHIFT)
#define GPIO_M_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_M_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_02_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_M_SCR_02_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_PR4_SHIFT)
#define GPIO_M_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_M_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_02_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_M_SCR_02_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_PR3_SHIFT)
#define GPIO_M_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_M_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_02_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_M_SCR_02_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_PR2_SHIFT)
#define GPIO_M_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_M_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_02_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_M_SCR_02_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_PR1_SHIFT)
#define GPIO_M_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_M_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_02_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_M_SCR_02_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_PR0_SHIFT)
#define GPIO_M_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_M_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_02_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_M_SCR_02_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G7W_SHIFT)
#define GPIO_M_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_M_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_02_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_M_SCR_02_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G6W_SHIFT)
#define GPIO_M_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_M_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_02_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_M_SCR_02_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G5W_SHIFT)
#define GPIO_M_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_M_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_02_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_M_SCR_02_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G4W_SHIFT)
#define GPIO_M_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_M_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_02_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_M_SCR_02_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G3W_SHIFT)
#define GPIO_M_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_M_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_02_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_M_SCR_02_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G2W_SHIFT)
#define GPIO_M_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_M_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_02_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_M_SCR_02_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G1W_SHIFT)
#define GPIO_M_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_M_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_02_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_M_SCR_02_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G0W_SHIFT)
#define GPIO_M_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_M_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_02_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_M_SCR_02_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G7R_SHIFT)
#define GPIO_M_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_M_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_02_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_M_SCR_02_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G6R_SHIFT)
#define GPIO_M_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_M_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_02_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_M_SCR_02_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G5R_SHIFT)
#define GPIO_M_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_M_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_02_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_M_SCR_02_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G4R_SHIFT)
#define GPIO_M_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_M_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_02_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_M_SCR_02_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G3R_SHIFT)
#define GPIO_M_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_M_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_02_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_M_SCR_02_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G2R_SHIFT)
#define GPIO_M_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_M_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_02_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_M_SCR_02_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G1R_SHIFT)
#define GPIO_M_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_M_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_02_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_M_SCR_02_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G0R_SHIFT)
#define GPIO_M_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_M_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_M_VM_03_0
#define GPIO_M_VM_03_0                  _MK_ADDR_CONST(0x20d8)
#define GPIO_M_VM_03_0_SECURE                   0x0
#define GPIO_M_VM_03_0_DUAL                     0x0
#define GPIO_M_VM_03_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_M_VM_03_0_WORD_COUNT                       0x1
#define GPIO_M_VM_03_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_03_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_03_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_03_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_M_VM_03_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_03_0_VM1_SHIFT)
#define GPIO_M_VM_03_0_VM1_RANGE                        1:0
#define GPIO_M_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_M_VM_03_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_03_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_03_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_03_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_M_VM_03_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_03_0_VM2_SHIFT)
#define GPIO_M_VM_03_0_VM2_RANGE                        3:2
#define GPIO_M_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_M_VM_03_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_03_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_03_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_03_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_M_VM_03_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_03_0_VM3_SHIFT)
#define GPIO_M_VM_03_0_VM3_RANGE                        5:4
#define GPIO_M_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_M_VM_03_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_03_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_03_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_03_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_M_VM_03_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_03_0_VM4_SHIFT)
#define GPIO_M_VM_03_0_VM4_RANGE                        7:6
#define GPIO_M_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_M_VM_03_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_03_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_03_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_03_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_M_VM_03_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_03_0_VM5_SHIFT)
#define GPIO_M_VM_03_0_VM5_RANGE                        9:8
#define GPIO_M_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_M_VM_03_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_03_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_03_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_03_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_M_VM_03_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_03_0_VM6_SHIFT)
#define GPIO_M_VM_03_0_VM6_RANGE                        11:10
#define GPIO_M_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_M_VM_03_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_03_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_03_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_03_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_M_VM_03_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_03_0_VM7_SHIFT)
#define GPIO_M_VM_03_0_VM7_RANGE                        13:12
#define GPIO_M_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_M_VM_03_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_03_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_03_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_03_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_M_VM_03_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_03_0_VM8_SHIFT)
#define GPIO_M_VM_03_0_VM8_RANGE                        15:14
#define GPIO_M_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_M_VM_03_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_03_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_03_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_M_SCR_03_0
#define GPIO_M_SCR_03_0                 _MK_ADDR_CONST(0x20dc)
#define GPIO_M_SCR_03_0_SECURE                  0x0
#define GPIO_M_SCR_03_0_DUAL                    0x0
#define GPIO_M_SCR_03_0_SCR                     0
#define GPIO_M_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_M_SCR_03_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_03_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_03_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_03_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_M_SCR_03_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_M_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_M_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_M_SCR_03_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_03_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_M_SCR_03_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_M_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_M_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_M_SCR_03_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_03_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_M_SCR_03_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_M_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_M_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_M_SCR_03_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_03_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_M_SCR_03_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_M_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_M_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_M_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_M_SCR_03_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_M_SCR_03_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_03_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_M_SCR_03_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_PR7_SHIFT)
#define GPIO_M_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_M_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_03_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_M_SCR_03_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_PR6_SHIFT)
#define GPIO_M_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_M_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_03_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_M_SCR_03_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_PR5_SHIFT)
#define GPIO_M_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_M_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_03_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_M_SCR_03_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_PR4_SHIFT)
#define GPIO_M_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_M_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_03_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_M_SCR_03_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_PR3_SHIFT)
#define GPIO_M_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_M_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_03_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_M_SCR_03_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_PR2_SHIFT)
#define GPIO_M_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_M_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_03_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_M_SCR_03_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_PR1_SHIFT)
#define GPIO_M_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_M_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_03_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_M_SCR_03_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_PR0_SHIFT)
#define GPIO_M_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_M_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_03_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_M_SCR_03_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G7W_SHIFT)
#define GPIO_M_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_M_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_03_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_M_SCR_03_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G6W_SHIFT)
#define GPIO_M_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_M_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_03_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_M_SCR_03_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G5W_SHIFT)
#define GPIO_M_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_M_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_03_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_M_SCR_03_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G4W_SHIFT)
#define GPIO_M_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_M_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_03_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_M_SCR_03_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G3W_SHIFT)
#define GPIO_M_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_M_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_03_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_M_SCR_03_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G2W_SHIFT)
#define GPIO_M_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_M_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_03_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_M_SCR_03_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G1W_SHIFT)
#define GPIO_M_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_M_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_03_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_M_SCR_03_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G0W_SHIFT)
#define GPIO_M_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_M_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_03_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_M_SCR_03_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G7R_SHIFT)
#define GPIO_M_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_M_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_03_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_M_SCR_03_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G6R_SHIFT)
#define GPIO_M_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_M_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_03_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_M_SCR_03_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G5R_SHIFT)
#define GPIO_M_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_M_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_03_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_M_SCR_03_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G4R_SHIFT)
#define GPIO_M_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_M_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_03_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_M_SCR_03_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G3R_SHIFT)
#define GPIO_M_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_M_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_03_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_M_SCR_03_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G2R_SHIFT)
#define GPIO_M_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_M_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_03_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_M_SCR_03_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G1R_SHIFT)
#define GPIO_M_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_M_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_03_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_M_SCR_03_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G0R_SHIFT)
#define GPIO_M_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_M_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_M_VM_04_0
#define GPIO_M_VM_04_0                  _MK_ADDR_CONST(0x20e0)
#define GPIO_M_VM_04_0_SECURE                   0x0
#define GPIO_M_VM_04_0_DUAL                     0x0
#define GPIO_M_VM_04_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_M_VM_04_0_WORD_COUNT                       0x1
#define GPIO_M_VM_04_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_04_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_04_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_04_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_M_VM_04_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_04_0_VM1_SHIFT)
#define GPIO_M_VM_04_0_VM1_RANGE                        1:0
#define GPIO_M_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_M_VM_04_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_04_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_04_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_04_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_M_VM_04_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_04_0_VM2_SHIFT)
#define GPIO_M_VM_04_0_VM2_RANGE                        3:2
#define GPIO_M_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_M_VM_04_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_04_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_04_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_04_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_M_VM_04_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_04_0_VM3_SHIFT)
#define GPIO_M_VM_04_0_VM3_RANGE                        5:4
#define GPIO_M_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_M_VM_04_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_04_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_04_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_04_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_M_VM_04_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_04_0_VM4_SHIFT)
#define GPIO_M_VM_04_0_VM4_RANGE                        7:6
#define GPIO_M_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_M_VM_04_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_04_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_04_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_04_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_M_VM_04_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_04_0_VM5_SHIFT)
#define GPIO_M_VM_04_0_VM5_RANGE                        9:8
#define GPIO_M_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_M_VM_04_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_04_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_04_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_04_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_M_VM_04_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_04_0_VM6_SHIFT)
#define GPIO_M_VM_04_0_VM6_RANGE                        11:10
#define GPIO_M_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_M_VM_04_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_04_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_04_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_04_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_M_VM_04_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_04_0_VM7_SHIFT)
#define GPIO_M_VM_04_0_VM7_RANGE                        13:12
#define GPIO_M_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_M_VM_04_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_04_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_04_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_04_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_M_VM_04_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_04_0_VM8_SHIFT)
#define GPIO_M_VM_04_0_VM8_RANGE                        15:14
#define GPIO_M_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_M_VM_04_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_04_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_04_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_M_SCR_04_0
#define GPIO_M_SCR_04_0                 _MK_ADDR_CONST(0x20e4)
#define GPIO_M_SCR_04_0_SECURE                  0x0
#define GPIO_M_SCR_04_0_DUAL                    0x0
#define GPIO_M_SCR_04_0_SCR                     0
#define GPIO_M_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_M_SCR_04_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_04_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_04_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_04_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_M_SCR_04_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_M_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_M_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_M_SCR_04_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_04_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_M_SCR_04_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_M_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_M_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_M_SCR_04_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_04_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_M_SCR_04_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_M_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_M_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_M_SCR_04_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_04_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_M_SCR_04_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_M_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_M_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_M_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_M_SCR_04_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_M_SCR_04_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_04_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_M_SCR_04_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_PR7_SHIFT)
#define GPIO_M_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_M_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_04_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_M_SCR_04_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_PR6_SHIFT)
#define GPIO_M_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_M_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_04_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_M_SCR_04_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_PR5_SHIFT)
#define GPIO_M_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_M_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_04_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_M_SCR_04_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_PR4_SHIFT)
#define GPIO_M_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_M_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_04_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_M_SCR_04_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_PR3_SHIFT)
#define GPIO_M_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_M_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_04_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_M_SCR_04_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_PR2_SHIFT)
#define GPIO_M_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_M_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_04_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_M_SCR_04_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_PR1_SHIFT)
#define GPIO_M_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_M_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_04_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_M_SCR_04_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_PR0_SHIFT)
#define GPIO_M_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_M_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_04_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_M_SCR_04_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G7W_SHIFT)
#define GPIO_M_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_M_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_04_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_M_SCR_04_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G6W_SHIFT)
#define GPIO_M_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_M_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_04_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_M_SCR_04_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G5W_SHIFT)
#define GPIO_M_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_M_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_04_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_M_SCR_04_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G4W_SHIFT)
#define GPIO_M_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_M_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_04_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_M_SCR_04_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G3W_SHIFT)
#define GPIO_M_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_M_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_04_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_M_SCR_04_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G2W_SHIFT)
#define GPIO_M_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_M_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_04_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_M_SCR_04_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G1W_SHIFT)
#define GPIO_M_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_M_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_04_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_M_SCR_04_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G0W_SHIFT)
#define GPIO_M_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_M_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_04_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_M_SCR_04_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G7R_SHIFT)
#define GPIO_M_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_M_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_04_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_M_SCR_04_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G6R_SHIFT)
#define GPIO_M_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_M_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_04_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_M_SCR_04_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G5R_SHIFT)
#define GPIO_M_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_M_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_04_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_M_SCR_04_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G4R_SHIFT)
#define GPIO_M_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_M_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_04_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_M_SCR_04_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G3R_SHIFT)
#define GPIO_M_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_M_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_04_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_M_SCR_04_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G2R_SHIFT)
#define GPIO_M_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_M_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_04_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_M_SCR_04_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G1R_SHIFT)
#define GPIO_M_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_M_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_04_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_M_SCR_04_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G0R_SHIFT)
#define GPIO_M_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_M_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_M_VM_05_0
#define GPIO_M_VM_05_0                  _MK_ADDR_CONST(0x20e8)
#define GPIO_M_VM_05_0_SECURE                   0x0
#define GPIO_M_VM_05_0_DUAL                     0x0
#define GPIO_M_VM_05_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_M_VM_05_0_WORD_COUNT                       0x1
#define GPIO_M_VM_05_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_05_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_05_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_05_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_M_VM_05_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_05_0_VM1_SHIFT)
#define GPIO_M_VM_05_0_VM1_RANGE                        1:0
#define GPIO_M_VM_05_0_VM1_WOFFSET                      0x0
#define GPIO_M_VM_05_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_05_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_05_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_05_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_M_VM_05_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_05_0_VM2_SHIFT)
#define GPIO_M_VM_05_0_VM2_RANGE                        3:2
#define GPIO_M_VM_05_0_VM2_WOFFSET                      0x0
#define GPIO_M_VM_05_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_05_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_05_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_05_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_M_VM_05_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_05_0_VM3_SHIFT)
#define GPIO_M_VM_05_0_VM3_RANGE                        5:4
#define GPIO_M_VM_05_0_VM3_WOFFSET                      0x0
#define GPIO_M_VM_05_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_05_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_05_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_05_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_M_VM_05_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_05_0_VM4_SHIFT)
#define GPIO_M_VM_05_0_VM4_RANGE                        7:6
#define GPIO_M_VM_05_0_VM4_WOFFSET                      0x0
#define GPIO_M_VM_05_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_05_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_05_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_05_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_M_VM_05_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_05_0_VM5_SHIFT)
#define GPIO_M_VM_05_0_VM5_RANGE                        9:8
#define GPIO_M_VM_05_0_VM5_WOFFSET                      0x0
#define GPIO_M_VM_05_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_05_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_05_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_05_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_M_VM_05_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_05_0_VM6_SHIFT)
#define GPIO_M_VM_05_0_VM6_RANGE                        11:10
#define GPIO_M_VM_05_0_VM6_WOFFSET                      0x0
#define GPIO_M_VM_05_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_05_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_05_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_05_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_M_VM_05_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_05_0_VM7_SHIFT)
#define GPIO_M_VM_05_0_VM7_RANGE                        13:12
#define GPIO_M_VM_05_0_VM7_WOFFSET                      0x0
#define GPIO_M_VM_05_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_05_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_05_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_05_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_M_VM_05_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_05_0_VM8_SHIFT)
#define GPIO_M_VM_05_0_VM8_RANGE                        15:14
#define GPIO_M_VM_05_0_VM8_WOFFSET                      0x0
#define GPIO_M_VM_05_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_05_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_05_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_M_SCR_05_0
#define GPIO_M_SCR_05_0                 _MK_ADDR_CONST(0x20ec)
#define GPIO_M_SCR_05_0_SECURE                  0x0
#define GPIO_M_SCR_05_0_DUAL                    0x0
#define GPIO_M_SCR_05_0_SCR                     0
#define GPIO_M_SCR_05_0_WORD_COUNT                      0x1
#define GPIO_M_SCR_05_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_05_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_05_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_05_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_M_SCR_05_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_M_SCR_05_0_SEC_LCK_RANGE                   29:29
#define GPIO_M_SCR_05_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_M_SCR_05_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_05_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_M_SCR_05_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_M_SCR_05_0_SEC_WEN_RANGE                   28:28
#define GPIO_M_SCR_05_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_M_SCR_05_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_05_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_M_SCR_05_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_M_SCR_05_0_SEC_REN_RANGE                   27:27
#define GPIO_M_SCR_05_0_SEC_REN_WOFFSET                 0x0
#define GPIO_M_SCR_05_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_05_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_M_SCR_05_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_M_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_M_SCR_05_0_SEC_OWNER_RANGE                 26:24
#define GPIO_M_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_M_SCR_05_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_M_SCR_05_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_05_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_M_SCR_05_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_PR7_SHIFT)
#define GPIO_M_SCR_05_0_PR7_RANGE                       23:23
#define GPIO_M_SCR_05_0_PR7_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_05_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_M_SCR_05_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_PR6_SHIFT)
#define GPIO_M_SCR_05_0_PR6_RANGE                       22:22
#define GPIO_M_SCR_05_0_PR6_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_05_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_M_SCR_05_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_PR5_SHIFT)
#define GPIO_M_SCR_05_0_PR5_RANGE                       21:21
#define GPIO_M_SCR_05_0_PR5_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_05_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_M_SCR_05_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_PR4_SHIFT)
#define GPIO_M_SCR_05_0_PR4_RANGE                       20:20
#define GPIO_M_SCR_05_0_PR4_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_05_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_M_SCR_05_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_PR3_SHIFT)
#define GPIO_M_SCR_05_0_PR3_RANGE                       19:19
#define GPIO_M_SCR_05_0_PR3_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_05_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_M_SCR_05_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_PR2_SHIFT)
#define GPIO_M_SCR_05_0_PR2_RANGE                       18:18
#define GPIO_M_SCR_05_0_PR2_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_05_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_M_SCR_05_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_PR1_SHIFT)
#define GPIO_M_SCR_05_0_PR1_RANGE                       17:17
#define GPIO_M_SCR_05_0_PR1_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_05_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_M_SCR_05_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_PR0_SHIFT)
#define GPIO_M_SCR_05_0_PR0_RANGE                       16:16
#define GPIO_M_SCR_05_0_PR0_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_05_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_M_SCR_05_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G7W_SHIFT)
#define GPIO_M_SCR_05_0_G7W_RANGE                       15:15
#define GPIO_M_SCR_05_0_G7W_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_05_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_M_SCR_05_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G6W_SHIFT)
#define GPIO_M_SCR_05_0_G6W_RANGE                       14:14
#define GPIO_M_SCR_05_0_G6W_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_05_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_M_SCR_05_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G5W_SHIFT)
#define GPIO_M_SCR_05_0_G5W_RANGE                       13:13
#define GPIO_M_SCR_05_0_G5W_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_05_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_M_SCR_05_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G4W_SHIFT)
#define GPIO_M_SCR_05_0_G4W_RANGE                       12:12
#define GPIO_M_SCR_05_0_G4W_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_05_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_M_SCR_05_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G3W_SHIFT)
#define GPIO_M_SCR_05_0_G3W_RANGE                       11:11
#define GPIO_M_SCR_05_0_G3W_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_05_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_M_SCR_05_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G2W_SHIFT)
#define GPIO_M_SCR_05_0_G2W_RANGE                       10:10
#define GPIO_M_SCR_05_0_G2W_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_05_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_M_SCR_05_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G1W_SHIFT)
#define GPIO_M_SCR_05_0_G1W_RANGE                       9:9
#define GPIO_M_SCR_05_0_G1W_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_05_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_M_SCR_05_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G0W_SHIFT)
#define GPIO_M_SCR_05_0_G0W_RANGE                       8:8
#define GPIO_M_SCR_05_0_G0W_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_05_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_M_SCR_05_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G7R_SHIFT)
#define GPIO_M_SCR_05_0_G7R_RANGE                       7:7
#define GPIO_M_SCR_05_0_G7R_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_05_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_M_SCR_05_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G6R_SHIFT)
#define GPIO_M_SCR_05_0_G6R_RANGE                       6:6
#define GPIO_M_SCR_05_0_G6R_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_05_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_M_SCR_05_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G5R_SHIFT)
#define GPIO_M_SCR_05_0_G5R_RANGE                       5:5
#define GPIO_M_SCR_05_0_G5R_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_05_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_M_SCR_05_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G4R_SHIFT)
#define GPIO_M_SCR_05_0_G4R_RANGE                       4:4
#define GPIO_M_SCR_05_0_G4R_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_05_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_M_SCR_05_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G3R_SHIFT)
#define GPIO_M_SCR_05_0_G3R_RANGE                       3:3
#define GPIO_M_SCR_05_0_G3R_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_05_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_M_SCR_05_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G2R_SHIFT)
#define GPIO_M_SCR_05_0_G2R_RANGE                       2:2
#define GPIO_M_SCR_05_0_G2R_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_05_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_M_SCR_05_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G1R_SHIFT)
#define GPIO_M_SCR_05_0_G1R_RANGE                       1:1
#define GPIO_M_SCR_05_0_G1R_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_05_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_M_SCR_05_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G0R_SHIFT)
#define GPIO_M_SCR_05_0_G0R_RANGE                       0:0
#define GPIO_M_SCR_05_0_G0R_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_M_VM_06_0
#define GPIO_M_VM_06_0                  _MK_ADDR_CONST(0x20f0)
#define GPIO_M_VM_06_0_SECURE                   0x0
#define GPIO_M_VM_06_0_DUAL                     0x0
#define GPIO_M_VM_06_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_M_VM_06_0_WORD_COUNT                       0x1
#define GPIO_M_VM_06_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_06_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_06_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_06_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_VM_06_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_06_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_06_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_M_VM_06_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_06_0_VM1_SHIFT)
#define GPIO_M_VM_06_0_VM1_RANGE                        1:0
#define GPIO_M_VM_06_0_VM1_WOFFSET                      0x0
#define GPIO_M_VM_06_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_06_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_06_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_06_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_06_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_06_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_06_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_M_VM_06_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_06_0_VM2_SHIFT)
#define GPIO_M_VM_06_0_VM2_RANGE                        3:2
#define GPIO_M_VM_06_0_VM2_WOFFSET                      0x0
#define GPIO_M_VM_06_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_06_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_06_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_06_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_06_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_06_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_06_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_M_VM_06_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_06_0_VM3_SHIFT)
#define GPIO_M_VM_06_0_VM3_RANGE                        5:4
#define GPIO_M_VM_06_0_VM3_WOFFSET                      0x0
#define GPIO_M_VM_06_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_06_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_06_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_06_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_06_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_06_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_06_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_M_VM_06_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_06_0_VM4_SHIFT)
#define GPIO_M_VM_06_0_VM4_RANGE                        7:6
#define GPIO_M_VM_06_0_VM4_WOFFSET                      0x0
#define GPIO_M_VM_06_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_06_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_06_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_06_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_06_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_06_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_06_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_M_VM_06_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_06_0_VM5_SHIFT)
#define GPIO_M_VM_06_0_VM5_RANGE                        9:8
#define GPIO_M_VM_06_0_VM5_WOFFSET                      0x0
#define GPIO_M_VM_06_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_06_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_06_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_06_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_06_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_06_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_06_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_M_VM_06_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_06_0_VM6_SHIFT)
#define GPIO_M_VM_06_0_VM6_RANGE                        11:10
#define GPIO_M_VM_06_0_VM6_WOFFSET                      0x0
#define GPIO_M_VM_06_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_06_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_06_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_06_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_06_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_06_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_06_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_M_VM_06_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_06_0_VM7_SHIFT)
#define GPIO_M_VM_06_0_VM7_RANGE                        13:12
#define GPIO_M_VM_06_0_VM7_WOFFSET                      0x0
#define GPIO_M_VM_06_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_06_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_06_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_06_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_06_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_06_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_06_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_M_VM_06_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_06_0_VM8_SHIFT)
#define GPIO_M_VM_06_0_VM8_RANGE                        15:14
#define GPIO_M_VM_06_0_VM8_WOFFSET                      0x0
#define GPIO_M_VM_06_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_06_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_06_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_06_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_06_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_06_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_M_SCR_06_0
#define GPIO_M_SCR_06_0                 _MK_ADDR_CONST(0x20f4)
#define GPIO_M_SCR_06_0_SECURE                  0x0
#define GPIO_M_SCR_06_0_DUAL                    0x0
#define GPIO_M_SCR_06_0_SCR                     0
#define GPIO_M_SCR_06_0_WORD_COUNT                      0x1
#define GPIO_M_SCR_06_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_06_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_06_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_06_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_M_SCR_06_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_SEC_LCK_SHIFT)
#define GPIO_M_SCR_06_0_SEC_LCK_RANGE                   29:29
#define GPIO_M_SCR_06_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_M_SCR_06_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_06_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_06_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_M_SCR_06_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_SEC_WEN_SHIFT)
#define GPIO_M_SCR_06_0_SEC_WEN_RANGE                   28:28
#define GPIO_M_SCR_06_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_M_SCR_06_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_06_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_06_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_M_SCR_06_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_SEC_REN_SHIFT)
#define GPIO_M_SCR_06_0_SEC_REN_RANGE                   27:27
#define GPIO_M_SCR_06_0_SEC_REN_WOFFSET                 0x0
#define GPIO_M_SCR_06_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_06_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_06_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_M_SCR_06_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_M_SCR_06_0_SEC_OWNER_SHIFT)
#define GPIO_M_SCR_06_0_SEC_OWNER_RANGE                 26:24
#define GPIO_M_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_M_SCR_06_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_M_SCR_06_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_06_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_M_SCR_06_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_PR7_SHIFT)
#define GPIO_M_SCR_06_0_PR7_RANGE                       23:23
#define GPIO_M_SCR_06_0_PR7_WOFFSET                     0x0
#define GPIO_M_SCR_06_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_06_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_06_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_M_SCR_06_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_PR6_SHIFT)
#define GPIO_M_SCR_06_0_PR6_RANGE                       22:22
#define GPIO_M_SCR_06_0_PR6_WOFFSET                     0x0
#define GPIO_M_SCR_06_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_06_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_06_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_M_SCR_06_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_PR5_SHIFT)
#define GPIO_M_SCR_06_0_PR5_RANGE                       21:21
#define GPIO_M_SCR_06_0_PR5_WOFFSET                     0x0
#define GPIO_M_SCR_06_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_06_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_06_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_M_SCR_06_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_PR4_SHIFT)
#define GPIO_M_SCR_06_0_PR4_RANGE                       20:20
#define GPIO_M_SCR_06_0_PR4_WOFFSET                     0x0
#define GPIO_M_SCR_06_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_06_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_06_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_M_SCR_06_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_PR3_SHIFT)
#define GPIO_M_SCR_06_0_PR3_RANGE                       19:19
#define GPIO_M_SCR_06_0_PR3_WOFFSET                     0x0
#define GPIO_M_SCR_06_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_06_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_06_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_M_SCR_06_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_PR2_SHIFT)
#define GPIO_M_SCR_06_0_PR2_RANGE                       18:18
#define GPIO_M_SCR_06_0_PR2_WOFFSET                     0x0
#define GPIO_M_SCR_06_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_06_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_06_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_M_SCR_06_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_PR1_SHIFT)
#define GPIO_M_SCR_06_0_PR1_RANGE                       17:17
#define GPIO_M_SCR_06_0_PR1_WOFFSET                     0x0
#define GPIO_M_SCR_06_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_06_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_06_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_M_SCR_06_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_PR0_SHIFT)
#define GPIO_M_SCR_06_0_PR0_RANGE                       16:16
#define GPIO_M_SCR_06_0_PR0_WOFFSET                     0x0
#define GPIO_M_SCR_06_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_06_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_06_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_M_SCR_06_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_G7W_SHIFT)
#define GPIO_M_SCR_06_0_G7W_RANGE                       15:15
#define GPIO_M_SCR_06_0_G7W_WOFFSET                     0x0
#define GPIO_M_SCR_06_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_06_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_06_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_M_SCR_06_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_G6W_SHIFT)
#define GPIO_M_SCR_06_0_G6W_RANGE                       14:14
#define GPIO_M_SCR_06_0_G6W_WOFFSET                     0x0
#define GPIO_M_SCR_06_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_06_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_06_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_M_SCR_06_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_G5W_SHIFT)
#define GPIO_M_SCR_06_0_G5W_RANGE                       13:13
#define GPIO_M_SCR_06_0_G5W_WOFFSET                     0x0
#define GPIO_M_SCR_06_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_06_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_06_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_M_SCR_06_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_G4W_SHIFT)
#define GPIO_M_SCR_06_0_G4W_RANGE                       12:12
#define GPIO_M_SCR_06_0_G4W_WOFFSET                     0x0
#define GPIO_M_SCR_06_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_06_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_06_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_M_SCR_06_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_G3W_SHIFT)
#define GPIO_M_SCR_06_0_G3W_RANGE                       11:11
#define GPIO_M_SCR_06_0_G3W_WOFFSET                     0x0
#define GPIO_M_SCR_06_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_06_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_06_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_M_SCR_06_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_G2W_SHIFT)
#define GPIO_M_SCR_06_0_G2W_RANGE                       10:10
#define GPIO_M_SCR_06_0_G2W_WOFFSET                     0x0
#define GPIO_M_SCR_06_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_06_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_06_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_M_SCR_06_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_G1W_SHIFT)
#define GPIO_M_SCR_06_0_G1W_RANGE                       9:9
#define GPIO_M_SCR_06_0_G1W_WOFFSET                     0x0
#define GPIO_M_SCR_06_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_06_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_06_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_M_SCR_06_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_G0W_SHIFT)
#define GPIO_M_SCR_06_0_G0W_RANGE                       8:8
#define GPIO_M_SCR_06_0_G0W_WOFFSET                     0x0
#define GPIO_M_SCR_06_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_06_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_06_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_M_SCR_06_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_G7R_SHIFT)
#define GPIO_M_SCR_06_0_G7R_RANGE                       7:7
#define GPIO_M_SCR_06_0_G7R_WOFFSET                     0x0
#define GPIO_M_SCR_06_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_06_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_06_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_M_SCR_06_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_G6R_SHIFT)
#define GPIO_M_SCR_06_0_G6R_RANGE                       6:6
#define GPIO_M_SCR_06_0_G6R_WOFFSET                     0x0
#define GPIO_M_SCR_06_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_06_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_06_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_M_SCR_06_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_G5R_SHIFT)
#define GPIO_M_SCR_06_0_G5R_RANGE                       5:5
#define GPIO_M_SCR_06_0_G5R_WOFFSET                     0x0
#define GPIO_M_SCR_06_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_06_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_06_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_M_SCR_06_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_G4R_SHIFT)
#define GPIO_M_SCR_06_0_G4R_RANGE                       4:4
#define GPIO_M_SCR_06_0_G4R_WOFFSET                     0x0
#define GPIO_M_SCR_06_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_06_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_06_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_M_SCR_06_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_G3R_SHIFT)
#define GPIO_M_SCR_06_0_G3R_RANGE                       3:3
#define GPIO_M_SCR_06_0_G3R_WOFFSET                     0x0
#define GPIO_M_SCR_06_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_06_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_06_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_M_SCR_06_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_G2R_SHIFT)
#define GPIO_M_SCR_06_0_G2R_RANGE                       2:2
#define GPIO_M_SCR_06_0_G2R_WOFFSET                     0x0
#define GPIO_M_SCR_06_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_06_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_06_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_M_SCR_06_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_G1R_SHIFT)
#define GPIO_M_SCR_06_0_G1R_RANGE                       1:1
#define GPIO_M_SCR_06_0_G1R_WOFFSET                     0x0
#define GPIO_M_SCR_06_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_06_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_06_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_M_SCR_06_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_G0R_SHIFT)
#define GPIO_M_SCR_06_0_G0R_RANGE                       0:0
#define GPIO_M_SCR_06_0_G0R_WOFFSET                     0x0
#define GPIO_M_SCR_06_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_06_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_M_VM_07_0
#define GPIO_M_VM_07_0                  _MK_ADDR_CONST(0x20f8)
#define GPIO_M_VM_07_0_SECURE                   0x0
#define GPIO_M_VM_07_0_DUAL                     0x0
#define GPIO_M_VM_07_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_M_VM_07_0_WORD_COUNT                       0x1
#define GPIO_M_VM_07_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_07_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_07_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_07_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_VM_07_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_07_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_M_VM_07_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_M_VM_07_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_07_0_VM1_SHIFT)
#define GPIO_M_VM_07_0_VM1_RANGE                        1:0
#define GPIO_M_VM_07_0_VM1_WOFFSET                      0x0
#define GPIO_M_VM_07_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_07_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_07_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_07_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_07_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_07_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_07_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_M_VM_07_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_07_0_VM2_SHIFT)
#define GPIO_M_VM_07_0_VM2_RANGE                        3:2
#define GPIO_M_VM_07_0_VM2_WOFFSET                      0x0
#define GPIO_M_VM_07_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_07_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_07_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_07_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_07_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_07_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_07_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_M_VM_07_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_07_0_VM3_SHIFT)
#define GPIO_M_VM_07_0_VM3_RANGE                        5:4
#define GPIO_M_VM_07_0_VM3_WOFFSET                      0x0
#define GPIO_M_VM_07_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_07_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_07_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_07_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_07_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_07_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_07_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_M_VM_07_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_07_0_VM4_SHIFT)
#define GPIO_M_VM_07_0_VM4_RANGE                        7:6
#define GPIO_M_VM_07_0_VM4_WOFFSET                      0x0
#define GPIO_M_VM_07_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_07_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_07_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_07_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_07_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_07_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_07_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_M_VM_07_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_07_0_VM5_SHIFT)
#define GPIO_M_VM_07_0_VM5_RANGE                        9:8
#define GPIO_M_VM_07_0_VM5_WOFFSET                      0x0
#define GPIO_M_VM_07_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_07_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_07_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_07_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_07_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_07_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_07_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_M_VM_07_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_07_0_VM6_SHIFT)
#define GPIO_M_VM_07_0_VM6_RANGE                        11:10
#define GPIO_M_VM_07_0_VM6_WOFFSET                      0x0
#define GPIO_M_VM_07_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_07_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_07_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_07_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_07_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_07_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_07_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_M_VM_07_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_07_0_VM7_SHIFT)
#define GPIO_M_VM_07_0_VM7_RANGE                        13:12
#define GPIO_M_VM_07_0_VM7_WOFFSET                      0x0
#define GPIO_M_VM_07_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_07_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_07_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_07_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_07_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_07_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_M_VM_07_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_M_VM_07_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_M_VM_07_0_VM8_SHIFT)
#define GPIO_M_VM_07_0_VM8_RANGE                        15:14
#define GPIO_M_VM_07_0_VM8_WOFFSET                      0x0
#define GPIO_M_VM_07_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_M_VM_07_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_M_VM_07_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_VM_07_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_VM_07_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_VM_07_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_M_SCR_07_0
#define GPIO_M_SCR_07_0                 _MK_ADDR_CONST(0x20fc)
#define GPIO_M_SCR_07_0_SECURE                  0x0
#define GPIO_M_SCR_07_0_DUAL                    0x0
#define GPIO_M_SCR_07_0_SCR                     0
#define GPIO_M_SCR_07_0_WORD_COUNT                      0x1
#define GPIO_M_SCR_07_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_07_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_07_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_07_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_M_SCR_07_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_SEC_LCK_SHIFT)
#define GPIO_M_SCR_07_0_SEC_LCK_RANGE                   29:29
#define GPIO_M_SCR_07_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_M_SCR_07_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_07_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_07_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_M_SCR_07_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_SEC_WEN_SHIFT)
#define GPIO_M_SCR_07_0_SEC_WEN_RANGE                   28:28
#define GPIO_M_SCR_07_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_M_SCR_07_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_07_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_07_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_M_SCR_07_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_SEC_REN_SHIFT)
#define GPIO_M_SCR_07_0_SEC_REN_RANGE                   27:27
#define GPIO_M_SCR_07_0_SEC_REN_WOFFSET                 0x0
#define GPIO_M_SCR_07_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_07_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_07_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_M_SCR_07_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_M_SCR_07_0_SEC_OWNER_SHIFT)
#define GPIO_M_SCR_07_0_SEC_OWNER_RANGE                 26:24
#define GPIO_M_SCR_07_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_M_SCR_07_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_M_SCR_07_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_07_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_M_SCR_07_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_PR7_SHIFT)
#define GPIO_M_SCR_07_0_PR7_RANGE                       23:23
#define GPIO_M_SCR_07_0_PR7_WOFFSET                     0x0
#define GPIO_M_SCR_07_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_07_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_07_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_M_SCR_07_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_PR6_SHIFT)
#define GPIO_M_SCR_07_0_PR6_RANGE                       22:22
#define GPIO_M_SCR_07_0_PR6_WOFFSET                     0x0
#define GPIO_M_SCR_07_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_07_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_07_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_M_SCR_07_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_PR5_SHIFT)
#define GPIO_M_SCR_07_0_PR5_RANGE                       21:21
#define GPIO_M_SCR_07_0_PR5_WOFFSET                     0x0
#define GPIO_M_SCR_07_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_07_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_07_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_M_SCR_07_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_PR4_SHIFT)
#define GPIO_M_SCR_07_0_PR4_RANGE                       20:20
#define GPIO_M_SCR_07_0_PR4_WOFFSET                     0x0
#define GPIO_M_SCR_07_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_07_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_07_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_M_SCR_07_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_PR3_SHIFT)
#define GPIO_M_SCR_07_0_PR3_RANGE                       19:19
#define GPIO_M_SCR_07_0_PR3_WOFFSET                     0x0
#define GPIO_M_SCR_07_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_07_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_07_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_M_SCR_07_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_PR2_SHIFT)
#define GPIO_M_SCR_07_0_PR2_RANGE                       18:18
#define GPIO_M_SCR_07_0_PR2_WOFFSET                     0x0
#define GPIO_M_SCR_07_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_07_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_07_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_M_SCR_07_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_PR1_SHIFT)
#define GPIO_M_SCR_07_0_PR1_RANGE                       17:17
#define GPIO_M_SCR_07_0_PR1_WOFFSET                     0x0
#define GPIO_M_SCR_07_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_07_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_07_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_M_SCR_07_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_PR0_SHIFT)
#define GPIO_M_SCR_07_0_PR0_RANGE                       16:16
#define GPIO_M_SCR_07_0_PR0_WOFFSET                     0x0
#define GPIO_M_SCR_07_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_07_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_07_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_M_SCR_07_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_G7W_SHIFT)
#define GPIO_M_SCR_07_0_G7W_RANGE                       15:15
#define GPIO_M_SCR_07_0_G7W_WOFFSET                     0x0
#define GPIO_M_SCR_07_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_07_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_07_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_M_SCR_07_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_G6W_SHIFT)
#define GPIO_M_SCR_07_0_G6W_RANGE                       14:14
#define GPIO_M_SCR_07_0_G6W_WOFFSET                     0x0
#define GPIO_M_SCR_07_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_07_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_07_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_M_SCR_07_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_G5W_SHIFT)
#define GPIO_M_SCR_07_0_G5W_RANGE                       13:13
#define GPIO_M_SCR_07_0_G5W_WOFFSET                     0x0
#define GPIO_M_SCR_07_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_07_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_07_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_M_SCR_07_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_G4W_SHIFT)
#define GPIO_M_SCR_07_0_G4W_RANGE                       12:12
#define GPIO_M_SCR_07_0_G4W_WOFFSET                     0x0
#define GPIO_M_SCR_07_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_07_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_07_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_M_SCR_07_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_G3W_SHIFT)
#define GPIO_M_SCR_07_0_G3W_RANGE                       11:11
#define GPIO_M_SCR_07_0_G3W_WOFFSET                     0x0
#define GPIO_M_SCR_07_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_07_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_07_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_M_SCR_07_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_G2W_SHIFT)
#define GPIO_M_SCR_07_0_G2W_RANGE                       10:10
#define GPIO_M_SCR_07_0_G2W_WOFFSET                     0x0
#define GPIO_M_SCR_07_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_07_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_07_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_M_SCR_07_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_G1W_SHIFT)
#define GPIO_M_SCR_07_0_G1W_RANGE                       9:9
#define GPIO_M_SCR_07_0_G1W_WOFFSET                     0x0
#define GPIO_M_SCR_07_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_07_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_07_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_M_SCR_07_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_G0W_SHIFT)
#define GPIO_M_SCR_07_0_G0W_RANGE                       8:8
#define GPIO_M_SCR_07_0_G0W_WOFFSET                     0x0
#define GPIO_M_SCR_07_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_07_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_07_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_M_SCR_07_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_G7R_SHIFT)
#define GPIO_M_SCR_07_0_G7R_RANGE                       7:7
#define GPIO_M_SCR_07_0_G7R_WOFFSET                     0x0
#define GPIO_M_SCR_07_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_07_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_07_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_M_SCR_07_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_G6R_SHIFT)
#define GPIO_M_SCR_07_0_G6R_RANGE                       6:6
#define GPIO_M_SCR_07_0_G6R_WOFFSET                     0x0
#define GPIO_M_SCR_07_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_07_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_07_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_M_SCR_07_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_G5R_SHIFT)
#define GPIO_M_SCR_07_0_G5R_RANGE                       5:5
#define GPIO_M_SCR_07_0_G5R_WOFFSET                     0x0
#define GPIO_M_SCR_07_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_07_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_07_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_M_SCR_07_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_G4R_SHIFT)
#define GPIO_M_SCR_07_0_G4R_RANGE                       4:4
#define GPIO_M_SCR_07_0_G4R_WOFFSET                     0x0
#define GPIO_M_SCR_07_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_07_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_07_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_M_SCR_07_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_G3R_SHIFT)
#define GPIO_M_SCR_07_0_G3R_RANGE                       3:3
#define GPIO_M_SCR_07_0_G3R_WOFFSET                     0x0
#define GPIO_M_SCR_07_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_07_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_07_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_M_SCR_07_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_G2R_SHIFT)
#define GPIO_M_SCR_07_0_G2R_RANGE                       2:2
#define GPIO_M_SCR_07_0_G2R_WOFFSET                     0x0
#define GPIO_M_SCR_07_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_07_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_07_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_M_SCR_07_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_G1R_SHIFT)
#define GPIO_M_SCR_07_0_G1R_RANGE                       1:1
#define GPIO_M_SCR_07_0_G1R_WOFFSET                     0x0
#define GPIO_M_SCR_07_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_07_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_M_SCR_07_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_M_SCR_07_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_G0R_SHIFT)
#define GPIO_M_SCR_07_0_G0R_RANGE                       0:0
#define GPIO_M_SCR_07_0_G0R_WOFFSET                     0x0
#define GPIO_M_SCR_07_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_SCR_07_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_N_VM_00_0
#define GPIO_N_VM_00_0                  _MK_ADDR_CONST(0x2100)
#define GPIO_N_VM_00_0_SECURE                   0x0
#define GPIO_N_VM_00_0_DUAL                     0x0
#define GPIO_N_VM_00_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_N_VM_00_0_WORD_COUNT                       0x1
#define GPIO_N_VM_00_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_N_VM_00_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_N_VM_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_N_VM_00_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_N_VM_00_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_N_VM_00_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_00_0_VM1_SHIFT)
#define GPIO_N_VM_00_0_VM1_RANGE                        1:0
#define GPIO_N_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_N_VM_00_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_00_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_00_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_N_VM_00_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_N_VM_00_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_00_0_VM2_SHIFT)
#define GPIO_N_VM_00_0_VM2_RANGE                        3:2
#define GPIO_N_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_N_VM_00_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_00_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_00_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_N_VM_00_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_N_VM_00_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_00_0_VM3_SHIFT)
#define GPIO_N_VM_00_0_VM3_RANGE                        5:4
#define GPIO_N_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_N_VM_00_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_00_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_00_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_N_VM_00_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_N_VM_00_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_00_0_VM4_SHIFT)
#define GPIO_N_VM_00_0_VM4_RANGE                        7:6
#define GPIO_N_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_N_VM_00_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_00_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_00_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_N_VM_00_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_N_VM_00_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_00_0_VM5_SHIFT)
#define GPIO_N_VM_00_0_VM5_RANGE                        9:8
#define GPIO_N_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_N_VM_00_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_00_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_00_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_N_VM_00_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_N_VM_00_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_00_0_VM6_SHIFT)
#define GPIO_N_VM_00_0_VM6_RANGE                        11:10
#define GPIO_N_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_N_VM_00_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_00_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_00_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_N_VM_00_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_N_VM_00_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_00_0_VM7_SHIFT)
#define GPIO_N_VM_00_0_VM7_RANGE                        13:12
#define GPIO_N_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_N_VM_00_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_00_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_00_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_N_VM_00_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_N_VM_00_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_00_0_VM8_SHIFT)
#define GPIO_N_VM_00_0_VM8_RANGE                        15:14
#define GPIO_N_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_N_VM_00_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_00_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_00_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_N_SCR_00_0
#define GPIO_N_SCR_00_0                 _MK_ADDR_CONST(0x2104)
#define GPIO_N_SCR_00_0_SECURE                  0x0
#define GPIO_N_SCR_00_0_DUAL                    0x0
#define GPIO_N_SCR_00_0_SCR                     0
#define GPIO_N_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_N_SCR_00_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_N_SCR_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_N_SCR_00_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_N_SCR_00_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_N_SCR_00_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_N_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_N_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_N_SCR_00_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_00_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_N_SCR_00_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_N_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_N_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_N_SCR_00_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_00_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_N_SCR_00_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_N_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_N_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_N_SCR_00_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_00_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_N_SCR_00_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_N_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_N_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_N_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_N_SCR_00_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_N_SCR_00_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_00_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_N_SCR_00_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_PR7_SHIFT)
#define GPIO_N_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_N_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_00_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_N_SCR_00_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_PR6_SHIFT)
#define GPIO_N_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_N_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_00_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_N_SCR_00_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_PR5_SHIFT)
#define GPIO_N_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_N_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_00_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_N_SCR_00_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_PR4_SHIFT)
#define GPIO_N_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_N_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_00_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_N_SCR_00_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_PR3_SHIFT)
#define GPIO_N_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_N_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_00_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_N_SCR_00_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_PR2_SHIFT)
#define GPIO_N_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_N_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_00_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_N_SCR_00_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_PR1_SHIFT)
#define GPIO_N_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_N_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_00_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_N_SCR_00_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_PR0_SHIFT)
#define GPIO_N_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_N_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_00_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_N_SCR_00_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G7W_SHIFT)
#define GPIO_N_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_N_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_00_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_N_SCR_00_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G6W_SHIFT)
#define GPIO_N_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_N_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_00_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_N_SCR_00_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G5W_SHIFT)
#define GPIO_N_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_N_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_00_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_N_SCR_00_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G4W_SHIFT)
#define GPIO_N_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_N_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_00_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_N_SCR_00_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G3W_SHIFT)
#define GPIO_N_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_N_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_00_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_N_SCR_00_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G2W_SHIFT)
#define GPIO_N_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_N_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_00_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_N_SCR_00_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G1W_SHIFT)
#define GPIO_N_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_N_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_00_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_N_SCR_00_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G0W_SHIFT)
#define GPIO_N_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_N_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_00_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_N_SCR_00_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G7R_SHIFT)
#define GPIO_N_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_N_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_00_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_N_SCR_00_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G6R_SHIFT)
#define GPIO_N_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_N_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_00_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_N_SCR_00_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G5R_SHIFT)
#define GPIO_N_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_N_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_00_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_N_SCR_00_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G4R_SHIFT)
#define GPIO_N_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_N_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_00_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_N_SCR_00_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G3R_SHIFT)
#define GPIO_N_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_N_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_00_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_N_SCR_00_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G2R_SHIFT)
#define GPIO_N_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_N_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_00_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_N_SCR_00_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G1R_SHIFT)
#define GPIO_N_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_N_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_00_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_N_SCR_00_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G0R_SHIFT)
#define GPIO_N_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_N_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_N_VM_01_0
#define GPIO_N_VM_01_0                  _MK_ADDR_CONST(0x2108)
#define GPIO_N_VM_01_0_SECURE                   0x0
#define GPIO_N_VM_01_0_DUAL                     0x0
#define GPIO_N_VM_01_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_N_VM_01_0_WORD_COUNT                       0x1
#define GPIO_N_VM_01_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_N_VM_01_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_N_VM_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_N_VM_01_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_N_VM_01_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_N_VM_01_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_01_0_VM1_SHIFT)
#define GPIO_N_VM_01_0_VM1_RANGE                        1:0
#define GPIO_N_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_N_VM_01_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_01_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_01_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_N_VM_01_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_N_VM_01_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_01_0_VM2_SHIFT)
#define GPIO_N_VM_01_0_VM2_RANGE                        3:2
#define GPIO_N_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_N_VM_01_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_01_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_01_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_N_VM_01_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_N_VM_01_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_01_0_VM3_SHIFT)
#define GPIO_N_VM_01_0_VM3_RANGE                        5:4
#define GPIO_N_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_N_VM_01_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_01_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_01_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_N_VM_01_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_N_VM_01_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_01_0_VM4_SHIFT)
#define GPIO_N_VM_01_0_VM4_RANGE                        7:6
#define GPIO_N_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_N_VM_01_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_01_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_01_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_N_VM_01_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_N_VM_01_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_01_0_VM5_SHIFT)
#define GPIO_N_VM_01_0_VM5_RANGE                        9:8
#define GPIO_N_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_N_VM_01_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_01_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_01_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_N_VM_01_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_N_VM_01_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_01_0_VM6_SHIFT)
#define GPIO_N_VM_01_0_VM6_RANGE                        11:10
#define GPIO_N_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_N_VM_01_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_01_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_01_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_N_VM_01_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_N_VM_01_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_01_0_VM7_SHIFT)
#define GPIO_N_VM_01_0_VM7_RANGE                        13:12
#define GPIO_N_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_N_VM_01_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_01_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_01_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_N_VM_01_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_N_VM_01_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_01_0_VM8_SHIFT)
#define GPIO_N_VM_01_0_VM8_RANGE                        15:14
#define GPIO_N_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_N_VM_01_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_01_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_01_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_N_SCR_01_0
#define GPIO_N_SCR_01_0                 _MK_ADDR_CONST(0x210c)
#define GPIO_N_SCR_01_0_SECURE                  0x0
#define GPIO_N_SCR_01_0_DUAL                    0x0
#define GPIO_N_SCR_01_0_SCR                     0
#define GPIO_N_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_N_SCR_01_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_N_SCR_01_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_N_SCR_01_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_N_SCR_01_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_N_SCR_01_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_N_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_N_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_N_SCR_01_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_01_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_N_SCR_01_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_N_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_N_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_N_SCR_01_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_01_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_N_SCR_01_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_N_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_N_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_N_SCR_01_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_01_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_N_SCR_01_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_N_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_N_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_N_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_N_SCR_01_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_N_SCR_01_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_01_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_N_SCR_01_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_PR7_SHIFT)
#define GPIO_N_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_N_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_01_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_N_SCR_01_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_PR6_SHIFT)
#define GPIO_N_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_N_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_01_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_N_SCR_01_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_PR5_SHIFT)
#define GPIO_N_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_N_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_01_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_N_SCR_01_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_PR4_SHIFT)
#define GPIO_N_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_N_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_01_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_N_SCR_01_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_PR3_SHIFT)
#define GPIO_N_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_N_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_01_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_N_SCR_01_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_PR2_SHIFT)
#define GPIO_N_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_N_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_01_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_N_SCR_01_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_PR1_SHIFT)
#define GPIO_N_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_N_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_01_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_N_SCR_01_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_PR0_SHIFT)
#define GPIO_N_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_N_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_01_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_N_SCR_01_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G7W_SHIFT)
#define GPIO_N_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_N_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_01_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_N_SCR_01_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G6W_SHIFT)
#define GPIO_N_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_N_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_01_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_N_SCR_01_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G5W_SHIFT)
#define GPIO_N_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_N_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_01_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_N_SCR_01_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G4W_SHIFT)
#define GPIO_N_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_N_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_01_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_N_SCR_01_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G3W_SHIFT)
#define GPIO_N_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_N_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_01_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_N_SCR_01_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G2W_SHIFT)
#define GPIO_N_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_N_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_01_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_N_SCR_01_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G1W_SHIFT)
#define GPIO_N_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_N_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_01_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_N_SCR_01_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G0W_SHIFT)
#define GPIO_N_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_N_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_01_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_N_SCR_01_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G7R_SHIFT)
#define GPIO_N_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_N_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_01_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_N_SCR_01_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G6R_SHIFT)
#define GPIO_N_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_N_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_01_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_N_SCR_01_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G5R_SHIFT)
#define GPIO_N_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_N_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_01_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_N_SCR_01_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G4R_SHIFT)
#define GPIO_N_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_N_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_01_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_N_SCR_01_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G3R_SHIFT)
#define GPIO_N_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_N_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_01_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_N_SCR_01_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G2R_SHIFT)
#define GPIO_N_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_N_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_01_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_N_SCR_01_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G1R_SHIFT)
#define GPIO_N_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_N_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_01_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_N_SCR_01_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G0R_SHIFT)
#define GPIO_N_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_N_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_N_VM_02_0
#define GPIO_N_VM_02_0                  _MK_ADDR_CONST(0x2110)
#define GPIO_N_VM_02_0_SECURE                   0x0
#define GPIO_N_VM_02_0_DUAL                     0x0
#define GPIO_N_VM_02_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_N_VM_02_0_WORD_COUNT                       0x1
#define GPIO_N_VM_02_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_N_VM_02_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_N_VM_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_N_VM_02_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_N_VM_02_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_N_VM_02_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_02_0_VM1_SHIFT)
#define GPIO_N_VM_02_0_VM1_RANGE                        1:0
#define GPIO_N_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_N_VM_02_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_02_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_02_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_N_VM_02_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_N_VM_02_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_02_0_VM2_SHIFT)
#define GPIO_N_VM_02_0_VM2_RANGE                        3:2
#define GPIO_N_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_N_VM_02_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_02_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_02_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_N_VM_02_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_N_VM_02_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_02_0_VM3_SHIFT)
#define GPIO_N_VM_02_0_VM3_RANGE                        5:4
#define GPIO_N_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_N_VM_02_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_02_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_02_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_N_VM_02_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_N_VM_02_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_02_0_VM4_SHIFT)
#define GPIO_N_VM_02_0_VM4_RANGE                        7:6
#define GPIO_N_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_N_VM_02_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_02_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_02_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_N_VM_02_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_N_VM_02_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_02_0_VM5_SHIFT)
#define GPIO_N_VM_02_0_VM5_RANGE                        9:8
#define GPIO_N_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_N_VM_02_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_02_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_02_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_N_VM_02_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_N_VM_02_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_02_0_VM6_SHIFT)
#define GPIO_N_VM_02_0_VM6_RANGE                        11:10
#define GPIO_N_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_N_VM_02_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_02_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_02_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_N_VM_02_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_N_VM_02_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_02_0_VM7_SHIFT)
#define GPIO_N_VM_02_0_VM7_RANGE                        13:12
#define GPIO_N_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_N_VM_02_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_02_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_02_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_N_VM_02_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_N_VM_02_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_N_VM_02_0_VM8_SHIFT)
#define GPIO_N_VM_02_0_VM8_RANGE                        15:14
#define GPIO_N_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_N_VM_02_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_N_VM_02_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_N_VM_02_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_N_SCR_02_0
#define GPIO_N_SCR_02_0                 _MK_ADDR_CONST(0x2114)
#define GPIO_N_SCR_02_0_SECURE                  0x0
#define GPIO_N_SCR_02_0_DUAL                    0x0
#define GPIO_N_SCR_02_0_SCR                     0
#define GPIO_N_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_N_SCR_02_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_N_SCR_02_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_N_SCR_02_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_N_SCR_02_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_N_SCR_02_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_N_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_N_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_N_SCR_02_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_02_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_N_SCR_02_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_N_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_N_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_N_SCR_02_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_02_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_N_SCR_02_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_N_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_N_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_N_SCR_02_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_02_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_N_SCR_02_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_N_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_N_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_N_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_N_SCR_02_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_N_SCR_02_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_02_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_N_SCR_02_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_PR7_SHIFT)
#define GPIO_N_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_N_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_02_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_N_SCR_02_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_PR6_SHIFT)
#define GPIO_N_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_N_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_02_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_N_SCR_02_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_PR5_SHIFT)
#define GPIO_N_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_N_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_02_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_N_SCR_02_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_PR4_SHIFT)
#define GPIO_N_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_N_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_02_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_N_SCR_02_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_PR3_SHIFT)
#define GPIO_N_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_N_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_02_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_N_SCR_02_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_PR2_SHIFT)
#define GPIO_N_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_N_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_02_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_N_SCR_02_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_PR1_SHIFT)
#define GPIO_N_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_N_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_02_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_N_SCR_02_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_PR0_SHIFT)
#define GPIO_N_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_N_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_02_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_N_SCR_02_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G7W_SHIFT)
#define GPIO_N_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_N_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_02_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_N_SCR_02_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G6W_SHIFT)
#define GPIO_N_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_N_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_02_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_N_SCR_02_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G5W_SHIFT)
#define GPIO_N_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_N_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_02_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_N_SCR_02_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G4W_SHIFT)
#define GPIO_N_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_N_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_02_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_N_SCR_02_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G3W_SHIFT)
#define GPIO_N_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_N_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_02_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_N_SCR_02_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G2W_SHIFT)
#define GPIO_N_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_N_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_02_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_N_SCR_02_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G1W_SHIFT)
#define GPIO_N_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_N_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_02_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_N_SCR_02_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G0W_SHIFT)
#define GPIO_N_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_N_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_02_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_N_SCR_02_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G7R_SHIFT)
#define GPIO_N_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_N_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_02_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_N_SCR_02_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G6R_SHIFT)
#define GPIO_N_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_N_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_02_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_N_SCR_02_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G5R_SHIFT)
#define GPIO_N_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_N_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_02_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_N_SCR_02_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G4R_SHIFT)
#define GPIO_N_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_N_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_02_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_N_SCR_02_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G3R_SHIFT)
#define GPIO_N_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_N_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_02_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_N_SCR_02_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G2R_SHIFT)
#define GPIO_N_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_N_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_02_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_N_SCR_02_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G1R_SHIFT)
#define GPIO_N_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_N_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_N_SCR_02_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_N_SCR_02_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G0R_SHIFT)
#define GPIO_N_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_N_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Reserved address 0x2118

// Reserved address 0x211c

// Reserved address 0x2120

// Reserved address 0x2124

// Reserved address 0x2128

// Reserved address 0x212c

// Reserved address 0x2130

// Reserved address 0x2134

// Reserved address 0x2138

// Reserved address 0x213c

// Register GPIO_P_VM_00_0
#define GPIO_P_VM_00_0                  _MK_ADDR_CONST(0x2140)
#define GPIO_P_VM_00_0_SECURE                   0x0
#define GPIO_P_VM_00_0_DUAL                     0x0
#define GPIO_P_VM_00_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_P_VM_00_0_WORD_COUNT                       0x1
#define GPIO_P_VM_00_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_00_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_00_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_00_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_P_VM_00_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_00_0_VM1_SHIFT)
#define GPIO_P_VM_00_0_VM1_RANGE                        1:0
#define GPIO_P_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_P_VM_00_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_00_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_00_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_00_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_P_VM_00_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_00_0_VM2_SHIFT)
#define GPIO_P_VM_00_0_VM2_RANGE                        3:2
#define GPIO_P_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_P_VM_00_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_00_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_00_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_00_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_P_VM_00_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_00_0_VM3_SHIFT)
#define GPIO_P_VM_00_0_VM3_RANGE                        5:4
#define GPIO_P_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_P_VM_00_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_00_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_00_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_00_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_P_VM_00_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_00_0_VM4_SHIFT)
#define GPIO_P_VM_00_0_VM4_RANGE                        7:6
#define GPIO_P_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_P_VM_00_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_00_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_00_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_00_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_P_VM_00_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_00_0_VM5_SHIFT)
#define GPIO_P_VM_00_0_VM5_RANGE                        9:8
#define GPIO_P_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_P_VM_00_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_00_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_00_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_00_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_P_VM_00_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_00_0_VM6_SHIFT)
#define GPIO_P_VM_00_0_VM6_RANGE                        11:10
#define GPIO_P_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_P_VM_00_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_00_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_00_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_00_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_P_VM_00_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_00_0_VM7_SHIFT)
#define GPIO_P_VM_00_0_VM7_RANGE                        13:12
#define GPIO_P_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_P_VM_00_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_00_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_00_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_00_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_P_VM_00_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_00_0_VM8_SHIFT)
#define GPIO_P_VM_00_0_VM8_RANGE                        15:14
#define GPIO_P_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_P_VM_00_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_00_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_00_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_P_SCR_00_0
#define GPIO_P_SCR_00_0                 _MK_ADDR_CONST(0x2144)
#define GPIO_P_SCR_00_0_SECURE                  0x0
#define GPIO_P_SCR_00_0_DUAL                    0x0
#define GPIO_P_SCR_00_0_SCR                     0
#define GPIO_P_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_P_SCR_00_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_00_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_00_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_P_SCR_00_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_P_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_P_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_P_SCR_00_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_00_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_P_SCR_00_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_P_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_P_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_P_SCR_00_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_00_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_P_SCR_00_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_P_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_P_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_P_SCR_00_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_00_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_P_SCR_00_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_P_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_P_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_P_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_P_SCR_00_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_P_SCR_00_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_00_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_P_SCR_00_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_PR7_SHIFT)
#define GPIO_P_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_P_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_00_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_P_SCR_00_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_PR6_SHIFT)
#define GPIO_P_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_P_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_00_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_P_SCR_00_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_PR5_SHIFT)
#define GPIO_P_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_P_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_00_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_P_SCR_00_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_PR4_SHIFT)
#define GPIO_P_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_P_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_00_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_P_SCR_00_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_PR3_SHIFT)
#define GPIO_P_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_P_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_00_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_P_SCR_00_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_PR2_SHIFT)
#define GPIO_P_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_P_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_00_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_P_SCR_00_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_PR1_SHIFT)
#define GPIO_P_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_P_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_00_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_P_SCR_00_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_PR0_SHIFT)
#define GPIO_P_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_P_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_00_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_P_SCR_00_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G7W_SHIFT)
#define GPIO_P_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_P_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_00_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_P_SCR_00_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G6W_SHIFT)
#define GPIO_P_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_P_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_00_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_P_SCR_00_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G5W_SHIFT)
#define GPIO_P_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_P_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_00_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_P_SCR_00_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G4W_SHIFT)
#define GPIO_P_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_P_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_00_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_P_SCR_00_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G3W_SHIFT)
#define GPIO_P_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_P_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_00_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_P_SCR_00_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G2W_SHIFT)
#define GPIO_P_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_P_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_00_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_P_SCR_00_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G1W_SHIFT)
#define GPIO_P_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_P_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_00_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_P_SCR_00_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G0W_SHIFT)
#define GPIO_P_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_P_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_00_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_P_SCR_00_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G7R_SHIFT)
#define GPIO_P_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_P_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_00_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_P_SCR_00_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G6R_SHIFT)
#define GPIO_P_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_P_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_00_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_P_SCR_00_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G5R_SHIFT)
#define GPIO_P_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_P_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_00_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_P_SCR_00_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G4R_SHIFT)
#define GPIO_P_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_P_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_00_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_P_SCR_00_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G3R_SHIFT)
#define GPIO_P_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_P_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_00_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_P_SCR_00_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G2R_SHIFT)
#define GPIO_P_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_P_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_00_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_P_SCR_00_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G1R_SHIFT)
#define GPIO_P_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_P_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_00_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_P_SCR_00_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G0R_SHIFT)
#define GPIO_P_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_P_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_P_VM_01_0
#define GPIO_P_VM_01_0                  _MK_ADDR_CONST(0x2148)
#define GPIO_P_VM_01_0_SECURE                   0x0
#define GPIO_P_VM_01_0_DUAL                     0x0
#define GPIO_P_VM_01_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_P_VM_01_0_WORD_COUNT                       0x1
#define GPIO_P_VM_01_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_01_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_01_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_01_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_P_VM_01_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_01_0_VM1_SHIFT)
#define GPIO_P_VM_01_0_VM1_RANGE                        1:0
#define GPIO_P_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_P_VM_01_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_01_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_01_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_01_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_P_VM_01_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_01_0_VM2_SHIFT)
#define GPIO_P_VM_01_0_VM2_RANGE                        3:2
#define GPIO_P_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_P_VM_01_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_01_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_01_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_01_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_P_VM_01_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_01_0_VM3_SHIFT)
#define GPIO_P_VM_01_0_VM3_RANGE                        5:4
#define GPIO_P_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_P_VM_01_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_01_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_01_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_01_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_P_VM_01_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_01_0_VM4_SHIFT)
#define GPIO_P_VM_01_0_VM4_RANGE                        7:6
#define GPIO_P_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_P_VM_01_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_01_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_01_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_01_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_P_VM_01_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_01_0_VM5_SHIFT)
#define GPIO_P_VM_01_0_VM5_RANGE                        9:8
#define GPIO_P_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_P_VM_01_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_01_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_01_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_01_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_P_VM_01_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_01_0_VM6_SHIFT)
#define GPIO_P_VM_01_0_VM6_RANGE                        11:10
#define GPIO_P_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_P_VM_01_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_01_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_01_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_01_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_P_VM_01_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_01_0_VM7_SHIFT)
#define GPIO_P_VM_01_0_VM7_RANGE                        13:12
#define GPIO_P_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_P_VM_01_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_01_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_01_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_01_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_P_VM_01_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_01_0_VM8_SHIFT)
#define GPIO_P_VM_01_0_VM8_RANGE                        15:14
#define GPIO_P_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_P_VM_01_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_01_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_01_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_P_SCR_01_0
#define GPIO_P_SCR_01_0                 _MK_ADDR_CONST(0x214c)
#define GPIO_P_SCR_01_0_SECURE                  0x0
#define GPIO_P_SCR_01_0_DUAL                    0x0
#define GPIO_P_SCR_01_0_SCR                     0
#define GPIO_P_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_P_SCR_01_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_01_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_01_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_01_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_P_SCR_01_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_P_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_P_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_P_SCR_01_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_01_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_P_SCR_01_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_P_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_P_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_P_SCR_01_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_01_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_P_SCR_01_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_P_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_P_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_P_SCR_01_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_01_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_P_SCR_01_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_P_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_P_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_P_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_P_SCR_01_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_P_SCR_01_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_01_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_P_SCR_01_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_PR7_SHIFT)
#define GPIO_P_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_P_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_01_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_P_SCR_01_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_PR6_SHIFT)
#define GPIO_P_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_P_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_01_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_P_SCR_01_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_PR5_SHIFT)
#define GPIO_P_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_P_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_01_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_P_SCR_01_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_PR4_SHIFT)
#define GPIO_P_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_P_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_01_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_P_SCR_01_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_PR3_SHIFT)
#define GPIO_P_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_P_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_01_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_P_SCR_01_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_PR2_SHIFT)
#define GPIO_P_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_P_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_01_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_P_SCR_01_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_PR1_SHIFT)
#define GPIO_P_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_P_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_01_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_P_SCR_01_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_PR0_SHIFT)
#define GPIO_P_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_P_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_01_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_P_SCR_01_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G7W_SHIFT)
#define GPIO_P_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_P_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_01_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_P_SCR_01_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G6W_SHIFT)
#define GPIO_P_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_P_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_01_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_P_SCR_01_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G5W_SHIFT)
#define GPIO_P_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_P_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_01_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_P_SCR_01_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G4W_SHIFT)
#define GPIO_P_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_P_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_01_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_P_SCR_01_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G3W_SHIFT)
#define GPIO_P_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_P_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_01_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_P_SCR_01_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G2W_SHIFT)
#define GPIO_P_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_P_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_01_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_P_SCR_01_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G1W_SHIFT)
#define GPIO_P_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_P_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_01_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_P_SCR_01_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G0W_SHIFT)
#define GPIO_P_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_P_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_01_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_P_SCR_01_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G7R_SHIFT)
#define GPIO_P_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_P_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_01_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_P_SCR_01_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G6R_SHIFT)
#define GPIO_P_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_P_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_01_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_P_SCR_01_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G5R_SHIFT)
#define GPIO_P_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_P_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_01_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_P_SCR_01_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G4R_SHIFT)
#define GPIO_P_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_P_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_01_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_P_SCR_01_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G3R_SHIFT)
#define GPIO_P_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_P_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_01_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_P_SCR_01_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G2R_SHIFT)
#define GPIO_P_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_P_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_01_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_P_SCR_01_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G1R_SHIFT)
#define GPIO_P_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_P_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_01_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_P_SCR_01_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G0R_SHIFT)
#define GPIO_P_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_P_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_P_VM_02_0
#define GPIO_P_VM_02_0                  _MK_ADDR_CONST(0x2150)
#define GPIO_P_VM_02_0_SECURE                   0x0
#define GPIO_P_VM_02_0_DUAL                     0x0
#define GPIO_P_VM_02_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_P_VM_02_0_WORD_COUNT                       0x1
#define GPIO_P_VM_02_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_02_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_02_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_02_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_P_VM_02_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_02_0_VM1_SHIFT)
#define GPIO_P_VM_02_0_VM1_RANGE                        1:0
#define GPIO_P_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_P_VM_02_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_02_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_02_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_02_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_P_VM_02_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_02_0_VM2_SHIFT)
#define GPIO_P_VM_02_0_VM2_RANGE                        3:2
#define GPIO_P_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_P_VM_02_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_02_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_02_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_02_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_P_VM_02_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_02_0_VM3_SHIFT)
#define GPIO_P_VM_02_0_VM3_RANGE                        5:4
#define GPIO_P_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_P_VM_02_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_02_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_02_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_02_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_P_VM_02_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_02_0_VM4_SHIFT)
#define GPIO_P_VM_02_0_VM4_RANGE                        7:6
#define GPIO_P_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_P_VM_02_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_02_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_02_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_02_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_P_VM_02_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_02_0_VM5_SHIFT)
#define GPIO_P_VM_02_0_VM5_RANGE                        9:8
#define GPIO_P_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_P_VM_02_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_02_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_02_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_02_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_P_VM_02_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_02_0_VM6_SHIFT)
#define GPIO_P_VM_02_0_VM6_RANGE                        11:10
#define GPIO_P_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_P_VM_02_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_02_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_02_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_02_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_P_VM_02_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_02_0_VM7_SHIFT)
#define GPIO_P_VM_02_0_VM7_RANGE                        13:12
#define GPIO_P_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_P_VM_02_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_02_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_02_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_02_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_P_VM_02_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_02_0_VM8_SHIFT)
#define GPIO_P_VM_02_0_VM8_RANGE                        15:14
#define GPIO_P_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_P_VM_02_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_02_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_02_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_P_SCR_02_0
#define GPIO_P_SCR_02_0                 _MK_ADDR_CONST(0x2154)
#define GPIO_P_SCR_02_0_SECURE                  0x0
#define GPIO_P_SCR_02_0_DUAL                    0x0
#define GPIO_P_SCR_02_0_SCR                     0
#define GPIO_P_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_P_SCR_02_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_02_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_02_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_02_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_P_SCR_02_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_P_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_P_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_P_SCR_02_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_02_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_P_SCR_02_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_P_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_P_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_P_SCR_02_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_02_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_P_SCR_02_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_P_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_P_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_P_SCR_02_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_02_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_P_SCR_02_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_P_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_P_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_P_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_P_SCR_02_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_P_SCR_02_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_02_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_P_SCR_02_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_PR7_SHIFT)
#define GPIO_P_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_P_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_02_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_P_SCR_02_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_PR6_SHIFT)
#define GPIO_P_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_P_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_02_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_P_SCR_02_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_PR5_SHIFT)
#define GPIO_P_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_P_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_02_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_P_SCR_02_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_PR4_SHIFT)
#define GPIO_P_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_P_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_02_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_P_SCR_02_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_PR3_SHIFT)
#define GPIO_P_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_P_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_02_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_P_SCR_02_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_PR2_SHIFT)
#define GPIO_P_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_P_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_02_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_P_SCR_02_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_PR1_SHIFT)
#define GPIO_P_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_P_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_02_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_P_SCR_02_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_PR0_SHIFT)
#define GPIO_P_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_P_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_02_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_P_SCR_02_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G7W_SHIFT)
#define GPIO_P_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_P_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_02_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_P_SCR_02_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G6W_SHIFT)
#define GPIO_P_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_P_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_02_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_P_SCR_02_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G5W_SHIFT)
#define GPIO_P_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_P_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_02_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_P_SCR_02_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G4W_SHIFT)
#define GPIO_P_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_P_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_02_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_P_SCR_02_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G3W_SHIFT)
#define GPIO_P_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_P_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_02_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_P_SCR_02_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G2W_SHIFT)
#define GPIO_P_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_P_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_02_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_P_SCR_02_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G1W_SHIFT)
#define GPIO_P_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_P_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_02_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_P_SCR_02_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G0W_SHIFT)
#define GPIO_P_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_P_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_02_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_P_SCR_02_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G7R_SHIFT)
#define GPIO_P_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_P_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_02_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_P_SCR_02_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G6R_SHIFT)
#define GPIO_P_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_P_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_02_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_P_SCR_02_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G5R_SHIFT)
#define GPIO_P_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_P_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_02_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_P_SCR_02_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G4R_SHIFT)
#define GPIO_P_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_P_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_02_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_P_SCR_02_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G3R_SHIFT)
#define GPIO_P_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_P_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_02_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_P_SCR_02_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G2R_SHIFT)
#define GPIO_P_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_P_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_02_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_P_SCR_02_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G1R_SHIFT)
#define GPIO_P_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_P_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_02_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_P_SCR_02_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G0R_SHIFT)
#define GPIO_P_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_P_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_P_VM_03_0
#define GPIO_P_VM_03_0                  _MK_ADDR_CONST(0x2158)
#define GPIO_P_VM_03_0_SECURE                   0x0
#define GPIO_P_VM_03_0_DUAL                     0x0
#define GPIO_P_VM_03_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_P_VM_03_0_WORD_COUNT                       0x1
#define GPIO_P_VM_03_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_03_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_03_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_03_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_P_VM_03_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_03_0_VM1_SHIFT)
#define GPIO_P_VM_03_0_VM1_RANGE                        1:0
#define GPIO_P_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_P_VM_03_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_03_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_03_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_03_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_P_VM_03_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_03_0_VM2_SHIFT)
#define GPIO_P_VM_03_0_VM2_RANGE                        3:2
#define GPIO_P_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_P_VM_03_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_03_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_03_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_03_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_P_VM_03_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_03_0_VM3_SHIFT)
#define GPIO_P_VM_03_0_VM3_RANGE                        5:4
#define GPIO_P_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_P_VM_03_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_03_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_03_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_03_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_P_VM_03_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_03_0_VM4_SHIFT)
#define GPIO_P_VM_03_0_VM4_RANGE                        7:6
#define GPIO_P_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_P_VM_03_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_03_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_03_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_03_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_P_VM_03_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_03_0_VM5_SHIFT)
#define GPIO_P_VM_03_0_VM5_RANGE                        9:8
#define GPIO_P_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_P_VM_03_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_03_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_03_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_03_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_P_VM_03_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_03_0_VM6_SHIFT)
#define GPIO_P_VM_03_0_VM6_RANGE                        11:10
#define GPIO_P_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_P_VM_03_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_03_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_03_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_03_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_P_VM_03_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_03_0_VM7_SHIFT)
#define GPIO_P_VM_03_0_VM7_RANGE                        13:12
#define GPIO_P_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_P_VM_03_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_03_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_03_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_03_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_P_VM_03_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_03_0_VM8_SHIFT)
#define GPIO_P_VM_03_0_VM8_RANGE                        15:14
#define GPIO_P_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_P_VM_03_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_03_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_03_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_P_SCR_03_0
#define GPIO_P_SCR_03_0                 _MK_ADDR_CONST(0x215c)
#define GPIO_P_SCR_03_0_SECURE                  0x0
#define GPIO_P_SCR_03_0_DUAL                    0x0
#define GPIO_P_SCR_03_0_SCR                     0
#define GPIO_P_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_P_SCR_03_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_03_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_03_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_03_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_P_SCR_03_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_P_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_P_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_P_SCR_03_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_03_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_P_SCR_03_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_P_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_P_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_P_SCR_03_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_03_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_P_SCR_03_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_P_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_P_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_P_SCR_03_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_03_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_P_SCR_03_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_P_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_P_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_P_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_P_SCR_03_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_P_SCR_03_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_03_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_P_SCR_03_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_PR7_SHIFT)
#define GPIO_P_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_P_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_03_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_P_SCR_03_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_PR6_SHIFT)
#define GPIO_P_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_P_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_03_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_P_SCR_03_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_PR5_SHIFT)
#define GPIO_P_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_P_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_03_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_P_SCR_03_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_PR4_SHIFT)
#define GPIO_P_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_P_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_03_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_P_SCR_03_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_PR3_SHIFT)
#define GPIO_P_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_P_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_03_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_P_SCR_03_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_PR2_SHIFT)
#define GPIO_P_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_P_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_03_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_P_SCR_03_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_PR1_SHIFT)
#define GPIO_P_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_P_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_03_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_P_SCR_03_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_PR0_SHIFT)
#define GPIO_P_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_P_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_03_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_P_SCR_03_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G7W_SHIFT)
#define GPIO_P_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_P_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_03_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_P_SCR_03_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G6W_SHIFT)
#define GPIO_P_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_P_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_03_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_P_SCR_03_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G5W_SHIFT)
#define GPIO_P_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_P_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_03_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_P_SCR_03_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G4W_SHIFT)
#define GPIO_P_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_P_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_03_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_P_SCR_03_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G3W_SHIFT)
#define GPIO_P_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_P_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_03_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_P_SCR_03_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G2W_SHIFT)
#define GPIO_P_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_P_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_03_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_P_SCR_03_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G1W_SHIFT)
#define GPIO_P_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_P_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_03_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_P_SCR_03_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G0W_SHIFT)
#define GPIO_P_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_P_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_03_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_P_SCR_03_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G7R_SHIFT)
#define GPIO_P_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_P_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_03_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_P_SCR_03_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G6R_SHIFT)
#define GPIO_P_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_P_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_03_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_P_SCR_03_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G5R_SHIFT)
#define GPIO_P_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_P_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_03_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_P_SCR_03_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G4R_SHIFT)
#define GPIO_P_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_P_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_03_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_P_SCR_03_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G3R_SHIFT)
#define GPIO_P_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_P_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_03_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_P_SCR_03_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G2R_SHIFT)
#define GPIO_P_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_P_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_03_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_P_SCR_03_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G1R_SHIFT)
#define GPIO_P_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_P_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_03_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_P_SCR_03_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G0R_SHIFT)
#define GPIO_P_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_P_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_P_VM_04_0
#define GPIO_P_VM_04_0                  _MK_ADDR_CONST(0x2160)
#define GPIO_P_VM_04_0_SECURE                   0x0
#define GPIO_P_VM_04_0_DUAL                     0x0
#define GPIO_P_VM_04_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_P_VM_04_0_WORD_COUNT                       0x1
#define GPIO_P_VM_04_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_04_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_04_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_04_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_P_VM_04_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_04_0_VM1_SHIFT)
#define GPIO_P_VM_04_0_VM1_RANGE                        1:0
#define GPIO_P_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_P_VM_04_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_04_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_04_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_04_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_P_VM_04_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_04_0_VM2_SHIFT)
#define GPIO_P_VM_04_0_VM2_RANGE                        3:2
#define GPIO_P_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_P_VM_04_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_04_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_04_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_04_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_P_VM_04_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_04_0_VM3_SHIFT)
#define GPIO_P_VM_04_0_VM3_RANGE                        5:4
#define GPIO_P_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_P_VM_04_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_04_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_04_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_04_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_P_VM_04_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_04_0_VM4_SHIFT)
#define GPIO_P_VM_04_0_VM4_RANGE                        7:6
#define GPIO_P_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_P_VM_04_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_04_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_04_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_04_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_P_VM_04_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_04_0_VM5_SHIFT)
#define GPIO_P_VM_04_0_VM5_RANGE                        9:8
#define GPIO_P_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_P_VM_04_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_04_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_04_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_04_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_P_VM_04_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_04_0_VM6_SHIFT)
#define GPIO_P_VM_04_0_VM6_RANGE                        11:10
#define GPIO_P_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_P_VM_04_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_04_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_04_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_04_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_P_VM_04_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_04_0_VM7_SHIFT)
#define GPIO_P_VM_04_0_VM7_RANGE                        13:12
#define GPIO_P_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_P_VM_04_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_04_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_04_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_04_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_P_VM_04_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_04_0_VM8_SHIFT)
#define GPIO_P_VM_04_0_VM8_RANGE                        15:14
#define GPIO_P_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_P_VM_04_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_04_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_04_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_P_SCR_04_0
#define GPIO_P_SCR_04_0                 _MK_ADDR_CONST(0x2164)
#define GPIO_P_SCR_04_0_SECURE                  0x0
#define GPIO_P_SCR_04_0_DUAL                    0x0
#define GPIO_P_SCR_04_0_SCR                     0
#define GPIO_P_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_P_SCR_04_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_04_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_04_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_04_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_P_SCR_04_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_P_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_P_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_P_SCR_04_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_04_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_P_SCR_04_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_P_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_P_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_P_SCR_04_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_04_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_P_SCR_04_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_P_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_P_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_P_SCR_04_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_04_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_P_SCR_04_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_P_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_P_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_P_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_P_SCR_04_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_P_SCR_04_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_04_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_P_SCR_04_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_PR7_SHIFT)
#define GPIO_P_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_P_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_04_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_P_SCR_04_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_PR6_SHIFT)
#define GPIO_P_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_P_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_04_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_P_SCR_04_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_PR5_SHIFT)
#define GPIO_P_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_P_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_04_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_P_SCR_04_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_PR4_SHIFT)
#define GPIO_P_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_P_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_04_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_P_SCR_04_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_PR3_SHIFT)
#define GPIO_P_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_P_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_04_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_P_SCR_04_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_PR2_SHIFT)
#define GPIO_P_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_P_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_04_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_P_SCR_04_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_PR1_SHIFT)
#define GPIO_P_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_P_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_04_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_P_SCR_04_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_PR0_SHIFT)
#define GPIO_P_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_P_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_04_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_P_SCR_04_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G7W_SHIFT)
#define GPIO_P_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_P_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_04_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_P_SCR_04_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G6W_SHIFT)
#define GPIO_P_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_P_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_04_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_P_SCR_04_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G5W_SHIFT)
#define GPIO_P_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_P_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_04_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_P_SCR_04_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G4W_SHIFT)
#define GPIO_P_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_P_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_04_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_P_SCR_04_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G3W_SHIFT)
#define GPIO_P_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_P_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_04_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_P_SCR_04_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G2W_SHIFT)
#define GPIO_P_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_P_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_04_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_P_SCR_04_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G1W_SHIFT)
#define GPIO_P_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_P_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_04_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_P_SCR_04_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G0W_SHIFT)
#define GPIO_P_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_P_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_04_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_P_SCR_04_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G7R_SHIFT)
#define GPIO_P_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_P_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_04_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_P_SCR_04_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G6R_SHIFT)
#define GPIO_P_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_P_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_04_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_P_SCR_04_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G5R_SHIFT)
#define GPIO_P_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_P_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_04_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_P_SCR_04_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G4R_SHIFT)
#define GPIO_P_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_P_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_04_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_P_SCR_04_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G3R_SHIFT)
#define GPIO_P_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_P_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_04_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_P_SCR_04_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G2R_SHIFT)
#define GPIO_P_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_P_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_04_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_P_SCR_04_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G1R_SHIFT)
#define GPIO_P_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_P_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_04_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_P_SCR_04_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G0R_SHIFT)
#define GPIO_P_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_P_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_P_VM_05_0
#define GPIO_P_VM_05_0                  _MK_ADDR_CONST(0x2168)
#define GPIO_P_VM_05_0_SECURE                   0x0
#define GPIO_P_VM_05_0_DUAL                     0x0
#define GPIO_P_VM_05_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_P_VM_05_0_WORD_COUNT                       0x1
#define GPIO_P_VM_05_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_05_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_05_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_05_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_P_VM_05_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_05_0_VM1_SHIFT)
#define GPIO_P_VM_05_0_VM1_RANGE                        1:0
#define GPIO_P_VM_05_0_VM1_WOFFSET                      0x0
#define GPIO_P_VM_05_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_05_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_05_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_05_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_P_VM_05_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_05_0_VM2_SHIFT)
#define GPIO_P_VM_05_0_VM2_RANGE                        3:2
#define GPIO_P_VM_05_0_VM2_WOFFSET                      0x0
#define GPIO_P_VM_05_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_05_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_05_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_05_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_P_VM_05_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_05_0_VM3_SHIFT)
#define GPIO_P_VM_05_0_VM3_RANGE                        5:4
#define GPIO_P_VM_05_0_VM3_WOFFSET                      0x0
#define GPIO_P_VM_05_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_05_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_05_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_05_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_P_VM_05_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_05_0_VM4_SHIFT)
#define GPIO_P_VM_05_0_VM4_RANGE                        7:6
#define GPIO_P_VM_05_0_VM4_WOFFSET                      0x0
#define GPIO_P_VM_05_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_05_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_05_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_05_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_P_VM_05_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_05_0_VM5_SHIFT)
#define GPIO_P_VM_05_0_VM5_RANGE                        9:8
#define GPIO_P_VM_05_0_VM5_WOFFSET                      0x0
#define GPIO_P_VM_05_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_05_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_05_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_05_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_P_VM_05_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_05_0_VM6_SHIFT)
#define GPIO_P_VM_05_0_VM6_RANGE                        11:10
#define GPIO_P_VM_05_0_VM6_WOFFSET                      0x0
#define GPIO_P_VM_05_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_05_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_05_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_05_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_P_VM_05_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_05_0_VM7_SHIFT)
#define GPIO_P_VM_05_0_VM7_RANGE                        13:12
#define GPIO_P_VM_05_0_VM7_WOFFSET                      0x0
#define GPIO_P_VM_05_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_05_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_05_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_05_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_P_VM_05_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_05_0_VM8_SHIFT)
#define GPIO_P_VM_05_0_VM8_RANGE                        15:14
#define GPIO_P_VM_05_0_VM8_WOFFSET                      0x0
#define GPIO_P_VM_05_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_05_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_05_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_P_SCR_05_0
#define GPIO_P_SCR_05_0                 _MK_ADDR_CONST(0x216c)
#define GPIO_P_SCR_05_0_SECURE                  0x0
#define GPIO_P_SCR_05_0_DUAL                    0x0
#define GPIO_P_SCR_05_0_SCR                     0
#define GPIO_P_SCR_05_0_WORD_COUNT                      0x1
#define GPIO_P_SCR_05_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_05_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_05_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_05_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_P_SCR_05_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_P_SCR_05_0_SEC_LCK_RANGE                   29:29
#define GPIO_P_SCR_05_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_P_SCR_05_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_05_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_P_SCR_05_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_P_SCR_05_0_SEC_WEN_RANGE                   28:28
#define GPIO_P_SCR_05_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_P_SCR_05_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_05_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_P_SCR_05_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_P_SCR_05_0_SEC_REN_RANGE                   27:27
#define GPIO_P_SCR_05_0_SEC_REN_WOFFSET                 0x0
#define GPIO_P_SCR_05_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_05_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_P_SCR_05_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_P_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_P_SCR_05_0_SEC_OWNER_RANGE                 26:24
#define GPIO_P_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_P_SCR_05_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_P_SCR_05_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_05_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_P_SCR_05_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_PR7_SHIFT)
#define GPIO_P_SCR_05_0_PR7_RANGE                       23:23
#define GPIO_P_SCR_05_0_PR7_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_05_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_P_SCR_05_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_PR6_SHIFT)
#define GPIO_P_SCR_05_0_PR6_RANGE                       22:22
#define GPIO_P_SCR_05_0_PR6_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_05_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_P_SCR_05_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_PR5_SHIFT)
#define GPIO_P_SCR_05_0_PR5_RANGE                       21:21
#define GPIO_P_SCR_05_0_PR5_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_05_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_P_SCR_05_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_PR4_SHIFT)
#define GPIO_P_SCR_05_0_PR4_RANGE                       20:20
#define GPIO_P_SCR_05_0_PR4_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_05_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_P_SCR_05_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_PR3_SHIFT)
#define GPIO_P_SCR_05_0_PR3_RANGE                       19:19
#define GPIO_P_SCR_05_0_PR3_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_05_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_P_SCR_05_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_PR2_SHIFT)
#define GPIO_P_SCR_05_0_PR2_RANGE                       18:18
#define GPIO_P_SCR_05_0_PR2_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_05_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_P_SCR_05_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_PR1_SHIFT)
#define GPIO_P_SCR_05_0_PR1_RANGE                       17:17
#define GPIO_P_SCR_05_0_PR1_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_05_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_P_SCR_05_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_PR0_SHIFT)
#define GPIO_P_SCR_05_0_PR0_RANGE                       16:16
#define GPIO_P_SCR_05_0_PR0_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_05_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_P_SCR_05_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G7W_SHIFT)
#define GPIO_P_SCR_05_0_G7W_RANGE                       15:15
#define GPIO_P_SCR_05_0_G7W_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_05_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_P_SCR_05_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G6W_SHIFT)
#define GPIO_P_SCR_05_0_G6W_RANGE                       14:14
#define GPIO_P_SCR_05_0_G6W_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_05_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_P_SCR_05_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G5W_SHIFT)
#define GPIO_P_SCR_05_0_G5W_RANGE                       13:13
#define GPIO_P_SCR_05_0_G5W_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_05_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_P_SCR_05_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G4W_SHIFT)
#define GPIO_P_SCR_05_0_G4W_RANGE                       12:12
#define GPIO_P_SCR_05_0_G4W_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_05_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_P_SCR_05_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G3W_SHIFT)
#define GPIO_P_SCR_05_0_G3W_RANGE                       11:11
#define GPIO_P_SCR_05_0_G3W_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_05_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_P_SCR_05_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G2W_SHIFT)
#define GPIO_P_SCR_05_0_G2W_RANGE                       10:10
#define GPIO_P_SCR_05_0_G2W_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_05_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_P_SCR_05_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G1W_SHIFT)
#define GPIO_P_SCR_05_0_G1W_RANGE                       9:9
#define GPIO_P_SCR_05_0_G1W_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_05_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_P_SCR_05_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G0W_SHIFT)
#define GPIO_P_SCR_05_0_G0W_RANGE                       8:8
#define GPIO_P_SCR_05_0_G0W_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_05_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_P_SCR_05_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G7R_SHIFT)
#define GPIO_P_SCR_05_0_G7R_RANGE                       7:7
#define GPIO_P_SCR_05_0_G7R_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_05_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_P_SCR_05_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G6R_SHIFT)
#define GPIO_P_SCR_05_0_G6R_RANGE                       6:6
#define GPIO_P_SCR_05_0_G6R_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_05_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_P_SCR_05_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G5R_SHIFT)
#define GPIO_P_SCR_05_0_G5R_RANGE                       5:5
#define GPIO_P_SCR_05_0_G5R_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_05_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_P_SCR_05_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G4R_SHIFT)
#define GPIO_P_SCR_05_0_G4R_RANGE                       4:4
#define GPIO_P_SCR_05_0_G4R_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_05_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_P_SCR_05_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G3R_SHIFT)
#define GPIO_P_SCR_05_0_G3R_RANGE                       3:3
#define GPIO_P_SCR_05_0_G3R_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_05_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_P_SCR_05_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G2R_SHIFT)
#define GPIO_P_SCR_05_0_G2R_RANGE                       2:2
#define GPIO_P_SCR_05_0_G2R_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_05_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_P_SCR_05_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G1R_SHIFT)
#define GPIO_P_SCR_05_0_G1R_RANGE                       1:1
#define GPIO_P_SCR_05_0_G1R_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_05_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_P_SCR_05_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G0R_SHIFT)
#define GPIO_P_SCR_05_0_G0R_RANGE                       0:0
#define GPIO_P_SCR_05_0_G0R_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_P_VM_06_0
#define GPIO_P_VM_06_0                  _MK_ADDR_CONST(0x2170)
#define GPIO_P_VM_06_0_SECURE                   0x0
#define GPIO_P_VM_06_0_DUAL                     0x0
#define GPIO_P_VM_06_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_P_VM_06_0_WORD_COUNT                       0x1
#define GPIO_P_VM_06_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_06_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_06_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_06_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_06_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_P_VM_06_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_06_0_VM1_SHIFT)
#define GPIO_P_VM_06_0_VM1_RANGE                        1:0
#define GPIO_P_VM_06_0_VM1_WOFFSET                      0x0
#define GPIO_P_VM_06_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_06_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_06_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_06_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_P_VM_06_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_06_0_VM2_SHIFT)
#define GPIO_P_VM_06_0_VM2_RANGE                        3:2
#define GPIO_P_VM_06_0_VM2_WOFFSET                      0x0
#define GPIO_P_VM_06_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_06_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_06_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_06_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_P_VM_06_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_06_0_VM3_SHIFT)
#define GPIO_P_VM_06_0_VM3_RANGE                        5:4
#define GPIO_P_VM_06_0_VM3_WOFFSET                      0x0
#define GPIO_P_VM_06_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_06_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_06_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_06_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_P_VM_06_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_06_0_VM4_SHIFT)
#define GPIO_P_VM_06_0_VM4_RANGE                        7:6
#define GPIO_P_VM_06_0_VM4_WOFFSET                      0x0
#define GPIO_P_VM_06_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_06_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_06_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_06_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_P_VM_06_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_06_0_VM5_SHIFT)
#define GPIO_P_VM_06_0_VM5_RANGE                        9:8
#define GPIO_P_VM_06_0_VM5_WOFFSET                      0x0
#define GPIO_P_VM_06_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_06_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_06_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_06_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_P_VM_06_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_06_0_VM6_SHIFT)
#define GPIO_P_VM_06_0_VM6_RANGE                        11:10
#define GPIO_P_VM_06_0_VM6_WOFFSET                      0x0
#define GPIO_P_VM_06_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_06_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_06_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_06_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_P_VM_06_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_06_0_VM7_SHIFT)
#define GPIO_P_VM_06_0_VM7_RANGE                        13:12
#define GPIO_P_VM_06_0_VM7_WOFFSET                      0x0
#define GPIO_P_VM_06_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_06_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_06_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_06_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_P_VM_06_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_06_0_VM8_SHIFT)
#define GPIO_P_VM_06_0_VM8_RANGE                        15:14
#define GPIO_P_VM_06_0_VM8_WOFFSET                      0x0
#define GPIO_P_VM_06_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_06_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_06_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_P_SCR_06_0
#define GPIO_P_SCR_06_0                 _MK_ADDR_CONST(0x2174)
#define GPIO_P_SCR_06_0_SECURE                  0x0
#define GPIO_P_SCR_06_0_DUAL                    0x0
#define GPIO_P_SCR_06_0_SCR                     0
#define GPIO_P_SCR_06_0_WORD_COUNT                      0x1
#define GPIO_P_SCR_06_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_06_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_06_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_06_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_P_SCR_06_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_SEC_LCK_SHIFT)
#define GPIO_P_SCR_06_0_SEC_LCK_RANGE                   29:29
#define GPIO_P_SCR_06_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_P_SCR_06_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_06_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_P_SCR_06_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_SEC_WEN_SHIFT)
#define GPIO_P_SCR_06_0_SEC_WEN_RANGE                   28:28
#define GPIO_P_SCR_06_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_P_SCR_06_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_06_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_P_SCR_06_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_SEC_REN_SHIFT)
#define GPIO_P_SCR_06_0_SEC_REN_RANGE                   27:27
#define GPIO_P_SCR_06_0_SEC_REN_WOFFSET                 0x0
#define GPIO_P_SCR_06_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_06_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_P_SCR_06_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_P_SCR_06_0_SEC_OWNER_SHIFT)
#define GPIO_P_SCR_06_0_SEC_OWNER_RANGE                 26:24
#define GPIO_P_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_P_SCR_06_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_P_SCR_06_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_06_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_P_SCR_06_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_PR7_SHIFT)
#define GPIO_P_SCR_06_0_PR7_RANGE                       23:23
#define GPIO_P_SCR_06_0_PR7_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_06_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_P_SCR_06_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_PR6_SHIFT)
#define GPIO_P_SCR_06_0_PR6_RANGE                       22:22
#define GPIO_P_SCR_06_0_PR6_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_06_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_P_SCR_06_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_PR5_SHIFT)
#define GPIO_P_SCR_06_0_PR5_RANGE                       21:21
#define GPIO_P_SCR_06_0_PR5_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_06_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_P_SCR_06_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_PR4_SHIFT)
#define GPIO_P_SCR_06_0_PR4_RANGE                       20:20
#define GPIO_P_SCR_06_0_PR4_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_06_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_P_SCR_06_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_PR3_SHIFT)
#define GPIO_P_SCR_06_0_PR3_RANGE                       19:19
#define GPIO_P_SCR_06_0_PR3_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_06_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_P_SCR_06_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_PR2_SHIFT)
#define GPIO_P_SCR_06_0_PR2_RANGE                       18:18
#define GPIO_P_SCR_06_0_PR2_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_06_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_P_SCR_06_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_PR1_SHIFT)
#define GPIO_P_SCR_06_0_PR1_RANGE                       17:17
#define GPIO_P_SCR_06_0_PR1_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_06_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_P_SCR_06_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_PR0_SHIFT)
#define GPIO_P_SCR_06_0_PR0_RANGE                       16:16
#define GPIO_P_SCR_06_0_PR0_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_06_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_P_SCR_06_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G7W_SHIFT)
#define GPIO_P_SCR_06_0_G7W_RANGE                       15:15
#define GPIO_P_SCR_06_0_G7W_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_06_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_P_SCR_06_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G6W_SHIFT)
#define GPIO_P_SCR_06_0_G6W_RANGE                       14:14
#define GPIO_P_SCR_06_0_G6W_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_06_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_P_SCR_06_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G5W_SHIFT)
#define GPIO_P_SCR_06_0_G5W_RANGE                       13:13
#define GPIO_P_SCR_06_0_G5W_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_06_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_P_SCR_06_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G4W_SHIFT)
#define GPIO_P_SCR_06_0_G4W_RANGE                       12:12
#define GPIO_P_SCR_06_0_G4W_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_06_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_P_SCR_06_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G3W_SHIFT)
#define GPIO_P_SCR_06_0_G3W_RANGE                       11:11
#define GPIO_P_SCR_06_0_G3W_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_06_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_P_SCR_06_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G2W_SHIFT)
#define GPIO_P_SCR_06_0_G2W_RANGE                       10:10
#define GPIO_P_SCR_06_0_G2W_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_06_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_P_SCR_06_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G1W_SHIFT)
#define GPIO_P_SCR_06_0_G1W_RANGE                       9:9
#define GPIO_P_SCR_06_0_G1W_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_06_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_P_SCR_06_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G0W_SHIFT)
#define GPIO_P_SCR_06_0_G0W_RANGE                       8:8
#define GPIO_P_SCR_06_0_G0W_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_06_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_P_SCR_06_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G7R_SHIFT)
#define GPIO_P_SCR_06_0_G7R_RANGE                       7:7
#define GPIO_P_SCR_06_0_G7R_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_06_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_P_SCR_06_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G6R_SHIFT)
#define GPIO_P_SCR_06_0_G6R_RANGE                       6:6
#define GPIO_P_SCR_06_0_G6R_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_06_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_P_SCR_06_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G5R_SHIFT)
#define GPIO_P_SCR_06_0_G5R_RANGE                       5:5
#define GPIO_P_SCR_06_0_G5R_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_06_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_P_SCR_06_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G4R_SHIFT)
#define GPIO_P_SCR_06_0_G4R_RANGE                       4:4
#define GPIO_P_SCR_06_0_G4R_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_06_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_P_SCR_06_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G3R_SHIFT)
#define GPIO_P_SCR_06_0_G3R_RANGE                       3:3
#define GPIO_P_SCR_06_0_G3R_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_06_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_P_SCR_06_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G2R_SHIFT)
#define GPIO_P_SCR_06_0_G2R_RANGE                       2:2
#define GPIO_P_SCR_06_0_G2R_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_06_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_P_SCR_06_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G1R_SHIFT)
#define GPIO_P_SCR_06_0_G1R_RANGE                       1:1
#define GPIO_P_SCR_06_0_G1R_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_06_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_P_SCR_06_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G0R_SHIFT)
#define GPIO_P_SCR_06_0_G0R_RANGE                       0:0
#define GPIO_P_SCR_06_0_G0R_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_P_VM_07_0
#define GPIO_P_VM_07_0                  _MK_ADDR_CONST(0x2178)
#define GPIO_P_VM_07_0_SECURE                   0x0
#define GPIO_P_VM_07_0_DUAL                     0x0
#define GPIO_P_VM_07_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_P_VM_07_0_WORD_COUNT                       0x1
#define GPIO_P_VM_07_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_07_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_07_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_07_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_VM_07_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_07_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_P_VM_07_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_P_VM_07_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_07_0_VM1_SHIFT)
#define GPIO_P_VM_07_0_VM1_RANGE                        1:0
#define GPIO_P_VM_07_0_VM1_WOFFSET                      0x0
#define GPIO_P_VM_07_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_07_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_07_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_07_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_07_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_07_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_07_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_P_VM_07_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_07_0_VM2_SHIFT)
#define GPIO_P_VM_07_0_VM2_RANGE                        3:2
#define GPIO_P_VM_07_0_VM2_WOFFSET                      0x0
#define GPIO_P_VM_07_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_07_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_07_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_07_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_07_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_07_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_07_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_P_VM_07_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_07_0_VM3_SHIFT)
#define GPIO_P_VM_07_0_VM3_RANGE                        5:4
#define GPIO_P_VM_07_0_VM3_WOFFSET                      0x0
#define GPIO_P_VM_07_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_07_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_07_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_07_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_07_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_07_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_07_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_P_VM_07_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_07_0_VM4_SHIFT)
#define GPIO_P_VM_07_0_VM4_RANGE                        7:6
#define GPIO_P_VM_07_0_VM4_WOFFSET                      0x0
#define GPIO_P_VM_07_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_07_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_07_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_07_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_07_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_07_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_07_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_P_VM_07_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_07_0_VM5_SHIFT)
#define GPIO_P_VM_07_0_VM5_RANGE                        9:8
#define GPIO_P_VM_07_0_VM5_WOFFSET                      0x0
#define GPIO_P_VM_07_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_07_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_07_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_07_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_07_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_07_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_07_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_P_VM_07_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_07_0_VM6_SHIFT)
#define GPIO_P_VM_07_0_VM6_RANGE                        11:10
#define GPIO_P_VM_07_0_VM6_WOFFSET                      0x0
#define GPIO_P_VM_07_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_07_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_07_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_07_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_07_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_07_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_07_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_P_VM_07_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_07_0_VM7_SHIFT)
#define GPIO_P_VM_07_0_VM7_RANGE                        13:12
#define GPIO_P_VM_07_0_VM7_WOFFSET                      0x0
#define GPIO_P_VM_07_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_07_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_07_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_07_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_07_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_07_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_P_VM_07_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_P_VM_07_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_P_VM_07_0_VM8_SHIFT)
#define GPIO_P_VM_07_0_VM8_RANGE                        15:14
#define GPIO_P_VM_07_0_VM8_WOFFSET                      0x0
#define GPIO_P_VM_07_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_P_VM_07_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_P_VM_07_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_VM_07_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_VM_07_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_VM_07_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_P_SCR_07_0
#define GPIO_P_SCR_07_0                 _MK_ADDR_CONST(0x217c)
#define GPIO_P_SCR_07_0_SECURE                  0x0
#define GPIO_P_SCR_07_0_DUAL                    0x0
#define GPIO_P_SCR_07_0_SCR                     0
#define GPIO_P_SCR_07_0_WORD_COUNT                      0x1
#define GPIO_P_SCR_07_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_07_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_07_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_07_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_P_SCR_07_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_SEC_LCK_SHIFT)
#define GPIO_P_SCR_07_0_SEC_LCK_RANGE                   29:29
#define GPIO_P_SCR_07_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_P_SCR_07_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_07_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_07_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_P_SCR_07_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_SEC_WEN_SHIFT)
#define GPIO_P_SCR_07_0_SEC_WEN_RANGE                   28:28
#define GPIO_P_SCR_07_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_P_SCR_07_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_07_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_07_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_P_SCR_07_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_SEC_REN_SHIFT)
#define GPIO_P_SCR_07_0_SEC_REN_RANGE                   27:27
#define GPIO_P_SCR_07_0_SEC_REN_WOFFSET                 0x0
#define GPIO_P_SCR_07_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_07_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_07_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_P_SCR_07_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_P_SCR_07_0_SEC_OWNER_SHIFT)
#define GPIO_P_SCR_07_0_SEC_OWNER_RANGE                 26:24
#define GPIO_P_SCR_07_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_P_SCR_07_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_P_SCR_07_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_07_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_P_SCR_07_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_PR7_SHIFT)
#define GPIO_P_SCR_07_0_PR7_RANGE                       23:23
#define GPIO_P_SCR_07_0_PR7_WOFFSET                     0x0
#define GPIO_P_SCR_07_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_07_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_07_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_P_SCR_07_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_PR6_SHIFT)
#define GPIO_P_SCR_07_0_PR6_RANGE                       22:22
#define GPIO_P_SCR_07_0_PR6_WOFFSET                     0x0
#define GPIO_P_SCR_07_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_07_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_07_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_P_SCR_07_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_PR5_SHIFT)
#define GPIO_P_SCR_07_0_PR5_RANGE                       21:21
#define GPIO_P_SCR_07_0_PR5_WOFFSET                     0x0
#define GPIO_P_SCR_07_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_07_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_07_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_P_SCR_07_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_PR4_SHIFT)
#define GPIO_P_SCR_07_0_PR4_RANGE                       20:20
#define GPIO_P_SCR_07_0_PR4_WOFFSET                     0x0
#define GPIO_P_SCR_07_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_07_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_07_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_P_SCR_07_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_PR3_SHIFT)
#define GPIO_P_SCR_07_0_PR3_RANGE                       19:19
#define GPIO_P_SCR_07_0_PR3_WOFFSET                     0x0
#define GPIO_P_SCR_07_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_07_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_07_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_P_SCR_07_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_PR2_SHIFT)
#define GPIO_P_SCR_07_0_PR2_RANGE                       18:18
#define GPIO_P_SCR_07_0_PR2_WOFFSET                     0x0
#define GPIO_P_SCR_07_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_07_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_07_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_P_SCR_07_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_PR1_SHIFT)
#define GPIO_P_SCR_07_0_PR1_RANGE                       17:17
#define GPIO_P_SCR_07_0_PR1_WOFFSET                     0x0
#define GPIO_P_SCR_07_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_07_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_07_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_P_SCR_07_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_PR0_SHIFT)
#define GPIO_P_SCR_07_0_PR0_RANGE                       16:16
#define GPIO_P_SCR_07_0_PR0_WOFFSET                     0x0
#define GPIO_P_SCR_07_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_07_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_07_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_P_SCR_07_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_G7W_SHIFT)
#define GPIO_P_SCR_07_0_G7W_RANGE                       15:15
#define GPIO_P_SCR_07_0_G7W_WOFFSET                     0x0
#define GPIO_P_SCR_07_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_07_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_07_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_P_SCR_07_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_G6W_SHIFT)
#define GPIO_P_SCR_07_0_G6W_RANGE                       14:14
#define GPIO_P_SCR_07_0_G6W_WOFFSET                     0x0
#define GPIO_P_SCR_07_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_07_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_07_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_P_SCR_07_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_G5W_SHIFT)
#define GPIO_P_SCR_07_0_G5W_RANGE                       13:13
#define GPIO_P_SCR_07_0_G5W_WOFFSET                     0x0
#define GPIO_P_SCR_07_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_07_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_07_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_P_SCR_07_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_G4W_SHIFT)
#define GPIO_P_SCR_07_0_G4W_RANGE                       12:12
#define GPIO_P_SCR_07_0_G4W_WOFFSET                     0x0
#define GPIO_P_SCR_07_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_07_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_07_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_P_SCR_07_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_G3W_SHIFT)
#define GPIO_P_SCR_07_0_G3W_RANGE                       11:11
#define GPIO_P_SCR_07_0_G3W_WOFFSET                     0x0
#define GPIO_P_SCR_07_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_07_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_07_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_P_SCR_07_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_G2W_SHIFT)
#define GPIO_P_SCR_07_0_G2W_RANGE                       10:10
#define GPIO_P_SCR_07_0_G2W_WOFFSET                     0x0
#define GPIO_P_SCR_07_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_07_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_07_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_P_SCR_07_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_G1W_SHIFT)
#define GPIO_P_SCR_07_0_G1W_RANGE                       9:9
#define GPIO_P_SCR_07_0_G1W_WOFFSET                     0x0
#define GPIO_P_SCR_07_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_07_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_07_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_P_SCR_07_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_G0W_SHIFT)
#define GPIO_P_SCR_07_0_G0W_RANGE                       8:8
#define GPIO_P_SCR_07_0_G0W_WOFFSET                     0x0
#define GPIO_P_SCR_07_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_07_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_07_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_P_SCR_07_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_G7R_SHIFT)
#define GPIO_P_SCR_07_0_G7R_RANGE                       7:7
#define GPIO_P_SCR_07_0_G7R_WOFFSET                     0x0
#define GPIO_P_SCR_07_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_07_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_07_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_P_SCR_07_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_G6R_SHIFT)
#define GPIO_P_SCR_07_0_G6R_RANGE                       6:6
#define GPIO_P_SCR_07_0_G6R_WOFFSET                     0x0
#define GPIO_P_SCR_07_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_07_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_07_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_P_SCR_07_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_G5R_SHIFT)
#define GPIO_P_SCR_07_0_G5R_RANGE                       5:5
#define GPIO_P_SCR_07_0_G5R_WOFFSET                     0x0
#define GPIO_P_SCR_07_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_07_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_07_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_P_SCR_07_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_G4R_SHIFT)
#define GPIO_P_SCR_07_0_G4R_RANGE                       4:4
#define GPIO_P_SCR_07_0_G4R_WOFFSET                     0x0
#define GPIO_P_SCR_07_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_07_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_07_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_P_SCR_07_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_G3R_SHIFT)
#define GPIO_P_SCR_07_0_G3R_RANGE                       3:3
#define GPIO_P_SCR_07_0_G3R_WOFFSET                     0x0
#define GPIO_P_SCR_07_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_07_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_07_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_P_SCR_07_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_G2R_SHIFT)
#define GPIO_P_SCR_07_0_G2R_RANGE                       2:2
#define GPIO_P_SCR_07_0_G2R_WOFFSET                     0x0
#define GPIO_P_SCR_07_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_07_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_07_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_P_SCR_07_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_G1R_SHIFT)
#define GPIO_P_SCR_07_0_G1R_RANGE                       1:1
#define GPIO_P_SCR_07_0_G1R_WOFFSET                     0x0
#define GPIO_P_SCR_07_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_07_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_P_SCR_07_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_P_SCR_07_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_G0R_SHIFT)
#define GPIO_P_SCR_07_0_G0R_RANGE                       0:0
#define GPIO_P_SCR_07_0_G0R_WOFFSET                     0x0
#define GPIO_P_SCR_07_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_SCR_07_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_Q_VM_00_0
#define GPIO_Q_VM_00_0                  _MK_ADDR_CONST(0x2180)
#define GPIO_Q_VM_00_0_SECURE                   0x0
#define GPIO_Q_VM_00_0_DUAL                     0x0
#define GPIO_Q_VM_00_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_Q_VM_00_0_WORD_COUNT                       0x1
#define GPIO_Q_VM_00_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_00_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_00_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_00_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Q_VM_00_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_00_0_VM1_SHIFT)
#define GPIO_Q_VM_00_0_VM1_RANGE                        1:0
#define GPIO_Q_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_Q_VM_00_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_00_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_00_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_00_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_Q_VM_00_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_00_0_VM2_SHIFT)
#define GPIO_Q_VM_00_0_VM2_RANGE                        3:2
#define GPIO_Q_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_Q_VM_00_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_00_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_00_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_00_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_Q_VM_00_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_00_0_VM3_SHIFT)
#define GPIO_Q_VM_00_0_VM3_RANGE                        5:4
#define GPIO_Q_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_Q_VM_00_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_00_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_00_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_00_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_Q_VM_00_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_00_0_VM4_SHIFT)
#define GPIO_Q_VM_00_0_VM4_RANGE                        7:6
#define GPIO_Q_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_Q_VM_00_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_00_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_00_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_00_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_Q_VM_00_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_00_0_VM5_SHIFT)
#define GPIO_Q_VM_00_0_VM5_RANGE                        9:8
#define GPIO_Q_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_Q_VM_00_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_00_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_00_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_00_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_Q_VM_00_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_00_0_VM6_SHIFT)
#define GPIO_Q_VM_00_0_VM6_RANGE                        11:10
#define GPIO_Q_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_Q_VM_00_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_00_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_00_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_00_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_Q_VM_00_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_00_0_VM7_SHIFT)
#define GPIO_Q_VM_00_0_VM7_RANGE                        13:12
#define GPIO_Q_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_Q_VM_00_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_00_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_00_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_00_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_Q_VM_00_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_00_0_VM8_SHIFT)
#define GPIO_Q_VM_00_0_VM8_RANGE                        15:14
#define GPIO_Q_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_Q_VM_00_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_00_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_00_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_Q_SCR_00_0
#define GPIO_Q_SCR_00_0                 _MK_ADDR_CONST(0x2184)
#define GPIO_Q_SCR_00_0_SECURE                  0x0
#define GPIO_Q_SCR_00_0_DUAL                    0x0
#define GPIO_Q_SCR_00_0_SCR                     0
#define GPIO_Q_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_Q_SCR_00_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_00_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_00_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_Q_SCR_00_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_Q_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_Q_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Q_SCR_00_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_00_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_Q_SCR_00_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_Q_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_Q_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Q_SCR_00_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_00_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_Q_SCR_00_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_Q_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_Q_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Q_SCR_00_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_00_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_Q_SCR_00_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_Q_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_Q_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Q_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Q_SCR_00_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_Q_SCR_00_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_00_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_Q_SCR_00_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_PR7_SHIFT)
#define GPIO_Q_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_Q_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_00_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_Q_SCR_00_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_PR6_SHIFT)
#define GPIO_Q_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_Q_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_00_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_Q_SCR_00_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_PR5_SHIFT)
#define GPIO_Q_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_Q_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_00_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_Q_SCR_00_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_PR4_SHIFT)
#define GPIO_Q_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_Q_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_00_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_Q_SCR_00_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_PR3_SHIFT)
#define GPIO_Q_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_Q_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_00_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_Q_SCR_00_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_PR2_SHIFT)
#define GPIO_Q_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_Q_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_00_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_Q_SCR_00_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_PR1_SHIFT)
#define GPIO_Q_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_Q_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_00_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_Q_SCR_00_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_PR0_SHIFT)
#define GPIO_Q_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_Q_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_00_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_Q_SCR_00_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G7W_SHIFT)
#define GPIO_Q_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_Q_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_00_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_Q_SCR_00_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G6W_SHIFT)
#define GPIO_Q_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_Q_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_00_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_Q_SCR_00_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G5W_SHIFT)
#define GPIO_Q_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_Q_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_00_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_Q_SCR_00_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G4W_SHIFT)
#define GPIO_Q_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_Q_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_00_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_Q_SCR_00_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G3W_SHIFT)
#define GPIO_Q_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_Q_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_00_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_Q_SCR_00_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G2W_SHIFT)
#define GPIO_Q_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_Q_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_00_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_Q_SCR_00_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G1W_SHIFT)
#define GPIO_Q_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_Q_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_00_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_Q_SCR_00_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G0W_SHIFT)
#define GPIO_Q_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_Q_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_00_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_Q_SCR_00_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G7R_SHIFT)
#define GPIO_Q_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_Q_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_00_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_Q_SCR_00_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G6R_SHIFT)
#define GPIO_Q_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_Q_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_00_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Q_SCR_00_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G5R_SHIFT)
#define GPIO_Q_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_Q_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_00_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_Q_SCR_00_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G4R_SHIFT)
#define GPIO_Q_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_Q_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_00_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_Q_SCR_00_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G3R_SHIFT)
#define GPIO_Q_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_Q_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_00_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_Q_SCR_00_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G2R_SHIFT)
#define GPIO_Q_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_Q_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_00_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_Q_SCR_00_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G1R_SHIFT)
#define GPIO_Q_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_Q_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_00_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Q_SCR_00_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G0R_SHIFT)
#define GPIO_Q_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_Q_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_Q_VM_01_0
#define GPIO_Q_VM_01_0                  _MK_ADDR_CONST(0x2188)
#define GPIO_Q_VM_01_0_SECURE                   0x0
#define GPIO_Q_VM_01_0_DUAL                     0x0
#define GPIO_Q_VM_01_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_Q_VM_01_0_WORD_COUNT                       0x1
#define GPIO_Q_VM_01_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_01_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_01_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_01_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Q_VM_01_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_01_0_VM1_SHIFT)
#define GPIO_Q_VM_01_0_VM1_RANGE                        1:0
#define GPIO_Q_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_Q_VM_01_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_01_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_01_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_01_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_Q_VM_01_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_01_0_VM2_SHIFT)
#define GPIO_Q_VM_01_0_VM2_RANGE                        3:2
#define GPIO_Q_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_Q_VM_01_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_01_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_01_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_01_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_Q_VM_01_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_01_0_VM3_SHIFT)
#define GPIO_Q_VM_01_0_VM3_RANGE                        5:4
#define GPIO_Q_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_Q_VM_01_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_01_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_01_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_01_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_Q_VM_01_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_01_0_VM4_SHIFT)
#define GPIO_Q_VM_01_0_VM4_RANGE                        7:6
#define GPIO_Q_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_Q_VM_01_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_01_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_01_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_01_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_Q_VM_01_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_01_0_VM5_SHIFT)
#define GPIO_Q_VM_01_0_VM5_RANGE                        9:8
#define GPIO_Q_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_Q_VM_01_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_01_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_01_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_01_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_Q_VM_01_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_01_0_VM6_SHIFT)
#define GPIO_Q_VM_01_0_VM6_RANGE                        11:10
#define GPIO_Q_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_Q_VM_01_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_01_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_01_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_01_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_Q_VM_01_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_01_0_VM7_SHIFT)
#define GPIO_Q_VM_01_0_VM7_RANGE                        13:12
#define GPIO_Q_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_Q_VM_01_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_01_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_01_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_01_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_Q_VM_01_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_01_0_VM8_SHIFT)
#define GPIO_Q_VM_01_0_VM8_RANGE                        15:14
#define GPIO_Q_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_Q_VM_01_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_01_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_01_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_Q_SCR_01_0
#define GPIO_Q_SCR_01_0                 _MK_ADDR_CONST(0x218c)
#define GPIO_Q_SCR_01_0_SECURE                  0x0
#define GPIO_Q_SCR_01_0_DUAL                    0x0
#define GPIO_Q_SCR_01_0_SCR                     0
#define GPIO_Q_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_Q_SCR_01_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_01_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_01_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_01_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_Q_SCR_01_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_Q_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_Q_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Q_SCR_01_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_01_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_Q_SCR_01_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_Q_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_Q_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Q_SCR_01_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_01_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_Q_SCR_01_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_Q_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_Q_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Q_SCR_01_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_01_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_Q_SCR_01_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_Q_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_Q_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Q_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Q_SCR_01_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_Q_SCR_01_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_01_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_Q_SCR_01_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_PR7_SHIFT)
#define GPIO_Q_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_Q_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_01_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_Q_SCR_01_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_PR6_SHIFT)
#define GPIO_Q_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_Q_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_01_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_Q_SCR_01_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_PR5_SHIFT)
#define GPIO_Q_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_Q_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_01_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_Q_SCR_01_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_PR4_SHIFT)
#define GPIO_Q_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_Q_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_01_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_Q_SCR_01_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_PR3_SHIFT)
#define GPIO_Q_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_Q_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_01_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_Q_SCR_01_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_PR2_SHIFT)
#define GPIO_Q_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_Q_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_01_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_Q_SCR_01_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_PR1_SHIFT)
#define GPIO_Q_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_Q_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_01_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_Q_SCR_01_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_PR0_SHIFT)
#define GPIO_Q_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_Q_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_01_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_Q_SCR_01_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G7W_SHIFT)
#define GPIO_Q_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_Q_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_01_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_Q_SCR_01_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G6W_SHIFT)
#define GPIO_Q_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_Q_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_01_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_Q_SCR_01_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G5W_SHIFT)
#define GPIO_Q_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_Q_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_01_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_Q_SCR_01_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G4W_SHIFT)
#define GPIO_Q_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_Q_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_01_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_Q_SCR_01_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G3W_SHIFT)
#define GPIO_Q_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_Q_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_01_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_Q_SCR_01_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G2W_SHIFT)
#define GPIO_Q_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_Q_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_01_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_Q_SCR_01_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G1W_SHIFT)
#define GPIO_Q_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_Q_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_01_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_Q_SCR_01_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G0W_SHIFT)
#define GPIO_Q_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_Q_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_01_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_Q_SCR_01_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G7R_SHIFT)
#define GPIO_Q_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_Q_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_01_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_Q_SCR_01_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G6R_SHIFT)
#define GPIO_Q_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_Q_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_01_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Q_SCR_01_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G5R_SHIFT)
#define GPIO_Q_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_Q_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_01_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_Q_SCR_01_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G4R_SHIFT)
#define GPIO_Q_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_Q_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_01_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_Q_SCR_01_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G3R_SHIFT)
#define GPIO_Q_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_Q_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_01_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_Q_SCR_01_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G2R_SHIFT)
#define GPIO_Q_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_Q_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_01_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_Q_SCR_01_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G1R_SHIFT)
#define GPIO_Q_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_Q_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_01_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Q_SCR_01_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G0R_SHIFT)
#define GPIO_Q_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_Q_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_Q_VM_02_0
#define GPIO_Q_VM_02_0                  _MK_ADDR_CONST(0x2190)
#define GPIO_Q_VM_02_0_SECURE                   0x0
#define GPIO_Q_VM_02_0_DUAL                     0x0
#define GPIO_Q_VM_02_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_Q_VM_02_0_WORD_COUNT                       0x1
#define GPIO_Q_VM_02_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_02_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_02_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_02_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Q_VM_02_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_02_0_VM1_SHIFT)
#define GPIO_Q_VM_02_0_VM1_RANGE                        1:0
#define GPIO_Q_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_Q_VM_02_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_02_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_02_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_02_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_Q_VM_02_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_02_0_VM2_SHIFT)
#define GPIO_Q_VM_02_0_VM2_RANGE                        3:2
#define GPIO_Q_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_Q_VM_02_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_02_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_02_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_02_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_Q_VM_02_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_02_0_VM3_SHIFT)
#define GPIO_Q_VM_02_0_VM3_RANGE                        5:4
#define GPIO_Q_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_Q_VM_02_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_02_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_02_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_02_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_Q_VM_02_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_02_0_VM4_SHIFT)
#define GPIO_Q_VM_02_0_VM4_RANGE                        7:6
#define GPIO_Q_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_Q_VM_02_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_02_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_02_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_02_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_Q_VM_02_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_02_0_VM5_SHIFT)
#define GPIO_Q_VM_02_0_VM5_RANGE                        9:8
#define GPIO_Q_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_Q_VM_02_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_02_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_02_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_02_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_Q_VM_02_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_02_0_VM6_SHIFT)
#define GPIO_Q_VM_02_0_VM6_RANGE                        11:10
#define GPIO_Q_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_Q_VM_02_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_02_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_02_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_02_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_Q_VM_02_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_02_0_VM7_SHIFT)
#define GPIO_Q_VM_02_0_VM7_RANGE                        13:12
#define GPIO_Q_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_Q_VM_02_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_02_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_02_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_02_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_Q_VM_02_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_02_0_VM8_SHIFT)
#define GPIO_Q_VM_02_0_VM8_RANGE                        15:14
#define GPIO_Q_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_Q_VM_02_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_02_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_02_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_Q_SCR_02_0
#define GPIO_Q_SCR_02_0                 _MK_ADDR_CONST(0x2194)
#define GPIO_Q_SCR_02_0_SECURE                  0x0
#define GPIO_Q_SCR_02_0_DUAL                    0x0
#define GPIO_Q_SCR_02_0_SCR                     0
#define GPIO_Q_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_Q_SCR_02_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_02_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_02_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_02_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_Q_SCR_02_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_Q_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_Q_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Q_SCR_02_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_02_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_Q_SCR_02_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_Q_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_Q_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Q_SCR_02_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_02_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_Q_SCR_02_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_Q_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_Q_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Q_SCR_02_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_02_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_Q_SCR_02_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_Q_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_Q_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Q_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Q_SCR_02_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_Q_SCR_02_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_02_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_Q_SCR_02_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_PR7_SHIFT)
#define GPIO_Q_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_Q_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_02_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_Q_SCR_02_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_PR6_SHIFT)
#define GPIO_Q_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_Q_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_02_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_Q_SCR_02_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_PR5_SHIFT)
#define GPIO_Q_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_Q_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_02_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_Q_SCR_02_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_PR4_SHIFT)
#define GPIO_Q_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_Q_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_02_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_Q_SCR_02_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_PR3_SHIFT)
#define GPIO_Q_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_Q_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_02_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_Q_SCR_02_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_PR2_SHIFT)
#define GPIO_Q_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_Q_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_02_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_Q_SCR_02_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_PR1_SHIFT)
#define GPIO_Q_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_Q_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_02_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_Q_SCR_02_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_PR0_SHIFT)
#define GPIO_Q_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_Q_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_02_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_Q_SCR_02_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G7W_SHIFT)
#define GPIO_Q_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_Q_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_02_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_Q_SCR_02_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G6W_SHIFT)
#define GPIO_Q_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_Q_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_02_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_Q_SCR_02_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G5W_SHIFT)
#define GPIO_Q_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_Q_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_02_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_Q_SCR_02_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G4W_SHIFT)
#define GPIO_Q_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_Q_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_02_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_Q_SCR_02_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G3W_SHIFT)
#define GPIO_Q_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_Q_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_02_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_Q_SCR_02_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G2W_SHIFT)
#define GPIO_Q_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_Q_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_02_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_Q_SCR_02_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G1W_SHIFT)
#define GPIO_Q_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_Q_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_02_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_Q_SCR_02_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G0W_SHIFT)
#define GPIO_Q_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_Q_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_02_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_Q_SCR_02_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G7R_SHIFT)
#define GPIO_Q_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_Q_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_02_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_Q_SCR_02_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G6R_SHIFT)
#define GPIO_Q_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_Q_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_02_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Q_SCR_02_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G5R_SHIFT)
#define GPIO_Q_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_Q_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_02_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_Q_SCR_02_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G4R_SHIFT)
#define GPIO_Q_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_Q_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_02_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_Q_SCR_02_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G3R_SHIFT)
#define GPIO_Q_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_Q_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_02_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_Q_SCR_02_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G2R_SHIFT)
#define GPIO_Q_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_Q_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_02_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_Q_SCR_02_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G1R_SHIFT)
#define GPIO_Q_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_Q_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_02_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Q_SCR_02_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G0R_SHIFT)
#define GPIO_Q_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_Q_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_Q_VM_03_0
#define GPIO_Q_VM_03_0                  _MK_ADDR_CONST(0x2198)
#define GPIO_Q_VM_03_0_SECURE                   0x0
#define GPIO_Q_VM_03_0_DUAL                     0x0
#define GPIO_Q_VM_03_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_Q_VM_03_0_WORD_COUNT                       0x1
#define GPIO_Q_VM_03_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_03_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_03_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_03_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Q_VM_03_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_03_0_VM1_SHIFT)
#define GPIO_Q_VM_03_0_VM1_RANGE                        1:0
#define GPIO_Q_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_Q_VM_03_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_03_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_03_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_03_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_Q_VM_03_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_03_0_VM2_SHIFT)
#define GPIO_Q_VM_03_0_VM2_RANGE                        3:2
#define GPIO_Q_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_Q_VM_03_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_03_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_03_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_03_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_Q_VM_03_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_03_0_VM3_SHIFT)
#define GPIO_Q_VM_03_0_VM3_RANGE                        5:4
#define GPIO_Q_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_Q_VM_03_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_03_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_03_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_03_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_Q_VM_03_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_03_0_VM4_SHIFT)
#define GPIO_Q_VM_03_0_VM4_RANGE                        7:6
#define GPIO_Q_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_Q_VM_03_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_03_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_03_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_03_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_Q_VM_03_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_03_0_VM5_SHIFT)
#define GPIO_Q_VM_03_0_VM5_RANGE                        9:8
#define GPIO_Q_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_Q_VM_03_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_03_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_03_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_03_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_Q_VM_03_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_03_0_VM6_SHIFT)
#define GPIO_Q_VM_03_0_VM6_RANGE                        11:10
#define GPIO_Q_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_Q_VM_03_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_03_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_03_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_03_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_Q_VM_03_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_03_0_VM7_SHIFT)
#define GPIO_Q_VM_03_0_VM7_RANGE                        13:12
#define GPIO_Q_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_Q_VM_03_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_03_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_03_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_03_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_Q_VM_03_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_03_0_VM8_SHIFT)
#define GPIO_Q_VM_03_0_VM8_RANGE                        15:14
#define GPIO_Q_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_Q_VM_03_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_03_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_03_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_Q_SCR_03_0
#define GPIO_Q_SCR_03_0                 _MK_ADDR_CONST(0x219c)
#define GPIO_Q_SCR_03_0_SECURE                  0x0
#define GPIO_Q_SCR_03_0_DUAL                    0x0
#define GPIO_Q_SCR_03_0_SCR                     0
#define GPIO_Q_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_Q_SCR_03_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_03_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_03_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_03_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_Q_SCR_03_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_Q_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_Q_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Q_SCR_03_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_03_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_Q_SCR_03_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_Q_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_Q_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Q_SCR_03_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_03_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_Q_SCR_03_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_Q_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_Q_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Q_SCR_03_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_03_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_Q_SCR_03_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_Q_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_Q_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Q_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Q_SCR_03_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_Q_SCR_03_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_03_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_Q_SCR_03_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_PR7_SHIFT)
#define GPIO_Q_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_Q_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_03_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_Q_SCR_03_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_PR6_SHIFT)
#define GPIO_Q_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_Q_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_03_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_Q_SCR_03_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_PR5_SHIFT)
#define GPIO_Q_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_Q_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_03_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_Q_SCR_03_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_PR4_SHIFT)
#define GPIO_Q_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_Q_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_03_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_Q_SCR_03_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_PR3_SHIFT)
#define GPIO_Q_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_Q_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_03_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_Q_SCR_03_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_PR2_SHIFT)
#define GPIO_Q_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_Q_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_03_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_Q_SCR_03_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_PR1_SHIFT)
#define GPIO_Q_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_Q_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_03_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_Q_SCR_03_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_PR0_SHIFT)
#define GPIO_Q_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_Q_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_03_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_Q_SCR_03_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G7W_SHIFT)
#define GPIO_Q_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_Q_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_03_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_Q_SCR_03_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G6W_SHIFT)
#define GPIO_Q_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_Q_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_03_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_Q_SCR_03_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G5W_SHIFT)
#define GPIO_Q_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_Q_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_03_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_Q_SCR_03_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G4W_SHIFT)
#define GPIO_Q_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_Q_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_03_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_Q_SCR_03_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G3W_SHIFT)
#define GPIO_Q_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_Q_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_03_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_Q_SCR_03_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G2W_SHIFT)
#define GPIO_Q_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_Q_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_03_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_Q_SCR_03_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G1W_SHIFT)
#define GPIO_Q_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_Q_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_03_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_Q_SCR_03_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G0W_SHIFT)
#define GPIO_Q_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_Q_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_03_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_Q_SCR_03_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G7R_SHIFT)
#define GPIO_Q_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_Q_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_03_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_Q_SCR_03_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G6R_SHIFT)
#define GPIO_Q_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_Q_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_03_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Q_SCR_03_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G5R_SHIFT)
#define GPIO_Q_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_Q_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_03_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_Q_SCR_03_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G4R_SHIFT)
#define GPIO_Q_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_Q_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_03_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_Q_SCR_03_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G3R_SHIFT)
#define GPIO_Q_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_Q_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_03_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_Q_SCR_03_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G2R_SHIFT)
#define GPIO_Q_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_Q_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_03_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_Q_SCR_03_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G1R_SHIFT)
#define GPIO_Q_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_Q_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_03_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Q_SCR_03_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G0R_SHIFT)
#define GPIO_Q_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_Q_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_Q_VM_04_0
#define GPIO_Q_VM_04_0                  _MK_ADDR_CONST(0x21a0)
#define GPIO_Q_VM_04_0_SECURE                   0x0
#define GPIO_Q_VM_04_0_DUAL                     0x0
#define GPIO_Q_VM_04_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_Q_VM_04_0_WORD_COUNT                       0x1
#define GPIO_Q_VM_04_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_04_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_04_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_04_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Q_VM_04_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_04_0_VM1_SHIFT)
#define GPIO_Q_VM_04_0_VM1_RANGE                        1:0
#define GPIO_Q_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_Q_VM_04_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_04_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_04_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_04_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_Q_VM_04_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_04_0_VM2_SHIFT)
#define GPIO_Q_VM_04_0_VM2_RANGE                        3:2
#define GPIO_Q_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_Q_VM_04_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_04_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_04_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_04_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_Q_VM_04_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_04_0_VM3_SHIFT)
#define GPIO_Q_VM_04_0_VM3_RANGE                        5:4
#define GPIO_Q_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_Q_VM_04_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_04_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_04_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_04_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_Q_VM_04_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_04_0_VM4_SHIFT)
#define GPIO_Q_VM_04_0_VM4_RANGE                        7:6
#define GPIO_Q_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_Q_VM_04_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_04_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_04_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_04_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_Q_VM_04_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_04_0_VM5_SHIFT)
#define GPIO_Q_VM_04_0_VM5_RANGE                        9:8
#define GPIO_Q_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_Q_VM_04_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_04_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_04_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_04_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_Q_VM_04_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_04_0_VM6_SHIFT)
#define GPIO_Q_VM_04_0_VM6_RANGE                        11:10
#define GPIO_Q_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_Q_VM_04_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_04_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_04_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_04_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_Q_VM_04_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_04_0_VM7_SHIFT)
#define GPIO_Q_VM_04_0_VM7_RANGE                        13:12
#define GPIO_Q_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_Q_VM_04_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_04_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_04_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_04_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_Q_VM_04_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_04_0_VM8_SHIFT)
#define GPIO_Q_VM_04_0_VM8_RANGE                        15:14
#define GPIO_Q_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_Q_VM_04_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_04_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_04_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_Q_SCR_04_0
#define GPIO_Q_SCR_04_0                 _MK_ADDR_CONST(0x21a4)
#define GPIO_Q_SCR_04_0_SECURE                  0x0
#define GPIO_Q_SCR_04_0_DUAL                    0x0
#define GPIO_Q_SCR_04_0_SCR                     0
#define GPIO_Q_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_Q_SCR_04_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_04_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_04_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_04_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_Q_SCR_04_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_Q_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_Q_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Q_SCR_04_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_04_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_Q_SCR_04_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_Q_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_Q_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Q_SCR_04_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_04_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_Q_SCR_04_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_Q_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_Q_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Q_SCR_04_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_04_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_Q_SCR_04_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_Q_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_Q_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Q_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Q_SCR_04_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_Q_SCR_04_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_04_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_Q_SCR_04_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_PR7_SHIFT)
#define GPIO_Q_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_Q_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_04_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_Q_SCR_04_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_PR6_SHIFT)
#define GPIO_Q_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_Q_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_04_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_Q_SCR_04_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_PR5_SHIFT)
#define GPIO_Q_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_Q_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_04_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_Q_SCR_04_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_PR4_SHIFT)
#define GPIO_Q_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_Q_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_04_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_Q_SCR_04_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_PR3_SHIFT)
#define GPIO_Q_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_Q_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_04_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_Q_SCR_04_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_PR2_SHIFT)
#define GPIO_Q_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_Q_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_04_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_Q_SCR_04_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_PR1_SHIFT)
#define GPIO_Q_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_Q_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_04_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_Q_SCR_04_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_PR0_SHIFT)
#define GPIO_Q_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_Q_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_04_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_Q_SCR_04_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G7W_SHIFT)
#define GPIO_Q_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_Q_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_04_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_Q_SCR_04_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G6W_SHIFT)
#define GPIO_Q_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_Q_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_04_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_Q_SCR_04_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G5W_SHIFT)
#define GPIO_Q_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_Q_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_04_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_Q_SCR_04_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G4W_SHIFT)
#define GPIO_Q_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_Q_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_04_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_Q_SCR_04_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G3W_SHIFT)
#define GPIO_Q_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_Q_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_04_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_Q_SCR_04_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G2W_SHIFT)
#define GPIO_Q_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_Q_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_04_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_Q_SCR_04_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G1W_SHIFT)
#define GPIO_Q_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_Q_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_04_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_Q_SCR_04_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G0W_SHIFT)
#define GPIO_Q_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_Q_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_04_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_Q_SCR_04_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G7R_SHIFT)
#define GPIO_Q_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_Q_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_04_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_Q_SCR_04_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G6R_SHIFT)
#define GPIO_Q_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_Q_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_04_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Q_SCR_04_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G5R_SHIFT)
#define GPIO_Q_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_Q_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_04_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_Q_SCR_04_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G4R_SHIFT)
#define GPIO_Q_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_Q_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_04_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_Q_SCR_04_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G3R_SHIFT)
#define GPIO_Q_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_Q_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_04_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_Q_SCR_04_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G2R_SHIFT)
#define GPIO_Q_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_Q_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_04_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_Q_SCR_04_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G1R_SHIFT)
#define GPIO_Q_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_Q_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_04_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Q_SCR_04_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G0R_SHIFT)
#define GPIO_Q_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_Q_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_Q_VM_05_0
#define GPIO_Q_VM_05_0                  _MK_ADDR_CONST(0x21a8)
#define GPIO_Q_VM_05_0_SECURE                   0x0
#define GPIO_Q_VM_05_0_DUAL                     0x0
#define GPIO_Q_VM_05_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_Q_VM_05_0_WORD_COUNT                       0x1
#define GPIO_Q_VM_05_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_05_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_05_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_05_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Q_VM_05_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_05_0_VM1_SHIFT)
#define GPIO_Q_VM_05_0_VM1_RANGE                        1:0
#define GPIO_Q_VM_05_0_VM1_WOFFSET                      0x0
#define GPIO_Q_VM_05_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_05_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_05_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_05_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_Q_VM_05_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_05_0_VM2_SHIFT)
#define GPIO_Q_VM_05_0_VM2_RANGE                        3:2
#define GPIO_Q_VM_05_0_VM2_WOFFSET                      0x0
#define GPIO_Q_VM_05_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_05_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_05_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_05_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_Q_VM_05_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_05_0_VM3_SHIFT)
#define GPIO_Q_VM_05_0_VM3_RANGE                        5:4
#define GPIO_Q_VM_05_0_VM3_WOFFSET                      0x0
#define GPIO_Q_VM_05_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_05_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_05_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_05_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_Q_VM_05_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_05_0_VM4_SHIFT)
#define GPIO_Q_VM_05_0_VM4_RANGE                        7:6
#define GPIO_Q_VM_05_0_VM4_WOFFSET                      0x0
#define GPIO_Q_VM_05_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_05_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_05_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_05_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_Q_VM_05_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_05_0_VM5_SHIFT)
#define GPIO_Q_VM_05_0_VM5_RANGE                        9:8
#define GPIO_Q_VM_05_0_VM5_WOFFSET                      0x0
#define GPIO_Q_VM_05_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_05_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_05_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_05_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_Q_VM_05_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_05_0_VM6_SHIFT)
#define GPIO_Q_VM_05_0_VM6_RANGE                        11:10
#define GPIO_Q_VM_05_0_VM6_WOFFSET                      0x0
#define GPIO_Q_VM_05_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_05_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_05_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_05_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_Q_VM_05_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_05_0_VM7_SHIFT)
#define GPIO_Q_VM_05_0_VM7_RANGE                        13:12
#define GPIO_Q_VM_05_0_VM7_WOFFSET                      0x0
#define GPIO_Q_VM_05_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_05_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_05_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_05_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_Q_VM_05_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_05_0_VM8_SHIFT)
#define GPIO_Q_VM_05_0_VM8_RANGE                        15:14
#define GPIO_Q_VM_05_0_VM8_WOFFSET                      0x0
#define GPIO_Q_VM_05_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_05_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_05_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_Q_SCR_05_0
#define GPIO_Q_SCR_05_0                 _MK_ADDR_CONST(0x21ac)
#define GPIO_Q_SCR_05_0_SECURE                  0x0
#define GPIO_Q_SCR_05_0_DUAL                    0x0
#define GPIO_Q_SCR_05_0_SCR                     0
#define GPIO_Q_SCR_05_0_WORD_COUNT                      0x1
#define GPIO_Q_SCR_05_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_05_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_05_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_05_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_Q_SCR_05_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_Q_SCR_05_0_SEC_LCK_RANGE                   29:29
#define GPIO_Q_SCR_05_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Q_SCR_05_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_05_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_Q_SCR_05_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_Q_SCR_05_0_SEC_WEN_RANGE                   28:28
#define GPIO_Q_SCR_05_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Q_SCR_05_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_05_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_Q_SCR_05_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_Q_SCR_05_0_SEC_REN_RANGE                   27:27
#define GPIO_Q_SCR_05_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Q_SCR_05_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_05_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_Q_SCR_05_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_Q_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_Q_SCR_05_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Q_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Q_SCR_05_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_Q_SCR_05_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_05_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_Q_SCR_05_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_PR7_SHIFT)
#define GPIO_Q_SCR_05_0_PR7_RANGE                       23:23
#define GPIO_Q_SCR_05_0_PR7_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_05_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_Q_SCR_05_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_PR6_SHIFT)
#define GPIO_Q_SCR_05_0_PR6_RANGE                       22:22
#define GPIO_Q_SCR_05_0_PR6_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_05_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_Q_SCR_05_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_PR5_SHIFT)
#define GPIO_Q_SCR_05_0_PR5_RANGE                       21:21
#define GPIO_Q_SCR_05_0_PR5_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_05_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_Q_SCR_05_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_PR4_SHIFT)
#define GPIO_Q_SCR_05_0_PR4_RANGE                       20:20
#define GPIO_Q_SCR_05_0_PR4_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_05_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_Q_SCR_05_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_PR3_SHIFT)
#define GPIO_Q_SCR_05_0_PR3_RANGE                       19:19
#define GPIO_Q_SCR_05_0_PR3_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_05_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_Q_SCR_05_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_PR2_SHIFT)
#define GPIO_Q_SCR_05_0_PR2_RANGE                       18:18
#define GPIO_Q_SCR_05_0_PR2_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_05_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_Q_SCR_05_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_PR1_SHIFT)
#define GPIO_Q_SCR_05_0_PR1_RANGE                       17:17
#define GPIO_Q_SCR_05_0_PR1_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_05_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_Q_SCR_05_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_PR0_SHIFT)
#define GPIO_Q_SCR_05_0_PR0_RANGE                       16:16
#define GPIO_Q_SCR_05_0_PR0_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_05_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_Q_SCR_05_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G7W_SHIFT)
#define GPIO_Q_SCR_05_0_G7W_RANGE                       15:15
#define GPIO_Q_SCR_05_0_G7W_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_05_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_Q_SCR_05_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G6W_SHIFT)
#define GPIO_Q_SCR_05_0_G6W_RANGE                       14:14
#define GPIO_Q_SCR_05_0_G6W_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_05_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_Q_SCR_05_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G5W_SHIFT)
#define GPIO_Q_SCR_05_0_G5W_RANGE                       13:13
#define GPIO_Q_SCR_05_0_G5W_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_05_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_Q_SCR_05_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G4W_SHIFT)
#define GPIO_Q_SCR_05_0_G4W_RANGE                       12:12
#define GPIO_Q_SCR_05_0_G4W_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_05_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_Q_SCR_05_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G3W_SHIFT)
#define GPIO_Q_SCR_05_0_G3W_RANGE                       11:11
#define GPIO_Q_SCR_05_0_G3W_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_05_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_Q_SCR_05_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G2W_SHIFT)
#define GPIO_Q_SCR_05_0_G2W_RANGE                       10:10
#define GPIO_Q_SCR_05_0_G2W_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_05_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_Q_SCR_05_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G1W_SHIFT)
#define GPIO_Q_SCR_05_0_G1W_RANGE                       9:9
#define GPIO_Q_SCR_05_0_G1W_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_05_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_Q_SCR_05_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G0W_SHIFT)
#define GPIO_Q_SCR_05_0_G0W_RANGE                       8:8
#define GPIO_Q_SCR_05_0_G0W_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_05_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_Q_SCR_05_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G7R_SHIFT)
#define GPIO_Q_SCR_05_0_G7R_RANGE                       7:7
#define GPIO_Q_SCR_05_0_G7R_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_05_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_Q_SCR_05_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G6R_SHIFT)
#define GPIO_Q_SCR_05_0_G6R_RANGE                       6:6
#define GPIO_Q_SCR_05_0_G6R_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_05_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Q_SCR_05_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G5R_SHIFT)
#define GPIO_Q_SCR_05_0_G5R_RANGE                       5:5
#define GPIO_Q_SCR_05_0_G5R_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_05_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_Q_SCR_05_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G4R_SHIFT)
#define GPIO_Q_SCR_05_0_G4R_RANGE                       4:4
#define GPIO_Q_SCR_05_0_G4R_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_05_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_Q_SCR_05_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G3R_SHIFT)
#define GPIO_Q_SCR_05_0_G3R_RANGE                       3:3
#define GPIO_Q_SCR_05_0_G3R_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_05_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_Q_SCR_05_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G2R_SHIFT)
#define GPIO_Q_SCR_05_0_G2R_RANGE                       2:2
#define GPIO_Q_SCR_05_0_G2R_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_05_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_Q_SCR_05_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G1R_SHIFT)
#define GPIO_Q_SCR_05_0_G1R_RANGE                       1:1
#define GPIO_Q_SCR_05_0_G1R_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_05_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Q_SCR_05_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G0R_SHIFT)
#define GPIO_Q_SCR_05_0_G0R_RANGE                       0:0
#define GPIO_Q_SCR_05_0_G0R_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_Q_VM_06_0
#define GPIO_Q_VM_06_0                  _MK_ADDR_CONST(0x21b0)
#define GPIO_Q_VM_06_0_SECURE                   0x0
#define GPIO_Q_VM_06_0_DUAL                     0x0
#define GPIO_Q_VM_06_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_Q_VM_06_0_WORD_COUNT                       0x1
#define GPIO_Q_VM_06_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_06_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_06_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_06_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_06_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_06_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_06_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Q_VM_06_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_06_0_VM1_SHIFT)
#define GPIO_Q_VM_06_0_VM1_RANGE                        1:0
#define GPIO_Q_VM_06_0_VM1_WOFFSET                      0x0
#define GPIO_Q_VM_06_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_06_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_06_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_06_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_06_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_06_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_06_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_Q_VM_06_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_06_0_VM2_SHIFT)
#define GPIO_Q_VM_06_0_VM2_RANGE                        3:2
#define GPIO_Q_VM_06_0_VM2_WOFFSET                      0x0
#define GPIO_Q_VM_06_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_06_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_06_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_06_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_06_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_06_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_06_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_Q_VM_06_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_06_0_VM3_SHIFT)
#define GPIO_Q_VM_06_0_VM3_RANGE                        5:4
#define GPIO_Q_VM_06_0_VM3_WOFFSET                      0x0
#define GPIO_Q_VM_06_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_06_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_06_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_06_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_06_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_06_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_06_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_Q_VM_06_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_06_0_VM4_SHIFT)
#define GPIO_Q_VM_06_0_VM4_RANGE                        7:6
#define GPIO_Q_VM_06_0_VM4_WOFFSET                      0x0
#define GPIO_Q_VM_06_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_06_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_06_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_06_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_06_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_06_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_06_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_Q_VM_06_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_06_0_VM5_SHIFT)
#define GPIO_Q_VM_06_0_VM5_RANGE                        9:8
#define GPIO_Q_VM_06_0_VM5_WOFFSET                      0x0
#define GPIO_Q_VM_06_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_06_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_06_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_06_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_06_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_06_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_06_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_Q_VM_06_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_06_0_VM6_SHIFT)
#define GPIO_Q_VM_06_0_VM6_RANGE                        11:10
#define GPIO_Q_VM_06_0_VM6_WOFFSET                      0x0
#define GPIO_Q_VM_06_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_06_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_06_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_06_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_06_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_06_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_06_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_Q_VM_06_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_06_0_VM7_SHIFT)
#define GPIO_Q_VM_06_0_VM7_RANGE                        13:12
#define GPIO_Q_VM_06_0_VM7_WOFFSET                      0x0
#define GPIO_Q_VM_06_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_06_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_06_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_06_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_06_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_06_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_06_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_Q_VM_06_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_06_0_VM8_SHIFT)
#define GPIO_Q_VM_06_0_VM8_RANGE                        15:14
#define GPIO_Q_VM_06_0_VM8_WOFFSET                      0x0
#define GPIO_Q_VM_06_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_06_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_06_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_06_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_06_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_06_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_Q_SCR_06_0
#define GPIO_Q_SCR_06_0                 _MK_ADDR_CONST(0x21b4)
#define GPIO_Q_SCR_06_0_SECURE                  0x0
#define GPIO_Q_SCR_06_0_DUAL                    0x0
#define GPIO_Q_SCR_06_0_SCR                     0
#define GPIO_Q_SCR_06_0_WORD_COUNT                      0x1
#define GPIO_Q_SCR_06_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_06_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_06_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_06_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_Q_SCR_06_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_SEC_LCK_SHIFT)
#define GPIO_Q_SCR_06_0_SEC_LCK_RANGE                   29:29
#define GPIO_Q_SCR_06_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Q_SCR_06_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_06_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_06_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_Q_SCR_06_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_SEC_WEN_SHIFT)
#define GPIO_Q_SCR_06_0_SEC_WEN_RANGE                   28:28
#define GPIO_Q_SCR_06_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Q_SCR_06_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_06_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_06_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_Q_SCR_06_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_SEC_REN_SHIFT)
#define GPIO_Q_SCR_06_0_SEC_REN_RANGE                   27:27
#define GPIO_Q_SCR_06_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Q_SCR_06_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_06_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_06_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_Q_SCR_06_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_Q_SCR_06_0_SEC_OWNER_SHIFT)
#define GPIO_Q_SCR_06_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Q_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Q_SCR_06_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_Q_SCR_06_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_06_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_Q_SCR_06_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_PR7_SHIFT)
#define GPIO_Q_SCR_06_0_PR7_RANGE                       23:23
#define GPIO_Q_SCR_06_0_PR7_WOFFSET                     0x0
#define GPIO_Q_SCR_06_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_06_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_06_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_Q_SCR_06_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_PR6_SHIFT)
#define GPIO_Q_SCR_06_0_PR6_RANGE                       22:22
#define GPIO_Q_SCR_06_0_PR6_WOFFSET                     0x0
#define GPIO_Q_SCR_06_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_06_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_06_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_Q_SCR_06_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_PR5_SHIFT)
#define GPIO_Q_SCR_06_0_PR5_RANGE                       21:21
#define GPIO_Q_SCR_06_0_PR5_WOFFSET                     0x0
#define GPIO_Q_SCR_06_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_06_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_06_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_Q_SCR_06_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_PR4_SHIFT)
#define GPIO_Q_SCR_06_0_PR4_RANGE                       20:20
#define GPIO_Q_SCR_06_0_PR4_WOFFSET                     0x0
#define GPIO_Q_SCR_06_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_06_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_06_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_Q_SCR_06_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_PR3_SHIFT)
#define GPIO_Q_SCR_06_0_PR3_RANGE                       19:19
#define GPIO_Q_SCR_06_0_PR3_WOFFSET                     0x0
#define GPIO_Q_SCR_06_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_06_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_06_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_Q_SCR_06_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_PR2_SHIFT)
#define GPIO_Q_SCR_06_0_PR2_RANGE                       18:18
#define GPIO_Q_SCR_06_0_PR2_WOFFSET                     0x0
#define GPIO_Q_SCR_06_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_06_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_06_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_Q_SCR_06_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_PR1_SHIFT)
#define GPIO_Q_SCR_06_0_PR1_RANGE                       17:17
#define GPIO_Q_SCR_06_0_PR1_WOFFSET                     0x0
#define GPIO_Q_SCR_06_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_06_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_06_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_Q_SCR_06_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_PR0_SHIFT)
#define GPIO_Q_SCR_06_0_PR0_RANGE                       16:16
#define GPIO_Q_SCR_06_0_PR0_WOFFSET                     0x0
#define GPIO_Q_SCR_06_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_06_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_06_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_Q_SCR_06_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_G7W_SHIFT)
#define GPIO_Q_SCR_06_0_G7W_RANGE                       15:15
#define GPIO_Q_SCR_06_0_G7W_WOFFSET                     0x0
#define GPIO_Q_SCR_06_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_06_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_06_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_Q_SCR_06_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_G6W_SHIFT)
#define GPIO_Q_SCR_06_0_G6W_RANGE                       14:14
#define GPIO_Q_SCR_06_0_G6W_WOFFSET                     0x0
#define GPIO_Q_SCR_06_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_06_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_06_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_Q_SCR_06_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_G5W_SHIFT)
#define GPIO_Q_SCR_06_0_G5W_RANGE                       13:13
#define GPIO_Q_SCR_06_0_G5W_WOFFSET                     0x0
#define GPIO_Q_SCR_06_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_06_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_06_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_Q_SCR_06_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_G4W_SHIFT)
#define GPIO_Q_SCR_06_0_G4W_RANGE                       12:12
#define GPIO_Q_SCR_06_0_G4W_WOFFSET                     0x0
#define GPIO_Q_SCR_06_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_06_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_06_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_Q_SCR_06_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_G3W_SHIFT)
#define GPIO_Q_SCR_06_0_G3W_RANGE                       11:11
#define GPIO_Q_SCR_06_0_G3W_WOFFSET                     0x0
#define GPIO_Q_SCR_06_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_06_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_06_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_Q_SCR_06_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_G2W_SHIFT)
#define GPIO_Q_SCR_06_0_G2W_RANGE                       10:10
#define GPIO_Q_SCR_06_0_G2W_WOFFSET                     0x0
#define GPIO_Q_SCR_06_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_06_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_06_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_Q_SCR_06_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_G1W_SHIFT)
#define GPIO_Q_SCR_06_0_G1W_RANGE                       9:9
#define GPIO_Q_SCR_06_0_G1W_WOFFSET                     0x0
#define GPIO_Q_SCR_06_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_06_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_06_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_Q_SCR_06_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_G0W_SHIFT)
#define GPIO_Q_SCR_06_0_G0W_RANGE                       8:8
#define GPIO_Q_SCR_06_0_G0W_WOFFSET                     0x0
#define GPIO_Q_SCR_06_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_06_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_06_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_Q_SCR_06_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_G7R_SHIFT)
#define GPIO_Q_SCR_06_0_G7R_RANGE                       7:7
#define GPIO_Q_SCR_06_0_G7R_WOFFSET                     0x0
#define GPIO_Q_SCR_06_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_06_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_06_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_Q_SCR_06_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_G6R_SHIFT)
#define GPIO_Q_SCR_06_0_G6R_RANGE                       6:6
#define GPIO_Q_SCR_06_0_G6R_WOFFSET                     0x0
#define GPIO_Q_SCR_06_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_06_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_06_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Q_SCR_06_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_G5R_SHIFT)
#define GPIO_Q_SCR_06_0_G5R_RANGE                       5:5
#define GPIO_Q_SCR_06_0_G5R_WOFFSET                     0x0
#define GPIO_Q_SCR_06_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_06_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_06_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_Q_SCR_06_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_G4R_SHIFT)
#define GPIO_Q_SCR_06_0_G4R_RANGE                       4:4
#define GPIO_Q_SCR_06_0_G4R_WOFFSET                     0x0
#define GPIO_Q_SCR_06_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_06_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_06_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_Q_SCR_06_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_G3R_SHIFT)
#define GPIO_Q_SCR_06_0_G3R_RANGE                       3:3
#define GPIO_Q_SCR_06_0_G3R_WOFFSET                     0x0
#define GPIO_Q_SCR_06_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_06_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_06_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_Q_SCR_06_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_G2R_SHIFT)
#define GPIO_Q_SCR_06_0_G2R_RANGE                       2:2
#define GPIO_Q_SCR_06_0_G2R_WOFFSET                     0x0
#define GPIO_Q_SCR_06_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_06_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_06_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_Q_SCR_06_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_G1R_SHIFT)
#define GPIO_Q_SCR_06_0_G1R_RANGE                       1:1
#define GPIO_Q_SCR_06_0_G1R_WOFFSET                     0x0
#define GPIO_Q_SCR_06_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_06_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_06_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Q_SCR_06_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_G0R_SHIFT)
#define GPIO_Q_SCR_06_0_G0R_RANGE                       0:0
#define GPIO_Q_SCR_06_0_G0R_WOFFSET                     0x0
#define GPIO_Q_SCR_06_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_06_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_Q_VM_07_0
#define GPIO_Q_VM_07_0                  _MK_ADDR_CONST(0x21b8)
#define GPIO_Q_VM_07_0_SECURE                   0x0
#define GPIO_Q_VM_07_0_DUAL                     0x0
#define GPIO_Q_VM_07_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_Q_VM_07_0_WORD_COUNT                       0x1
#define GPIO_Q_VM_07_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_07_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_07_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_07_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_07_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_07_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_07_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Q_VM_07_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_07_0_VM1_SHIFT)
#define GPIO_Q_VM_07_0_VM1_RANGE                        1:0
#define GPIO_Q_VM_07_0_VM1_WOFFSET                      0x0
#define GPIO_Q_VM_07_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_07_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_07_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_07_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_07_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_07_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_07_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_Q_VM_07_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_07_0_VM2_SHIFT)
#define GPIO_Q_VM_07_0_VM2_RANGE                        3:2
#define GPIO_Q_VM_07_0_VM2_WOFFSET                      0x0
#define GPIO_Q_VM_07_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_07_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_07_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_07_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_07_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_07_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_07_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_Q_VM_07_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_07_0_VM3_SHIFT)
#define GPIO_Q_VM_07_0_VM3_RANGE                        5:4
#define GPIO_Q_VM_07_0_VM3_WOFFSET                      0x0
#define GPIO_Q_VM_07_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_07_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_07_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_07_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_07_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_07_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_07_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_Q_VM_07_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_07_0_VM4_SHIFT)
#define GPIO_Q_VM_07_0_VM4_RANGE                        7:6
#define GPIO_Q_VM_07_0_VM4_WOFFSET                      0x0
#define GPIO_Q_VM_07_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_07_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_07_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_07_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_07_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_07_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_07_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_Q_VM_07_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_07_0_VM5_SHIFT)
#define GPIO_Q_VM_07_0_VM5_RANGE                        9:8
#define GPIO_Q_VM_07_0_VM5_WOFFSET                      0x0
#define GPIO_Q_VM_07_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_07_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_07_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_07_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_07_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_07_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_07_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_Q_VM_07_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_07_0_VM6_SHIFT)
#define GPIO_Q_VM_07_0_VM6_RANGE                        11:10
#define GPIO_Q_VM_07_0_VM6_WOFFSET                      0x0
#define GPIO_Q_VM_07_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_07_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_07_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_07_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_07_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_07_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_07_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_Q_VM_07_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_07_0_VM7_SHIFT)
#define GPIO_Q_VM_07_0_VM7_RANGE                        13:12
#define GPIO_Q_VM_07_0_VM7_WOFFSET                      0x0
#define GPIO_Q_VM_07_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_07_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_07_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_07_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_07_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_07_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_Q_VM_07_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_Q_VM_07_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_Q_VM_07_0_VM8_SHIFT)
#define GPIO_Q_VM_07_0_VM8_RANGE                        15:14
#define GPIO_Q_VM_07_0_VM8_WOFFSET                      0x0
#define GPIO_Q_VM_07_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_07_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_Q_VM_07_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_07_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_07_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_VM_07_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_Q_SCR_07_0
#define GPIO_Q_SCR_07_0                 _MK_ADDR_CONST(0x21bc)
#define GPIO_Q_SCR_07_0_SECURE                  0x0
#define GPIO_Q_SCR_07_0_DUAL                    0x0
#define GPIO_Q_SCR_07_0_SCR                     0
#define GPIO_Q_SCR_07_0_WORD_COUNT                      0x1
#define GPIO_Q_SCR_07_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_07_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_07_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_07_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_Q_SCR_07_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_SEC_LCK_SHIFT)
#define GPIO_Q_SCR_07_0_SEC_LCK_RANGE                   29:29
#define GPIO_Q_SCR_07_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Q_SCR_07_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_07_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_07_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_Q_SCR_07_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_SEC_WEN_SHIFT)
#define GPIO_Q_SCR_07_0_SEC_WEN_RANGE                   28:28
#define GPIO_Q_SCR_07_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Q_SCR_07_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_07_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_07_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_Q_SCR_07_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_SEC_REN_SHIFT)
#define GPIO_Q_SCR_07_0_SEC_REN_RANGE                   27:27
#define GPIO_Q_SCR_07_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Q_SCR_07_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_07_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_07_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_Q_SCR_07_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_Q_SCR_07_0_SEC_OWNER_SHIFT)
#define GPIO_Q_SCR_07_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Q_SCR_07_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Q_SCR_07_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_Q_SCR_07_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_07_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_Q_SCR_07_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_PR7_SHIFT)
#define GPIO_Q_SCR_07_0_PR7_RANGE                       23:23
#define GPIO_Q_SCR_07_0_PR7_WOFFSET                     0x0
#define GPIO_Q_SCR_07_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_07_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_07_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_Q_SCR_07_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_PR6_SHIFT)
#define GPIO_Q_SCR_07_0_PR6_RANGE                       22:22
#define GPIO_Q_SCR_07_0_PR6_WOFFSET                     0x0
#define GPIO_Q_SCR_07_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_07_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_07_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_Q_SCR_07_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_PR5_SHIFT)
#define GPIO_Q_SCR_07_0_PR5_RANGE                       21:21
#define GPIO_Q_SCR_07_0_PR5_WOFFSET                     0x0
#define GPIO_Q_SCR_07_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_07_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_07_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_Q_SCR_07_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_PR4_SHIFT)
#define GPIO_Q_SCR_07_0_PR4_RANGE                       20:20
#define GPIO_Q_SCR_07_0_PR4_WOFFSET                     0x0
#define GPIO_Q_SCR_07_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_07_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_07_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_Q_SCR_07_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_PR3_SHIFT)
#define GPIO_Q_SCR_07_0_PR3_RANGE                       19:19
#define GPIO_Q_SCR_07_0_PR3_WOFFSET                     0x0
#define GPIO_Q_SCR_07_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_07_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_07_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_Q_SCR_07_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_PR2_SHIFT)
#define GPIO_Q_SCR_07_0_PR2_RANGE                       18:18
#define GPIO_Q_SCR_07_0_PR2_WOFFSET                     0x0
#define GPIO_Q_SCR_07_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_07_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_07_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_Q_SCR_07_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_PR1_SHIFT)
#define GPIO_Q_SCR_07_0_PR1_RANGE                       17:17
#define GPIO_Q_SCR_07_0_PR1_WOFFSET                     0x0
#define GPIO_Q_SCR_07_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_07_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_07_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_Q_SCR_07_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_PR0_SHIFT)
#define GPIO_Q_SCR_07_0_PR0_RANGE                       16:16
#define GPIO_Q_SCR_07_0_PR0_WOFFSET                     0x0
#define GPIO_Q_SCR_07_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_07_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_07_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_Q_SCR_07_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_G7W_SHIFT)
#define GPIO_Q_SCR_07_0_G7W_RANGE                       15:15
#define GPIO_Q_SCR_07_0_G7W_WOFFSET                     0x0
#define GPIO_Q_SCR_07_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_07_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_07_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_Q_SCR_07_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_G6W_SHIFT)
#define GPIO_Q_SCR_07_0_G6W_RANGE                       14:14
#define GPIO_Q_SCR_07_0_G6W_WOFFSET                     0x0
#define GPIO_Q_SCR_07_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_07_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_07_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_Q_SCR_07_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_G5W_SHIFT)
#define GPIO_Q_SCR_07_0_G5W_RANGE                       13:13
#define GPIO_Q_SCR_07_0_G5W_WOFFSET                     0x0
#define GPIO_Q_SCR_07_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_07_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_07_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_Q_SCR_07_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_G4W_SHIFT)
#define GPIO_Q_SCR_07_0_G4W_RANGE                       12:12
#define GPIO_Q_SCR_07_0_G4W_WOFFSET                     0x0
#define GPIO_Q_SCR_07_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_07_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_07_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_Q_SCR_07_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_G3W_SHIFT)
#define GPIO_Q_SCR_07_0_G3W_RANGE                       11:11
#define GPIO_Q_SCR_07_0_G3W_WOFFSET                     0x0
#define GPIO_Q_SCR_07_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_07_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_07_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_Q_SCR_07_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_G2W_SHIFT)
#define GPIO_Q_SCR_07_0_G2W_RANGE                       10:10
#define GPIO_Q_SCR_07_0_G2W_WOFFSET                     0x0
#define GPIO_Q_SCR_07_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_07_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_07_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_Q_SCR_07_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_G1W_SHIFT)
#define GPIO_Q_SCR_07_0_G1W_RANGE                       9:9
#define GPIO_Q_SCR_07_0_G1W_WOFFSET                     0x0
#define GPIO_Q_SCR_07_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_07_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_07_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_Q_SCR_07_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_G0W_SHIFT)
#define GPIO_Q_SCR_07_0_G0W_RANGE                       8:8
#define GPIO_Q_SCR_07_0_G0W_WOFFSET                     0x0
#define GPIO_Q_SCR_07_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_07_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_07_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_Q_SCR_07_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_G7R_SHIFT)
#define GPIO_Q_SCR_07_0_G7R_RANGE                       7:7
#define GPIO_Q_SCR_07_0_G7R_WOFFSET                     0x0
#define GPIO_Q_SCR_07_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_07_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_07_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_Q_SCR_07_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_G6R_SHIFT)
#define GPIO_Q_SCR_07_0_G6R_RANGE                       6:6
#define GPIO_Q_SCR_07_0_G6R_WOFFSET                     0x0
#define GPIO_Q_SCR_07_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_07_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_07_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Q_SCR_07_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_G5R_SHIFT)
#define GPIO_Q_SCR_07_0_G5R_RANGE                       5:5
#define GPIO_Q_SCR_07_0_G5R_WOFFSET                     0x0
#define GPIO_Q_SCR_07_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_07_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_07_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_Q_SCR_07_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_G4R_SHIFT)
#define GPIO_Q_SCR_07_0_G4R_RANGE                       4:4
#define GPIO_Q_SCR_07_0_G4R_WOFFSET                     0x0
#define GPIO_Q_SCR_07_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_07_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_07_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_Q_SCR_07_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_G3R_SHIFT)
#define GPIO_Q_SCR_07_0_G3R_RANGE                       3:3
#define GPIO_Q_SCR_07_0_G3R_WOFFSET                     0x0
#define GPIO_Q_SCR_07_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_07_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_07_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_Q_SCR_07_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_G2R_SHIFT)
#define GPIO_Q_SCR_07_0_G2R_RANGE                       2:2
#define GPIO_Q_SCR_07_0_G2R_WOFFSET                     0x0
#define GPIO_Q_SCR_07_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_07_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_07_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_Q_SCR_07_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_G1R_SHIFT)
#define GPIO_Q_SCR_07_0_G1R_RANGE                       1:1
#define GPIO_Q_SCR_07_0_G1R_WOFFSET                     0x0
#define GPIO_Q_SCR_07_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_07_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_07_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Q_SCR_07_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_G0R_SHIFT)
#define GPIO_Q_SCR_07_0_G0R_RANGE                       0:0
#define GPIO_Q_SCR_07_0_G0R_WOFFSET                     0x0
#define GPIO_Q_SCR_07_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_07_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_R_VM_00_0
#define GPIO_R_VM_00_0                  _MK_ADDR_CONST(0x21c0)
#define GPIO_R_VM_00_0_SECURE                   0x0
#define GPIO_R_VM_00_0_DUAL                     0x0
#define GPIO_R_VM_00_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_R_VM_00_0_WORD_COUNT                       0x1
#define GPIO_R_VM_00_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_R_VM_00_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_R_VM_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_R_VM_00_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_R_VM_00_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_R_VM_00_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_00_0_VM1_SHIFT)
#define GPIO_R_VM_00_0_VM1_RANGE                        1:0
#define GPIO_R_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_R_VM_00_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_00_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_00_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_R_VM_00_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_R_VM_00_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_00_0_VM2_SHIFT)
#define GPIO_R_VM_00_0_VM2_RANGE                        3:2
#define GPIO_R_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_R_VM_00_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_00_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_00_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_R_VM_00_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_R_VM_00_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_00_0_VM3_SHIFT)
#define GPIO_R_VM_00_0_VM3_RANGE                        5:4
#define GPIO_R_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_R_VM_00_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_00_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_00_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_R_VM_00_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_R_VM_00_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_00_0_VM4_SHIFT)
#define GPIO_R_VM_00_0_VM4_RANGE                        7:6
#define GPIO_R_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_R_VM_00_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_00_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_00_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_R_VM_00_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_R_VM_00_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_00_0_VM5_SHIFT)
#define GPIO_R_VM_00_0_VM5_RANGE                        9:8
#define GPIO_R_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_R_VM_00_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_00_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_00_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_R_VM_00_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_R_VM_00_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_00_0_VM6_SHIFT)
#define GPIO_R_VM_00_0_VM6_RANGE                        11:10
#define GPIO_R_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_R_VM_00_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_00_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_00_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_R_VM_00_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_R_VM_00_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_00_0_VM7_SHIFT)
#define GPIO_R_VM_00_0_VM7_RANGE                        13:12
#define GPIO_R_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_R_VM_00_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_00_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_00_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_R_VM_00_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_R_VM_00_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_00_0_VM8_SHIFT)
#define GPIO_R_VM_00_0_VM8_RANGE                        15:14
#define GPIO_R_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_R_VM_00_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_00_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_00_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_R_SCR_00_0
#define GPIO_R_SCR_00_0                 _MK_ADDR_CONST(0x21c4)
#define GPIO_R_SCR_00_0_SECURE                  0x0
#define GPIO_R_SCR_00_0_DUAL                    0x0
#define GPIO_R_SCR_00_0_SCR                     0
#define GPIO_R_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_R_SCR_00_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_R_SCR_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_R_SCR_00_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_R_SCR_00_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_R_SCR_00_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_R_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_R_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_R_SCR_00_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_00_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_R_SCR_00_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_R_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_R_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_R_SCR_00_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_00_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_R_SCR_00_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_R_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_R_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_R_SCR_00_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_00_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_R_SCR_00_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_R_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_R_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_R_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_R_SCR_00_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_R_SCR_00_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_00_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_R_SCR_00_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_PR7_SHIFT)
#define GPIO_R_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_R_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_00_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_R_SCR_00_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_PR6_SHIFT)
#define GPIO_R_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_R_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_00_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_R_SCR_00_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_PR5_SHIFT)
#define GPIO_R_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_R_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_00_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_R_SCR_00_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_PR4_SHIFT)
#define GPIO_R_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_R_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_00_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_R_SCR_00_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_PR3_SHIFT)
#define GPIO_R_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_R_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_00_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_R_SCR_00_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_PR2_SHIFT)
#define GPIO_R_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_R_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_00_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_R_SCR_00_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_PR1_SHIFT)
#define GPIO_R_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_R_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_00_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_R_SCR_00_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_PR0_SHIFT)
#define GPIO_R_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_R_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_00_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_R_SCR_00_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G7W_SHIFT)
#define GPIO_R_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_R_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_00_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_R_SCR_00_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G6W_SHIFT)
#define GPIO_R_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_R_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_00_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_R_SCR_00_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G5W_SHIFT)
#define GPIO_R_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_R_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_00_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_R_SCR_00_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G4W_SHIFT)
#define GPIO_R_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_R_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_00_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_R_SCR_00_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G3W_SHIFT)
#define GPIO_R_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_R_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_00_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_R_SCR_00_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G2W_SHIFT)
#define GPIO_R_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_R_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_00_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_R_SCR_00_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G1W_SHIFT)
#define GPIO_R_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_R_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_00_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_R_SCR_00_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G0W_SHIFT)
#define GPIO_R_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_R_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_00_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_R_SCR_00_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G7R_SHIFT)
#define GPIO_R_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_R_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_00_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_R_SCR_00_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G6R_SHIFT)
#define GPIO_R_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_R_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_00_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_R_SCR_00_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G5R_SHIFT)
#define GPIO_R_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_R_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_00_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_R_SCR_00_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G4R_SHIFT)
#define GPIO_R_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_R_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_00_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_R_SCR_00_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G3R_SHIFT)
#define GPIO_R_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_R_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_00_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_R_SCR_00_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G2R_SHIFT)
#define GPIO_R_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_R_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_00_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_R_SCR_00_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G1R_SHIFT)
#define GPIO_R_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_R_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_00_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_R_SCR_00_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G0R_SHIFT)
#define GPIO_R_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_R_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_R_VM_01_0
#define GPIO_R_VM_01_0                  _MK_ADDR_CONST(0x21c8)
#define GPIO_R_VM_01_0_SECURE                   0x0
#define GPIO_R_VM_01_0_DUAL                     0x0
#define GPIO_R_VM_01_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_R_VM_01_0_WORD_COUNT                       0x1
#define GPIO_R_VM_01_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_R_VM_01_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_R_VM_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_R_VM_01_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_R_VM_01_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_R_VM_01_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_01_0_VM1_SHIFT)
#define GPIO_R_VM_01_0_VM1_RANGE                        1:0
#define GPIO_R_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_R_VM_01_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_01_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_01_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_R_VM_01_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_R_VM_01_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_01_0_VM2_SHIFT)
#define GPIO_R_VM_01_0_VM2_RANGE                        3:2
#define GPIO_R_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_R_VM_01_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_01_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_01_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_R_VM_01_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_R_VM_01_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_01_0_VM3_SHIFT)
#define GPIO_R_VM_01_0_VM3_RANGE                        5:4
#define GPIO_R_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_R_VM_01_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_01_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_01_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_R_VM_01_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_R_VM_01_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_01_0_VM4_SHIFT)
#define GPIO_R_VM_01_0_VM4_RANGE                        7:6
#define GPIO_R_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_R_VM_01_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_01_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_01_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_R_VM_01_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_R_VM_01_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_01_0_VM5_SHIFT)
#define GPIO_R_VM_01_0_VM5_RANGE                        9:8
#define GPIO_R_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_R_VM_01_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_01_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_01_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_R_VM_01_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_R_VM_01_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_01_0_VM6_SHIFT)
#define GPIO_R_VM_01_0_VM6_RANGE                        11:10
#define GPIO_R_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_R_VM_01_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_01_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_01_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_R_VM_01_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_R_VM_01_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_01_0_VM7_SHIFT)
#define GPIO_R_VM_01_0_VM7_RANGE                        13:12
#define GPIO_R_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_R_VM_01_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_01_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_01_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_R_VM_01_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_R_VM_01_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_01_0_VM8_SHIFT)
#define GPIO_R_VM_01_0_VM8_RANGE                        15:14
#define GPIO_R_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_R_VM_01_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_01_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_01_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_R_SCR_01_0
#define GPIO_R_SCR_01_0                 _MK_ADDR_CONST(0x21cc)
#define GPIO_R_SCR_01_0_SECURE                  0x0
#define GPIO_R_SCR_01_0_DUAL                    0x0
#define GPIO_R_SCR_01_0_SCR                     0
#define GPIO_R_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_R_SCR_01_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_R_SCR_01_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_R_SCR_01_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_R_SCR_01_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_R_SCR_01_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_R_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_R_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_R_SCR_01_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_01_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_R_SCR_01_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_R_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_R_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_R_SCR_01_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_01_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_R_SCR_01_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_R_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_R_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_R_SCR_01_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_01_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_R_SCR_01_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_R_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_R_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_R_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_R_SCR_01_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_R_SCR_01_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_01_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_R_SCR_01_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_PR7_SHIFT)
#define GPIO_R_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_R_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_01_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_R_SCR_01_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_PR6_SHIFT)
#define GPIO_R_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_R_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_01_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_R_SCR_01_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_PR5_SHIFT)
#define GPIO_R_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_R_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_01_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_R_SCR_01_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_PR4_SHIFT)
#define GPIO_R_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_R_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_01_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_R_SCR_01_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_PR3_SHIFT)
#define GPIO_R_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_R_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_01_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_R_SCR_01_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_PR2_SHIFT)
#define GPIO_R_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_R_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_01_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_R_SCR_01_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_PR1_SHIFT)
#define GPIO_R_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_R_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_01_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_R_SCR_01_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_PR0_SHIFT)
#define GPIO_R_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_R_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_01_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_R_SCR_01_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G7W_SHIFT)
#define GPIO_R_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_R_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_01_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_R_SCR_01_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G6W_SHIFT)
#define GPIO_R_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_R_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_01_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_R_SCR_01_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G5W_SHIFT)
#define GPIO_R_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_R_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_01_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_R_SCR_01_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G4W_SHIFT)
#define GPIO_R_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_R_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_01_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_R_SCR_01_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G3W_SHIFT)
#define GPIO_R_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_R_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_01_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_R_SCR_01_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G2W_SHIFT)
#define GPIO_R_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_R_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_01_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_R_SCR_01_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G1W_SHIFT)
#define GPIO_R_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_R_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_01_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_R_SCR_01_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G0W_SHIFT)
#define GPIO_R_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_R_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_01_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_R_SCR_01_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G7R_SHIFT)
#define GPIO_R_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_R_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_01_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_R_SCR_01_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G6R_SHIFT)
#define GPIO_R_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_R_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_01_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_R_SCR_01_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G5R_SHIFT)
#define GPIO_R_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_R_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_01_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_R_SCR_01_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G4R_SHIFT)
#define GPIO_R_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_R_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_01_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_R_SCR_01_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G3R_SHIFT)
#define GPIO_R_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_R_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_01_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_R_SCR_01_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G2R_SHIFT)
#define GPIO_R_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_R_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_01_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_R_SCR_01_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G1R_SHIFT)
#define GPIO_R_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_R_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_01_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_R_SCR_01_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G0R_SHIFT)
#define GPIO_R_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_R_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_R_VM_02_0
#define GPIO_R_VM_02_0                  _MK_ADDR_CONST(0x21d0)
#define GPIO_R_VM_02_0_SECURE                   0x0
#define GPIO_R_VM_02_0_DUAL                     0x0
#define GPIO_R_VM_02_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_R_VM_02_0_WORD_COUNT                       0x1
#define GPIO_R_VM_02_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_R_VM_02_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_R_VM_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_R_VM_02_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_R_VM_02_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_R_VM_02_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_02_0_VM1_SHIFT)
#define GPIO_R_VM_02_0_VM1_RANGE                        1:0
#define GPIO_R_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_R_VM_02_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_02_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_02_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_R_VM_02_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_R_VM_02_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_02_0_VM2_SHIFT)
#define GPIO_R_VM_02_0_VM2_RANGE                        3:2
#define GPIO_R_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_R_VM_02_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_02_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_02_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_R_VM_02_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_R_VM_02_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_02_0_VM3_SHIFT)
#define GPIO_R_VM_02_0_VM3_RANGE                        5:4
#define GPIO_R_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_R_VM_02_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_02_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_02_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_R_VM_02_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_R_VM_02_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_02_0_VM4_SHIFT)
#define GPIO_R_VM_02_0_VM4_RANGE                        7:6
#define GPIO_R_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_R_VM_02_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_02_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_02_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_R_VM_02_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_R_VM_02_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_02_0_VM5_SHIFT)
#define GPIO_R_VM_02_0_VM5_RANGE                        9:8
#define GPIO_R_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_R_VM_02_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_02_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_02_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_R_VM_02_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_R_VM_02_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_02_0_VM6_SHIFT)
#define GPIO_R_VM_02_0_VM6_RANGE                        11:10
#define GPIO_R_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_R_VM_02_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_02_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_02_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_R_VM_02_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_R_VM_02_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_02_0_VM7_SHIFT)
#define GPIO_R_VM_02_0_VM7_RANGE                        13:12
#define GPIO_R_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_R_VM_02_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_02_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_02_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_R_VM_02_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_R_VM_02_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_02_0_VM8_SHIFT)
#define GPIO_R_VM_02_0_VM8_RANGE                        15:14
#define GPIO_R_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_R_VM_02_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_02_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_02_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_R_SCR_02_0
#define GPIO_R_SCR_02_0                 _MK_ADDR_CONST(0x21d4)
#define GPIO_R_SCR_02_0_SECURE                  0x0
#define GPIO_R_SCR_02_0_DUAL                    0x0
#define GPIO_R_SCR_02_0_SCR                     0
#define GPIO_R_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_R_SCR_02_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_R_SCR_02_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_R_SCR_02_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_R_SCR_02_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_R_SCR_02_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_R_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_R_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_R_SCR_02_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_02_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_R_SCR_02_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_R_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_R_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_R_SCR_02_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_02_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_R_SCR_02_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_R_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_R_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_R_SCR_02_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_02_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_R_SCR_02_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_R_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_R_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_R_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_R_SCR_02_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_R_SCR_02_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_02_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_R_SCR_02_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_PR7_SHIFT)
#define GPIO_R_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_R_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_02_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_R_SCR_02_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_PR6_SHIFT)
#define GPIO_R_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_R_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_02_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_R_SCR_02_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_PR5_SHIFT)
#define GPIO_R_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_R_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_02_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_R_SCR_02_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_PR4_SHIFT)
#define GPIO_R_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_R_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_02_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_R_SCR_02_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_PR3_SHIFT)
#define GPIO_R_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_R_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_02_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_R_SCR_02_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_PR2_SHIFT)
#define GPIO_R_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_R_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_02_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_R_SCR_02_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_PR1_SHIFT)
#define GPIO_R_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_R_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_02_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_R_SCR_02_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_PR0_SHIFT)
#define GPIO_R_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_R_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_02_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_R_SCR_02_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G7W_SHIFT)
#define GPIO_R_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_R_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_02_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_R_SCR_02_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G6W_SHIFT)
#define GPIO_R_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_R_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_02_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_R_SCR_02_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G5W_SHIFT)
#define GPIO_R_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_R_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_02_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_R_SCR_02_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G4W_SHIFT)
#define GPIO_R_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_R_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_02_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_R_SCR_02_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G3W_SHIFT)
#define GPIO_R_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_R_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_02_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_R_SCR_02_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G2W_SHIFT)
#define GPIO_R_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_R_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_02_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_R_SCR_02_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G1W_SHIFT)
#define GPIO_R_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_R_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_02_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_R_SCR_02_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G0W_SHIFT)
#define GPIO_R_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_R_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_02_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_R_SCR_02_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G7R_SHIFT)
#define GPIO_R_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_R_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_02_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_R_SCR_02_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G6R_SHIFT)
#define GPIO_R_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_R_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_02_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_R_SCR_02_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G5R_SHIFT)
#define GPIO_R_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_R_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_02_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_R_SCR_02_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G4R_SHIFT)
#define GPIO_R_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_R_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_02_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_R_SCR_02_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G3R_SHIFT)
#define GPIO_R_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_R_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_02_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_R_SCR_02_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G2R_SHIFT)
#define GPIO_R_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_R_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_02_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_R_SCR_02_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G1R_SHIFT)
#define GPIO_R_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_R_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_02_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_R_SCR_02_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G0R_SHIFT)
#define GPIO_R_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_R_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_R_VM_03_0
#define GPIO_R_VM_03_0                  _MK_ADDR_CONST(0x21d8)
#define GPIO_R_VM_03_0_SECURE                   0x0
#define GPIO_R_VM_03_0_DUAL                     0x0
#define GPIO_R_VM_03_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_R_VM_03_0_WORD_COUNT                       0x1
#define GPIO_R_VM_03_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_R_VM_03_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_R_VM_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_R_VM_03_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_R_VM_03_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_R_VM_03_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_03_0_VM1_SHIFT)
#define GPIO_R_VM_03_0_VM1_RANGE                        1:0
#define GPIO_R_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_R_VM_03_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_03_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_03_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_R_VM_03_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_R_VM_03_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_03_0_VM2_SHIFT)
#define GPIO_R_VM_03_0_VM2_RANGE                        3:2
#define GPIO_R_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_R_VM_03_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_03_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_03_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_R_VM_03_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_R_VM_03_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_03_0_VM3_SHIFT)
#define GPIO_R_VM_03_0_VM3_RANGE                        5:4
#define GPIO_R_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_R_VM_03_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_03_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_03_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_R_VM_03_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_R_VM_03_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_03_0_VM4_SHIFT)
#define GPIO_R_VM_03_0_VM4_RANGE                        7:6
#define GPIO_R_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_R_VM_03_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_03_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_03_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_R_VM_03_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_R_VM_03_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_03_0_VM5_SHIFT)
#define GPIO_R_VM_03_0_VM5_RANGE                        9:8
#define GPIO_R_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_R_VM_03_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_03_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_03_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_R_VM_03_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_R_VM_03_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_03_0_VM6_SHIFT)
#define GPIO_R_VM_03_0_VM6_RANGE                        11:10
#define GPIO_R_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_R_VM_03_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_03_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_03_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_R_VM_03_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_R_VM_03_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_03_0_VM7_SHIFT)
#define GPIO_R_VM_03_0_VM7_RANGE                        13:12
#define GPIO_R_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_R_VM_03_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_03_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_03_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_R_VM_03_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_R_VM_03_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_03_0_VM8_SHIFT)
#define GPIO_R_VM_03_0_VM8_RANGE                        15:14
#define GPIO_R_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_R_VM_03_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_03_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_03_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_R_SCR_03_0
#define GPIO_R_SCR_03_0                 _MK_ADDR_CONST(0x21dc)
#define GPIO_R_SCR_03_0_SECURE                  0x0
#define GPIO_R_SCR_03_0_DUAL                    0x0
#define GPIO_R_SCR_03_0_SCR                     0
#define GPIO_R_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_R_SCR_03_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_R_SCR_03_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_R_SCR_03_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_R_SCR_03_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_R_SCR_03_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_R_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_R_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_R_SCR_03_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_03_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_R_SCR_03_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_R_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_R_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_R_SCR_03_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_03_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_R_SCR_03_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_R_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_R_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_R_SCR_03_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_03_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_R_SCR_03_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_R_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_R_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_R_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_R_SCR_03_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_R_SCR_03_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_03_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_R_SCR_03_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_PR7_SHIFT)
#define GPIO_R_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_R_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_03_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_R_SCR_03_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_PR6_SHIFT)
#define GPIO_R_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_R_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_03_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_R_SCR_03_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_PR5_SHIFT)
#define GPIO_R_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_R_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_03_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_R_SCR_03_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_PR4_SHIFT)
#define GPIO_R_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_R_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_03_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_R_SCR_03_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_PR3_SHIFT)
#define GPIO_R_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_R_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_03_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_R_SCR_03_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_PR2_SHIFT)
#define GPIO_R_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_R_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_03_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_R_SCR_03_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_PR1_SHIFT)
#define GPIO_R_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_R_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_03_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_R_SCR_03_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_PR0_SHIFT)
#define GPIO_R_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_R_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_03_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_R_SCR_03_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G7W_SHIFT)
#define GPIO_R_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_R_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_03_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_R_SCR_03_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G6W_SHIFT)
#define GPIO_R_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_R_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_03_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_R_SCR_03_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G5W_SHIFT)
#define GPIO_R_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_R_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_03_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_R_SCR_03_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G4W_SHIFT)
#define GPIO_R_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_R_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_03_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_R_SCR_03_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G3W_SHIFT)
#define GPIO_R_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_R_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_03_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_R_SCR_03_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G2W_SHIFT)
#define GPIO_R_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_R_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_03_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_R_SCR_03_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G1W_SHIFT)
#define GPIO_R_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_R_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_03_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_R_SCR_03_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G0W_SHIFT)
#define GPIO_R_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_R_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_03_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_R_SCR_03_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G7R_SHIFT)
#define GPIO_R_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_R_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_03_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_R_SCR_03_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G6R_SHIFT)
#define GPIO_R_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_R_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_03_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_R_SCR_03_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G5R_SHIFT)
#define GPIO_R_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_R_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_03_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_R_SCR_03_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G4R_SHIFT)
#define GPIO_R_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_R_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_03_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_R_SCR_03_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G3R_SHIFT)
#define GPIO_R_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_R_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_03_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_R_SCR_03_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G2R_SHIFT)
#define GPIO_R_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_R_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_03_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_R_SCR_03_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G1R_SHIFT)
#define GPIO_R_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_R_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_03_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_R_SCR_03_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G0R_SHIFT)
#define GPIO_R_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_R_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_R_VM_04_0
#define GPIO_R_VM_04_0                  _MK_ADDR_CONST(0x21e0)
#define GPIO_R_VM_04_0_SECURE                   0x0
#define GPIO_R_VM_04_0_DUAL                     0x0
#define GPIO_R_VM_04_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_R_VM_04_0_WORD_COUNT                       0x1
#define GPIO_R_VM_04_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_R_VM_04_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_R_VM_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_R_VM_04_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_R_VM_04_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_R_VM_04_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_04_0_VM1_SHIFT)
#define GPIO_R_VM_04_0_VM1_RANGE                        1:0
#define GPIO_R_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_R_VM_04_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_04_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_04_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_R_VM_04_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_R_VM_04_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_04_0_VM2_SHIFT)
#define GPIO_R_VM_04_0_VM2_RANGE                        3:2
#define GPIO_R_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_R_VM_04_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_04_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_04_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_R_VM_04_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_R_VM_04_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_04_0_VM3_SHIFT)
#define GPIO_R_VM_04_0_VM3_RANGE                        5:4
#define GPIO_R_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_R_VM_04_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_04_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_04_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_R_VM_04_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_R_VM_04_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_04_0_VM4_SHIFT)
#define GPIO_R_VM_04_0_VM4_RANGE                        7:6
#define GPIO_R_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_R_VM_04_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_04_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_04_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_R_VM_04_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_R_VM_04_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_04_0_VM5_SHIFT)
#define GPIO_R_VM_04_0_VM5_RANGE                        9:8
#define GPIO_R_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_R_VM_04_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_04_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_04_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_R_VM_04_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_R_VM_04_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_04_0_VM6_SHIFT)
#define GPIO_R_VM_04_0_VM6_RANGE                        11:10
#define GPIO_R_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_R_VM_04_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_04_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_04_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_R_VM_04_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_R_VM_04_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_04_0_VM7_SHIFT)
#define GPIO_R_VM_04_0_VM7_RANGE                        13:12
#define GPIO_R_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_R_VM_04_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_04_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_04_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_R_VM_04_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_R_VM_04_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_04_0_VM8_SHIFT)
#define GPIO_R_VM_04_0_VM8_RANGE                        15:14
#define GPIO_R_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_R_VM_04_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_04_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_04_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_R_SCR_04_0
#define GPIO_R_SCR_04_0                 _MK_ADDR_CONST(0x21e4)
#define GPIO_R_SCR_04_0_SECURE                  0x0
#define GPIO_R_SCR_04_0_DUAL                    0x0
#define GPIO_R_SCR_04_0_SCR                     0
#define GPIO_R_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_R_SCR_04_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_R_SCR_04_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_R_SCR_04_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_R_SCR_04_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_R_SCR_04_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_R_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_R_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_R_SCR_04_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_04_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_R_SCR_04_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_R_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_R_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_R_SCR_04_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_04_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_R_SCR_04_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_R_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_R_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_R_SCR_04_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_04_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_R_SCR_04_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_R_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_R_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_R_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_R_SCR_04_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_R_SCR_04_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_04_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_R_SCR_04_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_PR7_SHIFT)
#define GPIO_R_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_R_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_04_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_R_SCR_04_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_PR6_SHIFT)
#define GPIO_R_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_R_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_04_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_R_SCR_04_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_PR5_SHIFT)
#define GPIO_R_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_R_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_04_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_R_SCR_04_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_PR4_SHIFT)
#define GPIO_R_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_R_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_04_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_R_SCR_04_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_PR3_SHIFT)
#define GPIO_R_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_R_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_04_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_R_SCR_04_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_PR2_SHIFT)
#define GPIO_R_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_R_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_04_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_R_SCR_04_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_PR1_SHIFT)
#define GPIO_R_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_R_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_04_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_R_SCR_04_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_PR0_SHIFT)
#define GPIO_R_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_R_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_04_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_R_SCR_04_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G7W_SHIFT)
#define GPIO_R_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_R_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_04_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_R_SCR_04_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G6W_SHIFT)
#define GPIO_R_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_R_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_04_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_R_SCR_04_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G5W_SHIFT)
#define GPIO_R_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_R_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_04_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_R_SCR_04_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G4W_SHIFT)
#define GPIO_R_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_R_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_04_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_R_SCR_04_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G3W_SHIFT)
#define GPIO_R_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_R_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_04_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_R_SCR_04_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G2W_SHIFT)
#define GPIO_R_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_R_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_04_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_R_SCR_04_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G1W_SHIFT)
#define GPIO_R_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_R_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_04_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_R_SCR_04_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G0W_SHIFT)
#define GPIO_R_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_R_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_04_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_R_SCR_04_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G7R_SHIFT)
#define GPIO_R_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_R_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_04_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_R_SCR_04_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G6R_SHIFT)
#define GPIO_R_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_R_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_04_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_R_SCR_04_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G5R_SHIFT)
#define GPIO_R_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_R_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_04_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_R_SCR_04_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G4R_SHIFT)
#define GPIO_R_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_R_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_04_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_R_SCR_04_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G3R_SHIFT)
#define GPIO_R_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_R_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_04_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_R_SCR_04_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G2R_SHIFT)
#define GPIO_R_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_R_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_04_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_R_SCR_04_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G1R_SHIFT)
#define GPIO_R_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_R_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_04_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_R_SCR_04_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G0R_SHIFT)
#define GPIO_R_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_R_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_R_VM_05_0
#define GPIO_R_VM_05_0                  _MK_ADDR_CONST(0x21e8)
#define GPIO_R_VM_05_0_SECURE                   0x0
#define GPIO_R_VM_05_0_DUAL                     0x0
#define GPIO_R_VM_05_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_R_VM_05_0_WORD_COUNT                       0x1
#define GPIO_R_VM_05_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_R_VM_05_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_R_VM_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_R_VM_05_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_R_VM_05_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_R_VM_05_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_05_0_VM1_SHIFT)
#define GPIO_R_VM_05_0_VM1_RANGE                        1:0
#define GPIO_R_VM_05_0_VM1_WOFFSET                      0x0
#define GPIO_R_VM_05_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_05_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_05_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_R_VM_05_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_R_VM_05_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_05_0_VM2_SHIFT)
#define GPIO_R_VM_05_0_VM2_RANGE                        3:2
#define GPIO_R_VM_05_0_VM2_WOFFSET                      0x0
#define GPIO_R_VM_05_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_05_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_05_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_R_VM_05_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_R_VM_05_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_05_0_VM3_SHIFT)
#define GPIO_R_VM_05_0_VM3_RANGE                        5:4
#define GPIO_R_VM_05_0_VM3_WOFFSET                      0x0
#define GPIO_R_VM_05_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_05_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_05_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_R_VM_05_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_R_VM_05_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_05_0_VM4_SHIFT)
#define GPIO_R_VM_05_0_VM4_RANGE                        7:6
#define GPIO_R_VM_05_0_VM4_WOFFSET                      0x0
#define GPIO_R_VM_05_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_05_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_05_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_R_VM_05_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_R_VM_05_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_05_0_VM5_SHIFT)
#define GPIO_R_VM_05_0_VM5_RANGE                        9:8
#define GPIO_R_VM_05_0_VM5_WOFFSET                      0x0
#define GPIO_R_VM_05_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_05_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_05_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_R_VM_05_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_R_VM_05_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_05_0_VM6_SHIFT)
#define GPIO_R_VM_05_0_VM6_RANGE                        11:10
#define GPIO_R_VM_05_0_VM6_WOFFSET                      0x0
#define GPIO_R_VM_05_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_05_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_05_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_R_VM_05_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_R_VM_05_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_05_0_VM7_SHIFT)
#define GPIO_R_VM_05_0_VM7_RANGE                        13:12
#define GPIO_R_VM_05_0_VM7_WOFFSET                      0x0
#define GPIO_R_VM_05_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_05_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_05_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_R_VM_05_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_R_VM_05_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_R_VM_05_0_VM8_SHIFT)
#define GPIO_R_VM_05_0_VM8_RANGE                        15:14
#define GPIO_R_VM_05_0_VM8_WOFFSET                      0x0
#define GPIO_R_VM_05_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_R_VM_05_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_R_VM_05_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_R_SCR_05_0
#define GPIO_R_SCR_05_0                 _MK_ADDR_CONST(0x21ec)
#define GPIO_R_SCR_05_0_SECURE                  0x0
#define GPIO_R_SCR_05_0_DUAL                    0x0
#define GPIO_R_SCR_05_0_SCR                     0
#define GPIO_R_SCR_05_0_WORD_COUNT                      0x1
#define GPIO_R_SCR_05_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_R_SCR_05_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_R_SCR_05_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_R_SCR_05_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_R_SCR_05_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_R_SCR_05_0_SEC_LCK_RANGE                   29:29
#define GPIO_R_SCR_05_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_R_SCR_05_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_05_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_R_SCR_05_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_R_SCR_05_0_SEC_WEN_RANGE                   28:28
#define GPIO_R_SCR_05_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_R_SCR_05_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_05_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_R_SCR_05_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_R_SCR_05_0_SEC_REN_RANGE                   27:27
#define GPIO_R_SCR_05_0_SEC_REN_WOFFSET                 0x0
#define GPIO_R_SCR_05_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_05_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_R_SCR_05_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_R_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_R_SCR_05_0_SEC_OWNER_RANGE                 26:24
#define GPIO_R_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_R_SCR_05_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_R_SCR_05_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_05_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_R_SCR_05_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_PR7_SHIFT)
#define GPIO_R_SCR_05_0_PR7_RANGE                       23:23
#define GPIO_R_SCR_05_0_PR7_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_05_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_R_SCR_05_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_PR6_SHIFT)
#define GPIO_R_SCR_05_0_PR6_RANGE                       22:22
#define GPIO_R_SCR_05_0_PR6_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_05_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_R_SCR_05_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_PR5_SHIFT)
#define GPIO_R_SCR_05_0_PR5_RANGE                       21:21
#define GPIO_R_SCR_05_0_PR5_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_05_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_R_SCR_05_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_PR4_SHIFT)
#define GPIO_R_SCR_05_0_PR4_RANGE                       20:20
#define GPIO_R_SCR_05_0_PR4_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_05_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_R_SCR_05_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_PR3_SHIFT)
#define GPIO_R_SCR_05_0_PR3_RANGE                       19:19
#define GPIO_R_SCR_05_0_PR3_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_05_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_R_SCR_05_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_PR2_SHIFT)
#define GPIO_R_SCR_05_0_PR2_RANGE                       18:18
#define GPIO_R_SCR_05_0_PR2_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_05_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_R_SCR_05_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_PR1_SHIFT)
#define GPIO_R_SCR_05_0_PR1_RANGE                       17:17
#define GPIO_R_SCR_05_0_PR1_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_05_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_R_SCR_05_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_PR0_SHIFT)
#define GPIO_R_SCR_05_0_PR0_RANGE                       16:16
#define GPIO_R_SCR_05_0_PR0_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_05_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_R_SCR_05_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G7W_SHIFT)
#define GPIO_R_SCR_05_0_G7W_RANGE                       15:15
#define GPIO_R_SCR_05_0_G7W_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_05_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_R_SCR_05_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G6W_SHIFT)
#define GPIO_R_SCR_05_0_G6W_RANGE                       14:14
#define GPIO_R_SCR_05_0_G6W_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_05_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_R_SCR_05_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G5W_SHIFT)
#define GPIO_R_SCR_05_0_G5W_RANGE                       13:13
#define GPIO_R_SCR_05_0_G5W_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_05_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_R_SCR_05_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G4W_SHIFT)
#define GPIO_R_SCR_05_0_G4W_RANGE                       12:12
#define GPIO_R_SCR_05_0_G4W_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_05_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_R_SCR_05_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G3W_SHIFT)
#define GPIO_R_SCR_05_0_G3W_RANGE                       11:11
#define GPIO_R_SCR_05_0_G3W_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_05_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_R_SCR_05_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G2W_SHIFT)
#define GPIO_R_SCR_05_0_G2W_RANGE                       10:10
#define GPIO_R_SCR_05_0_G2W_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_05_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_R_SCR_05_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G1W_SHIFT)
#define GPIO_R_SCR_05_0_G1W_RANGE                       9:9
#define GPIO_R_SCR_05_0_G1W_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_05_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_R_SCR_05_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G0W_SHIFT)
#define GPIO_R_SCR_05_0_G0W_RANGE                       8:8
#define GPIO_R_SCR_05_0_G0W_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_05_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_R_SCR_05_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G7R_SHIFT)
#define GPIO_R_SCR_05_0_G7R_RANGE                       7:7
#define GPIO_R_SCR_05_0_G7R_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_05_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_R_SCR_05_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G6R_SHIFT)
#define GPIO_R_SCR_05_0_G6R_RANGE                       6:6
#define GPIO_R_SCR_05_0_G6R_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_05_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_R_SCR_05_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G5R_SHIFT)
#define GPIO_R_SCR_05_0_G5R_RANGE                       5:5
#define GPIO_R_SCR_05_0_G5R_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_05_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_R_SCR_05_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G4R_SHIFT)
#define GPIO_R_SCR_05_0_G4R_RANGE                       4:4
#define GPIO_R_SCR_05_0_G4R_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_05_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_R_SCR_05_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G3R_SHIFT)
#define GPIO_R_SCR_05_0_G3R_RANGE                       3:3
#define GPIO_R_SCR_05_0_G3R_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_05_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_R_SCR_05_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G2R_SHIFT)
#define GPIO_R_SCR_05_0_G2R_RANGE                       2:2
#define GPIO_R_SCR_05_0_G2R_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_05_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_R_SCR_05_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G1R_SHIFT)
#define GPIO_R_SCR_05_0_G1R_RANGE                       1:1
#define GPIO_R_SCR_05_0_G1R_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_R_SCR_05_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_R_SCR_05_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G0R_SHIFT)
#define GPIO_R_SCR_05_0_G0R_RANGE                       0:0
#define GPIO_R_SCR_05_0_G0R_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Reserved address 0x21f0

// Reserved address 0x21f4

// Reserved address 0x21f8

// Reserved address 0x21fc

// Register GPIO_CTL2_VM_SCR_0
#define GPIO_CTL2_VM_SCR_0                      _MK_ADDR_CONST(0x2800)
#define GPIO_CTL2_VM_SCR_0_SECURE                       0x0
#define GPIO_CTL2_VM_SCR_0_DUAL                         0x0
#define GPIO_CTL2_VM_SCR_0_SCR                  0
#define GPIO_CTL2_VM_SCR_0_WORD_COUNT                   0x1
#define GPIO_CTL2_VM_SCR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_RESET_MASK                   _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL2_VM_SCR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_READ_MASK                    _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL2_VM_SCR_0_WRITE_MASK                   _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL2_VM_SCR_0_SEC_LCK_SHIFT                        _MK_SHIFT_CONST(29)
#define GPIO_CTL2_VM_SCR_0_SEC_LCK_FIELD                        _MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_SEC_LCK_SHIFT)
#define GPIO_CTL2_VM_SCR_0_SEC_LCK_RANGE                        29:29
#define GPIO_CTL2_VM_SCR_0_SEC_LCK_WOFFSET                      0x0
#define GPIO_CTL2_VM_SCR_0_SEC_LCK_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_SEC_LCK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_SEC_LCK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_SEC_LCK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_SEC_LCK_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_CTL2_VM_SCR_0_SEC_WEN_SHIFT                        _MK_SHIFT_CONST(28)
#define GPIO_CTL2_VM_SCR_0_SEC_WEN_FIELD                        _MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_SEC_WEN_SHIFT)
#define GPIO_CTL2_VM_SCR_0_SEC_WEN_RANGE                        28:28
#define GPIO_CTL2_VM_SCR_0_SEC_WEN_WOFFSET                      0x0
#define GPIO_CTL2_VM_SCR_0_SEC_WEN_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_SEC_WEN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_SEC_WEN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_SEC_WEN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_SEC_WEN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_CTL2_VM_SCR_0_SEC_REN_SHIFT                        _MK_SHIFT_CONST(27)
#define GPIO_CTL2_VM_SCR_0_SEC_REN_FIELD                        _MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_SEC_REN_SHIFT)
#define GPIO_CTL2_VM_SCR_0_SEC_REN_RANGE                        27:27
#define GPIO_CTL2_VM_SCR_0_SEC_REN_WOFFSET                      0x0
#define GPIO_CTL2_VM_SCR_0_SEC_REN_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_SEC_REN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_SEC_REN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_SEC_REN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_SEC_REN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_SEC_REN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_CTL2_VM_SCR_0_SEC_OWNER_SHIFT                      _MK_SHIFT_CONST(24)
#define GPIO_CTL2_VM_SCR_0_SEC_OWNER_FIELD                      _MK_FIELD_CONST(0x7, GPIO_CTL2_VM_SCR_0_SEC_OWNER_SHIFT)
#define GPIO_CTL2_VM_SCR_0_SEC_OWNER_RANGE                      26:24
#define GPIO_CTL2_VM_SCR_0_SEC_OWNER_WOFFSET                    0x0
#define GPIO_CTL2_VM_SCR_0_SEC_OWNER_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_SEC_OWNER_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
#define GPIO_CTL2_VM_SCR_0_SEC_OWNER_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_SEC_OWNER_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_CTL2_VM_SCR_0_PR7_SHIFT                    _MK_SHIFT_CONST(23)
#define GPIO_CTL2_VM_SCR_0_PR7_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_PR7_SHIFT)
#define GPIO_CTL2_VM_SCR_0_PR7_RANGE                    23:23
#define GPIO_CTL2_VM_SCR_0_PR7_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_PR7_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR7_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_PR7_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR7_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR7_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR7_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL2_VM_SCR_0_PR6_SHIFT                    _MK_SHIFT_CONST(22)
#define GPIO_CTL2_VM_SCR_0_PR6_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_PR6_SHIFT)
#define GPIO_CTL2_VM_SCR_0_PR6_RANGE                    22:22
#define GPIO_CTL2_VM_SCR_0_PR6_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_PR6_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR6_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_PR6_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR6_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR6_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL2_VM_SCR_0_PR5_SHIFT                    _MK_SHIFT_CONST(21)
#define GPIO_CTL2_VM_SCR_0_PR5_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_PR5_SHIFT)
#define GPIO_CTL2_VM_SCR_0_PR5_RANGE                    21:21
#define GPIO_CTL2_VM_SCR_0_PR5_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_PR5_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR5_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_PR5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR5_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR5_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL2_VM_SCR_0_PR4_SHIFT                    _MK_SHIFT_CONST(20)
#define GPIO_CTL2_VM_SCR_0_PR4_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_PR4_SHIFT)
#define GPIO_CTL2_VM_SCR_0_PR4_RANGE                    20:20
#define GPIO_CTL2_VM_SCR_0_PR4_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_PR4_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR4_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_PR4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR4_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR4_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL2_VM_SCR_0_PR3_SHIFT                    _MK_SHIFT_CONST(19)
#define GPIO_CTL2_VM_SCR_0_PR3_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_PR3_SHIFT)
#define GPIO_CTL2_VM_SCR_0_PR3_RANGE                    19:19
#define GPIO_CTL2_VM_SCR_0_PR3_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_PR3_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_PR3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR3_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR3_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL2_VM_SCR_0_PR2_SHIFT                    _MK_SHIFT_CONST(18)
#define GPIO_CTL2_VM_SCR_0_PR2_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_PR2_SHIFT)
#define GPIO_CTL2_VM_SCR_0_PR2_RANGE                    18:18
#define GPIO_CTL2_VM_SCR_0_PR2_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_PR2_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_PR2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR2_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR2_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL2_VM_SCR_0_PR1_SHIFT                    _MK_SHIFT_CONST(17)
#define GPIO_CTL2_VM_SCR_0_PR1_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_PR1_SHIFT)
#define GPIO_CTL2_VM_SCR_0_PR1_RANGE                    17:17
#define GPIO_CTL2_VM_SCR_0_PR1_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_PR1_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_PR1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR1_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR1_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL2_VM_SCR_0_PR0_SHIFT                    _MK_SHIFT_CONST(16)
#define GPIO_CTL2_VM_SCR_0_PR0_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_PR0_SHIFT)
#define GPIO_CTL2_VM_SCR_0_PR0_RANGE                    16:16
#define GPIO_CTL2_VM_SCR_0_PR0_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_PR0_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_PR0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR0_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR0_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL2_VM_SCR_0_G7W_SHIFT                    _MK_SHIFT_CONST(15)
#define GPIO_CTL2_VM_SCR_0_G7W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G7W_SHIFT)
#define GPIO_CTL2_VM_SCR_0_G7W_RANGE                    15:15
#define GPIO_CTL2_VM_SCR_0_G7W_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_G7W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G7W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_G7W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G7W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G7W_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G7W_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL2_VM_SCR_0_G6W_SHIFT                    _MK_SHIFT_CONST(14)
#define GPIO_CTL2_VM_SCR_0_G6W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G6W_SHIFT)
#define GPIO_CTL2_VM_SCR_0_G6W_RANGE                    14:14
#define GPIO_CTL2_VM_SCR_0_G6W_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_G6W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G6W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_G6W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G6W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G6W_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G6W_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL2_VM_SCR_0_G5W_SHIFT                    _MK_SHIFT_CONST(13)
#define GPIO_CTL2_VM_SCR_0_G5W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G5W_SHIFT)
#define GPIO_CTL2_VM_SCR_0_G5W_RANGE                    13:13
#define GPIO_CTL2_VM_SCR_0_G5W_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_G5W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G5W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_G5W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G5W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G5W_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G5W_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL2_VM_SCR_0_G4W_SHIFT                    _MK_SHIFT_CONST(12)
#define GPIO_CTL2_VM_SCR_0_G4W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G4W_SHIFT)
#define GPIO_CTL2_VM_SCR_0_G4W_RANGE                    12:12
#define GPIO_CTL2_VM_SCR_0_G4W_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_G4W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G4W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_G4W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G4W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G4W_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G4W_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL2_VM_SCR_0_G3W_SHIFT                    _MK_SHIFT_CONST(11)
#define GPIO_CTL2_VM_SCR_0_G3W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G3W_SHIFT)
#define GPIO_CTL2_VM_SCR_0_G3W_RANGE                    11:11
#define GPIO_CTL2_VM_SCR_0_G3W_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_G3W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G3W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_G3W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G3W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G3W_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G3W_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL2_VM_SCR_0_G2W_SHIFT                    _MK_SHIFT_CONST(10)
#define GPIO_CTL2_VM_SCR_0_G2W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G2W_SHIFT)
#define GPIO_CTL2_VM_SCR_0_G2W_RANGE                    10:10
#define GPIO_CTL2_VM_SCR_0_G2W_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_G2W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G2W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_G2W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G2W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G2W_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G2W_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL2_VM_SCR_0_G1W_SHIFT                    _MK_SHIFT_CONST(9)
#define GPIO_CTL2_VM_SCR_0_G1W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G1W_SHIFT)
#define GPIO_CTL2_VM_SCR_0_G1W_RANGE                    9:9
#define GPIO_CTL2_VM_SCR_0_G1W_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_G1W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G1W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_G1W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G1W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G1W_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G1W_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL2_VM_SCR_0_G0W_SHIFT                    _MK_SHIFT_CONST(8)
#define GPIO_CTL2_VM_SCR_0_G0W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G0W_SHIFT)
#define GPIO_CTL2_VM_SCR_0_G0W_RANGE                    8:8
#define GPIO_CTL2_VM_SCR_0_G0W_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_G0W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G0W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_G0W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G0W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G0W_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G0W_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL2_VM_SCR_0_G7R_SHIFT                    _MK_SHIFT_CONST(7)
#define GPIO_CTL2_VM_SCR_0_G7R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G7R_SHIFT)
#define GPIO_CTL2_VM_SCR_0_G7R_RANGE                    7:7
#define GPIO_CTL2_VM_SCR_0_G7R_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_G7R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G7R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_G7R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G7R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G7R_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G7R_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL2_VM_SCR_0_G6R_SHIFT                    _MK_SHIFT_CONST(6)
#define GPIO_CTL2_VM_SCR_0_G6R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G6R_SHIFT)
#define GPIO_CTL2_VM_SCR_0_G6R_RANGE                    6:6
#define GPIO_CTL2_VM_SCR_0_G6R_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_G6R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G6R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_G6R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G6R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G6R_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G6R_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL2_VM_SCR_0_G5R_SHIFT                    _MK_SHIFT_CONST(5)
#define GPIO_CTL2_VM_SCR_0_G5R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G5R_SHIFT)
#define GPIO_CTL2_VM_SCR_0_G5R_RANGE                    5:5
#define GPIO_CTL2_VM_SCR_0_G5R_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_G5R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G5R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_G5R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G5R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G5R_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G5R_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL2_VM_SCR_0_G4R_SHIFT                    _MK_SHIFT_CONST(4)
#define GPIO_CTL2_VM_SCR_0_G4R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G4R_SHIFT)
#define GPIO_CTL2_VM_SCR_0_G4R_RANGE                    4:4
#define GPIO_CTL2_VM_SCR_0_G4R_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_G4R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G4R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_G4R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G4R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G4R_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G4R_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL2_VM_SCR_0_G3R_SHIFT                    _MK_SHIFT_CONST(3)
#define GPIO_CTL2_VM_SCR_0_G3R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G3R_SHIFT)
#define GPIO_CTL2_VM_SCR_0_G3R_RANGE                    3:3
#define GPIO_CTL2_VM_SCR_0_G3R_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_G3R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G3R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_G3R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G3R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G3R_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G3R_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL2_VM_SCR_0_G2R_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_CTL2_VM_SCR_0_G2R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G2R_SHIFT)
#define GPIO_CTL2_VM_SCR_0_G2R_RANGE                    2:2
#define GPIO_CTL2_VM_SCR_0_G2R_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_G2R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G2R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_G2R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G2R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G2R_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G2R_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL2_VM_SCR_0_G1R_SHIFT                    _MK_SHIFT_CONST(1)
#define GPIO_CTL2_VM_SCR_0_G1R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G1R_SHIFT)
#define GPIO_CTL2_VM_SCR_0_G1R_RANGE                    1:1
#define GPIO_CTL2_VM_SCR_0_G1R_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_G1R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G1R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_G1R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G1R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G1R_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G1R_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL2_VM_SCR_0_G0R_SHIFT                    _MK_SHIFT_CONST(0)
#define GPIO_CTL2_VM_SCR_0_G0R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G0R_SHIFT)
#define GPIO_CTL2_VM_SCR_0_G0R_RANGE                    0:0
#define GPIO_CTL2_VM_SCR_0_G0R_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_G0R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G0R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_G0R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G0R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G0R_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G0R_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0                     _MK_ADDR_CONST(0x2804)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SECURE                      0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_DUAL                        0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SCR                         0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_WORD_COUNT                  0x1
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_RESET_MASK                  _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_READ_MASK                   _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_WRITE_MASK                  _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SHIFT                       _MK_SHIFT_CONST(29)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_RANGE                       29:29
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_WOFFSET                     0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SHIFT                       _MK_SHIFT_CONST(28)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_RANGE                       28:28
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_WOFFSET                     0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SHIFT                       _MK_SHIFT_CONST(27)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_RANGE                       27:27
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_WOFFSET                     0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SHIFT                     _MK_SHIFT_CONST(24)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_FIELD                     _MK_FIELD_CONST(0x7, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_RANGE                     26:24
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_WOFFSET                   0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR7_SHIFT                   _MK_SHIFT_CONST(23)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR7_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR7_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR7_RANGE                   23:23
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR7_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR7_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR7_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR7_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR7_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR7_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR7_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR6_SHIFT                   _MK_SHIFT_CONST(22)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR6_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR6_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR6_RANGE                   22:22
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR6_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR6_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR6_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR6_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR6_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR6_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR6_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR5_SHIFT                   _MK_SHIFT_CONST(21)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR5_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR5_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR5_RANGE                   21:21
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR5_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR5_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR5_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR5_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR5_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR5_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR5_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR4_SHIFT                   _MK_SHIFT_CONST(20)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR4_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR4_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR4_RANGE                   20:20
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR4_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR4_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR4_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR4_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR4_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR3_SHIFT                   _MK_SHIFT_CONST(19)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR3_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR3_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR3_RANGE                   19:19
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR3_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR3_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR3_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR3_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR2_SHIFT                   _MK_SHIFT_CONST(18)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR2_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR2_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR2_RANGE                   18:18
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR2_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR2_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR2_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR2_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR1_SHIFT                   _MK_SHIFT_CONST(17)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR1_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR1_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR1_RANGE                   17:17
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR1_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR1_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR1_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR1_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR0_SHIFT                   _MK_SHIFT_CONST(16)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR0_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR0_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR0_RANGE                   16:16
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR0_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR0_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR0_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR0_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7W_SHIFT                   _MK_SHIFT_CONST(15)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7W_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7W_RANGE                   15:15
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7W_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6W_SHIFT                   _MK_SHIFT_CONST(14)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6W_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6W_RANGE                   14:14
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6W_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5W_SHIFT                   _MK_SHIFT_CONST(13)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5W_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5W_RANGE                   13:13
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5W_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4W_SHIFT                   _MK_SHIFT_CONST(12)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4W_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4W_RANGE                   12:12
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4W_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3W_SHIFT                   _MK_SHIFT_CONST(11)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3W_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3W_RANGE                   11:11
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3W_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2W_SHIFT                   _MK_SHIFT_CONST(10)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2W_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2W_RANGE                   10:10
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2W_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1W_SHIFT                   _MK_SHIFT_CONST(9)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1W_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1W_RANGE                   9:9
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1W_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0W_SHIFT                   _MK_SHIFT_CONST(8)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0W_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0W_RANGE                   8:8
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0W_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7R_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7R_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7R_RANGE                   7:7
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7R_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6R_SHIFT                   _MK_SHIFT_CONST(6)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6R_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6R_RANGE                   6:6
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6R_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5R_SHIFT                   _MK_SHIFT_CONST(5)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5R_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5R_RANGE                   5:5
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5R_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4R_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4R_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4R_RANGE                   4:4
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4R_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3R_SHIFT                   _MK_SHIFT_CONST(3)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3R_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3R_RANGE                   3:3
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3R_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2R_SHIFT                   _MK_SHIFT_CONST(2)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2R_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2R_RANGE                   2:2
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2R_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1R_SHIFT                   _MK_SHIFT_CONST(1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1R_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1R_RANGE                   1:1
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1R_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0R_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0R_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0R_RANGE                   0:0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0R_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_CTL2_INTERRUPT_STATUS_VM_0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0                 _MK_ADDR_CONST(0x2808)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_SECURE                  0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_DUAL                    0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_SCR                     GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_WORD_COUNT                      0x1
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_RESET_MASK                      _MK_MASK_CONST(0xff)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_READ_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_FIELD                  _MK_FIELD_CONST(0xff, GPIO_CTL2_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_RANGE                  7:0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_WOFFSET                        0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register GPIO_CTL2_SCR_0
#define GPIO_CTL2_SCR_0                 _MK_ADDR_CONST(0x280c)
#define GPIO_CTL2_SCR_0_SECURE                  0x0
#define GPIO_CTL2_SCR_0_DUAL                    0x0
#define GPIO_CTL2_SCR_0_SCR                     0
#define GPIO_CTL2_SCR_0_WORD_COUNT                      0x1
#define GPIO_CTL2_SCR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL2_SCR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL2_SCR_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL2_SCR_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_CTL2_SCR_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_SEC_LCK_SHIFT)
#define GPIO_CTL2_SCR_0_SEC_LCK_RANGE                   29:29
#define GPIO_CTL2_SCR_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_CTL2_SCR_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL2_SCR_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_CTL2_SCR_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_SEC_WEN_SHIFT)
#define GPIO_CTL2_SCR_0_SEC_WEN_RANGE                   28:28
#define GPIO_CTL2_SCR_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_CTL2_SCR_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL2_SCR_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_CTL2_SCR_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_SEC_REN_SHIFT)
#define GPIO_CTL2_SCR_0_SEC_REN_RANGE                   27:27
#define GPIO_CTL2_SCR_0_SEC_REN_WOFFSET                 0x0
#define GPIO_CTL2_SCR_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL2_SCR_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_CTL2_SCR_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_CTL2_SCR_0_SEC_OWNER_SHIFT)
#define GPIO_CTL2_SCR_0_SEC_OWNER_RANGE                 26:24
#define GPIO_CTL2_SCR_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_CTL2_SCR_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_CTL2_SCR_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_CTL2_SCR_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_CTL2_SCR_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_PR7_SHIFT)
#define GPIO_CTL2_SCR_0_PR7_RANGE                       23:23
#define GPIO_CTL2_SCR_0_PR7_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL2_SCR_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_CTL2_SCR_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_PR6_SHIFT)
#define GPIO_CTL2_SCR_0_PR6_RANGE                       22:22
#define GPIO_CTL2_SCR_0_PR6_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL2_SCR_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_CTL2_SCR_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_PR5_SHIFT)
#define GPIO_CTL2_SCR_0_PR5_RANGE                       21:21
#define GPIO_CTL2_SCR_0_PR5_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL2_SCR_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_CTL2_SCR_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_PR4_SHIFT)
#define GPIO_CTL2_SCR_0_PR4_RANGE                       20:20
#define GPIO_CTL2_SCR_0_PR4_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL2_SCR_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_CTL2_SCR_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_PR3_SHIFT)
#define GPIO_CTL2_SCR_0_PR3_RANGE                       19:19
#define GPIO_CTL2_SCR_0_PR3_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL2_SCR_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_CTL2_SCR_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_PR2_SHIFT)
#define GPIO_CTL2_SCR_0_PR2_RANGE                       18:18
#define GPIO_CTL2_SCR_0_PR2_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL2_SCR_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_CTL2_SCR_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_PR1_SHIFT)
#define GPIO_CTL2_SCR_0_PR1_RANGE                       17:17
#define GPIO_CTL2_SCR_0_PR1_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL2_SCR_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_CTL2_SCR_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_PR0_SHIFT)
#define GPIO_CTL2_SCR_0_PR0_RANGE                       16:16
#define GPIO_CTL2_SCR_0_PR0_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL2_SCR_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_CTL2_SCR_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G7W_SHIFT)
#define GPIO_CTL2_SCR_0_G7W_RANGE                       15:15
#define GPIO_CTL2_SCR_0_G7W_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL2_SCR_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_CTL2_SCR_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G6W_SHIFT)
#define GPIO_CTL2_SCR_0_G6W_RANGE                       14:14
#define GPIO_CTL2_SCR_0_G6W_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL2_SCR_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_CTL2_SCR_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G5W_SHIFT)
#define GPIO_CTL2_SCR_0_G5W_RANGE                       13:13
#define GPIO_CTL2_SCR_0_G5W_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL2_SCR_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_CTL2_SCR_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G4W_SHIFT)
#define GPIO_CTL2_SCR_0_G4W_RANGE                       12:12
#define GPIO_CTL2_SCR_0_G4W_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL2_SCR_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_CTL2_SCR_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G3W_SHIFT)
#define GPIO_CTL2_SCR_0_G3W_RANGE                       11:11
#define GPIO_CTL2_SCR_0_G3W_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL2_SCR_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_CTL2_SCR_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G2W_SHIFT)
#define GPIO_CTL2_SCR_0_G2W_RANGE                       10:10
#define GPIO_CTL2_SCR_0_G2W_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL2_SCR_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_CTL2_SCR_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G1W_SHIFT)
#define GPIO_CTL2_SCR_0_G1W_RANGE                       9:9
#define GPIO_CTL2_SCR_0_G1W_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL2_SCR_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_CTL2_SCR_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G0W_SHIFT)
#define GPIO_CTL2_SCR_0_G0W_RANGE                       8:8
#define GPIO_CTL2_SCR_0_G0W_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL2_SCR_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_CTL2_SCR_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G7R_SHIFT)
#define GPIO_CTL2_SCR_0_G7R_RANGE                       7:7
#define GPIO_CTL2_SCR_0_G7R_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL2_SCR_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_CTL2_SCR_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G6R_SHIFT)
#define GPIO_CTL2_SCR_0_G6R_RANGE                       6:6
#define GPIO_CTL2_SCR_0_G6R_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL2_SCR_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_CTL2_SCR_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G5R_SHIFT)
#define GPIO_CTL2_SCR_0_G5R_RANGE                       5:5
#define GPIO_CTL2_SCR_0_G5R_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL2_SCR_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_CTL2_SCR_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G4R_SHIFT)
#define GPIO_CTL2_SCR_0_G4R_RANGE                       4:4
#define GPIO_CTL2_SCR_0_G4R_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL2_SCR_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_CTL2_SCR_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G3R_SHIFT)
#define GPIO_CTL2_SCR_0_G3R_RANGE                       3:3
#define GPIO_CTL2_SCR_0_G3R_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL2_SCR_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_CTL2_SCR_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G2R_SHIFT)
#define GPIO_CTL2_SCR_0_G2R_RANGE                       2:2
#define GPIO_CTL2_SCR_0_G2R_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL2_SCR_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_CTL2_SCR_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G1R_SHIFT)
#define GPIO_CTL2_SCR_0_G1R_RANGE                       1:1
#define GPIO_CTL2_SCR_0_G1R_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL2_SCR_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_CTL2_SCR_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G0R_SHIFT)
#define GPIO_CTL2_SCR_0_G0R_RANGE                       0:0
#define GPIO_CTL2_SCR_0_G0R_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_CTL2_ICG_EN_OVERRIDE_0
#define GPIO_CTL2_ICG_EN_OVERRIDE_0                     _MK_ADDR_CONST(0x2810)
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_SECURE                      0x0
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_DUAL                        0x0
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_WORD_COUNT                  0x1
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_FIELD                  _MK_FIELD_CONST(0x1, GPIO_CTL2_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SHIFT)
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_RANGE                  0:0
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_WOFFSET                        0x0
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register GPIO_X_INT0_ROUTE_MAPPING_0
#define GPIO_X_INT0_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x2814)
#define GPIO_X_INT0_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_X_INT0_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_X_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_X_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_X_INT0_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_INT0_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_X_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_X_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_INT0_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_X_INT0_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_X_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_X_INT0_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_X_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_X_INT0_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_X_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_X_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_X_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_X_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_X_INT1_ROUTE_MAPPING_0
#define GPIO_X_INT1_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x2818)
#define GPIO_X_INT1_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_X_INT1_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_X_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_X_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_X_INT1_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_INT1_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_X_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_X_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_INT1_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_X_INT1_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_X_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_X_INT1_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_X_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_X_INT1_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_X_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_X_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_X_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_X_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_X_INT2_ROUTE_MAPPING_0
#define GPIO_X_INT2_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x281c)
#define GPIO_X_INT2_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_X_INT2_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_X_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_X_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_X_INT2_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_INT2_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_X_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_X_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_INT2_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_X_INT2_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_X_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_X_INT2_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_X_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_X_INT2_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_X_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_X_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_X_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_X_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_X_INT3_ROUTE_MAPPING_0
#define GPIO_X_INT3_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x2820)
#define GPIO_X_INT3_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_X_INT3_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_X_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_X_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_X_INT3_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_INT3_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_X_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_X_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_INT3_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_X_INT3_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_X_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_X_INT3_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_X_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_X_INT3_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_X_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_X_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_X_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_X_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_X_INT4_ROUTE_MAPPING_0
#define GPIO_X_INT4_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x2824)
#define GPIO_X_INT4_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_X_INT4_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_X_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_X_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_X_INT4_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_INT4_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_X_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_X_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_INT4_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_X_INT4_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_X_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_X_INT4_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_X_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_X_INT4_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_X_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_X_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_X_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_X_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_X_INT5_ROUTE_MAPPING_0
#define GPIO_X_INT5_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x2828)
#define GPIO_X_INT5_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_X_INT5_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_X_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_X_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_X_INT5_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_INT5_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_X_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_X_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_INT5_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_X_INT5_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_X_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_X_INT5_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_X_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_X_INT5_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_X_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_X_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_X_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_X_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_X_INT6_ROUTE_MAPPING_0
#define GPIO_X_INT6_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x282c)
#define GPIO_X_INT6_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_X_INT6_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_X_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_X_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_X_INT6_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_INT6_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_X_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_X_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_INT6_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_X_INT6_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_X_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_X_INT6_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_X_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_X_INT6_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_X_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_X_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_X_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_X_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_X_INT7_ROUTE_MAPPING_0
#define GPIO_X_INT7_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x2830)
#define GPIO_X_INT7_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_X_INT7_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_X_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_X_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_X_INT7_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_INT7_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_X_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_X_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_INT7_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_X_INT7_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_X_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_X_INT7_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_X_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_X_INT7_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_X_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_X_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_X_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_X_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_Y_INT0_ROUTE_MAPPING_0
#define GPIO_Y_INT0_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x2834)
#define GPIO_Y_INT0_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_Y_INT0_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_Y_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_Y_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_Y_INT0_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Y_INT0_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Y_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INT0_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_Y_INT0_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Y_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_Y_INT0_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_Y_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_Y_INT0_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_Y_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_Y_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Y_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Y_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_Y_INT1_ROUTE_MAPPING_0
#define GPIO_Y_INT1_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x2838)
#define GPIO_Y_INT1_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_Y_INT1_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_Y_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_Y_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_Y_INT1_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Y_INT1_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Y_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INT1_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_Y_INT1_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Y_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_Y_INT1_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_Y_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_Y_INT1_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_Y_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_Y_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Y_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Y_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_Y_INT2_ROUTE_MAPPING_0
#define GPIO_Y_INT2_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x283c)
#define GPIO_Y_INT2_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_Y_INT2_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_Y_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_Y_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_Y_INT2_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Y_INT2_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Y_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INT2_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_Y_INT2_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Y_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_Y_INT2_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_Y_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_Y_INT2_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_Y_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_Y_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Y_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Y_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_Y_INT3_ROUTE_MAPPING_0
#define GPIO_Y_INT3_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x2840)
#define GPIO_Y_INT3_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_Y_INT3_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_Y_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_Y_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_Y_INT3_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Y_INT3_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Y_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INT3_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_Y_INT3_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Y_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_Y_INT3_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_Y_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_Y_INT3_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_Y_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_Y_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Y_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Y_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_Y_INT4_ROUTE_MAPPING_0
#define GPIO_Y_INT4_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x2844)
#define GPIO_Y_INT4_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_Y_INT4_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_Y_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_Y_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_Y_INT4_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Y_INT4_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Y_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INT4_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_Y_INT4_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Y_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_Y_INT4_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_Y_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_Y_INT4_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_Y_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_Y_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Y_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Y_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_Y_INT5_ROUTE_MAPPING_0
#define GPIO_Y_INT5_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x2848)
#define GPIO_Y_INT5_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_Y_INT5_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_Y_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_Y_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_Y_INT5_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Y_INT5_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Y_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INT5_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_Y_INT5_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Y_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_Y_INT5_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_Y_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_Y_INT5_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_Y_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_Y_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Y_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Y_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_Y_INT6_ROUTE_MAPPING_0
#define GPIO_Y_INT6_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x284c)
#define GPIO_Y_INT6_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_Y_INT6_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_Y_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_Y_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_Y_INT6_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Y_INT6_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Y_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INT6_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_Y_INT6_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Y_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_Y_INT6_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_Y_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_Y_INT6_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_Y_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_Y_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Y_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Y_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_Y_INT7_ROUTE_MAPPING_0
#define GPIO_Y_INT7_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x2850)
#define GPIO_Y_INT7_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_Y_INT7_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_Y_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_Y_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_Y_INT7_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Y_INT7_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Y_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INT7_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_Y_INT7_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Y_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_Y_INT7_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_Y_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_Y_INT7_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_Y_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_Y_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Y_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Y_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_Z_INT0_ROUTE_MAPPING_0
#define GPIO_Z_INT0_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x2854)
#define GPIO_Z_INT0_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_Z_INT0_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_Z_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_Z_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_Z_INT0_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Z_INT0_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Z_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Z_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_INT0_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_Z_INT0_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Z_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_Z_INT0_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_Z_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_Z_INT0_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_Z_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_Z_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Z_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Z_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Z_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_Z_INT1_ROUTE_MAPPING_0
#define GPIO_Z_INT1_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x2858)
#define GPIO_Z_INT1_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_Z_INT1_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_Z_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_Z_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_Z_INT1_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Z_INT1_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Z_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Z_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_INT1_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_Z_INT1_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Z_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_Z_INT1_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_Z_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_Z_INT1_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_Z_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_Z_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Z_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Z_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Z_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_Z_INT2_ROUTE_MAPPING_0
#define GPIO_Z_INT2_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x285c)
#define GPIO_Z_INT2_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_Z_INT2_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_Z_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_Z_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_Z_INT2_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Z_INT2_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Z_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Z_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_INT2_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_Z_INT2_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Z_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_Z_INT2_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_Z_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_Z_INT2_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_Z_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_Z_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Z_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Z_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Z_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_Z_INT3_ROUTE_MAPPING_0
#define GPIO_Z_INT3_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x2860)
#define GPIO_Z_INT3_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_Z_INT3_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_Z_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_Z_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_Z_INT3_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Z_INT3_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Z_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Z_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_INT3_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_Z_INT3_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Z_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_Z_INT3_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_Z_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_Z_INT3_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_Z_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_Z_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Z_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Z_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Z_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_Z_INT4_ROUTE_MAPPING_0
#define GPIO_Z_INT4_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x2864)
#define GPIO_Z_INT4_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_Z_INT4_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_Z_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_Z_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_Z_INT4_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Z_INT4_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Z_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Z_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_INT4_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_Z_INT4_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Z_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_Z_INT4_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_Z_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_Z_INT4_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_Z_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_Z_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Z_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Z_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Z_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_Z_INT5_ROUTE_MAPPING_0
#define GPIO_Z_INT5_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x2868)
#define GPIO_Z_INT5_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_Z_INT5_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_Z_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_Z_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_Z_INT5_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Z_INT5_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Z_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Z_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_INT5_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_Z_INT5_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Z_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_Z_INT5_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_Z_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_Z_INT5_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_Z_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_Z_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Z_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Z_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Z_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_Z_INT6_ROUTE_MAPPING_0
#define GPIO_Z_INT6_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x286c)
#define GPIO_Z_INT6_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_Z_INT6_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_Z_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_Z_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_Z_INT6_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Z_INT6_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Z_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Z_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_INT6_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_Z_INT6_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Z_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_Z_INT6_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_Z_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_Z_INT6_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_Z_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_Z_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Z_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Z_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Z_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_Z_INT7_ROUTE_MAPPING_0
#define GPIO_Z_INT7_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x2870)
#define GPIO_Z_INT7_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_Z_INT7_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_Z_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_Z_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_Z_INT7_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Z_INT7_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Z_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Z_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_INT7_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_Z_INT7_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Z_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_Z_INT7_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_Z_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_Z_INT7_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_Z_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_Z_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Z_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Z_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Z_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_M_INT0_ROUTE_MAPPING_0
#define GPIO_M_INT0_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x2874)
#define GPIO_M_INT0_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_M_INT0_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_M_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_M_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_M_INT0_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_M_INT0_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_M_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_M_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_INT0_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_M_INT0_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_M_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_M_INT0_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_M_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_M_INT0_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_M_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_M_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_M_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_M_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_M_INT1_ROUTE_MAPPING_0
#define GPIO_M_INT1_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x2878)
#define GPIO_M_INT1_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_M_INT1_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_M_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_M_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_M_INT1_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_M_INT1_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_M_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_M_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_INT1_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_M_INT1_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_M_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_M_INT1_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_M_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_M_INT1_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_M_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_M_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_M_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_M_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_M_INT2_ROUTE_MAPPING_0
#define GPIO_M_INT2_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x287c)
#define GPIO_M_INT2_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_M_INT2_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_M_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_M_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_M_INT2_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_M_INT2_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_M_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_M_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_INT2_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_M_INT2_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_M_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_M_INT2_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_M_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_M_INT2_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_M_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_M_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_M_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_M_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_M_INT3_ROUTE_MAPPING_0
#define GPIO_M_INT3_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x2880)
#define GPIO_M_INT3_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_M_INT3_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_M_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_M_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_M_INT3_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_M_INT3_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_M_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_M_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_INT3_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_M_INT3_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_M_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_M_INT3_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_M_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_M_INT3_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_M_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_M_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_M_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_M_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_M_INT4_ROUTE_MAPPING_0
#define GPIO_M_INT4_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x2884)
#define GPIO_M_INT4_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_M_INT4_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_M_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_M_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_M_INT4_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_M_INT4_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_M_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_M_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_INT4_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_M_INT4_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_M_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_M_INT4_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_M_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_M_INT4_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_M_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_M_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_M_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_M_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_M_INT5_ROUTE_MAPPING_0
#define GPIO_M_INT5_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x2888)
#define GPIO_M_INT5_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_M_INT5_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_M_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_M_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_M_INT5_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_M_INT5_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_M_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_M_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_INT5_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_M_INT5_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_M_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_M_INT5_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_M_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_M_INT5_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_M_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_M_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_M_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_M_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_M_INT6_ROUTE_MAPPING_0
#define GPIO_M_INT6_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x288c)
#define GPIO_M_INT6_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_M_INT6_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_M_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_M_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_M_INT6_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_M_INT6_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_M_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_M_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_INT6_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_M_INT6_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_M_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_M_INT6_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_M_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_M_INT6_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_M_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_M_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_M_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_M_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_M_INT7_ROUTE_MAPPING_0
#define GPIO_M_INT7_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x2890)
#define GPIO_M_INT7_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_M_INT7_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_M_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_M_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_M_INT7_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_M_INT7_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_M_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_M_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_INT7_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_M_INT7_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_M_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_M_INT7_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_M_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_M_INT7_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_M_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_M_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_M_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_M_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_N_INT0_ROUTE_MAPPING_0
#define GPIO_N_INT0_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x2894)
#define GPIO_N_INT0_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_N_INT0_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_N_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_N_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_N_INT0_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_N_INT0_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_N_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_N_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_INT0_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x7)
#define GPIO_N_INT0_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_N_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_N_INT0_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x7, GPIO_N_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_N_INT0_ROUTE_MAPPING_0_VAL_RANGE                   2:0
#define GPIO_N_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_N_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define GPIO_N_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_N_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_N_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_N_INT1_ROUTE_MAPPING_0
#define GPIO_N_INT1_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x2898)
#define GPIO_N_INT1_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_N_INT1_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_N_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_N_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_N_INT1_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_N_INT1_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_N_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_N_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_INT1_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x7)
#define GPIO_N_INT1_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_N_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_N_INT1_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x7, GPIO_N_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_N_INT1_ROUTE_MAPPING_0_VAL_RANGE                   2:0
#define GPIO_N_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_N_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define GPIO_N_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_N_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_N_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_N_INT2_ROUTE_MAPPING_0
#define GPIO_N_INT2_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x289c)
#define GPIO_N_INT2_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_N_INT2_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_N_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_N_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_N_INT2_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_N_INT2_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_N_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_N_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_INT2_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x7)
#define GPIO_N_INT2_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_N_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_N_INT2_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x7, GPIO_N_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_N_INT2_ROUTE_MAPPING_0_VAL_RANGE                   2:0
#define GPIO_N_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_N_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define GPIO_N_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_N_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_N_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_N_INT3_ROUTE_MAPPING_0
#define GPIO_N_INT3_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x28a0)
#define GPIO_N_INT3_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_N_INT3_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_N_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_N_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_N_INT3_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_N_INT3_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_N_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_N_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_INT3_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x7)
#define GPIO_N_INT3_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_N_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_N_INT3_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x7, GPIO_N_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_N_INT3_ROUTE_MAPPING_0_VAL_RANGE                   2:0
#define GPIO_N_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_N_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define GPIO_N_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_N_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_N_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_N_INT4_ROUTE_MAPPING_0
#define GPIO_N_INT4_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x28a4)
#define GPIO_N_INT4_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_N_INT4_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_N_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_N_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_N_INT4_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_N_INT4_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_N_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_N_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_INT4_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x7)
#define GPIO_N_INT4_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_N_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_N_INT4_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x7, GPIO_N_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_N_INT4_ROUTE_MAPPING_0_VAL_RANGE                   2:0
#define GPIO_N_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_N_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define GPIO_N_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_N_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_N_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_N_INT5_ROUTE_MAPPING_0
#define GPIO_N_INT5_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x28a8)
#define GPIO_N_INT5_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_N_INT5_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_N_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_N_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_N_INT5_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_N_INT5_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_N_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_N_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_INT5_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x7)
#define GPIO_N_INT5_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_N_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_N_INT5_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x7, GPIO_N_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_N_INT5_ROUTE_MAPPING_0_VAL_RANGE                   2:0
#define GPIO_N_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_N_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define GPIO_N_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_N_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_N_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_N_INT6_ROUTE_MAPPING_0
#define GPIO_N_INT6_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x28ac)
#define GPIO_N_INT6_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_N_INT6_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_N_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_N_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_N_INT6_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_N_INT6_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_N_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_N_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_INT6_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x7)
#define GPIO_N_INT6_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_N_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_N_INT6_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x7, GPIO_N_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_N_INT6_ROUTE_MAPPING_0_VAL_RANGE                   2:0
#define GPIO_N_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_N_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define GPIO_N_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_N_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_N_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_N_INT7_ROUTE_MAPPING_0
#define GPIO_N_INT7_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x28b0)
#define GPIO_N_INT7_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_N_INT7_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_N_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_N_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_N_INT7_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_N_INT7_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_N_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_N_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_INT7_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x7)
#define GPIO_N_INT7_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_N_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_N_INT7_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x7, GPIO_N_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_N_INT7_ROUTE_MAPPING_0_VAL_RANGE                   2:0
#define GPIO_N_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_N_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define GPIO_N_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_N_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_N_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_P_INT0_ROUTE_MAPPING_0
#define GPIO_P_INT0_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x28b4)
#define GPIO_P_INT0_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_P_INT0_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_P_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_P_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_P_INT0_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_P_INT0_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_P_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_P_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_INT0_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_P_INT0_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_P_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_P_INT0_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_P_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_P_INT0_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_P_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_P_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_P_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_P_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_P_INT1_ROUTE_MAPPING_0
#define GPIO_P_INT1_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x28b8)
#define GPIO_P_INT1_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_P_INT1_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_P_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_P_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_P_INT1_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_P_INT1_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_P_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_P_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_INT1_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_P_INT1_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_P_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_P_INT1_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_P_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_P_INT1_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_P_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_P_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_P_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_P_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_P_INT2_ROUTE_MAPPING_0
#define GPIO_P_INT2_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x28bc)
#define GPIO_P_INT2_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_P_INT2_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_P_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_P_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_P_INT2_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_P_INT2_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_P_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_P_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_INT2_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_P_INT2_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_P_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_P_INT2_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_P_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_P_INT2_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_P_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_P_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_P_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_P_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_P_INT3_ROUTE_MAPPING_0
#define GPIO_P_INT3_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x28c0)
#define GPIO_P_INT3_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_P_INT3_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_P_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_P_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_P_INT3_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_P_INT3_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_P_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_P_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_INT3_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_P_INT3_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_P_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_P_INT3_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_P_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_P_INT3_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_P_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_P_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_P_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_P_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_P_INT4_ROUTE_MAPPING_0
#define GPIO_P_INT4_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x28c4)
#define GPIO_P_INT4_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_P_INT4_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_P_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_P_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_P_INT4_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_P_INT4_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_P_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_P_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_INT4_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_P_INT4_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_P_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_P_INT4_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_P_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_P_INT4_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_P_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_P_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_P_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_P_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_P_INT5_ROUTE_MAPPING_0
#define GPIO_P_INT5_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x28c8)
#define GPIO_P_INT5_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_P_INT5_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_P_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_P_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_P_INT5_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_P_INT5_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_P_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_P_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_INT5_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_P_INT5_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_P_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_P_INT5_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_P_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_P_INT5_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_P_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_P_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_P_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_P_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_P_INT6_ROUTE_MAPPING_0
#define GPIO_P_INT6_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x28cc)
#define GPIO_P_INT6_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_P_INT6_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_P_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_P_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_P_INT6_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_P_INT6_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_P_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_P_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_INT6_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_P_INT6_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_P_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_P_INT6_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_P_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_P_INT6_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_P_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_P_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_P_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_P_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_P_INT7_ROUTE_MAPPING_0
#define GPIO_P_INT7_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x28d0)
#define GPIO_P_INT7_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_P_INT7_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_P_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_P_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_P_INT7_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_P_INT7_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_P_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_P_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_INT7_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_P_INT7_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_P_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_P_INT7_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_P_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_P_INT7_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_P_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_P_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_P_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_P_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_Q_INT0_ROUTE_MAPPING_0
#define GPIO_Q_INT0_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x28d4)
#define GPIO_Q_INT0_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_Q_INT0_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_Q_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_Q_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_Q_INT0_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Q_INT0_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Q_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INT0_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_Q_INT0_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Q_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_Q_INT0_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_Q_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_Q_INT0_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_Q_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_Q_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Q_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Q_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_Q_INT1_ROUTE_MAPPING_0
#define GPIO_Q_INT1_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x28d8)
#define GPIO_Q_INT1_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_Q_INT1_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_Q_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_Q_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_Q_INT1_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Q_INT1_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Q_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INT1_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_Q_INT1_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Q_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_Q_INT1_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_Q_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_Q_INT1_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_Q_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_Q_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Q_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Q_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_Q_INT2_ROUTE_MAPPING_0
#define GPIO_Q_INT2_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x28dc)
#define GPIO_Q_INT2_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_Q_INT2_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_Q_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_Q_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_Q_INT2_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Q_INT2_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Q_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INT2_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_Q_INT2_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Q_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_Q_INT2_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_Q_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_Q_INT2_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_Q_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_Q_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Q_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Q_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_Q_INT3_ROUTE_MAPPING_0
#define GPIO_Q_INT3_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x28e0)
#define GPIO_Q_INT3_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_Q_INT3_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_Q_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_Q_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_Q_INT3_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Q_INT3_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Q_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INT3_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_Q_INT3_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Q_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_Q_INT3_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_Q_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_Q_INT3_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_Q_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_Q_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Q_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Q_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_Q_INT4_ROUTE_MAPPING_0
#define GPIO_Q_INT4_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x28e4)
#define GPIO_Q_INT4_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_Q_INT4_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_Q_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_Q_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_Q_INT4_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Q_INT4_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Q_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INT4_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_Q_INT4_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Q_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_Q_INT4_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_Q_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_Q_INT4_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_Q_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_Q_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Q_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Q_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_Q_INT5_ROUTE_MAPPING_0
#define GPIO_Q_INT5_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x28e8)
#define GPIO_Q_INT5_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_Q_INT5_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_Q_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_Q_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_Q_INT5_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Q_INT5_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Q_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INT5_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_Q_INT5_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Q_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_Q_INT5_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_Q_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_Q_INT5_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_Q_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_Q_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Q_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Q_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_Q_INT6_ROUTE_MAPPING_0
#define GPIO_Q_INT6_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x28ec)
#define GPIO_Q_INT6_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_Q_INT6_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_Q_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_Q_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_Q_INT6_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Q_INT6_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Q_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INT6_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_Q_INT6_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Q_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_Q_INT6_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_Q_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_Q_INT6_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_Q_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_Q_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Q_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Q_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_Q_INT7_ROUTE_MAPPING_0
#define GPIO_Q_INT7_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x28f0)
#define GPIO_Q_INT7_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_Q_INT7_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_Q_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_Q_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_Q_INT7_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Q_INT7_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Q_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INT7_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_Q_INT7_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Q_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_Q_INT7_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_Q_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_Q_INT7_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_Q_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_Q_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Q_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Q_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_R_INT0_ROUTE_MAPPING_0
#define GPIO_R_INT0_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x28f4)
#define GPIO_R_INT0_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_R_INT0_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_R_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_R_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_R_INT0_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_R_INT0_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_R_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_R_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_INT0_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x3f)
#define GPIO_R_INT0_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_R_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_R_INT0_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x3f, GPIO_R_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_R_INT0_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_R_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_R_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
#define GPIO_R_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_R_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_R_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_R_INT1_ROUTE_MAPPING_0
#define GPIO_R_INT1_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x28f8)
#define GPIO_R_INT1_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_R_INT1_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_R_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_R_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_R_INT1_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_R_INT1_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_R_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_R_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_INT1_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x3f)
#define GPIO_R_INT1_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_R_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_R_INT1_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x3f, GPIO_R_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_R_INT1_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_R_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_R_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
#define GPIO_R_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_R_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_R_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_R_INT2_ROUTE_MAPPING_0
#define GPIO_R_INT2_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x28fc)
#define GPIO_R_INT2_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_R_INT2_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_R_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_R_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_R_INT2_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_R_INT2_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_R_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_R_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_INT2_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x3f)
#define GPIO_R_INT2_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_R_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_R_INT2_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x3f, GPIO_R_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_R_INT2_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_R_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_R_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
#define GPIO_R_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_R_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_R_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_R_INT3_ROUTE_MAPPING_0
#define GPIO_R_INT3_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x2900)
#define GPIO_R_INT3_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_R_INT3_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_R_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_R_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_R_INT3_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_R_INT3_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_R_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_R_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_INT3_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x3f)
#define GPIO_R_INT3_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_R_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_R_INT3_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x3f, GPIO_R_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_R_INT3_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_R_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_R_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
#define GPIO_R_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_R_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_R_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_R_INT4_ROUTE_MAPPING_0
#define GPIO_R_INT4_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x2904)
#define GPIO_R_INT4_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_R_INT4_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_R_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_R_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_R_INT4_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_R_INT4_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_R_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_R_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_INT4_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x3f)
#define GPIO_R_INT4_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_R_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_R_INT4_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x3f, GPIO_R_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_R_INT4_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_R_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_R_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
#define GPIO_R_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_R_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_R_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_R_INT5_ROUTE_MAPPING_0
#define GPIO_R_INT5_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x2908)
#define GPIO_R_INT5_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_R_INT5_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_R_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_R_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_R_INT5_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_R_INT5_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_R_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_R_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_INT5_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x3f)
#define GPIO_R_INT5_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_R_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_R_INT5_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x3f, GPIO_R_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_R_INT5_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_R_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_R_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
#define GPIO_R_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_R_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_R_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_R_INT6_ROUTE_MAPPING_0
#define GPIO_R_INT6_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x290c)
#define GPIO_R_INT6_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_R_INT6_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_R_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_R_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_R_INT6_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_R_INT6_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_R_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_R_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_INT6_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x3f)
#define GPIO_R_INT6_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_R_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_R_INT6_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x3f, GPIO_R_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_R_INT6_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_R_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_R_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
#define GPIO_R_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_R_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_R_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_R_INT7_ROUTE_MAPPING_0
#define GPIO_R_INT7_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x2910)
#define GPIO_R_INT7_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_R_INT7_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_R_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_R_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_R_INT7_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_R_INT7_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_R_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_R_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_INT7_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x3f)
#define GPIO_R_INT7_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_R_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_R_INT7_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x3f, GPIO_R_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_R_INT7_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_R_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_R_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
#define GPIO_R_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_R_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_R_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_CTL2_SPARE_0
#define GPIO_CTL2_SPARE_0                       _MK_ADDR_CONST(0x2914)
#define GPIO_CTL2_SPARE_0_SECURE                        0x0
#define GPIO_CTL2_SPARE_0_DUAL                  0x0
#define GPIO_CTL2_SPARE_0_SCR                   0
#define GPIO_CTL2_SPARE_0_WORD_COUNT                    0x1
#define GPIO_CTL2_SPARE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SPARE_0_RESET_MASK                    _MK_MASK_CONST(0xffff)
#define GPIO_CTL2_SPARE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SPARE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SPARE_0_READ_MASK                     _MK_MASK_CONST(0xffff)
#define GPIO_CTL2_SPARE_0_WRITE_MASK                    _MK_MASK_CONST(0xffff)
#define GPIO_CTL2_SPARE_0_SPARE_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_CTL2_SPARE_0_SPARE_FIELD                   _MK_FIELD_CONST(0xffff, GPIO_CTL2_SPARE_0_SPARE_SHIFT)
#define GPIO_CTL2_SPARE_0_SPARE_RANGE                   15:0
#define GPIO_CTL2_SPARE_0_SPARE_WOFFSET                 0x0
#define GPIO_CTL2_SPARE_0_SPARE_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SPARE_0_SPARE_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define GPIO_CTL2_SPARE_0_SPARE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SPARE_0_SPARE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SPARE_0_SPARE_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL2_SPARE_0_SPARE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_K_VM_00_0
#define GPIO_K_VM_00_0                  _MK_ADDR_CONST(0x3000)
#define GPIO_K_VM_00_0_SECURE                   0x0
#define GPIO_K_VM_00_0_DUAL                     0x0
#define GPIO_K_VM_00_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_K_VM_00_0_WORD_COUNT                       0x1
#define GPIO_K_VM_00_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_K_VM_00_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_K_VM_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_K_VM_00_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_K_VM_00_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_K_VM_00_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_00_0_VM1_SHIFT)
#define GPIO_K_VM_00_0_VM1_RANGE                        1:0
#define GPIO_K_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_K_VM_00_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_00_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_00_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_00_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_K_VM_00_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_00_0_VM2_SHIFT)
#define GPIO_K_VM_00_0_VM2_RANGE                        3:2
#define GPIO_K_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_K_VM_00_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_00_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_00_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_00_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_K_VM_00_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_00_0_VM3_SHIFT)
#define GPIO_K_VM_00_0_VM3_RANGE                        5:4
#define GPIO_K_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_K_VM_00_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_00_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_00_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_00_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_K_VM_00_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_00_0_VM4_SHIFT)
#define GPIO_K_VM_00_0_VM4_RANGE                        7:6
#define GPIO_K_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_K_VM_00_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_00_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_00_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_00_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_K_VM_00_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_00_0_VM5_SHIFT)
#define GPIO_K_VM_00_0_VM5_RANGE                        9:8
#define GPIO_K_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_K_VM_00_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_00_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_00_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_00_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_K_VM_00_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_00_0_VM6_SHIFT)
#define GPIO_K_VM_00_0_VM6_RANGE                        11:10
#define GPIO_K_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_K_VM_00_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_00_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_00_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_00_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_K_VM_00_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_00_0_VM7_SHIFT)
#define GPIO_K_VM_00_0_VM7_RANGE                        13:12
#define GPIO_K_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_K_VM_00_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_00_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_00_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_00_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_K_VM_00_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_00_0_VM8_SHIFT)
#define GPIO_K_VM_00_0_VM8_RANGE                        15:14
#define GPIO_K_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_K_VM_00_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_00_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_00_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_K_SCR_00_0
#define GPIO_K_SCR_00_0                 _MK_ADDR_CONST(0x3004)
#define GPIO_K_SCR_00_0_SECURE                  0x0
#define GPIO_K_SCR_00_0_DUAL                    0x0
#define GPIO_K_SCR_00_0_SCR                     0
#define GPIO_K_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_K_SCR_00_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_K_SCR_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_K_SCR_00_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_K_SCR_00_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_K_SCR_00_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_K_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_K_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_K_SCR_00_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_00_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_K_SCR_00_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_K_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_K_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_K_SCR_00_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_00_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_K_SCR_00_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_K_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_K_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_K_SCR_00_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_00_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_K_SCR_00_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_K_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_K_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_K_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_K_SCR_00_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_K_SCR_00_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_00_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_K_SCR_00_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_PR7_SHIFT)
#define GPIO_K_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_K_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_00_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_K_SCR_00_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_PR6_SHIFT)
#define GPIO_K_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_K_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_00_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_K_SCR_00_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_PR5_SHIFT)
#define GPIO_K_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_K_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_00_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_K_SCR_00_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_PR4_SHIFT)
#define GPIO_K_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_K_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_00_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_K_SCR_00_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_PR3_SHIFT)
#define GPIO_K_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_K_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_00_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_K_SCR_00_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_PR2_SHIFT)
#define GPIO_K_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_K_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_00_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_K_SCR_00_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_PR1_SHIFT)
#define GPIO_K_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_K_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_00_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_K_SCR_00_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_PR0_SHIFT)
#define GPIO_K_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_K_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_00_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_K_SCR_00_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G7W_SHIFT)
#define GPIO_K_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_K_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_00_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_K_SCR_00_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G6W_SHIFT)
#define GPIO_K_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_K_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_00_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_K_SCR_00_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G5W_SHIFT)
#define GPIO_K_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_K_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_00_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_K_SCR_00_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G4W_SHIFT)
#define GPIO_K_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_K_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_00_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_K_SCR_00_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G3W_SHIFT)
#define GPIO_K_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_K_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_00_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_K_SCR_00_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G2W_SHIFT)
#define GPIO_K_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_K_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_00_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_K_SCR_00_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G1W_SHIFT)
#define GPIO_K_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_K_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_00_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_K_SCR_00_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G0W_SHIFT)
#define GPIO_K_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_K_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_00_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_K_SCR_00_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G7R_SHIFT)
#define GPIO_K_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_K_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_00_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_K_SCR_00_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G6R_SHIFT)
#define GPIO_K_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_K_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_00_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_K_SCR_00_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G5R_SHIFT)
#define GPIO_K_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_K_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_00_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_K_SCR_00_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G4R_SHIFT)
#define GPIO_K_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_K_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_00_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_K_SCR_00_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G3R_SHIFT)
#define GPIO_K_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_K_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_00_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_K_SCR_00_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G2R_SHIFT)
#define GPIO_K_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_K_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_00_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_K_SCR_00_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G1R_SHIFT)
#define GPIO_K_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_K_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_00_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_K_SCR_00_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G0R_SHIFT)
#define GPIO_K_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_K_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_K_VM_01_0
#define GPIO_K_VM_01_0                  _MK_ADDR_CONST(0x3008)
#define GPIO_K_VM_01_0_SECURE                   0x0
#define GPIO_K_VM_01_0_DUAL                     0x0
#define GPIO_K_VM_01_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_K_VM_01_0_WORD_COUNT                       0x1
#define GPIO_K_VM_01_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_K_VM_01_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_K_VM_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_K_VM_01_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_K_VM_01_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_K_VM_01_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_K_VM_01_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_01_0_VM1_SHIFT)
#define GPIO_K_VM_01_0_VM1_RANGE                        1:0
#define GPIO_K_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_K_VM_01_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_01_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_01_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_01_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_01_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_01_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_01_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_K_VM_01_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_01_0_VM2_SHIFT)
#define GPIO_K_VM_01_0_VM2_RANGE                        3:2
#define GPIO_K_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_K_VM_01_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_01_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_01_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_01_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_01_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_01_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_01_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_K_VM_01_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_01_0_VM3_SHIFT)
#define GPIO_K_VM_01_0_VM3_RANGE                        5:4
#define GPIO_K_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_K_VM_01_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_01_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_01_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_01_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_01_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_01_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_01_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_K_VM_01_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_01_0_VM4_SHIFT)
#define GPIO_K_VM_01_0_VM4_RANGE                        7:6
#define GPIO_K_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_K_VM_01_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_01_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_01_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_01_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_01_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_01_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_01_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_K_VM_01_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_01_0_VM5_SHIFT)
#define GPIO_K_VM_01_0_VM5_RANGE                        9:8
#define GPIO_K_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_K_VM_01_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_01_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_01_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_01_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_01_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_01_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_01_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_K_VM_01_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_01_0_VM6_SHIFT)
#define GPIO_K_VM_01_0_VM6_RANGE                        11:10
#define GPIO_K_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_K_VM_01_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_01_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_01_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_01_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_01_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_01_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_01_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_K_VM_01_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_01_0_VM7_SHIFT)
#define GPIO_K_VM_01_0_VM7_RANGE                        13:12
#define GPIO_K_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_K_VM_01_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_01_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_01_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_01_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_01_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_01_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_01_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_K_VM_01_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_01_0_VM8_SHIFT)
#define GPIO_K_VM_01_0_VM8_RANGE                        15:14
#define GPIO_K_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_K_VM_01_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_01_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_01_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_01_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_01_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_01_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_K_SCR_01_0
#define GPIO_K_SCR_01_0                 _MK_ADDR_CONST(0x300c)
#define GPIO_K_SCR_01_0_SECURE                  0x0
#define GPIO_K_SCR_01_0_DUAL                    0x0
#define GPIO_K_SCR_01_0_SCR                     0
#define GPIO_K_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_K_SCR_01_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_K_SCR_01_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_K_SCR_01_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_K_SCR_01_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_K_SCR_01_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_K_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_K_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_K_SCR_01_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_01_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_01_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_K_SCR_01_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_K_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_K_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_K_SCR_01_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_01_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_01_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_K_SCR_01_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_K_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_K_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_K_SCR_01_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_01_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_01_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_K_SCR_01_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_K_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_K_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_K_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_K_SCR_01_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_K_SCR_01_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_01_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_K_SCR_01_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_PR7_SHIFT)
#define GPIO_K_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_K_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_K_SCR_01_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_01_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_01_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_K_SCR_01_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_PR6_SHIFT)
#define GPIO_K_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_K_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_K_SCR_01_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_01_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_01_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_K_SCR_01_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_PR5_SHIFT)
#define GPIO_K_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_K_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_K_SCR_01_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_01_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_01_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_K_SCR_01_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_PR4_SHIFT)
#define GPIO_K_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_K_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_K_SCR_01_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_01_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_01_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_K_SCR_01_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_PR3_SHIFT)
#define GPIO_K_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_K_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_K_SCR_01_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_01_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_01_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_K_SCR_01_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_PR2_SHIFT)
#define GPIO_K_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_K_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_K_SCR_01_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_01_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_01_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_K_SCR_01_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_PR1_SHIFT)
#define GPIO_K_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_K_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_K_SCR_01_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_01_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_01_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_K_SCR_01_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_PR0_SHIFT)
#define GPIO_K_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_K_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_K_SCR_01_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_01_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_01_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_K_SCR_01_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_G7W_SHIFT)
#define GPIO_K_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_K_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_K_SCR_01_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_01_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_01_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_K_SCR_01_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_G6W_SHIFT)
#define GPIO_K_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_K_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_K_SCR_01_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_01_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_01_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_K_SCR_01_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_G5W_SHIFT)
#define GPIO_K_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_K_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_K_SCR_01_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_01_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_01_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_K_SCR_01_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_G4W_SHIFT)
#define GPIO_K_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_K_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_K_SCR_01_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_01_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_01_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_K_SCR_01_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_G3W_SHIFT)
#define GPIO_K_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_K_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_K_SCR_01_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_01_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_01_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_K_SCR_01_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_G2W_SHIFT)
#define GPIO_K_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_K_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_K_SCR_01_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_01_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_01_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_K_SCR_01_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_G1W_SHIFT)
#define GPIO_K_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_K_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_K_SCR_01_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_01_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_01_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_K_SCR_01_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_G0W_SHIFT)
#define GPIO_K_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_K_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_K_SCR_01_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_01_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_01_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_K_SCR_01_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_G7R_SHIFT)
#define GPIO_K_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_K_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_K_SCR_01_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_01_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_01_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_K_SCR_01_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_G6R_SHIFT)
#define GPIO_K_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_K_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_K_SCR_01_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_01_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_01_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_K_SCR_01_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_G5R_SHIFT)
#define GPIO_K_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_K_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_K_SCR_01_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_01_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_01_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_K_SCR_01_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_G4R_SHIFT)
#define GPIO_K_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_K_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_K_SCR_01_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_01_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_01_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_K_SCR_01_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_G3R_SHIFT)
#define GPIO_K_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_K_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_K_SCR_01_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_01_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_01_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_K_SCR_01_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_G2R_SHIFT)
#define GPIO_K_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_K_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_K_SCR_01_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_01_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_01_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_K_SCR_01_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_G1R_SHIFT)
#define GPIO_K_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_K_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_K_SCR_01_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_01_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_01_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_K_SCR_01_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_G0R_SHIFT)
#define GPIO_K_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_K_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_K_SCR_01_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_01_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_K_VM_02_0
#define GPIO_K_VM_02_0                  _MK_ADDR_CONST(0x3010)
#define GPIO_K_VM_02_0_SECURE                   0x0
#define GPIO_K_VM_02_0_DUAL                     0x0
#define GPIO_K_VM_02_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_K_VM_02_0_WORD_COUNT                       0x1
#define GPIO_K_VM_02_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_K_VM_02_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_K_VM_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_K_VM_02_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_K_VM_02_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_K_VM_02_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_K_VM_02_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_02_0_VM1_SHIFT)
#define GPIO_K_VM_02_0_VM1_RANGE                        1:0
#define GPIO_K_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_K_VM_02_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_02_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_02_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_02_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_02_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_02_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_02_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_K_VM_02_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_02_0_VM2_SHIFT)
#define GPIO_K_VM_02_0_VM2_RANGE                        3:2
#define GPIO_K_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_K_VM_02_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_02_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_02_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_02_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_02_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_02_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_02_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_K_VM_02_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_02_0_VM3_SHIFT)
#define GPIO_K_VM_02_0_VM3_RANGE                        5:4
#define GPIO_K_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_K_VM_02_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_02_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_02_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_02_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_02_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_02_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_02_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_K_VM_02_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_02_0_VM4_SHIFT)
#define GPIO_K_VM_02_0_VM4_RANGE                        7:6
#define GPIO_K_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_K_VM_02_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_02_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_02_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_02_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_02_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_02_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_02_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_K_VM_02_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_02_0_VM5_SHIFT)
#define GPIO_K_VM_02_0_VM5_RANGE                        9:8
#define GPIO_K_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_K_VM_02_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_02_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_02_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_02_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_02_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_02_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_02_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_K_VM_02_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_02_0_VM6_SHIFT)
#define GPIO_K_VM_02_0_VM6_RANGE                        11:10
#define GPIO_K_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_K_VM_02_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_02_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_02_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_02_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_02_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_02_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_02_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_K_VM_02_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_02_0_VM7_SHIFT)
#define GPIO_K_VM_02_0_VM7_RANGE                        13:12
#define GPIO_K_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_K_VM_02_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_02_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_02_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_02_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_02_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_02_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_02_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_K_VM_02_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_02_0_VM8_SHIFT)
#define GPIO_K_VM_02_0_VM8_RANGE                        15:14
#define GPIO_K_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_K_VM_02_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_02_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_02_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_02_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_02_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_02_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_K_SCR_02_0
#define GPIO_K_SCR_02_0                 _MK_ADDR_CONST(0x3014)
#define GPIO_K_SCR_02_0_SECURE                  0x0
#define GPIO_K_SCR_02_0_DUAL                    0x0
#define GPIO_K_SCR_02_0_SCR                     0
#define GPIO_K_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_K_SCR_02_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_K_SCR_02_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_K_SCR_02_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_K_SCR_02_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_K_SCR_02_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_K_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_K_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_K_SCR_02_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_02_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_02_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_K_SCR_02_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_K_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_K_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_K_SCR_02_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_02_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_02_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_K_SCR_02_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_K_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_K_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_K_SCR_02_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_02_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_02_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_K_SCR_02_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_K_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_K_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_K_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_K_SCR_02_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_K_SCR_02_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_02_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_K_SCR_02_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_PR7_SHIFT)
#define GPIO_K_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_K_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_K_SCR_02_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_02_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_02_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_K_SCR_02_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_PR6_SHIFT)
#define GPIO_K_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_K_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_K_SCR_02_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_02_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_02_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_K_SCR_02_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_PR5_SHIFT)
#define GPIO_K_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_K_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_K_SCR_02_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_02_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_02_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_K_SCR_02_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_PR4_SHIFT)
#define GPIO_K_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_K_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_K_SCR_02_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_02_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_02_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_K_SCR_02_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_PR3_SHIFT)
#define GPIO_K_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_K_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_K_SCR_02_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_02_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_02_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_K_SCR_02_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_PR2_SHIFT)
#define GPIO_K_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_K_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_K_SCR_02_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_02_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_02_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_K_SCR_02_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_PR1_SHIFT)
#define GPIO_K_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_K_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_K_SCR_02_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_02_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_02_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_K_SCR_02_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_PR0_SHIFT)
#define GPIO_K_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_K_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_K_SCR_02_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_02_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_02_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_K_SCR_02_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_G7W_SHIFT)
#define GPIO_K_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_K_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_K_SCR_02_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_02_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_02_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_K_SCR_02_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_G6W_SHIFT)
#define GPIO_K_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_K_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_K_SCR_02_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_02_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_02_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_K_SCR_02_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_G5W_SHIFT)
#define GPIO_K_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_K_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_K_SCR_02_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_02_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_02_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_K_SCR_02_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_G4W_SHIFT)
#define GPIO_K_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_K_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_K_SCR_02_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_02_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_02_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_K_SCR_02_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_G3W_SHIFT)
#define GPIO_K_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_K_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_K_SCR_02_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_02_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_02_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_K_SCR_02_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_G2W_SHIFT)
#define GPIO_K_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_K_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_K_SCR_02_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_02_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_02_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_K_SCR_02_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_G1W_SHIFT)
#define GPIO_K_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_K_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_K_SCR_02_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_02_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_02_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_K_SCR_02_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_G0W_SHIFT)
#define GPIO_K_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_K_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_K_SCR_02_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_02_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_02_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_K_SCR_02_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_G7R_SHIFT)
#define GPIO_K_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_K_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_K_SCR_02_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_02_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_02_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_K_SCR_02_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_G6R_SHIFT)
#define GPIO_K_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_K_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_K_SCR_02_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_02_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_02_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_K_SCR_02_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_G5R_SHIFT)
#define GPIO_K_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_K_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_K_SCR_02_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_02_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_02_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_K_SCR_02_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_G4R_SHIFT)
#define GPIO_K_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_K_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_K_SCR_02_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_02_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_02_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_K_SCR_02_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_G3R_SHIFT)
#define GPIO_K_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_K_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_K_SCR_02_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_02_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_02_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_K_SCR_02_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_G2R_SHIFT)
#define GPIO_K_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_K_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_K_SCR_02_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_02_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_02_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_K_SCR_02_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_G1R_SHIFT)
#define GPIO_K_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_K_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_K_SCR_02_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_02_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_02_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_K_SCR_02_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_G0R_SHIFT)
#define GPIO_K_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_K_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_K_SCR_02_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_02_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_K_VM_03_0
#define GPIO_K_VM_03_0                  _MK_ADDR_CONST(0x3018)
#define GPIO_K_VM_03_0_SECURE                   0x0
#define GPIO_K_VM_03_0_DUAL                     0x0
#define GPIO_K_VM_03_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_K_VM_03_0_WORD_COUNT                       0x1
#define GPIO_K_VM_03_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_K_VM_03_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_K_VM_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_K_VM_03_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_K_VM_03_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_K_VM_03_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_K_VM_03_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_03_0_VM1_SHIFT)
#define GPIO_K_VM_03_0_VM1_RANGE                        1:0
#define GPIO_K_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_K_VM_03_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_03_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_03_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_03_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_03_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_03_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_03_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_K_VM_03_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_03_0_VM2_SHIFT)
#define GPIO_K_VM_03_0_VM2_RANGE                        3:2
#define GPIO_K_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_K_VM_03_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_03_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_03_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_03_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_03_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_03_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_03_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_K_VM_03_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_03_0_VM3_SHIFT)
#define GPIO_K_VM_03_0_VM3_RANGE                        5:4
#define GPIO_K_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_K_VM_03_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_03_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_03_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_03_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_03_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_03_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_03_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_K_VM_03_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_03_0_VM4_SHIFT)
#define GPIO_K_VM_03_0_VM4_RANGE                        7:6
#define GPIO_K_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_K_VM_03_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_03_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_03_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_03_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_03_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_03_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_03_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_K_VM_03_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_03_0_VM5_SHIFT)
#define GPIO_K_VM_03_0_VM5_RANGE                        9:8
#define GPIO_K_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_K_VM_03_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_03_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_03_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_03_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_03_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_03_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_03_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_K_VM_03_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_03_0_VM6_SHIFT)
#define GPIO_K_VM_03_0_VM6_RANGE                        11:10
#define GPIO_K_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_K_VM_03_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_03_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_03_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_03_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_03_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_03_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_03_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_K_VM_03_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_03_0_VM7_SHIFT)
#define GPIO_K_VM_03_0_VM7_RANGE                        13:12
#define GPIO_K_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_K_VM_03_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_03_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_03_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_03_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_03_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_03_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_03_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_K_VM_03_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_03_0_VM8_SHIFT)
#define GPIO_K_VM_03_0_VM8_RANGE                        15:14
#define GPIO_K_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_K_VM_03_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_03_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_03_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_03_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_03_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_03_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_K_SCR_03_0
#define GPIO_K_SCR_03_0                 _MK_ADDR_CONST(0x301c)
#define GPIO_K_SCR_03_0_SECURE                  0x0
#define GPIO_K_SCR_03_0_DUAL                    0x0
#define GPIO_K_SCR_03_0_SCR                     0
#define GPIO_K_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_K_SCR_03_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_K_SCR_03_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_K_SCR_03_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_K_SCR_03_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_K_SCR_03_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_K_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_K_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_K_SCR_03_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_03_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_03_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_K_SCR_03_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_K_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_K_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_K_SCR_03_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_03_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_03_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_K_SCR_03_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_K_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_K_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_K_SCR_03_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_03_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_03_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_K_SCR_03_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_K_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_K_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_K_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_K_SCR_03_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_K_SCR_03_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_03_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_K_SCR_03_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_PR7_SHIFT)
#define GPIO_K_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_K_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_K_SCR_03_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_03_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_03_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_K_SCR_03_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_PR6_SHIFT)
#define GPIO_K_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_K_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_K_SCR_03_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_03_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_03_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_K_SCR_03_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_PR5_SHIFT)
#define GPIO_K_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_K_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_K_SCR_03_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_03_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_03_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_K_SCR_03_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_PR4_SHIFT)
#define GPIO_K_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_K_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_K_SCR_03_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_03_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_03_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_K_SCR_03_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_PR3_SHIFT)
#define GPIO_K_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_K_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_K_SCR_03_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_03_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_03_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_K_SCR_03_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_PR2_SHIFT)
#define GPIO_K_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_K_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_K_SCR_03_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_03_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_03_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_K_SCR_03_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_PR1_SHIFT)
#define GPIO_K_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_K_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_K_SCR_03_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_03_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_03_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_K_SCR_03_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_PR0_SHIFT)
#define GPIO_K_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_K_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_K_SCR_03_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_03_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_03_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_K_SCR_03_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_G7W_SHIFT)
#define GPIO_K_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_K_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_K_SCR_03_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_03_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_03_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_K_SCR_03_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_G6W_SHIFT)
#define GPIO_K_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_K_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_K_SCR_03_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_03_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_03_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_K_SCR_03_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_G5W_SHIFT)
#define GPIO_K_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_K_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_K_SCR_03_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_03_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_03_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_K_SCR_03_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_G4W_SHIFT)
#define GPIO_K_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_K_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_K_SCR_03_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_03_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_03_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_K_SCR_03_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_G3W_SHIFT)
#define GPIO_K_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_K_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_K_SCR_03_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_03_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_03_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_K_SCR_03_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_G2W_SHIFT)
#define GPIO_K_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_K_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_K_SCR_03_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_03_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_03_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_K_SCR_03_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_G1W_SHIFT)
#define GPIO_K_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_K_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_K_SCR_03_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_03_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_03_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_K_SCR_03_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_G0W_SHIFT)
#define GPIO_K_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_K_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_K_SCR_03_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_03_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_03_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_K_SCR_03_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_G7R_SHIFT)
#define GPIO_K_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_K_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_K_SCR_03_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_03_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_03_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_K_SCR_03_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_G6R_SHIFT)
#define GPIO_K_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_K_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_K_SCR_03_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_03_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_03_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_K_SCR_03_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_G5R_SHIFT)
#define GPIO_K_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_K_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_K_SCR_03_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_03_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_03_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_K_SCR_03_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_G4R_SHIFT)
#define GPIO_K_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_K_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_K_SCR_03_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_03_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_03_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_K_SCR_03_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_G3R_SHIFT)
#define GPIO_K_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_K_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_K_SCR_03_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_03_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_03_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_K_SCR_03_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_G2R_SHIFT)
#define GPIO_K_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_K_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_K_SCR_03_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_03_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_03_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_K_SCR_03_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_G1R_SHIFT)
#define GPIO_K_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_K_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_K_SCR_03_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_03_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_03_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_K_SCR_03_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_G0R_SHIFT)
#define GPIO_K_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_K_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_K_SCR_03_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_03_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_K_VM_04_0
#define GPIO_K_VM_04_0                  _MK_ADDR_CONST(0x3020)
#define GPIO_K_VM_04_0_SECURE                   0x0
#define GPIO_K_VM_04_0_DUAL                     0x0
#define GPIO_K_VM_04_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_K_VM_04_0_WORD_COUNT                       0x1
#define GPIO_K_VM_04_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_K_VM_04_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_K_VM_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_K_VM_04_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_K_VM_04_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_K_VM_04_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_K_VM_04_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_04_0_VM1_SHIFT)
#define GPIO_K_VM_04_0_VM1_RANGE                        1:0
#define GPIO_K_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_K_VM_04_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_04_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_04_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_04_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_04_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_04_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_04_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_K_VM_04_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_04_0_VM2_SHIFT)
#define GPIO_K_VM_04_0_VM2_RANGE                        3:2
#define GPIO_K_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_K_VM_04_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_04_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_04_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_04_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_04_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_04_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_04_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_K_VM_04_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_04_0_VM3_SHIFT)
#define GPIO_K_VM_04_0_VM3_RANGE                        5:4
#define GPIO_K_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_K_VM_04_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_04_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_04_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_04_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_04_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_04_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_04_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_K_VM_04_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_04_0_VM4_SHIFT)
#define GPIO_K_VM_04_0_VM4_RANGE                        7:6
#define GPIO_K_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_K_VM_04_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_04_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_04_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_04_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_04_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_04_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_04_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_K_VM_04_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_04_0_VM5_SHIFT)
#define GPIO_K_VM_04_0_VM5_RANGE                        9:8
#define GPIO_K_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_K_VM_04_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_04_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_04_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_04_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_04_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_04_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_04_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_K_VM_04_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_04_0_VM6_SHIFT)
#define GPIO_K_VM_04_0_VM6_RANGE                        11:10
#define GPIO_K_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_K_VM_04_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_04_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_04_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_04_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_04_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_04_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_04_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_K_VM_04_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_04_0_VM7_SHIFT)
#define GPIO_K_VM_04_0_VM7_RANGE                        13:12
#define GPIO_K_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_K_VM_04_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_04_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_04_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_04_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_04_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_04_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_04_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_K_VM_04_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_04_0_VM8_SHIFT)
#define GPIO_K_VM_04_0_VM8_RANGE                        15:14
#define GPIO_K_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_K_VM_04_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_04_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_04_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_04_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_04_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_04_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_K_SCR_04_0
#define GPIO_K_SCR_04_0                 _MK_ADDR_CONST(0x3024)
#define GPIO_K_SCR_04_0_SECURE                  0x0
#define GPIO_K_SCR_04_0_DUAL                    0x0
#define GPIO_K_SCR_04_0_SCR                     0
#define GPIO_K_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_K_SCR_04_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_K_SCR_04_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_K_SCR_04_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_K_SCR_04_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_K_SCR_04_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_K_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_K_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_K_SCR_04_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_04_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_04_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_K_SCR_04_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_K_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_K_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_K_SCR_04_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_04_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_04_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_K_SCR_04_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_K_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_K_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_K_SCR_04_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_04_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_04_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_K_SCR_04_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_K_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_K_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_K_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_K_SCR_04_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_K_SCR_04_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_04_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_K_SCR_04_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_PR7_SHIFT)
#define GPIO_K_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_K_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_K_SCR_04_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_04_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_04_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_K_SCR_04_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_PR6_SHIFT)
#define GPIO_K_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_K_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_K_SCR_04_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_04_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_04_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_K_SCR_04_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_PR5_SHIFT)
#define GPIO_K_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_K_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_K_SCR_04_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_04_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_04_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_K_SCR_04_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_PR4_SHIFT)
#define GPIO_K_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_K_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_K_SCR_04_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_04_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_04_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_K_SCR_04_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_PR3_SHIFT)
#define GPIO_K_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_K_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_K_SCR_04_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_04_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_04_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_K_SCR_04_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_PR2_SHIFT)
#define GPIO_K_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_K_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_K_SCR_04_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_04_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_04_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_K_SCR_04_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_PR1_SHIFT)
#define GPIO_K_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_K_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_K_SCR_04_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_04_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_04_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_K_SCR_04_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_PR0_SHIFT)
#define GPIO_K_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_K_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_K_SCR_04_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_04_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_04_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_K_SCR_04_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_G7W_SHIFT)
#define GPIO_K_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_K_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_K_SCR_04_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_04_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_04_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_K_SCR_04_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_G6W_SHIFT)
#define GPIO_K_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_K_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_K_SCR_04_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_04_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_04_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_K_SCR_04_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_G5W_SHIFT)
#define GPIO_K_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_K_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_K_SCR_04_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_04_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_04_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_K_SCR_04_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_G4W_SHIFT)
#define GPIO_K_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_K_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_K_SCR_04_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_04_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_04_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_K_SCR_04_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_G3W_SHIFT)
#define GPIO_K_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_K_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_K_SCR_04_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_04_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_04_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_K_SCR_04_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_G2W_SHIFT)
#define GPIO_K_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_K_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_K_SCR_04_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_04_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_04_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_K_SCR_04_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_G1W_SHIFT)
#define GPIO_K_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_K_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_K_SCR_04_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_04_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_04_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_K_SCR_04_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_G0W_SHIFT)
#define GPIO_K_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_K_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_K_SCR_04_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_04_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_04_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_K_SCR_04_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_G7R_SHIFT)
#define GPIO_K_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_K_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_K_SCR_04_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_04_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_04_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_K_SCR_04_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_G6R_SHIFT)
#define GPIO_K_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_K_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_K_SCR_04_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_04_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_04_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_K_SCR_04_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_G5R_SHIFT)
#define GPIO_K_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_K_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_K_SCR_04_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_04_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_04_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_K_SCR_04_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_G4R_SHIFT)
#define GPIO_K_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_K_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_K_SCR_04_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_04_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_04_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_K_SCR_04_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_G3R_SHIFT)
#define GPIO_K_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_K_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_K_SCR_04_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_04_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_04_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_K_SCR_04_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_G2R_SHIFT)
#define GPIO_K_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_K_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_K_SCR_04_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_04_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_04_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_K_SCR_04_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_G1R_SHIFT)
#define GPIO_K_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_K_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_K_SCR_04_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_04_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_04_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_K_SCR_04_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_G0R_SHIFT)
#define GPIO_K_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_K_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_K_SCR_04_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_04_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_K_VM_05_0
#define GPIO_K_VM_05_0                  _MK_ADDR_CONST(0x3028)
#define GPIO_K_VM_05_0_SECURE                   0x0
#define GPIO_K_VM_05_0_DUAL                     0x0
#define GPIO_K_VM_05_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_K_VM_05_0_WORD_COUNT                       0x1
#define GPIO_K_VM_05_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_K_VM_05_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_K_VM_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_K_VM_05_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_K_VM_05_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_K_VM_05_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_K_VM_05_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_05_0_VM1_SHIFT)
#define GPIO_K_VM_05_0_VM1_RANGE                        1:0
#define GPIO_K_VM_05_0_VM1_WOFFSET                      0x0
#define GPIO_K_VM_05_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_05_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_05_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_05_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_05_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_05_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_05_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_K_VM_05_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_05_0_VM2_SHIFT)
#define GPIO_K_VM_05_0_VM2_RANGE                        3:2
#define GPIO_K_VM_05_0_VM2_WOFFSET                      0x0
#define GPIO_K_VM_05_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_05_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_05_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_05_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_05_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_05_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_05_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_K_VM_05_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_05_0_VM3_SHIFT)
#define GPIO_K_VM_05_0_VM3_RANGE                        5:4
#define GPIO_K_VM_05_0_VM3_WOFFSET                      0x0
#define GPIO_K_VM_05_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_05_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_05_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_05_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_05_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_05_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_05_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_K_VM_05_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_05_0_VM4_SHIFT)
#define GPIO_K_VM_05_0_VM4_RANGE                        7:6
#define GPIO_K_VM_05_0_VM4_WOFFSET                      0x0
#define GPIO_K_VM_05_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_05_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_05_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_05_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_05_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_05_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_05_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_K_VM_05_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_05_0_VM5_SHIFT)
#define GPIO_K_VM_05_0_VM5_RANGE                        9:8
#define GPIO_K_VM_05_0_VM5_WOFFSET                      0x0
#define GPIO_K_VM_05_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_05_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_05_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_05_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_05_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_05_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_05_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_K_VM_05_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_05_0_VM6_SHIFT)
#define GPIO_K_VM_05_0_VM6_RANGE                        11:10
#define GPIO_K_VM_05_0_VM6_WOFFSET                      0x0
#define GPIO_K_VM_05_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_05_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_05_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_05_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_05_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_05_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_05_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_K_VM_05_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_05_0_VM7_SHIFT)
#define GPIO_K_VM_05_0_VM7_RANGE                        13:12
#define GPIO_K_VM_05_0_VM7_WOFFSET                      0x0
#define GPIO_K_VM_05_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_05_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_05_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_05_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_05_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_05_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_05_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_K_VM_05_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_05_0_VM8_SHIFT)
#define GPIO_K_VM_05_0_VM8_RANGE                        15:14
#define GPIO_K_VM_05_0_VM8_WOFFSET                      0x0
#define GPIO_K_VM_05_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_05_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_05_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_05_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_05_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_05_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_K_SCR_05_0
#define GPIO_K_SCR_05_0                 _MK_ADDR_CONST(0x302c)
#define GPIO_K_SCR_05_0_SECURE                  0x0
#define GPIO_K_SCR_05_0_DUAL                    0x0
#define GPIO_K_SCR_05_0_SCR                     0
#define GPIO_K_SCR_05_0_WORD_COUNT                      0x1
#define GPIO_K_SCR_05_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_K_SCR_05_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_K_SCR_05_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_K_SCR_05_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_K_SCR_05_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_K_SCR_05_0_SEC_LCK_RANGE                   29:29
#define GPIO_K_SCR_05_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_K_SCR_05_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_05_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_05_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_K_SCR_05_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_K_SCR_05_0_SEC_WEN_RANGE                   28:28
#define GPIO_K_SCR_05_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_K_SCR_05_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_05_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_05_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_K_SCR_05_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_K_SCR_05_0_SEC_REN_RANGE                   27:27
#define GPIO_K_SCR_05_0_SEC_REN_WOFFSET                 0x0
#define GPIO_K_SCR_05_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_05_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_05_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_K_SCR_05_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_K_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_K_SCR_05_0_SEC_OWNER_RANGE                 26:24
#define GPIO_K_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_K_SCR_05_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_K_SCR_05_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_05_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_K_SCR_05_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_PR7_SHIFT)
#define GPIO_K_SCR_05_0_PR7_RANGE                       23:23
#define GPIO_K_SCR_05_0_PR7_WOFFSET                     0x0
#define GPIO_K_SCR_05_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_05_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_05_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_K_SCR_05_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_PR6_SHIFT)
#define GPIO_K_SCR_05_0_PR6_RANGE                       22:22
#define GPIO_K_SCR_05_0_PR6_WOFFSET                     0x0
#define GPIO_K_SCR_05_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_05_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_05_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_K_SCR_05_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_PR5_SHIFT)
#define GPIO_K_SCR_05_0_PR5_RANGE                       21:21
#define GPIO_K_SCR_05_0_PR5_WOFFSET                     0x0
#define GPIO_K_SCR_05_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_05_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_05_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_K_SCR_05_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_PR4_SHIFT)
#define GPIO_K_SCR_05_0_PR4_RANGE                       20:20
#define GPIO_K_SCR_05_0_PR4_WOFFSET                     0x0
#define GPIO_K_SCR_05_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_05_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_05_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_K_SCR_05_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_PR3_SHIFT)
#define GPIO_K_SCR_05_0_PR3_RANGE                       19:19
#define GPIO_K_SCR_05_0_PR3_WOFFSET                     0x0
#define GPIO_K_SCR_05_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_05_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_05_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_K_SCR_05_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_PR2_SHIFT)
#define GPIO_K_SCR_05_0_PR2_RANGE                       18:18
#define GPIO_K_SCR_05_0_PR2_WOFFSET                     0x0
#define GPIO_K_SCR_05_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_05_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_05_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_K_SCR_05_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_PR1_SHIFT)
#define GPIO_K_SCR_05_0_PR1_RANGE                       17:17
#define GPIO_K_SCR_05_0_PR1_WOFFSET                     0x0
#define GPIO_K_SCR_05_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_05_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_05_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_K_SCR_05_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_PR0_SHIFT)
#define GPIO_K_SCR_05_0_PR0_RANGE                       16:16
#define GPIO_K_SCR_05_0_PR0_WOFFSET                     0x0
#define GPIO_K_SCR_05_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_05_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_05_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_K_SCR_05_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_G7W_SHIFT)
#define GPIO_K_SCR_05_0_G7W_RANGE                       15:15
#define GPIO_K_SCR_05_0_G7W_WOFFSET                     0x0
#define GPIO_K_SCR_05_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_05_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_05_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_K_SCR_05_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_G6W_SHIFT)
#define GPIO_K_SCR_05_0_G6W_RANGE                       14:14
#define GPIO_K_SCR_05_0_G6W_WOFFSET                     0x0
#define GPIO_K_SCR_05_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_05_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_05_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_K_SCR_05_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_G5W_SHIFT)
#define GPIO_K_SCR_05_0_G5W_RANGE                       13:13
#define GPIO_K_SCR_05_0_G5W_WOFFSET                     0x0
#define GPIO_K_SCR_05_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_05_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_05_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_K_SCR_05_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_G4W_SHIFT)
#define GPIO_K_SCR_05_0_G4W_RANGE                       12:12
#define GPIO_K_SCR_05_0_G4W_WOFFSET                     0x0
#define GPIO_K_SCR_05_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_05_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_05_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_K_SCR_05_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_G3W_SHIFT)
#define GPIO_K_SCR_05_0_G3W_RANGE                       11:11
#define GPIO_K_SCR_05_0_G3W_WOFFSET                     0x0
#define GPIO_K_SCR_05_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_05_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_05_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_K_SCR_05_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_G2W_SHIFT)
#define GPIO_K_SCR_05_0_G2W_RANGE                       10:10
#define GPIO_K_SCR_05_0_G2W_WOFFSET                     0x0
#define GPIO_K_SCR_05_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_05_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_05_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_K_SCR_05_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_G1W_SHIFT)
#define GPIO_K_SCR_05_0_G1W_RANGE                       9:9
#define GPIO_K_SCR_05_0_G1W_WOFFSET                     0x0
#define GPIO_K_SCR_05_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_05_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_05_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_K_SCR_05_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_G0W_SHIFT)
#define GPIO_K_SCR_05_0_G0W_RANGE                       8:8
#define GPIO_K_SCR_05_0_G0W_WOFFSET                     0x0
#define GPIO_K_SCR_05_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_05_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_05_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_K_SCR_05_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_G7R_SHIFT)
#define GPIO_K_SCR_05_0_G7R_RANGE                       7:7
#define GPIO_K_SCR_05_0_G7R_WOFFSET                     0x0
#define GPIO_K_SCR_05_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_05_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_05_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_K_SCR_05_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_G6R_SHIFT)
#define GPIO_K_SCR_05_0_G6R_RANGE                       6:6
#define GPIO_K_SCR_05_0_G6R_WOFFSET                     0x0
#define GPIO_K_SCR_05_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_05_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_05_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_K_SCR_05_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_G5R_SHIFT)
#define GPIO_K_SCR_05_0_G5R_RANGE                       5:5
#define GPIO_K_SCR_05_0_G5R_WOFFSET                     0x0
#define GPIO_K_SCR_05_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_05_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_05_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_K_SCR_05_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_G4R_SHIFT)
#define GPIO_K_SCR_05_0_G4R_RANGE                       4:4
#define GPIO_K_SCR_05_0_G4R_WOFFSET                     0x0
#define GPIO_K_SCR_05_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_05_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_05_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_K_SCR_05_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_G3R_SHIFT)
#define GPIO_K_SCR_05_0_G3R_RANGE                       3:3
#define GPIO_K_SCR_05_0_G3R_WOFFSET                     0x0
#define GPIO_K_SCR_05_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_05_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_05_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_K_SCR_05_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_G2R_SHIFT)
#define GPIO_K_SCR_05_0_G2R_RANGE                       2:2
#define GPIO_K_SCR_05_0_G2R_WOFFSET                     0x0
#define GPIO_K_SCR_05_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_05_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_05_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_K_SCR_05_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_G1R_SHIFT)
#define GPIO_K_SCR_05_0_G1R_RANGE                       1:1
#define GPIO_K_SCR_05_0_G1R_WOFFSET                     0x0
#define GPIO_K_SCR_05_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_05_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_05_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_K_SCR_05_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_G0R_SHIFT)
#define GPIO_K_SCR_05_0_G0R_RANGE                       0:0
#define GPIO_K_SCR_05_0_G0R_WOFFSET                     0x0
#define GPIO_K_SCR_05_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_05_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_K_VM_06_0
#define GPIO_K_VM_06_0                  _MK_ADDR_CONST(0x3030)
#define GPIO_K_VM_06_0_SECURE                   0x0
#define GPIO_K_VM_06_0_DUAL                     0x0
#define GPIO_K_VM_06_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_K_VM_06_0_WORD_COUNT                       0x1
#define GPIO_K_VM_06_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_K_VM_06_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_K_VM_06_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_06_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_K_VM_06_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_K_VM_06_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_K_VM_06_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_K_VM_06_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_06_0_VM1_SHIFT)
#define GPIO_K_VM_06_0_VM1_RANGE                        1:0
#define GPIO_K_VM_06_0_VM1_WOFFSET                      0x0
#define GPIO_K_VM_06_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_06_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_06_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_06_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_06_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_06_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_06_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_K_VM_06_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_06_0_VM2_SHIFT)
#define GPIO_K_VM_06_0_VM2_RANGE                        3:2
#define GPIO_K_VM_06_0_VM2_WOFFSET                      0x0
#define GPIO_K_VM_06_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_06_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_06_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_06_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_06_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_06_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_06_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_K_VM_06_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_06_0_VM3_SHIFT)
#define GPIO_K_VM_06_0_VM3_RANGE                        5:4
#define GPIO_K_VM_06_0_VM3_WOFFSET                      0x0
#define GPIO_K_VM_06_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_06_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_06_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_06_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_06_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_06_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_06_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_K_VM_06_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_06_0_VM4_SHIFT)
#define GPIO_K_VM_06_0_VM4_RANGE                        7:6
#define GPIO_K_VM_06_0_VM4_WOFFSET                      0x0
#define GPIO_K_VM_06_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_06_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_06_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_06_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_06_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_06_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_06_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_K_VM_06_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_06_0_VM5_SHIFT)
#define GPIO_K_VM_06_0_VM5_RANGE                        9:8
#define GPIO_K_VM_06_0_VM5_WOFFSET                      0x0
#define GPIO_K_VM_06_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_06_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_06_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_06_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_06_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_06_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_06_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_K_VM_06_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_06_0_VM6_SHIFT)
#define GPIO_K_VM_06_0_VM6_RANGE                        11:10
#define GPIO_K_VM_06_0_VM6_WOFFSET                      0x0
#define GPIO_K_VM_06_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_06_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_06_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_06_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_06_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_06_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_06_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_K_VM_06_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_06_0_VM7_SHIFT)
#define GPIO_K_VM_06_0_VM7_RANGE                        13:12
#define GPIO_K_VM_06_0_VM7_WOFFSET                      0x0
#define GPIO_K_VM_06_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_06_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_06_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_06_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_06_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_06_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_06_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_K_VM_06_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_06_0_VM8_SHIFT)
#define GPIO_K_VM_06_0_VM8_RANGE                        15:14
#define GPIO_K_VM_06_0_VM8_WOFFSET                      0x0
#define GPIO_K_VM_06_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_06_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_06_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_06_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_06_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_06_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_K_SCR_06_0
#define GPIO_K_SCR_06_0                 _MK_ADDR_CONST(0x3034)
#define GPIO_K_SCR_06_0_SECURE                  0x0
#define GPIO_K_SCR_06_0_DUAL                    0x0
#define GPIO_K_SCR_06_0_SCR                     0
#define GPIO_K_SCR_06_0_WORD_COUNT                      0x1
#define GPIO_K_SCR_06_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_K_SCR_06_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_K_SCR_06_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_K_SCR_06_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_K_SCR_06_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_SEC_LCK_SHIFT)
#define GPIO_K_SCR_06_0_SEC_LCK_RANGE                   29:29
#define GPIO_K_SCR_06_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_K_SCR_06_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_06_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_06_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_K_SCR_06_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_SEC_WEN_SHIFT)
#define GPIO_K_SCR_06_0_SEC_WEN_RANGE                   28:28
#define GPIO_K_SCR_06_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_K_SCR_06_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_06_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_06_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_K_SCR_06_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_SEC_REN_SHIFT)
#define GPIO_K_SCR_06_0_SEC_REN_RANGE                   27:27
#define GPIO_K_SCR_06_0_SEC_REN_WOFFSET                 0x0
#define GPIO_K_SCR_06_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_06_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_06_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_K_SCR_06_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_K_SCR_06_0_SEC_OWNER_SHIFT)
#define GPIO_K_SCR_06_0_SEC_OWNER_RANGE                 26:24
#define GPIO_K_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_K_SCR_06_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_K_SCR_06_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_06_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_K_SCR_06_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_PR7_SHIFT)
#define GPIO_K_SCR_06_0_PR7_RANGE                       23:23
#define GPIO_K_SCR_06_0_PR7_WOFFSET                     0x0
#define GPIO_K_SCR_06_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_06_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_06_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_K_SCR_06_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_PR6_SHIFT)
#define GPIO_K_SCR_06_0_PR6_RANGE                       22:22
#define GPIO_K_SCR_06_0_PR6_WOFFSET                     0x0
#define GPIO_K_SCR_06_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_06_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_06_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_K_SCR_06_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_PR5_SHIFT)
#define GPIO_K_SCR_06_0_PR5_RANGE                       21:21
#define GPIO_K_SCR_06_0_PR5_WOFFSET                     0x0
#define GPIO_K_SCR_06_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_06_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_06_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_K_SCR_06_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_PR4_SHIFT)
#define GPIO_K_SCR_06_0_PR4_RANGE                       20:20
#define GPIO_K_SCR_06_0_PR4_WOFFSET                     0x0
#define GPIO_K_SCR_06_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_06_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_06_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_K_SCR_06_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_PR3_SHIFT)
#define GPIO_K_SCR_06_0_PR3_RANGE                       19:19
#define GPIO_K_SCR_06_0_PR3_WOFFSET                     0x0
#define GPIO_K_SCR_06_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_06_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_06_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_K_SCR_06_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_PR2_SHIFT)
#define GPIO_K_SCR_06_0_PR2_RANGE                       18:18
#define GPIO_K_SCR_06_0_PR2_WOFFSET                     0x0
#define GPIO_K_SCR_06_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_06_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_06_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_K_SCR_06_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_PR1_SHIFT)
#define GPIO_K_SCR_06_0_PR1_RANGE                       17:17
#define GPIO_K_SCR_06_0_PR1_WOFFSET                     0x0
#define GPIO_K_SCR_06_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_06_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_06_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_K_SCR_06_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_PR0_SHIFT)
#define GPIO_K_SCR_06_0_PR0_RANGE                       16:16
#define GPIO_K_SCR_06_0_PR0_WOFFSET                     0x0
#define GPIO_K_SCR_06_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_06_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_06_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_K_SCR_06_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_G7W_SHIFT)
#define GPIO_K_SCR_06_0_G7W_RANGE                       15:15
#define GPIO_K_SCR_06_0_G7W_WOFFSET                     0x0
#define GPIO_K_SCR_06_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_06_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_06_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_K_SCR_06_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_G6W_SHIFT)
#define GPIO_K_SCR_06_0_G6W_RANGE                       14:14
#define GPIO_K_SCR_06_0_G6W_WOFFSET                     0x0
#define GPIO_K_SCR_06_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_06_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_06_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_K_SCR_06_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_G5W_SHIFT)
#define GPIO_K_SCR_06_0_G5W_RANGE                       13:13
#define GPIO_K_SCR_06_0_G5W_WOFFSET                     0x0
#define GPIO_K_SCR_06_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_06_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_06_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_K_SCR_06_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_G4W_SHIFT)
#define GPIO_K_SCR_06_0_G4W_RANGE                       12:12
#define GPIO_K_SCR_06_0_G4W_WOFFSET                     0x0
#define GPIO_K_SCR_06_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_06_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_06_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_K_SCR_06_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_G3W_SHIFT)
#define GPIO_K_SCR_06_0_G3W_RANGE                       11:11
#define GPIO_K_SCR_06_0_G3W_WOFFSET                     0x0
#define GPIO_K_SCR_06_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_06_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_06_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_K_SCR_06_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_G2W_SHIFT)
#define GPIO_K_SCR_06_0_G2W_RANGE                       10:10
#define GPIO_K_SCR_06_0_G2W_WOFFSET                     0x0
#define GPIO_K_SCR_06_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_06_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_06_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_K_SCR_06_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_G1W_SHIFT)
#define GPIO_K_SCR_06_0_G1W_RANGE                       9:9
#define GPIO_K_SCR_06_0_G1W_WOFFSET                     0x0
#define GPIO_K_SCR_06_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_06_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_06_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_K_SCR_06_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_G0W_SHIFT)
#define GPIO_K_SCR_06_0_G0W_RANGE                       8:8
#define GPIO_K_SCR_06_0_G0W_WOFFSET                     0x0
#define GPIO_K_SCR_06_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_06_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_06_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_K_SCR_06_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_G7R_SHIFT)
#define GPIO_K_SCR_06_0_G7R_RANGE                       7:7
#define GPIO_K_SCR_06_0_G7R_WOFFSET                     0x0
#define GPIO_K_SCR_06_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_06_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_06_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_K_SCR_06_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_G6R_SHIFT)
#define GPIO_K_SCR_06_0_G6R_RANGE                       6:6
#define GPIO_K_SCR_06_0_G6R_WOFFSET                     0x0
#define GPIO_K_SCR_06_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_06_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_06_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_K_SCR_06_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_G5R_SHIFT)
#define GPIO_K_SCR_06_0_G5R_RANGE                       5:5
#define GPIO_K_SCR_06_0_G5R_WOFFSET                     0x0
#define GPIO_K_SCR_06_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_06_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_06_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_K_SCR_06_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_G4R_SHIFT)
#define GPIO_K_SCR_06_0_G4R_RANGE                       4:4
#define GPIO_K_SCR_06_0_G4R_WOFFSET                     0x0
#define GPIO_K_SCR_06_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_06_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_06_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_K_SCR_06_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_G3R_SHIFT)
#define GPIO_K_SCR_06_0_G3R_RANGE                       3:3
#define GPIO_K_SCR_06_0_G3R_WOFFSET                     0x0
#define GPIO_K_SCR_06_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_06_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_06_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_K_SCR_06_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_G2R_SHIFT)
#define GPIO_K_SCR_06_0_G2R_RANGE                       2:2
#define GPIO_K_SCR_06_0_G2R_WOFFSET                     0x0
#define GPIO_K_SCR_06_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_06_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_06_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_K_SCR_06_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_G1R_SHIFT)
#define GPIO_K_SCR_06_0_G1R_RANGE                       1:1
#define GPIO_K_SCR_06_0_G1R_WOFFSET                     0x0
#define GPIO_K_SCR_06_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_06_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_06_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_K_SCR_06_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_G0R_SHIFT)
#define GPIO_K_SCR_06_0_G0R_RANGE                       0:0
#define GPIO_K_SCR_06_0_G0R_WOFFSET                     0x0
#define GPIO_K_SCR_06_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_06_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_K_VM_07_0
#define GPIO_K_VM_07_0                  _MK_ADDR_CONST(0x3038)
#define GPIO_K_VM_07_0_SECURE                   0x0
#define GPIO_K_VM_07_0_DUAL                     0x0
#define GPIO_K_VM_07_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_K_VM_07_0_WORD_COUNT                       0x1
#define GPIO_K_VM_07_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_K_VM_07_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_K_VM_07_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_07_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_K_VM_07_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_K_VM_07_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_K_VM_07_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_K_VM_07_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_07_0_VM1_SHIFT)
#define GPIO_K_VM_07_0_VM1_RANGE                        1:0
#define GPIO_K_VM_07_0_VM1_WOFFSET                      0x0
#define GPIO_K_VM_07_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_07_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_07_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_07_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_07_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_07_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_07_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_K_VM_07_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_07_0_VM2_SHIFT)
#define GPIO_K_VM_07_0_VM2_RANGE                        3:2
#define GPIO_K_VM_07_0_VM2_WOFFSET                      0x0
#define GPIO_K_VM_07_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_07_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_07_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_07_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_07_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_07_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_07_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_K_VM_07_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_07_0_VM3_SHIFT)
#define GPIO_K_VM_07_0_VM3_RANGE                        5:4
#define GPIO_K_VM_07_0_VM3_WOFFSET                      0x0
#define GPIO_K_VM_07_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_07_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_07_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_07_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_07_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_07_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_07_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_K_VM_07_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_07_0_VM4_SHIFT)
#define GPIO_K_VM_07_0_VM4_RANGE                        7:6
#define GPIO_K_VM_07_0_VM4_WOFFSET                      0x0
#define GPIO_K_VM_07_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_07_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_07_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_07_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_07_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_07_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_07_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_K_VM_07_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_07_0_VM5_SHIFT)
#define GPIO_K_VM_07_0_VM5_RANGE                        9:8
#define GPIO_K_VM_07_0_VM5_WOFFSET                      0x0
#define GPIO_K_VM_07_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_07_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_07_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_07_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_07_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_07_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_07_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_K_VM_07_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_07_0_VM6_SHIFT)
#define GPIO_K_VM_07_0_VM6_RANGE                        11:10
#define GPIO_K_VM_07_0_VM6_WOFFSET                      0x0
#define GPIO_K_VM_07_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_07_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_07_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_07_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_07_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_07_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_07_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_K_VM_07_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_07_0_VM7_SHIFT)
#define GPIO_K_VM_07_0_VM7_RANGE                        13:12
#define GPIO_K_VM_07_0_VM7_WOFFSET                      0x0
#define GPIO_K_VM_07_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_07_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_07_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_07_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_07_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_07_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_K_VM_07_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_K_VM_07_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_K_VM_07_0_VM8_SHIFT)
#define GPIO_K_VM_07_0_VM8_RANGE                        15:14
#define GPIO_K_VM_07_0_VM8_WOFFSET                      0x0
#define GPIO_K_VM_07_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_K_VM_07_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_K_VM_07_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_VM_07_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_VM_07_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_VM_07_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_K_SCR_07_0
#define GPIO_K_SCR_07_0                 _MK_ADDR_CONST(0x303c)
#define GPIO_K_SCR_07_0_SECURE                  0x0
#define GPIO_K_SCR_07_0_DUAL                    0x0
#define GPIO_K_SCR_07_0_SCR                     0
#define GPIO_K_SCR_07_0_WORD_COUNT                      0x1
#define GPIO_K_SCR_07_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_K_SCR_07_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_K_SCR_07_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_K_SCR_07_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_K_SCR_07_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_SEC_LCK_SHIFT)
#define GPIO_K_SCR_07_0_SEC_LCK_RANGE                   29:29
#define GPIO_K_SCR_07_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_K_SCR_07_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_07_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_07_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_K_SCR_07_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_SEC_WEN_SHIFT)
#define GPIO_K_SCR_07_0_SEC_WEN_RANGE                   28:28
#define GPIO_K_SCR_07_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_K_SCR_07_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_07_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_07_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_K_SCR_07_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_SEC_REN_SHIFT)
#define GPIO_K_SCR_07_0_SEC_REN_RANGE                   27:27
#define GPIO_K_SCR_07_0_SEC_REN_WOFFSET                 0x0
#define GPIO_K_SCR_07_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_07_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_07_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_K_SCR_07_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_K_SCR_07_0_SEC_OWNER_SHIFT)
#define GPIO_K_SCR_07_0_SEC_OWNER_RANGE                 26:24
#define GPIO_K_SCR_07_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_K_SCR_07_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_K_SCR_07_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_07_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_K_SCR_07_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_PR7_SHIFT)
#define GPIO_K_SCR_07_0_PR7_RANGE                       23:23
#define GPIO_K_SCR_07_0_PR7_WOFFSET                     0x0
#define GPIO_K_SCR_07_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_07_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_07_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_K_SCR_07_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_PR6_SHIFT)
#define GPIO_K_SCR_07_0_PR6_RANGE                       22:22
#define GPIO_K_SCR_07_0_PR6_WOFFSET                     0x0
#define GPIO_K_SCR_07_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_07_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_07_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_K_SCR_07_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_PR5_SHIFT)
#define GPIO_K_SCR_07_0_PR5_RANGE                       21:21
#define GPIO_K_SCR_07_0_PR5_WOFFSET                     0x0
#define GPIO_K_SCR_07_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_07_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_07_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_K_SCR_07_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_PR4_SHIFT)
#define GPIO_K_SCR_07_0_PR4_RANGE                       20:20
#define GPIO_K_SCR_07_0_PR4_WOFFSET                     0x0
#define GPIO_K_SCR_07_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_07_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_07_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_K_SCR_07_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_PR3_SHIFT)
#define GPIO_K_SCR_07_0_PR3_RANGE                       19:19
#define GPIO_K_SCR_07_0_PR3_WOFFSET                     0x0
#define GPIO_K_SCR_07_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_07_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_07_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_K_SCR_07_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_PR2_SHIFT)
#define GPIO_K_SCR_07_0_PR2_RANGE                       18:18
#define GPIO_K_SCR_07_0_PR2_WOFFSET                     0x0
#define GPIO_K_SCR_07_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_07_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_07_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_K_SCR_07_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_PR1_SHIFT)
#define GPIO_K_SCR_07_0_PR1_RANGE                       17:17
#define GPIO_K_SCR_07_0_PR1_WOFFSET                     0x0
#define GPIO_K_SCR_07_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_07_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_07_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_K_SCR_07_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_PR0_SHIFT)
#define GPIO_K_SCR_07_0_PR0_RANGE                       16:16
#define GPIO_K_SCR_07_0_PR0_WOFFSET                     0x0
#define GPIO_K_SCR_07_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_07_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_07_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_K_SCR_07_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_G7W_SHIFT)
#define GPIO_K_SCR_07_0_G7W_RANGE                       15:15
#define GPIO_K_SCR_07_0_G7W_WOFFSET                     0x0
#define GPIO_K_SCR_07_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_07_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_07_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_K_SCR_07_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_G6W_SHIFT)
#define GPIO_K_SCR_07_0_G6W_RANGE                       14:14
#define GPIO_K_SCR_07_0_G6W_WOFFSET                     0x0
#define GPIO_K_SCR_07_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_07_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_07_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_K_SCR_07_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_G5W_SHIFT)
#define GPIO_K_SCR_07_0_G5W_RANGE                       13:13
#define GPIO_K_SCR_07_0_G5W_WOFFSET                     0x0
#define GPIO_K_SCR_07_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_07_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_07_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_K_SCR_07_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_G4W_SHIFT)
#define GPIO_K_SCR_07_0_G4W_RANGE                       12:12
#define GPIO_K_SCR_07_0_G4W_WOFFSET                     0x0
#define GPIO_K_SCR_07_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_07_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_07_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_K_SCR_07_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_G3W_SHIFT)
#define GPIO_K_SCR_07_0_G3W_RANGE                       11:11
#define GPIO_K_SCR_07_0_G3W_WOFFSET                     0x0
#define GPIO_K_SCR_07_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_07_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_07_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_K_SCR_07_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_G2W_SHIFT)
#define GPIO_K_SCR_07_0_G2W_RANGE                       10:10
#define GPIO_K_SCR_07_0_G2W_WOFFSET                     0x0
#define GPIO_K_SCR_07_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_07_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_07_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_K_SCR_07_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_G1W_SHIFT)
#define GPIO_K_SCR_07_0_G1W_RANGE                       9:9
#define GPIO_K_SCR_07_0_G1W_WOFFSET                     0x0
#define GPIO_K_SCR_07_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_07_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_07_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_K_SCR_07_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_G0W_SHIFT)
#define GPIO_K_SCR_07_0_G0W_RANGE                       8:8
#define GPIO_K_SCR_07_0_G0W_WOFFSET                     0x0
#define GPIO_K_SCR_07_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_07_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_07_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_K_SCR_07_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_G7R_SHIFT)
#define GPIO_K_SCR_07_0_G7R_RANGE                       7:7
#define GPIO_K_SCR_07_0_G7R_WOFFSET                     0x0
#define GPIO_K_SCR_07_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_07_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_07_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_K_SCR_07_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_G6R_SHIFT)
#define GPIO_K_SCR_07_0_G6R_RANGE                       6:6
#define GPIO_K_SCR_07_0_G6R_WOFFSET                     0x0
#define GPIO_K_SCR_07_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_07_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_07_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_K_SCR_07_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_G5R_SHIFT)
#define GPIO_K_SCR_07_0_G5R_RANGE                       5:5
#define GPIO_K_SCR_07_0_G5R_WOFFSET                     0x0
#define GPIO_K_SCR_07_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_07_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_07_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_K_SCR_07_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_G4R_SHIFT)
#define GPIO_K_SCR_07_0_G4R_RANGE                       4:4
#define GPIO_K_SCR_07_0_G4R_WOFFSET                     0x0
#define GPIO_K_SCR_07_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_07_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_07_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_K_SCR_07_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_G3R_SHIFT)
#define GPIO_K_SCR_07_0_G3R_RANGE                       3:3
#define GPIO_K_SCR_07_0_G3R_WOFFSET                     0x0
#define GPIO_K_SCR_07_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_07_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_07_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_K_SCR_07_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_G2R_SHIFT)
#define GPIO_K_SCR_07_0_G2R_RANGE                       2:2
#define GPIO_K_SCR_07_0_G2R_WOFFSET                     0x0
#define GPIO_K_SCR_07_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_07_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_07_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_K_SCR_07_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_G1R_SHIFT)
#define GPIO_K_SCR_07_0_G1R_RANGE                       1:1
#define GPIO_K_SCR_07_0_G1R_WOFFSET                     0x0
#define GPIO_K_SCR_07_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_07_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_K_SCR_07_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_K_SCR_07_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_G0R_SHIFT)
#define GPIO_K_SCR_07_0_G0R_RANGE                       0:0
#define GPIO_K_SCR_07_0_G0R_WOFFSET                     0x0
#define GPIO_K_SCR_07_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_SCR_07_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_L_VM_00_0
#define GPIO_L_VM_00_0                  _MK_ADDR_CONST(0x3040)
#define GPIO_L_VM_00_0_SECURE                   0x0
#define GPIO_L_VM_00_0_DUAL                     0x0
#define GPIO_L_VM_00_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_L_VM_00_0_WORD_COUNT                       0x1
#define GPIO_L_VM_00_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_L_VM_00_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_L_VM_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_L_VM_00_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_L_VM_00_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_L_VM_00_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_00_0_VM1_SHIFT)
#define GPIO_L_VM_00_0_VM1_RANGE                        1:0
#define GPIO_L_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_L_VM_00_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_00_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_00_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_L_VM_00_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_L_VM_00_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_00_0_VM2_SHIFT)
#define GPIO_L_VM_00_0_VM2_RANGE                        3:2
#define GPIO_L_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_L_VM_00_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_00_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_00_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_L_VM_00_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_L_VM_00_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_00_0_VM3_SHIFT)
#define GPIO_L_VM_00_0_VM3_RANGE                        5:4
#define GPIO_L_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_L_VM_00_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_00_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_00_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_L_VM_00_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_L_VM_00_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_00_0_VM4_SHIFT)
#define GPIO_L_VM_00_0_VM4_RANGE                        7:6
#define GPIO_L_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_L_VM_00_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_00_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_00_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_L_VM_00_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_L_VM_00_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_00_0_VM5_SHIFT)
#define GPIO_L_VM_00_0_VM5_RANGE                        9:8
#define GPIO_L_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_L_VM_00_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_00_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_00_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_L_VM_00_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_L_VM_00_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_00_0_VM6_SHIFT)
#define GPIO_L_VM_00_0_VM6_RANGE                        11:10
#define GPIO_L_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_L_VM_00_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_00_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_00_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_L_VM_00_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_L_VM_00_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_00_0_VM7_SHIFT)
#define GPIO_L_VM_00_0_VM7_RANGE                        13:12
#define GPIO_L_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_L_VM_00_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_00_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_00_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_L_VM_00_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_L_VM_00_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_00_0_VM8_SHIFT)
#define GPIO_L_VM_00_0_VM8_RANGE                        15:14
#define GPIO_L_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_L_VM_00_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_00_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_00_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_L_SCR_00_0
#define GPIO_L_SCR_00_0                 _MK_ADDR_CONST(0x3044)
#define GPIO_L_SCR_00_0_SECURE                  0x0
#define GPIO_L_SCR_00_0_DUAL                    0x0
#define GPIO_L_SCR_00_0_SCR                     0
#define GPIO_L_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_L_SCR_00_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_L_SCR_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_L_SCR_00_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_L_SCR_00_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_L_SCR_00_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_L_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_L_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_L_SCR_00_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_00_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_L_SCR_00_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_L_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_L_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_L_SCR_00_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_00_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_L_SCR_00_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_L_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_L_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_L_SCR_00_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_00_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_L_SCR_00_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_L_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_L_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_L_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_L_SCR_00_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_L_SCR_00_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_00_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_L_SCR_00_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_PR7_SHIFT)
#define GPIO_L_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_L_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_00_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_L_SCR_00_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_PR6_SHIFT)
#define GPIO_L_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_L_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_00_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_L_SCR_00_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_PR5_SHIFT)
#define GPIO_L_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_L_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_00_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_L_SCR_00_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_PR4_SHIFT)
#define GPIO_L_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_L_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_00_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_L_SCR_00_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_PR3_SHIFT)
#define GPIO_L_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_L_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_00_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_L_SCR_00_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_PR2_SHIFT)
#define GPIO_L_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_L_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_00_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_L_SCR_00_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_PR1_SHIFT)
#define GPIO_L_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_L_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_00_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_L_SCR_00_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_PR0_SHIFT)
#define GPIO_L_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_L_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_00_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_L_SCR_00_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G7W_SHIFT)
#define GPIO_L_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_L_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_00_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_L_SCR_00_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G6W_SHIFT)
#define GPIO_L_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_L_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_00_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_L_SCR_00_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G5W_SHIFT)
#define GPIO_L_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_L_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_00_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_L_SCR_00_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G4W_SHIFT)
#define GPIO_L_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_L_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_00_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_L_SCR_00_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G3W_SHIFT)
#define GPIO_L_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_L_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_00_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_L_SCR_00_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G2W_SHIFT)
#define GPIO_L_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_L_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_00_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_L_SCR_00_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G1W_SHIFT)
#define GPIO_L_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_L_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_00_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_L_SCR_00_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G0W_SHIFT)
#define GPIO_L_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_L_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_00_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_L_SCR_00_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G7R_SHIFT)
#define GPIO_L_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_L_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_00_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_L_SCR_00_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G6R_SHIFT)
#define GPIO_L_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_L_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_00_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_L_SCR_00_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G5R_SHIFT)
#define GPIO_L_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_L_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_00_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_L_SCR_00_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G4R_SHIFT)
#define GPIO_L_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_L_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_00_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_L_SCR_00_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G3R_SHIFT)
#define GPIO_L_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_L_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_00_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_L_SCR_00_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G2R_SHIFT)
#define GPIO_L_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_L_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_00_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_L_SCR_00_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G1R_SHIFT)
#define GPIO_L_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_L_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_00_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_L_SCR_00_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G0R_SHIFT)
#define GPIO_L_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_L_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_L_VM_01_0
#define GPIO_L_VM_01_0                  _MK_ADDR_CONST(0x3048)
#define GPIO_L_VM_01_0_SECURE                   0x0
#define GPIO_L_VM_01_0_DUAL                     0x0
#define GPIO_L_VM_01_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_L_VM_01_0_WORD_COUNT                       0x1
#define GPIO_L_VM_01_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_L_VM_01_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_L_VM_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_L_VM_01_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_L_VM_01_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_L_VM_01_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_01_0_VM1_SHIFT)
#define GPIO_L_VM_01_0_VM1_RANGE                        1:0
#define GPIO_L_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_L_VM_01_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_01_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_01_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_L_VM_01_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_L_VM_01_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_01_0_VM2_SHIFT)
#define GPIO_L_VM_01_0_VM2_RANGE                        3:2
#define GPIO_L_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_L_VM_01_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_01_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_01_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_L_VM_01_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_L_VM_01_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_01_0_VM3_SHIFT)
#define GPIO_L_VM_01_0_VM3_RANGE                        5:4
#define GPIO_L_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_L_VM_01_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_01_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_01_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_L_VM_01_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_L_VM_01_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_01_0_VM4_SHIFT)
#define GPIO_L_VM_01_0_VM4_RANGE                        7:6
#define GPIO_L_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_L_VM_01_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_01_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_01_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_L_VM_01_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_L_VM_01_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_01_0_VM5_SHIFT)
#define GPIO_L_VM_01_0_VM5_RANGE                        9:8
#define GPIO_L_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_L_VM_01_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_01_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_01_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_L_VM_01_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_L_VM_01_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_01_0_VM6_SHIFT)
#define GPIO_L_VM_01_0_VM6_RANGE                        11:10
#define GPIO_L_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_L_VM_01_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_01_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_01_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_L_VM_01_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_L_VM_01_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_01_0_VM7_SHIFT)
#define GPIO_L_VM_01_0_VM7_RANGE                        13:12
#define GPIO_L_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_L_VM_01_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_01_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_01_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_L_VM_01_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_L_VM_01_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_01_0_VM8_SHIFT)
#define GPIO_L_VM_01_0_VM8_RANGE                        15:14
#define GPIO_L_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_L_VM_01_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_01_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_01_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_L_SCR_01_0
#define GPIO_L_SCR_01_0                 _MK_ADDR_CONST(0x304c)
#define GPIO_L_SCR_01_0_SECURE                  0x0
#define GPIO_L_SCR_01_0_DUAL                    0x0
#define GPIO_L_SCR_01_0_SCR                     0
#define GPIO_L_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_L_SCR_01_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_L_SCR_01_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_L_SCR_01_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_L_SCR_01_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_L_SCR_01_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_L_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_L_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_L_SCR_01_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_01_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_L_SCR_01_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_L_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_L_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_L_SCR_01_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_01_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_L_SCR_01_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_L_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_L_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_L_SCR_01_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_01_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_L_SCR_01_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_L_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_L_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_L_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_L_SCR_01_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_L_SCR_01_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_01_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_L_SCR_01_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_PR7_SHIFT)
#define GPIO_L_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_L_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_01_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_L_SCR_01_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_PR6_SHIFT)
#define GPIO_L_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_L_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_01_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_L_SCR_01_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_PR5_SHIFT)
#define GPIO_L_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_L_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_01_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_L_SCR_01_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_PR4_SHIFT)
#define GPIO_L_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_L_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_01_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_L_SCR_01_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_PR3_SHIFT)
#define GPIO_L_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_L_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_01_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_L_SCR_01_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_PR2_SHIFT)
#define GPIO_L_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_L_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_01_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_L_SCR_01_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_PR1_SHIFT)
#define GPIO_L_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_L_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_01_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_L_SCR_01_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_PR0_SHIFT)
#define GPIO_L_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_L_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_01_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_L_SCR_01_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G7W_SHIFT)
#define GPIO_L_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_L_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_01_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_L_SCR_01_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G6W_SHIFT)
#define GPIO_L_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_L_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_01_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_L_SCR_01_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G5W_SHIFT)
#define GPIO_L_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_L_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_01_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_L_SCR_01_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G4W_SHIFT)
#define GPIO_L_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_L_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_01_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_L_SCR_01_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G3W_SHIFT)
#define GPIO_L_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_L_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_01_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_L_SCR_01_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G2W_SHIFT)
#define GPIO_L_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_L_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_01_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_L_SCR_01_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G1W_SHIFT)
#define GPIO_L_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_L_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_01_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_L_SCR_01_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G0W_SHIFT)
#define GPIO_L_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_L_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_01_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_L_SCR_01_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G7R_SHIFT)
#define GPIO_L_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_L_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_01_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_L_SCR_01_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G6R_SHIFT)
#define GPIO_L_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_L_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_01_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_L_SCR_01_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G5R_SHIFT)
#define GPIO_L_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_L_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_01_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_L_SCR_01_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G4R_SHIFT)
#define GPIO_L_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_L_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_01_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_L_SCR_01_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G3R_SHIFT)
#define GPIO_L_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_L_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_01_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_L_SCR_01_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G2R_SHIFT)
#define GPIO_L_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_L_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_01_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_L_SCR_01_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G1R_SHIFT)
#define GPIO_L_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_L_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_01_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_L_SCR_01_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G0R_SHIFT)
#define GPIO_L_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_L_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_L_VM_02_0
#define GPIO_L_VM_02_0                  _MK_ADDR_CONST(0x3050)
#define GPIO_L_VM_02_0_SECURE                   0x0
#define GPIO_L_VM_02_0_DUAL                     0x0
#define GPIO_L_VM_02_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_L_VM_02_0_WORD_COUNT                       0x1
#define GPIO_L_VM_02_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_L_VM_02_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_L_VM_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_L_VM_02_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_L_VM_02_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_L_VM_02_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_02_0_VM1_SHIFT)
#define GPIO_L_VM_02_0_VM1_RANGE                        1:0
#define GPIO_L_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_L_VM_02_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_02_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_02_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_L_VM_02_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_L_VM_02_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_02_0_VM2_SHIFT)
#define GPIO_L_VM_02_0_VM2_RANGE                        3:2
#define GPIO_L_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_L_VM_02_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_02_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_02_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_L_VM_02_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_L_VM_02_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_02_0_VM3_SHIFT)
#define GPIO_L_VM_02_0_VM3_RANGE                        5:4
#define GPIO_L_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_L_VM_02_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_02_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_02_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_L_VM_02_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_L_VM_02_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_02_0_VM4_SHIFT)
#define GPIO_L_VM_02_0_VM4_RANGE                        7:6
#define GPIO_L_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_L_VM_02_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_02_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_02_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_L_VM_02_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_L_VM_02_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_02_0_VM5_SHIFT)
#define GPIO_L_VM_02_0_VM5_RANGE                        9:8
#define GPIO_L_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_L_VM_02_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_02_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_02_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_L_VM_02_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_L_VM_02_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_02_0_VM6_SHIFT)
#define GPIO_L_VM_02_0_VM6_RANGE                        11:10
#define GPIO_L_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_L_VM_02_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_02_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_02_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_L_VM_02_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_L_VM_02_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_02_0_VM7_SHIFT)
#define GPIO_L_VM_02_0_VM7_RANGE                        13:12
#define GPIO_L_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_L_VM_02_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_02_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_02_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_L_VM_02_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_L_VM_02_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_02_0_VM8_SHIFT)
#define GPIO_L_VM_02_0_VM8_RANGE                        15:14
#define GPIO_L_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_L_VM_02_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_02_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_02_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_L_SCR_02_0
#define GPIO_L_SCR_02_0                 _MK_ADDR_CONST(0x3054)
#define GPIO_L_SCR_02_0_SECURE                  0x0
#define GPIO_L_SCR_02_0_DUAL                    0x0
#define GPIO_L_SCR_02_0_SCR                     0
#define GPIO_L_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_L_SCR_02_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_L_SCR_02_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_L_SCR_02_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_L_SCR_02_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_L_SCR_02_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_L_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_L_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_L_SCR_02_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_02_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_L_SCR_02_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_L_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_L_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_L_SCR_02_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_02_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_L_SCR_02_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_L_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_L_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_L_SCR_02_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_02_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_L_SCR_02_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_L_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_L_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_L_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_L_SCR_02_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_L_SCR_02_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_02_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_L_SCR_02_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_PR7_SHIFT)
#define GPIO_L_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_L_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_02_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_L_SCR_02_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_PR6_SHIFT)
#define GPIO_L_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_L_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_02_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_L_SCR_02_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_PR5_SHIFT)
#define GPIO_L_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_L_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_02_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_L_SCR_02_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_PR4_SHIFT)
#define GPIO_L_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_L_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_02_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_L_SCR_02_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_PR3_SHIFT)
#define GPIO_L_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_L_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_02_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_L_SCR_02_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_PR2_SHIFT)
#define GPIO_L_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_L_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_02_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_L_SCR_02_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_PR1_SHIFT)
#define GPIO_L_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_L_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_02_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_L_SCR_02_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_PR0_SHIFT)
#define GPIO_L_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_L_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_02_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_L_SCR_02_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G7W_SHIFT)
#define GPIO_L_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_L_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_02_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_L_SCR_02_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G6W_SHIFT)
#define GPIO_L_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_L_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_02_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_L_SCR_02_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G5W_SHIFT)
#define GPIO_L_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_L_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_02_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_L_SCR_02_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G4W_SHIFT)
#define GPIO_L_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_L_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_02_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_L_SCR_02_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G3W_SHIFT)
#define GPIO_L_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_L_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_02_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_L_SCR_02_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G2W_SHIFT)
#define GPIO_L_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_L_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_02_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_L_SCR_02_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G1W_SHIFT)
#define GPIO_L_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_L_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_02_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_L_SCR_02_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G0W_SHIFT)
#define GPIO_L_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_L_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_02_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_L_SCR_02_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G7R_SHIFT)
#define GPIO_L_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_L_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_02_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_L_SCR_02_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G6R_SHIFT)
#define GPIO_L_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_L_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_02_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_L_SCR_02_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G5R_SHIFT)
#define GPIO_L_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_L_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_02_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_L_SCR_02_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G4R_SHIFT)
#define GPIO_L_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_L_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_02_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_L_SCR_02_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G3R_SHIFT)
#define GPIO_L_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_L_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_02_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_L_SCR_02_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G2R_SHIFT)
#define GPIO_L_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_L_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_02_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_L_SCR_02_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G1R_SHIFT)
#define GPIO_L_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_L_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_02_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_L_SCR_02_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G0R_SHIFT)
#define GPIO_L_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_L_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_L_VM_03_0
#define GPIO_L_VM_03_0                  _MK_ADDR_CONST(0x3058)
#define GPIO_L_VM_03_0_SECURE                   0x0
#define GPIO_L_VM_03_0_DUAL                     0x0
#define GPIO_L_VM_03_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_L_VM_03_0_WORD_COUNT                       0x1
#define GPIO_L_VM_03_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_L_VM_03_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_L_VM_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_L_VM_03_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_L_VM_03_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_L_VM_03_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_03_0_VM1_SHIFT)
#define GPIO_L_VM_03_0_VM1_RANGE                        1:0
#define GPIO_L_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_L_VM_03_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_03_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_03_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_L_VM_03_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_L_VM_03_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_03_0_VM2_SHIFT)
#define GPIO_L_VM_03_0_VM2_RANGE                        3:2
#define GPIO_L_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_L_VM_03_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_03_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_03_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_L_VM_03_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_L_VM_03_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_03_0_VM3_SHIFT)
#define GPIO_L_VM_03_0_VM3_RANGE                        5:4
#define GPIO_L_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_L_VM_03_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_03_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_03_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_L_VM_03_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_L_VM_03_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_03_0_VM4_SHIFT)
#define GPIO_L_VM_03_0_VM4_RANGE                        7:6
#define GPIO_L_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_L_VM_03_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_03_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_03_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_L_VM_03_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_L_VM_03_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_03_0_VM5_SHIFT)
#define GPIO_L_VM_03_0_VM5_RANGE                        9:8
#define GPIO_L_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_L_VM_03_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_03_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_03_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_L_VM_03_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_L_VM_03_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_03_0_VM6_SHIFT)
#define GPIO_L_VM_03_0_VM6_RANGE                        11:10
#define GPIO_L_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_L_VM_03_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_03_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_03_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_L_VM_03_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_L_VM_03_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_03_0_VM7_SHIFT)
#define GPIO_L_VM_03_0_VM7_RANGE                        13:12
#define GPIO_L_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_L_VM_03_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_03_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_03_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_L_VM_03_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_L_VM_03_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_L_VM_03_0_VM8_SHIFT)
#define GPIO_L_VM_03_0_VM8_RANGE                        15:14
#define GPIO_L_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_L_VM_03_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_L_VM_03_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_L_VM_03_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_L_SCR_03_0
#define GPIO_L_SCR_03_0                 _MK_ADDR_CONST(0x305c)
#define GPIO_L_SCR_03_0_SECURE                  0x0
#define GPIO_L_SCR_03_0_DUAL                    0x0
#define GPIO_L_SCR_03_0_SCR                     0
#define GPIO_L_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_L_SCR_03_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_L_SCR_03_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_L_SCR_03_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_L_SCR_03_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_L_SCR_03_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_L_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_L_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_L_SCR_03_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_03_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_L_SCR_03_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_L_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_L_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_L_SCR_03_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_03_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_L_SCR_03_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_L_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_L_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_L_SCR_03_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_03_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_L_SCR_03_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_L_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_L_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_L_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_L_SCR_03_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_L_SCR_03_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_03_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_L_SCR_03_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_PR7_SHIFT)
#define GPIO_L_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_L_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_03_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_L_SCR_03_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_PR6_SHIFT)
#define GPIO_L_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_L_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_03_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_L_SCR_03_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_PR5_SHIFT)
#define GPIO_L_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_L_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_03_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_L_SCR_03_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_PR4_SHIFT)
#define GPIO_L_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_L_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_03_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_L_SCR_03_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_PR3_SHIFT)
#define GPIO_L_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_L_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_03_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_L_SCR_03_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_PR2_SHIFT)
#define GPIO_L_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_L_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_03_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_L_SCR_03_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_PR1_SHIFT)
#define GPIO_L_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_L_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_03_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_L_SCR_03_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_PR0_SHIFT)
#define GPIO_L_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_L_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_03_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_L_SCR_03_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G7W_SHIFT)
#define GPIO_L_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_L_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_03_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_L_SCR_03_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G6W_SHIFT)
#define GPIO_L_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_L_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_03_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_L_SCR_03_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G5W_SHIFT)
#define GPIO_L_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_L_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_03_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_L_SCR_03_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G4W_SHIFT)
#define GPIO_L_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_L_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_03_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_L_SCR_03_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G3W_SHIFT)
#define GPIO_L_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_L_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_03_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_L_SCR_03_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G2W_SHIFT)
#define GPIO_L_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_L_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_03_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_L_SCR_03_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G1W_SHIFT)
#define GPIO_L_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_L_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_03_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_L_SCR_03_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G0W_SHIFT)
#define GPIO_L_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_L_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_03_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_L_SCR_03_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G7R_SHIFT)
#define GPIO_L_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_L_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_03_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_L_SCR_03_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G6R_SHIFT)
#define GPIO_L_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_L_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_03_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_L_SCR_03_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G5R_SHIFT)
#define GPIO_L_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_L_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_03_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_L_SCR_03_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G4R_SHIFT)
#define GPIO_L_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_L_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_03_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_L_SCR_03_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G3R_SHIFT)
#define GPIO_L_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_L_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_03_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_L_SCR_03_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G2R_SHIFT)
#define GPIO_L_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_L_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_03_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_L_SCR_03_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G1R_SHIFT)
#define GPIO_L_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_L_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_L_SCR_03_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_L_SCR_03_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G0R_SHIFT)
#define GPIO_L_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_L_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Reserved address 0x3060

// Reserved address 0x3064

// Reserved address 0x3068

// Reserved address 0x306c

// Reserved address 0x3070

// Reserved address 0x3074

// Reserved address 0x3078

// Reserved address 0x307c

// Register GPIO_FF_VM_00_0
#define GPIO_FF_VM_00_0                 _MK_ADDR_CONST(0x3080)
#define GPIO_FF_VM_00_0_SECURE                  0x0
#define GPIO_FF_VM_00_0_DUAL                    0x0
#define GPIO_FF_VM_00_0_SCR                     GPIO_CTL3_VM_SCR_0
#define GPIO_FF_VM_00_0_WORD_COUNT                      0x1
#define GPIO_FF_VM_00_0_RESET_VAL                       _MK_MASK_CONST(0xffff)
#define GPIO_FF_VM_00_0_RESET_MASK                      _MK_MASK_CONST(0xffff)
#define GPIO_FF_VM_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_FF_VM_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_FF_VM_00_0_READ_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_FF_VM_00_0_WRITE_MASK                      _MK_MASK_CONST(0xffff)
#define GPIO_FF_VM_00_0_VM1_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_FF_VM_00_0_VM1_FIELD                       _MK_FIELD_CONST(0x3, GPIO_FF_VM_00_0_VM1_SHIFT)
#define GPIO_FF_VM_00_0_VM1_RANGE                       1:0
#define GPIO_FF_VM_00_0_VM1_WOFFSET                     0x0
#define GPIO_FF_VM_00_0_VM1_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_FF_VM_00_0_VM1_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_FF_VM_00_0_VM1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_FF_VM_00_0_VM1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_FF_VM_00_0_VM1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_FF_VM_00_0_VM1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_FF_VM_00_0_VM2_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_FF_VM_00_0_VM2_FIELD                       _MK_FIELD_CONST(0x3, GPIO_FF_VM_00_0_VM2_SHIFT)
#define GPIO_FF_VM_00_0_VM2_RANGE                       3:2
#define GPIO_FF_VM_00_0_VM2_WOFFSET                     0x0
#define GPIO_FF_VM_00_0_VM2_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_FF_VM_00_0_VM2_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_FF_VM_00_0_VM2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_FF_VM_00_0_VM2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_FF_VM_00_0_VM2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_FF_VM_00_0_VM2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_FF_VM_00_0_VM3_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_FF_VM_00_0_VM3_FIELD                       _MK_FIELD_CONST(0x3, GPIO_FF_VM_00_0_VM3_SHIFT)
#define GPIO_FF_VM_00_0_VM3_RANGE                       5:4
#define GPIO_FF_VM_00_0_VM3_WOFFSET                     0x0
#define GPIO_FF_VM_00_0_VM3_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_FF_VM_00_0_VM3_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_FF_VM_00_0_VM3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_FF_VM_00_0_VM3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_FF_VM_00_0_VM3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_FF_VM_00_0_VM3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_FF_VM_00_0_VM4_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_FF_VM_00_0_VM4_FIELD                       _MK_FIELD_CONST(0x3, GPIO_FF_VM_00_0_VM4_SHIFT)
#define GPIO_FF_VM_00_0_VM4_RANGE                       7:6
#define GPIO_FF_VM_00_0_VM4_WOFFSET                     0x0
#define GPIO_FF_VM_00_0_VM4_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_FF_VM_00_0_VM4_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_FF_VM_00_0_VM4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_FF_VM_00_0_VM4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_FF_VM_00_0_VM4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_FF_VM_00_0_VM4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_FF_VM_00_0_VM5_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_FF_VM_00_0_VM5_FIELD                       _MK_FIELD_CONST(0x3, GPIO_FF_VM_00_0_VM5_SHIFT)
#define GPIO_FF_VM_00_0_VM5_RANGE                       9:8
#define GPIO_FF_VM_00_0_VM5_WOFFSET                     0x0
#define GPIO_FF_VM_00_0_VM5_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_FF_VM_00_0_VM5_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_FF_VM_00_0_VM5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_FF_VM_00_0_VM5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_FF_VM_00_0_VM5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_FF_VM_00_0_VM5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_FF_VM_00_0_VM6_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_FF_VM_00_0_VM6_FIELD                       _MK_FIELD_CONST(0x3, GPIO_FF_VM_00_0_VM6_SHIFT)
#define GPIO_FF_VM_00_0_VM6_RANGE                       11:10
#define GPIO_FF_VM_00_0_VM6_WOFFSET                     0x0
#define GPIO_FF_VM_00_0_VM6_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_FF_VM_00_0_VM6_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_FF_VM_00_0_VM6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_FF_VM_00_0_VM6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_FF_VM_00_0_VM6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_FF_VM_00_0_VM6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_FF_VM_00_0_VM7_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_FF_VM_00_0_VM7_FIELD                       _MK_FIELD_CONST(0x3, GPIO_FF_VM_00_0_VM7_SHIFT)
#define GPIO_FF_VM_00_0_VM7_RANGE                       13:12
#define GPIO_FF_VM_00_0_VM7_WOFFSET                     0x0
#define GPIO_FF_VM_00_0_VM7_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_FF_VM_00_0_VM7_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_FF_VM_00_0_VM7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_FF_VM_00_0_VM7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_FF_VM_00_0_VM7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_FF_VM_00_0_VM7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_FF_VM_00_0_VM8_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_FF_VM_00_0_VM8_FIELD                       _MK_FIELD_CONST(0x3, GPIO_FF_VM_00_0_VM8_SHIFT)
#define GPIO_FF_VM_00_0_VM8_RANGE                       15:14
#define GPIO_FF_VM_00_0_VM8_WOFFSET                     0x0
#define GPIO_FF_VM_00_0_VM8_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_FF_VM_00_0_VM8_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_FF_VM_00_0_VM8_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_FF_VM_00_0_VM8_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_FF_VM_00_0_VM8_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_FF_VM_00_0_VM8_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_FF_SCR_00_0
#define GPIO_FF_SCR_00_0                        _MK_ADDR_CONST(0x3084)
#define GPIO_FF_SCR_00_0_SECURE                         0x0
#define GPIO_FF_SCR_00_0_DUAL                   0x0
#define GPIO_FF_SCR_00_0_SCR                    0
#define GPIO_FF_SCR_00_0_WORD_COUNT                     0x1
#define GPIO_FF_SCR_00_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_RESET_MASK                     _MK_MASK_CONST(0x3fffffff)
#define GPIO_FF_SCR_00_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_READ_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_FF_SCR_00_0_WRITE_MASK                     _MK_MASK_CONST(0x3fffffff)
#define GPIO_FF_SCR_00_0_SEC_LCK_SHIFT                  _MK_SHIFT_CONST(29)
#define GPIO_FF_SCR_00_0_SEC_LCK_FIELD                  _MK_FIELD_CONST(0x1, GPIO_FF_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_FF_SCR_00_0_SEC_LCK_RANGE                  29:29
#define GPIO_FF_SCR_00_0_SEC_LCK_WOFFSET                        0x0
#define GPIO_FF_SCR_00_0_SEC_LCK_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_SEC_LCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_FF_SCR_00_0_SEC_LCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_SEC_LCK_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define GPIO_FF_SCR_00_0_SEC_WEN_SHIFT                  _MK_SHIFT_CONST(28)
#define GPIO_FF_SCR_00_0_SEC_WEN_FIELD                  _MK_FIELD_CONST(0x1, GPIO_FF_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_FF_SCR_00_0_SEC_WEN_RANGE                  28:28
#define GPIO_FF_SCR_00_0_SEC_WEN_WOFFSET                        0x0
#define GPIO_FF_SCR_00_0_SEC_WEN_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_SEC_WEN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_FF_SCR_00_0_SEC_WEN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_SEC_WEN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define GPIO_FF_SCR_00_0_SEC_REN_SHIFT                  _MK_SHIFT_CONST(27)
#define GPIO_FF_SCR_00_0_SEC_REN_FIELD                  _MK_FIELD_CONST(0x1, GPIO_FF_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_FF_SCR_00_0_SEC_REN_RANGE                  27:27
#define GPIO_FF_SCR_00_0_SEC_REN_WOFFSET                        0x0
#define GPIO_FF_SCR_00_0_SEC_REN_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_SEC_REN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_FF_SCR_00_0_SEC_REN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_SEC_REN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define GPIO_FF_SCR_00_0_SEC_OWNER_SHIFT                        _MK_SHIFT_CONST(24)
#define GPIO_FF_SCR_00_0_SEC_OWNER_FIELD                        _MK_FIELD_CONST(0x7, GPIO_FF_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_FF_SCR_00_0_SEC_OWNER_RANGE                        26:24
#define GPIO_FF_SCR_00_0_SEC_OWNER_WOFFSET                      0x0
#define GPIO_FF_SCR_00_0_SEC_OWNER_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_SEC_OWNER_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
#define GPIO_FF_SCR_00_0_SEC_OWNER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_FF_SCR_00_0_PR7_SHIFT                      _MK_SHIFT_CONST(23)
#define GPIO_FF_SCR_00_0_PR7_FIELD                      _MK_FIELD_CONST(0x1, GPIO_FF_SCR_00_0_PR7_SHIFT)
#define GPIO_FF_SCR_00_0_PR7_RANGE                      23:23
#define GPIO_FF_SCR_00_0_PR7_WOFFSET                    0x0
#define GPIO_FF_SCR_00_0_PR7_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_PR7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_FF_SCR_00_0_PR7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_PR7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_PR7_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_PR7_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_FF_SCR_00_0_PR6_SHIFT                      _MK_SHIFT_CONST(22)
#define GPIO_FF_SCR_00_0_PR6_FIELD                      _MK_FIELD_CONST(0x1, GPIO_FF_SCR_00_0_PR6_SHIFT)
#define GPIO_FF_SCR_00_0_PR6_RANGE                      22:22
#define GPIO_FF_SCR_00_0_PR6_WOFFSET                    0x0
#define GPIO_FF_SCR_00_0_PR6_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_PR6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_FF_SCR_00_0_PR6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_PR6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_PR6_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_PR6_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_FF_SCR_00_0_PR5_SHIFT                      _MK_SHIFT_CONST(21)
#define GPIO_FF_SCR_00_0_PR5_FIELD                      _MK_FIELD_CONST(0x1, GPIO_FF_SCR_00_0_PR5_SHIFT)
#define GPIO_FF_SCR_00_0_PR5_RANGE                      21:21
#define GPIO_FF_SCR_00_0_PR5_WOFFSET                    0x0
#define GPIO_FF_SCR_00_0_PR5_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_PR5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_FF_SCR_00_0_PR5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_PR5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_PR5_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_PR5_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_FF_SCR_00_0_PR4_SHIFT                      _MK_SHIFT_CONST(20)
#define GPIO_FF_SCR_00_0_PR4_FIELD                      _MK_FIELD_CONST(0x1, GPIO_FF_SCR_00_0_PR4_SHIFT)
#define GPIO_FF_SCR_00_0_PR4_RANGE                      20:20
#define GPIO_FF_SCR_00_0_PR4_WOFFSET                    0x0
#define GPIO_FF_SCR_00_0_PR4_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_PR4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_FF_SCR_00_0_PR4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_PR4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_PR4_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_PR4_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_FF_SCR_00_0_PR3_SHIFT                      _MK_SHIFT_CONST(19)
#define GPIO_FF_SCR_00_0_PR3_FIELD                      _MK_FIELD_CONST(0x1, GPIO_FF_SCR_00_0_PR3_SHIFT)
#define GPIO_FF_SCR_00_0_PR3_RANGE                      19:19
#define GPIO_FF_SCR_00_0_PR3_WOFFSET                    0x0
#define GPIO_FF_SCR_00_0_PR3_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_PR3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_FF_SCR_00_0_PR3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_PR3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_PR3_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_PR3_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_FF_SCR_00_0_PR2_SHIFT                      _MK_SHIFT_CONST(18)
#define GPIO_FF_SCR_00_0_PR2_FIELD                      _MK_FIELD_CONST(0x1, GPIO_FF_SCR_00_0_PR2_SHIFT)
#define GPIO_FF_SCR_00_0_PR2_RANGE                      18:18
#define GPIO_FF_SCR_00_0_PR2_WOFFSET                    0x0
#define GPIO_FF_SCR_00_0_PR2_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_PR2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_FF_SCR_00_0_PR2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_PR2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_PR2_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_PR2_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_FF_SCR_00_0_PR1_SHIFT                      _MK_SHIFT_CONST(17)
#define GPIO_FF_SCR_00_0_PR1_FIELD                      _MK_FIELD_CONST(0x1, GPIO_FF_SCR_00_0_PR1_SHIFT)
#define GPIO_FF_SCR_00_0_PR1_RANGE                      17:17
#define GPIO_FF_SCR_00_0_PR1_WOFFSET                    0x0
#define GPIO_FF_SCR_00_0_PR1_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_PR1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_FF_SCR_00_0_PR1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_PR1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_PR1_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_PR1_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_FF_SCR_00_0_PR0_SHIFT                      _MK_SHIFT_CONST(16)
#define GPIO_FF_SCR_00_0_PR0_FIELD                      _MK_FIELD_CONST(0x1, GPIO_FF_SCR_00_0_PR0_SHIFT)
#define GPIO_FF_SCR_00_0_PR0_RANGE                      16:16
#define GPIO_FF_SCR_00_0_PR0_WOFFSET                    0x0
#define GPIO_FF_SCR_00_0_PR0_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_PR0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_FF_SCR_00_0_PR0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_PR0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_PR0_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_PR0_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_FF_SCR_00_0_G7W_SHIFT                      _MK_SHIFT_CONST(15)
#define GPIO_FF_SCR_00_0_G7W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_FF_SCR_00_0_G7W_SHIFT)
#define GPIO_FF_SCR_00_0_G7W_RANGE                      15:15
#define GPIO_FF_SCR_00_0_G7W_WOFFSET                    0x0
#define GPIO_FF_SCR_00_0_G7W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G7W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_FF_SCR_00_0_G7W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G7W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G7W_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G7W_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_FF_SCR_00_0_G6W_SHIFT                      _MK_SHIFT_CONST(14)
#define GPIO_FF_SCR_00_0_G6W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_FF_SCR_00_0_G6W_SHIFT)
#define GPIO_FF_SCR_00_0_G6W_RANGE                      14:14
#define GPIO_FF_SCR_00_0_G6W_WOFFSET                    0x0
#define GPIO_FF_SCR_00_0_G6W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G6W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_FF_SCR_00_0_G6W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G6W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G6W_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G6W_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_FF_SCR_00_0_G5W_SHIFT                      _MK_SHIFT_CONST(13)
#define GPIO_FF_SCR_00_0_G5W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_FF_SCR_00_0_G5W_SHIFT)
#define GPIO_FF_SCR_00_0_G5W_RANGE                      13:13
#define GPIO_FF_SCR_00_0_G5W_WOFFSET                    0x0
#define GPIO_FF_SCR_00_0_G5W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G5W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_FF_SCR_00_0_G5W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G5W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G5W_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G5W_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_FF_SCR_00_0_G4W_SHIFT                      _MK_SHIFT_CONST(12)
#define GPIO_FF_SCR_00_0_G4W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_FF_SCR_00_0_G4W_SHIFT)
#define GPIO_FF_SCR_00_0_G4W_RANGE                      12:12
#define GPIO_FF_SCR_00_0_G4W_WOFFSET                    0x0
#define GPIO_FF_SCR_00_0_G4W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G4W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_FF_SCR_00_0_G4W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G4W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G4W_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G4W_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_FF_SCR_00_0_G3W_SHIFT                      _MK_SHIFT_CONST(11)
#define GPIO_FF_SCR_00_0_G3W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_FF_SCR_00_0_G3W_SHIFT)
#define GPIO_FF_SCR_00_0_G3W_RANGE                      11:11
#define GPIO_FF_SCR_00_0_G3W_WOFFSET                    0x0
#define GPIO_FF_SCR_00_0_G3W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G3W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_FF_SCR_00_0_G3W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G3W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G3W_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G3W_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_FF_SCR_00_0_G2W_SHIFT                      _MK_SHIFT_CONST(10)
#define GPIO_FF_SCR_00_0_G2W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_FF_SCR_00_0_G2W_SHIFT)
#define GPIO_FF_SCR_00_0_G2W_RANGE                      10:10
#define GPIO_FF_SCR_00_0_G2W_WOFFSET                    0x0
#define GPIO_FF_SCR_00_0_G2W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G2W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_FF_SCR_00_0_G2W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G2W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G2W_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G2W_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_FF_SCR_00_0_G1W_SHIFT                      _MK_SHIFT_CONST(9)
#define GPIO_FF_SCR_00_0_G1W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_FF_SCR_00_0_G1W_SHIFT)
#define GPIO_FF_SCR_00_0_G1W_RANGE                      9:9
#define GPIO_FF_SCR_00_0_G1W_WOFFSET                    0x0
#define GPIO_FF_SCR_00_0_G1W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G1W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_FF_SCR_00_0_G1W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G1W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G1W_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G1W_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_FF_SCR_00_0_G0W_SHIFT                      _MK_SHIFT_CONST(8)
#define GPIO_FF_SCR_00_0_G0W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_FF_SCR_00_0_G0W_SHIFT)
#define GPIO_FF_SCR_00_0_G0W_RANGE                      8:8
#define GPIO_FF_SCR_00_0_G0W_WOFFSET                    0x0
#define GPIO_FF_SCR_00_0_G0W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G0W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_FF_SCR_00_0_G0W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G0W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G0W_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G0W_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_FF_SCR_00_0_G7R_SHIFT                      _MK_SHIFT_CONST(7)
#define GPIO_FF_SCR_00_0_G7R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_FF_SCR_00_0_G7R_SHIFT)
#define GPIO_FF_SCR_00_0_G7R_RANGE                      7:7
#define GPIO_FF_SCR_00_0_G7R_WOFFSET                    0x0
#define GPIO_FF_SCR_00_0_G7R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G7R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_FF_SCR_00_0_G7R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G7R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G7R_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G7R_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_FF_SCR_00_0_G6R_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_FF_SCR_00_0_G6R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_FF_SCR_00_0_G6R_SHIFT)
#define GPIO_FF_SCR_00_0_G6R_RANGE                      6:6
#define GPIO_FF_SCR_00_0_G6R_WOFFSET                    0x0
#define GPIO_FF_SCR_00_0_G6R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G6R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_FF_SCR_00_0_G6R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G6R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G6R_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G6R_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_FF_SCR_00_0_G5R_SHIFT                      _MK_SHIFT_CONST(5)
#define GPIO_FF_SCR_00_0_G5R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_FF_SCR_00_0_G5R_SHIFT)
#define GPIO_FF_SCR_00_0_G5R_RANGE                      5:5
#define GPIO_FF_SCR_00_0_G5R_WOFFSET                    0x0
#define GPIO_FF_SCR_00_0_G5R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G5R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_FF_SCR_00_0_G5R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G5R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G5R_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G5R_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_FF_SCR_00_0_G4R_SHIFT                      _MK_SHIFT_CONST(4)
#define GPIO_FF_SCR_00_0_G4R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_FF_SCR_00_0_G4R_SHIFT)
#define GPIO_FF_SCR_00_0_G4R_RANGE                      4:4
#define GPIO_FF_SCR_00_0_G4R_WOFFSET                    0x0
#define GPIO_FF_SCR_00_0_G4R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G4R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_FF_SCR_00_0_G4R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G4R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G4R_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G4R_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_FF_SCR_00_0_G3R_SHIFT                      _MK_SHIFT_CONST(3)
#define GPIO_FF_SCR_00_0_G3R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_FF_SCR_00_0_G3R_SHIFT)
#define GPIO_FF_SCR_00_0_G3R_RANGE                      3:3
#define GPIO_FF_SCR_00_0_G3R_WOFFSET                    0x0
#define GPIO_FF_SCR_00_0_G3R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G3R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_FF_SCR_00_0_G3R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G3R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G3R_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G3R_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_FF_SCR_00_0_G2R_SHIFT                      _MK_SHIFT_CONST(2)
#define GPIO_FF_SCR_00_0_G2R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_FF_SCR_00_0_G2R_SHIFT)
#define GPIO_FF_SCR_00_0_G2R_RANGE                      2:2
#define GPIO_FF_SCR_00_0_G2R_WOFFSET                    0x0
#define GPIO_FF_SCR_00_0_G2R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G2R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_FF_SCR_00_0_G2R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G2R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G2R_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G2R_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_FF_SCR_00_0_G1R_SHIFT                      _MK_SHIFT_CONST(1)
#define GPIO_FF_SCR_00_0_G1R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_FF_SCR_00_0_G1R_SHIFT)
#define GPIO_FF_SCR_00_0_G1R_RANGE                      1:1
#define GPIO_FF_SCR_00_0_G1R_WOFFSET                    0x0
#define GPIO_FF_SCR_00_0_G1R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G1R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_FF_SCR_00_0_G1R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G1R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G1R_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G1R_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_FF_SCR_00_0_G0R_SHIFT                      _MK_SHIFT_CONST(0)
#define GPIO_FF_SCR_00_0_G0R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_FF_SCR_00_0_G0R_SHIFT)
#define GPIO_FF_SCR_00_0_G0R_RANGE                      0:0
#define GPIO_FF_SCR_00_0_G0R_WOFFSET                    0x0
#define GPIO_FF_SCR_00_0_G0R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G0R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_FF_SCR_00_0_G0R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G0R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G0R_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_00_0_G0R_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Register GPIO_FF_VM_01_0
#define GPIO_FF_VM_01_0                 _MK_ADDR_CONST(0x3088)
#define GPIO_FF_VM_01_0_SECURE                  0x0
#define GPIO_FF_VM_01_0_DUAL                    0x0
#define GPIO_FF_VM_01_0_SCR                     GPIO_CTL3_VM_SCR_0
#define GPIO_FF_VM_01_0_WORD_COUNT                      0x1
#define GPIO_FF_VM_01_0_RESET_VAL                       _MK_MASK_CONST(0xffff)
#define GPIO_FF_VM_01_0_RESET_MASK                      _MK_MASK_CONST(0xffff)
#define GPIO_FF_VM_01_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_FF_VM_01_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_FF_VM_01_0_READ_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_FF_VM_01_0_WRITE_MASK                      _MK_MASK_CONST(0xffff)
#define GPIO_FF_VM_01_0_VM1_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_FF_VM_01_0_VM1_FIELD                       _MK_FIELD_CONST(0x3, GPIO_FF_VM_01_0_VM1_SHIFT)
#define GPIO_FF_VM_01_0_VM1_RANGE                       1:0
#define GPIO_FF_VM_01_0_VM1_WOFFSET                     0x0
#define GPIO_FF_VM_01_0_VM1_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_FF_VM_01_0_VM1_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_FF_VM_01_0_VM1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_FF_VM_01_0_VM1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_FF_VM_01_0_VM1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_FF_VM_01_0_VM1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_FF_VM_01_0_VM2_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_FF_VM_01_0_VM2_FIELD                       _MK_FIELD_CONST(0x3, GPIO_FF_VM_01_0_VM2_SHIFT)
#define GPIO_FF_VM_01_0_VM2_RANGE                       3:2
#define GPIO_FF_VM_01_0_VM2_WOFFSET                     0x0
#define GPIO_FF_VM_01_0_VM2_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_FF_VM_01_0_VM2_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_FF_VM_01_0_VM2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_FF_VM_01_0_VM2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_FF_VM_01_0_VM2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_FF_VM_01_0_VM2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_FF_VM_01_0_VM3_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_FF_VM_01_0_VM3_FIELD                       _MK_FIELD_CONST(0x3, GPIO_FF_VM_01_0_VM3_SHIFT)
#define GPIO_FF_VM_01_0_VM3_RANGE                       5:4
#define GPIO_FF_VM_01_0_VM3_WOFFSET                     0x0
#define GPIO_FF_VM_01_0_VM3_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_FF_VM_01_0_VM3_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_FF_VM_01_0_VM3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_FF_VM_01_0_VM3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_FF_VM_01_0_VM3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_FF_VM_01_0_VM3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_FF_VM_01_0_VM4_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_FF_VM_01_0_VM4_FIELD                       _MK_FIELD_CONST(0x3, GPIO_FF_VM_01_0_VM4_SHIFT)
#define GPIO_FF_VM_01_0_VM4_RANGE                       7:6
#define GPIO_FF_VM_01_0_VM4_WOFFSET                     0x0
#define GPIO_FF_VM_01_0_VM4_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_FF_VM_01_0_VM4_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_FF_VM_01_0_VM4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_FF_VM_01_0_VM4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_FF_VM_01_0_VM4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_FF_VM_01_0_VM4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_FF_VM_01_0_VM5_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_FF_VM_01_0_VM5_FIELD                       _MK_FIELD_CONST(0x3, GPIO_FF_VM_01_0_VM5_SHIFT)
#define GPIO_FF_VM_01_0_VM5_RANGE                       9:8
#define GPIO_FF_VM_01_0_VM5_WOFFSET                     0x0
#define GPIO_FF_VM_01_0_VM5_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_FF_VM_01_0_VM5_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_FF_VM_01_0_VM5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_FF_VM_01_0_VM5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_FF_VM_01_0_VM5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_FF_VM_01_0_VM5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_FF_VM_01_0_VM6_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_FF_VM_01_0_VM6_FIELD                       _MK_FIELD_CONST(0x3, GPIO_FF_VM_01_0_VM6_SHIFT)
#define GPIO_FF_VM_01_0_VM6_RANGE                       11:10
#define GPIO_FF_VM_01_0_VM6_WOFFSET                     0x0
#define GPIO_FF_VM_01_0_VM6_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_FF_VM_01_0_VM6_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_FF_VM_01_0_VM6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_FF_VM_01_0_VM6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_FF_VM_01_0_VM6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_FF_VM_01_0_VM6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_FF_VM_01_0_VM7_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_FF_VM_01_0_VM7_FIELD                       _MK_FIELD_CONST(0x3, GPIO_FF_VM_01_0_VM7_SHIFT)
#define GPIO_FF_VM_01_0_VM7_RANGE                       13:12
#define GPIO_FF_VM_01_0_VM7_WOFFSET                     0x0
#define GPIO_FF_VM_01_0_VM7_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_FF_VM_01_0_VM7_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_FF_VM_01_0_VM7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_FF_VM_01_0_VM7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_FF_VM_01_0_VM7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_FF_VM_01_0_VM7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_FF_VM_01_0_VM8_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_FF_VM_01_0_VM8_FIELD                       _MK_FIELD_CONST(0x3, GPIO_FF_VM_01_0_VM8_SHIFT)
#define GPIO_FF_VM_01_0_VM8_RANGE                       15:14
#define GPIO_FF_VM_01_0_VM8_WOFFSET                     0x0
#define GPIO_FF_VM_01_0_VM8_DEFAULT                     _MK_MASK_CONST(0x3)
#define GPIO_FF_VM_01_0_VM8_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_FF_VM_01_0_VM8_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_FF_VM_01_0_VM8_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_FF_VM_01_0_VM8_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_FF_VM_01_0_VM8_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_FF_SCR_01_0
#define GPIO_FF_SCR_01_0                        _MK_ADDR_CONST(0x308c)
#define GPIO_FF_SCR_01_0_SECURE                         0x0
#define GPIO_FF_SCR_01_0_DUAL                   0x0
#define GPIO_FF_SCR_01_0_SCR                    0
#define GPIO_FF_SCR_01_0_WORD_COUNT                     0x1
#define GPIO_FF_SCR_01_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_RESET_MASK                     _MK_MASK_CONST(0x3fffffff)
#define GPIO_FF_SCR_01_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_READ_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_FF_SCR_01_0_WRITE_MASK                     _MK_MASK_CONST(0x3fffffff)
#define GPIO_FF_SCR_01_0_SEC_LCK_SHIFT                  _MK_SHIFT_CONST(29)
#define GPIO_FF_SCR_01_0_SEC_LCK_FIELD                  _MK_FIELD_CONST(0x1, GPIO_FF_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_FF_SCR_01_0_SEC_LCK_RANGE                  29:29
#define GPIO_FF_SCR_01_0_SEC_LCK_WOFFSET                        0x0
#define GPIO_FF_SCR_01_0_SEC_LCK_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_SEC_LCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_FF_SCR_01_0_SEC_LCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_SEC_LCK_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define GPIO_FF_SCR_01_0_SEC_WEN_SHIFT                  _MK_SHIFT_CONST(28)
#define GPIO_FF_SCR_01_0_SEC_WEN_FIELD                  _MK_FIELD_CONST(0x1, GPIO_FF_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_FF_SCR_01_0_SEC_WEN_RANGE                  28:28
#define GPIO_FF_SCR_01_0_SEC_WEN_WOFFSET                        0x0
#define GPIO_FF_SCR_01_0_SEC_WEN_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_SEC_WEN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_FF_SCR_01_0_SEC_WEN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_SEC_WEN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define GPIO_FF_SCR_01_0_SEC_REN_SHIFT                  _MK_SHIFT_CONST(27)
#define GPIO_FF_SCR_01_0_SEC_REN_FIELD                  _MK_FIELD_CONST(0x1, GPIO_FF_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_FF_SCR_01_0_SEC_REN_RANGE                  27:27
#define GPIO_FF_SCR_01_0_SEC_REN_WOFFSET                        0x0
#define GPIO_FF_SCR_01_0_SEC_REN_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_SEC_REN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_FF_SCR_01_0_SEC_REN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_SEC_REN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define GPIO_FF_SCR_01_0_SEC_OWNER_SHIFT                        _MK_SHIFT_CONST(24)
#define GPIO_FF_SCR_01_0_SEC_OWNER_FIELD                        _MK_FIELD_CONST(0x7, GPIO_FF_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_FF_SCR_01_0_SEC_OWNER_RANGE                        26:24
#define GPIO_FF_SCR_01_0_SEC_OWNER_WOFFSET                      0x0
#define GPIO_FF_SCR_01_0_SEC_OWNER_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_SEC_OWNER_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
#define GPIO_FF_SCR_01_0_SEC_OWNER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_FF_SCR_01_0_PR7_SHIFT                      _MK_SHIFT_CONST(23)
#define GPIO_FF_SCR_01_0_PR7_FIELD                      _MK_FIELD_CONST(0x1, GPIO_FF_SCR_01_0_PR7_SHIFT)
#define GPIO_FF_SCR_01_0_PR7_RANGE                      23:23
#define GPIO_FF_SCR_01_0_PR7_WOFFSET                    0x0
#define GPIO_FF_SCR_01_0_PR7_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_PR7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_FF_SCR_01_0_PR7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_PR7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_PR7_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_PR7_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_FF_SCR_01_0_PR6_SHIFT                      _MK_SHIFT_CONST(22)
#define GPIO_FF_SCR_01_0_PR6_FIELD                      _MK_FIELD_CONST(0x1, GPIO_FF_SCR_01_0_PR6_SHIFT)
#define GPIO_FF_SCR_01_0_PR6_RANGE                      22:22
#define GPIO_FF_SCR_01_0_PR6_WOFFSET                    0x0
#define GPIO_FF_SCR_01_0_PR6_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_PR6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_FF_SCR_01_0_PR6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_PR6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_PR6_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_PR6_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_FF_SCR_01_0_PR5_SHIFT                      _MK_SHIFT_CONST(21)
#define GPIO_FF_SCR_01_0_PR5_FIELD                      _MK_FIELD_CONST(0x1, GPIO_FF_SCR_01_0_PR5_SHIFT)
#define GPIO_FF_SCR_01_0_PR5_RANGE                      21:21
#define GPIO_FF_SCR_01_0_PR5_WOFFSET                    0x0
#define GPIO_FF_SCR_01_0_PR5_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_PR5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_FF_SCR_01_0_PR5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_PR5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_PR5_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_PR5_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_FF_SCR_01_0_PR4_SHIFT                      _MK_SHIFT_CONST(20)
#define GPIO_FF_SCR_01_0_PR4_FIELD                      _MK_FIELD_CONST(0x1, GPIO_FF_SCR_01_0_PR4_SHIFT)
#define GPIO_FF_SCR_01_0_PR4_RANGE                      20:20
#define GPIO_FF_SCR_01_0_PR4_WOFFSET                    0x0
#define GPIO_FF_SCR_01_0_PR4_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_PR4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_FF_SCR_01_0_PR4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_PR4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_PR4_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_PR4_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_FF_SCR_01_0_PR3_SHIFT                      _MK_SHIFT_CONST(19)
#define GPIO_FF_SCR_01_0_PR3_FIELD                      _MK_FIELD_CONST(0x1, GPIO_FF_SCR_01_0_PR3_SHIFT)
#define GPIO_FF_SCR_01_0_PR3_RANGE                      19:19
#define GPIO_FF_SCR_01_0_PR3_WOFFSET                    0x0
#define GPIO_FF_SCR_01_0_PR3_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_PR3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_FF_SCR_01_0_PR3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_PR3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_PR3_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_PR3_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_FF_SCR_01_0_PR2_SHIFT                      _MK_SHIFT_CONST(18)
#define GPIO_FF_SCR_01_0_PR2_FIELD                      _MK_FIELD_CONST(0x1, GPIO_FF_SCR_01_0_PR2_SHIFT)
#define GPIO_FF_SCR_01_0_PR2_RANGE                      18:18
#define GPIO_FF_SCR_01_0_PR2_WOFFSET                    0x0
#define GPIO_FF_SCR_01_0_PR2_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_PR2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_FF_SCR_01_0_PR2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_PR2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_PR2_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_PR2_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_FF_SCR_01_0_PR1_SHIFT                      _MK_SHIFT_CONST(17)
#define GPIO_FF_SCR_01_0_PR1_FIELD                      _MK_FIELD_CONST(0x1, GPIO_FF_SCR_01_0_PR1_SHIFT)
#define GPIO_FF_SCR_01_0_PR1_RANGE                      17:17
#define GPIO_FF_SCR_01_0_PR1_WOFFSET                    0x0
#define GPIO_FF_SCR_01_0_PR1_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_PR1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_FF_SCR_01_0_PR1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_PR1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_PR1_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_PR1_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_FF_SCR_01_0_PR0_SHIFT                      _MK_SHIFT_CONST(16)
#define GPIO_FF_SCR_01_0_PR0_FIELD                      _MK_FIELD_CONST(0x1, GPIO_FF_SCR_01_0_PR0_SHIFT)
#define GPIO_FF_SCR_01_0_PR0_RANGE                      16:16
#define GPIO_FF_SCR_01_0_PR0_WOFFSET                    0x0
#define GPIO_FF_SCR_01_0_PR0_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_PR0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_FF_SCR_01_0_PR0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_PR0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_PR0_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_PR0_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_FF_SCR_01_0_G7W_SHIFT                      _MK_SHIFT_CONST(15)
#define GPIO_FF_SCR_01_0_G7W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_FF_SCR_01_0_G7W_SHIFT)
#define GPIO_FF_SCR_01_0_G7W_RANGE                      15:15
#define GPIO_FF_SCR_01_0_G7W_WOFFSET                    0x0
#define GPIO_FF_SCR_01_0_G7W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G7W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_FF_SCR_01_0_G7W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G7W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G7W_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G7W_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_FF_SCR_01_0_G6W_SHIFT                      _MK_SHIFT_CONST(14)
#define GPIO_FF_SCR_01_0_G6W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_FF_SCR_01_0_G6W_SHIFT)
#define GPIO_FF_SCR_01_0_G6W_RANGE                      14:14
#define GPIO_FF_SCR_01_0_G6W_WOFFSET                    0x0
#define GPIO_FF_SCR_01_0_G6W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G6W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_FF_SCR_01_0_G6W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G6W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G6W_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G6W_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_FF_SCR_01_0_G5W_SHIFT                      _MK_SHIFT_CONST(13)
#define GPIO_FF_SCR_01_0_G5W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_FF_SCR_01_0_G5W_SHIFT)
#define GPIO_FF_SCR_01_0_G5W_RANGE                      13:13
#define GPIO_FF_SCR_01_0_G5W_WOFFSET                    0x0
#define GPIO_FF_SCR_01_0_G5W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G5W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_FF_SCR_01_0_G5W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G5W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G5W_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G5W_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_FF_SCR_01_0_G4W_SHIFT                      _MK_SHIFT_CONST(12)
#define GPIO_FF_SCR_01_0_G4W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_FF_SCR_01_0_G4W_SHIFT)
#define GPIO_FF_SCR_01_0_G4W_RANGE                      12:12
#define GPIO_FF_SCR_01_0_G4W_WOFFSET                    0x0
#define GPIO_FF_SCR_01_0_G4W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G4W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_FF_SCR_01_0_G4W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G4W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G4W_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G4W_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_FF_SCR_01_0_G3W_SHIFT                      _MK_SHIFT_CONST(11)
#define GPIO_FF_SCR_01_0_G3W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_FF_SCR_01_0_G3W_SHIFT)
#define GPIO_FF_SCR_01_0_G3W_RANGE                      11:11
#define GPIO_FF_SCR_01_0_G3W_WOFFSET                    0x0
#define GPIO_FF_SCR_01_0_G3W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G3W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_FF_SCR_01_0_G3W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G3W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G3W_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G3W_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_FF_SCR_01_0_G2W_SHIFT                      _MK_SHIFT_CONST(10)
#define GPIO_FF_SCR_01_0_G2W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_FF_SCR_01_0_G2W_SHIFT)
#define GPIO_FF_SCR_01_0_G2W_RANGE                      10:10
#define GPIO_FF_SCR_01_0_G2W_WOFFSET                    0x0
#define GPIO_FF_SCR_01_0_G2W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G2W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_FF_SCR_01_0_G2W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G2W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G2W_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G2W_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_FF_SCR_01_0_G1W_SHIFT                      _MK_SHIFT_CONST(9)
#define GPIO_FF_SCR_01_0_G1W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_FF_SCR_01_0_G1W_SHIFT)
#define GPIO_FF_SCR_01_0_G1W_RANGE                      9:9
#define GPIO_FF_SCR_01_0_G1W_WOFFSET                    0x0
#define GPIO_FF_SCR_01_0_G1W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G1W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_FF_SCR_01_0_G1W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G1W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G1W_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G1W_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_FF_SCR_01_0_G0W_SHIFT                      _MK_SHIFT_CONST(8)
#define GPIO_FF_SCR_01_0_G0W_FIELD                      _MK_FIELD_CONST(0x1, GPIO_FF_SCR_01_0_G0W_SHIFT)
#define GPIO_FF_SCR_01_0_G0W_RANGE                      8:8
#define GPIO_FF_SCR_01_0_G0W_WOFFSET                    0x0
#define GPIO_FF_SCR_01_0_G0W_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G0W_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_FF_SCR_01_0_G0W_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G0W_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G0W_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G0W_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_FF_SCR_01_0_G7R_SHIFT                      _MK_SHIFT_CONST(7)
#define GPIO_FF_SCR_01_0_G7R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_FF_SCR_01_0_G7R_SHIFT)
#define GPIO_FF_SCR_01_0_G7R_RANGE                      7:7
#define GPIO_FF_SCR_01_0_G7R_WOFFSET                    0x0
#define GPIO_FF_SCR_01_0_G7R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G7R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_FF_SCR_01_0_G7R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G7R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G7R_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G7R_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_FF_SCR_01_0_G6R_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_FF_SCR_01_0_G6R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_FF_SCR_01_0_G6R_SHIFT)
#define GPIO_FF_SCR_01_0_G6R_RANGE                      6:6
#define GPIO_FF_SCR_01_0_G6R_WOFFSET                    0x0
#define GPIO_FF_SCR_01_0_G6R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G6R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_FF_SCR_01_0_G6R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G6R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G6R_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G6R_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_FF_SCR_01_0_G5R_SHIFT                      _MK_SHIFT_CONST(5)
#define GPIO_FF_SCR_01_0_G5R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_FF_SCR_01_0_G5R_SHIFT)
#define GPIO_FF_SCR_01_0_G5R_RANGE                      5:5
#define GPIO_FF_SCR_01_0_G5R_WOFFSET                    0x0
#define GPIO_FF_SCR_01_0_G5R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G5R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_FF_SCR_01_0_G5R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G5R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G5R_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G5R_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_FF_SCR_01_0_G4R_SHIFT                      _MK_SHIFT_CONST(4)
#define GPIO_FF_SCR_01_0_G4R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_FF_SCR_01_0_G4R_SHIFT)
#define GPIO_FF_SCR_01_0_G4R_RANGE                      4:4
#define GPIO_FF_SCR_01_0_G4R_WOFFSET                    0x0
#define GPIO_FF_SCR_01_0_G4R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G4R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_FF_SCR_01_0_G4R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G4R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G4R_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G4R_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_FF_SCR_01_0_G3R_SHIFT                      _MK_SHIFT_CONST(3)
#define GPIO_FF_SCR_01_0_G3R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_FF_SCR_01_0_G3R_SHIFT)
#define GPIO_FF_SCR_01_0_G3R_RANGE                      3:3
#define GPIO_FF_SCR_01_0_G3R_WOFFSET                    0x0
#define GPIO_FF_SCR_01_0_G3R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G3R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_FF_SCR_01_0_G3R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G3R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G3R_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G3R_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_FF_SCR_01_0_G2R_SHIFT                      _MK_SHIFT_CONST(2)
#define GPIO_FF_SCR_01_0_G2R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_FF_SCR_01_0_G2R_SHIFT)
#define GPIO_FF_SCR_01_0_G2R_RANGE                      2:2
#define GPIO_FF_SCR_01_0_G2R_WOFFSET                    0x0
#define GPIO_FF_SCR_01_0_G2R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G2R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_FF_SCR_01_0_G2R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G2R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G2R_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G2R_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_FF_SCR_01_0_G1R_SHIFT                      _MK_SHIFT_CONST(1)
#define GPIO_FF_SCR_01_0_G1R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_FF_SCR_01_0_G1R_SHIFT)
#define GPIO_FF_SCR_01_0_G1R_RANGE                      1:1
#define GPIO_FF_SCR_01_0_G1R_WOFFSET                    0x0
#define GPIO_FF_SCR_01_0_G1R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G1R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_FF_SCR_01_0_G1R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G1R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G1R_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G1R_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_FF_SCR_01_0_G0R_SHIFT                      _MK_SHIFT_CONST(0)
#define GPIO_FF_SCR_01_0_G0R_FIELD                      _MK_FIELD_CONST(0x1, GPIO_FF_SCR_01_0_G0R_SHIFT)
#define GPIO_FF_SCR_01_0_G0R_RANGE                      0:0
#define GPIO_FF_SCR_01_0_G0R_WOFFSET                    0x0
#define GPIO_FF_SCR_01_0_G0R_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G0R_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_FF_SCR_01_0_G0R_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G0R_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G0R_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_FF_SCR_01_0_G0R_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Reserved address 0x3090

// Reserved address 0x3094

// Reserved address 0x3098

// Reserved address 0x309c

// Reserved address 0x30a0

// Reserved address 0x30a4

// Reserved address 0x30a8

// Reserved address 0x30ac

// Reserved address 0x30b0

// Reserved address 0x30b4

// Reserved address 0x30b8

// Reserved address 0x30bc

// Register GPIO_S_VM_00_0
#define GPIO_S_VM_00_0                  _MK_ADDR_CONST(0x30c0)
#define GPIO_S_VM_00_0_SECURE                   0x0
#define GPIO_S_VM_00_0_DUAL                     0x0
#define GPIO_S_VM_00_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_S_VM_00_0_WORD_COUNT                       0x1
#define GPIO_S_VM_00_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_S_VM_00_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_S_VM_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_S_VM_00_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_S_VM_00_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_S_VM_00_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_S_VM_00_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_00_0_VM1_SHIFT)
#define GPIO_S_VM_00_0_VM1_RANGE                        1:0
#define GPIO_S_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_S_VM_00_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_00_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_00_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_00_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_00_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_00_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_00_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_S_VM_00_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_00_0_VM2_SHIFT)
#define GPIO_S_VM_00_0_VM2_RANGE                        3:2
#define GPIO_S_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_S_VM_00_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_00_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_00_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_00_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_00_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_00_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_00_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_S_VM_00_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_00_0_VM3_SHIFT)
#define GPIO_S_VM_00_0_VM3_RANGE                        5:4
#define GPIO_S_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_S_VM_00_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_00_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_00_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_00_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_00_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_00_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_00_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_S_VM_00_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_00_0_VM4_SHIFT)
#define GPIO_S_VM_00_0_VM4_RANGE                        7:6
#define GPIO_S_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_S_VM_00_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_00_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_00_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_00_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_00_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_00_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_00_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_S_VM_00_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_00_0_VM5_SHIFT)
#define GPIO_S_VM_00_0_VM5_RANGE                        9:8
#define GPIO_S_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_S_VM_00_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_00_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_00_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_00_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_00_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_00_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_00_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_S_VM_00_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_00_0_VM6_SHIFT)
#define GPIO_S_VM_00_0_VM6_RANGE                        11:10
#define GPIO_S_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_S_VM_00_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_00_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_00_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_00_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_00_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_00_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_00_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_S_VM_00_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_00_0_VM7_SHIFT)
#define GPIO_S_VM_00_0_VM7_RANGE                        13:12
#define GPIO_S_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_S_VM_00_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_00_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_00_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_00_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_00_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_00_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_00_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_S_VM_00_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_00_0_VM8_SHIFT)
#define GPIO_S_VM_00_0_VM8_RANGE                        15:14
#define GPIO_S_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_S_VM_00_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_00_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_00_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_00_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_00_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_00_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_S_SCR_00_0
#define GPIO_S_SCR_00_0                 _MK_ADDR_CONST(0x30c4)
#define GPIO_S_SCR_00_0_SECURE                  0x0
#define GPIO_S_SCR_00_0_DUAL                    0x0
#define GPIO_S_SCR_00_0_SCR                     0
#define GPIO_S_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_S_SCR_00_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_S_SCR_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_S_SCR_00_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_S_SCR_00_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_S_SCR_00_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_S_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_S_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_S_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_S_SCR_00_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_00_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_00_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_S_SCR_00_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_S_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_S_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_S_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_S_SCR_00_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_00_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_00_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_S_SCR_00_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_S_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_S_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_S_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_S_SCR_00_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_00_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_00_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_S_SCR_00_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_S_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_S_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_S_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_S_SCR_00_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_S_SCR_00_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_00_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_S_SCR_00_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_00_0_PR7_SHIFT)
#define GPIO_S_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_S_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_S_SCR_00_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_00_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_00_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_S_SCR_00_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_00_0_PR6_SHIFT)
#define GPIO_S_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_S_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_S_SCR_00_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_00_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_00_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_S_SCR_00_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_00_0_PR5_SHIFT)
#define GPIO_S_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_S_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_S_SCR_00_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_00_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_00_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_S_SCR_00_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_00_0_PR4_SHIFT)
#define GPIO_S_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_S_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_S_SCR_00_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_00_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_00_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_S_SCR_00_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_00_0_PR3_SHIFT)
#define GPIO_S_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_S_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_S_SCR_00_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_00_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_00_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_S_SCR_00_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_00_0_PR2_SHIFT)
#define GPIO_S_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_S_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_S_SCR_00_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_00_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_00_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_S_SCR_00_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_00_0_PR1_SHIFT)
#define GPIO_S_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_S_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_S_SCR_00_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_00_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_00_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_S_SCR_00_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_00_0_PR0_SHIFT)
#define GPIO_S_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_S_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_S_SCR_00_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_00_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_00_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_S_SCR_00_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_00_0_G7W_SHIFT)
#define GPIO_S_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_S_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_S_SCR_00_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_00_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_00_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_S_SCR_00_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_00_0_G6W_SHIFT)
#define GPIO_S_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_S_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_S_SCR_00_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_00_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_00_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_S_SCR_00_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_00_0_G5W_SHIFT)
#define GPIO_S_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_S_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_S_SCR_00_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_00_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_00_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_S_SCR_00_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_00_0_G4W_SHIFT)
#define GPIO_S_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_S_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_S_SCR_00_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_00_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_00_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_S_SCR_00_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_00_0_G3W_SHIFT)
#define GPIO_S_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_S_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_S_SCR_00_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_00_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_00_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_S_SCR_00_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_00_0_G2W_SHIFT)
#define GPIO_S_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_S_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_S_SCR_00_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_00_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_00_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_S_SCR_00_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_00_0_G1W_SHIFT)
#define GPIO_S_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_S_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_S_SCR_00_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_00_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_00_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_S_SCR_00_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_00_0_G0W_SHIFT)
#define GPIO_S_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_S_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_S_SCR_00_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_00_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_00_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_S_SCR_00_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_00_0_G7R_SHIFT)
#define GPIO_S_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_S_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_S_SCR_00_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_00_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_00_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_S_SCR_00_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_00_0_G6R_SHIFT)
#define GPIO_S_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_S_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_S_SCR_00_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_00_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_00_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_S_SCR_00_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_00_0_G5R_SHIFT)
#define GPIO_S_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_S_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_S_SCR_00_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_00_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_00_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_S_SCR_00_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_00_0_G4R_SHIFT)
#define GPIO_S_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_S_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_S_SCR_00_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_00_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_00_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_S_SCR_00_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_00_0_G3R_SHIFT)
#define GPIO_S_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_S_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_S_SCR_00_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_00_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_00_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_S_SCR_00_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_00_0_G2R_SHIFT)
#define GPIO_S_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_S_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_S_SCR_00_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_00_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_00_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_S_SCR_00_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_00_0_G1R_SHIFT)
#define GPIO_S_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_S_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_S_SCR_00_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_00_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_00_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_S_SCR_00_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_00_0_G0R_SHIFT)
#define GPIO_S_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_S_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_S_SCR_00_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_00_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_00_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_S_VM_01_0
#define GPIO_S_VM_01_0                  _MK_ADDR_CONST(0x30c8)
#define GPIO_S_VM_01_0_SECURE                   0x0
#define GPIO_S_VM_01_0_DUAL                     0x0
#define GPIO_S_VM_01_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_S_VM_01_0_WORD_COUNT                       0x1
#define GPIO_S_VM_01_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_S_VM_01_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_S_VM_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_S_VM_01_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_S_VM_01_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_S_VM_01_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_S_VM_01_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_01_0_VM1_SHIFT)
#define GPIO_S_VM_01_0_VM1_RANGE                        1:0
#define GPIO_S_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_S_VM_01_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_01_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_01_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_01_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_01_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_01_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_01_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_S_VM_01_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_01_0_VM2_SHIFT)
#define GPIO_S_VM_01_0_VM2_RANGE                        3:2
#define GPIO_S_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_S_VM_01_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_01_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_01_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_01_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_01_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_01_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_01_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_S_VM_01_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_01_0_VM3_SHIFT)
#define GPIO_S_VM_01_0_VM3_RANGE                        5:4
#define GPIO_S_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_S_VM_01_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_01_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_01_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_01_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_01_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_01_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_01_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_S_VM_01_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_01_0_VM4_SHIFT)
#define GPIO_S_VM_01_0_VM4_RANGE                        7:6
#define GPIO_S_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_S_VM_01_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_01_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_01_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_01_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_01_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_01_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_01_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_S_VM_01_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_01_0_VM5_SHIFT)
#define GPIO_S_VM_01_0_VM5_RANGE                        9:8
#define GPIO_S_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_S_VM_01_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_01_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_01_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_01_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_01_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_01_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_01_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_S_VM_01_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_01_0_VM6_SHIFT)
#define GPIO_S_VM_01_0_VM6_RANGE                        11:10
#define GPIO_S_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_S_VM_01_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_01_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_01_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_01_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_01_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_01_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_01_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_S_VM_01_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_01_0_VM7_SHIFT)
#define GPIO_S_VM_01_0_VM7_RANGE                        13:12
#define GPIO_S_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_S_VM_01_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_01_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_01_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_01_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_01_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_01_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_01_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_S_VM_01_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_01_0_VM8_SHIFT)
#define GPIO_S_VM_01_0_VM8_RANGE                        15:14
#define GPIO_S_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_S_VM_01_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_01_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_01_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_01_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_01_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_01_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_S_SCR_01_0
#define GPIO_S_SCR_01_0                 _MK_ADDR_CONST(0x30cc)
#define GPIO_S_SCR_01_0_SECURE                  0x0
#define GPIO_S_SCR_01_0_DUAL                    0x0
#define GPIO_S_SCR_01_0_SCR                     0
#define GPIO_S_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_S_SCR_01_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_S_SCR_01_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_S_SCR_01_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_S_SCR_01_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_S_SCR_01_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_S_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_S_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_S_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_S_SCR_01_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_01_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_01_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_S_SCR_01_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_S_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_S_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_S_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_S_SCR_01_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_01_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_01_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_S_SCR_01_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_S_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_S_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_S_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_S_SCR_01_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_01_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_01_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_S_SCR_01_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_S_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_S_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_S_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_S_SCR_01_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_S_SCR_01_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_01_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_S_SCR_01_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_01_0_PR7_SHIFT)
#define GPIO_S_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_S_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_S_SCR_01_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_01_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_01_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_S_SCR_01_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_01_0_PR6_SHIFT)
#define GPIO_S_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_S_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_S_SCR_01_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_01_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_01_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_S_SCR_01_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_01_0_PR5_SHIFT)
#define GPIO_S_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_S_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_S_SCR_01_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_01_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_01_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_S_SCR_01_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_01_0_PR4_SHIFT)
#define GPIO_S_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_S_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_S_SCR_01_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_01_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_01_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_S_SCR_01_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_01_0_PR3_SHIFT)
#define GPIO_S_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_S_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_S_SCR_01_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_01_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_01_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_S_SCR_01_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_01_0_PR2_SHIFT)
#define GPIO_S_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_S_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_S_SCR_01_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_01_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_01_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_S_SCR_01_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_01_0_PR1_SHIFT)
#define GPIO_S_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_S_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_S_SCR_01_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_01_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_01_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_S_SCR_01_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_01_0_PR0_SHIFT)
#define GPIO_S_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_S_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_S_SCR_01_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_01_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_01_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_S_SCR_01_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_01_0_G7W_SHIFT)
#define GPIO_S_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_S_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_S_SCR_01_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_01_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_01_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_S_SCR_01_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_01_0_G6W_SHIFT)
#define GPIO_S_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_S_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_S_SCR_01_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_01_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_01_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_S_SCR_01_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_01_0_G5W_SHIFT)
#define GPIO_S_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_S_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_S_SCR_01_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_01_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_01_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_S_SCR_01_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_01_0_G4W_SHIFT)
#define GPIO_S_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_S_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_S_SCR_01_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_01_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_01_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_S_SCR_01_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_01_0_G3W_SHIFT)
#define GPIO_S_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_S_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_S_SCR_01_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_01_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_01_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_S_SCR_01_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_01_0_G2W_SHIFT)
#define GPIO_S_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_S_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_S_SCR_01_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_01_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_01_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_S_SCR_01_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_01_0_G1W_SHIFT)
#define GPIO_S_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_S_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_S_SCR_01_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_01_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_01_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_S_SCR_01_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_01_0_G0W_SHIFT)
#define GPIO_S_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_S_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_S_SCR_01_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_01_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_01_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_S_SCR_01_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_01_0_G7R_SHIFT)
#define GPIO_S_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_S_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_S_SCR_01_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_01_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_01_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_S_SCR_01_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_01_0_G6R_SHIFT)
#define GPIO_S_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_S_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_S_SCR_01_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_01_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_01_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_S_SCR_01_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_01_0_G5R_SHIFT)
#define GPIO_S_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_S_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_S_SCR_01_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_01_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_01_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_S_SCR_01_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_01_0_G4R_SHIFT)
#define GPIO_S_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_S_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_S_SCR_01_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_01_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_01_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_S_SCR_01_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_01_0_G3R_SHIFT)
#define GPIO_S_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_S_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_S_SCR_01_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_01_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_01_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_S_SCR_01_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_01_0_G2R_SHIFT)
#define GPIO_S_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_S_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_S_SCR_01_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_01_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_01_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_S_SCR_01_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_01_0_G1R_SHIFT)
#define GPIO_S_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_S_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_S_SCR_01_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_01_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_01_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_S_SCR_01_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_01_0_G0R_SHIFT)
#define GPIO_S_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_S_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_S_SCR_01_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_01_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_01_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_S_VM_02_0
#define GPIO_S_VM_02_0                  _MK_ADDR_CONST(0x30d0)
#define GPIO_S_VM_02_0_SECURE                   0x0
#define GPIO_S_VM_02_0_DUAL                     0x0
#define GPIO_S_VM_02_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_S_VM_02_0_WORD_COUNT                       0x1
#define GPIO_S_VM_02_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_S_VM_02_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_S_VM_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_S_VM_02_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_S_VM_02_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_S_VM_02_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_S_VM_02_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_02_0_VM1_SHIFT)
#define GPIO_S_VM_02_0_VM1_RANGE                        1:0
#define GPIO_S_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_S_VM_02_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_02_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_02_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_02_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_02_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_02_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_02_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_S_VM_02_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_02_0_VM2_SHIFT)
#define GPIO_S_VM_02_0_VM2_RANGE                        3:2
#define GPIO_S_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_S_VM_02_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_02_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_02_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_02_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_02_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_02_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_02_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_S_VM_02_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_02_0_VM3_SHIFT)
#define GPIO_S_VM_02_0_VM3_RANGE                        5:4
#define GPIO_S_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_S_VM_02_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_02_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_02_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_02_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_02_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_02_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_02_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_S_VM_02_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_02_0_VM4_SHIFT)
#define GPIO_S_VM_02_0_VM4_RANGE                        7:6
#define GPIO_S_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_S_VM_02_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_02_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_02_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_02_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_02_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_02_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_02_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_S_VM_02_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_02_0_VM5_SHIFT)
#define GPIO_S_VM_02_0_VM5_RANGE                        9:8
#define GPIO_S_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_S_VM_02_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_02_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_02_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_02_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_02_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_02_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_02_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_S_VM_02_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_02_0_VM6_SHIFT)
#define GPIO_S_VM_02_0_VM6_RANGE                        11:10
#define GPIO_S_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_S_VM_02_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_02_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_02_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_02_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_02_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_02_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_02_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_S_VM_02_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_02_0_VM7_SHIFT)
#define GPIO_S_VM_02_0_VM7_RANGE                        13:12
#define GPIO_S_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_S_VM_02_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_02_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_02_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_02_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_02_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_02_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_02_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_S_VM_02_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_02_0_VM8_SHIFT)
#define GPIO_S_VM_02_0_VM8_RANGE                        15:14
#define GPIO_S_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_S_VM_02_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_02_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_02_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_02_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_02_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_02_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_S_SCR_02_0
#define GPIO_S_SCR_02_0                 _MK_ADDR_CONST(0x30d4)
#define GPIO_S_SCR_02_0_SECURE                  0x0
#define GPIO_S_SCR_02_0_DUAL                    0x0
#define GPIO_S_SCR_02_0_SCR                     0
#define GPIO_S_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_S_SCR_02_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_S_SCR_02_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_S_SCR_02_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_S_SCR_02_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_S_SCR_02_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_S_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_S_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_S_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_S_SCR_02_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_02_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_02_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_S_SCR_02_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_S_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_S_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_S_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_S_SCR_02_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_02_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_02_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_S_SCR_02_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_S_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_S_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_S_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_S_SCR_02_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_02_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_02_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_S_SCR_02_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_S_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_S_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_S_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_S_SCR_02_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_S_SCR_02_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_02_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_S_SCR_02_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_02_0_PR7_SHIFT)
#define GPIO_S_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_S_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_S_SCR_02_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_02_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_02_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_S_SCR_02_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_02_0_PR6_SHIFT)
#define GPIO_S_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_S_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_S_SCR_02_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_02_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_02_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_S_SCR_02_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_02_0_PR5_SHIFT)
#define GPIO_S_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_S_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_S_SCR_02_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_02_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_02_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_S_SCR_02_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_02_0_PR4_SHIFT)
#define GPIO_S_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_S_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_S_SCR_02_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_02_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_02_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_S_SCR_02_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_02_0_PR3_SHIFT)
#define GPIO_S_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_S_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_S_SCR_02_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_02_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_02_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_S_SCR_02_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_02_0_PR2_SHIFT)
#define GPIO_S_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_S_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_S_SCR_02_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_02_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_02_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_S_SCR_02_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_02_0_PR1_SHIFT)
#define GPIO_S_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_S_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_S_SCR_02_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_02_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_02_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_S_SCR_02_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_02_0_PR0_SHIFT)
#define GPIO_S_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_S_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_S_SCR_02_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_02_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_02_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_S_SCR_02_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_02_0_G7W_SHIFT)
#define GPIO_S_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_S_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_S_SCR_02_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_02_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_02_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_S_SCR_02_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_02_0_G6W_SHIFT)
#define GPIO_S_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_S_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_S_SCR_02_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_02_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_02_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_S_SCR_02_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_02_0_G5W_SHIFT)
#define GPIO_S_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_S_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_S_SCR_02_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_02_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_02_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_S_SCR_02_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_02_0_G4W_SHIFT)
#define GPIO_S_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_S_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_S_SCR_02_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_02_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_02_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_S_SCR_02_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_02_0_G3W_SHIFT)
#define GPIO_S_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_S_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_S_SCR_02_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_02_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_02_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_S_SCR_02_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_02_0_G2W_SHIFT)
#define GPIO_S_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_S_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_S_SCR_02_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_02_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_02_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_S_SCR_02_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_02_0_G1W_SHIFT)
#define GPIO_S_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_S_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_S_SCR_02_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_02_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_02_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_S_SCR_02_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_02_0_G0W_SHIFT)
#define GPIO_S_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_S_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_S_SCR_02_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_02_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_02_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_S_SCR_02_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_02_0_G7R_SHIFT)
#define GPIO_S_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_S_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_S_SCR_02_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_02_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_02_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_S_SCR_02_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_02_0_G6R_SHIFT)
#define GPIO_S_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_S_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_S_SCR_02_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_02_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_02_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_S_SCR_02_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_02_0_G5R_SHIFT)
#define GPIO_S_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_S_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_S_SCR_02_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_02_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_02_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_S_SCR_02_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_02_0_G4R_SHIFT)
#define GPIO_S_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_S_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_S_SCR_02_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_02_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_02_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_S_SCR_02_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_02_0_G3R_SHIFT)
#define GPIO_S_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_S_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_S_SCR_02_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_02_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_02_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_S_SCR_02_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_02_0_G2R_SHIFT)
#define GPIO_S_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_S_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_S_SCR_02_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_02_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_02_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_S_SCR_02_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_02_0_G1R_SHIFT)
#define GPIO_S_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_S_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_S_SCR_02_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_02_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_02_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_S_SCR_02_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_02_0_G0R_SHIFT)
#define GPIO_S_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_S_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_S_SCR_02_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_02_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_02_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_S_VM_03_0
#define GPIO_S_VM_03_0                  _MK_ADDR_CONST(0x30d8)
#define GPIO_S_VM_03_0_SECURE                   0x0
#define GPIO_S_VM_03_0_DUAL                     0x0
#define GPIO_S_VM_03_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_S_VM_03_0_WORD_COUNT                       0x1
#define GPIO_S_VM_03_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_S_VM_03_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_S_VM_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_S_VM_03_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_S_VM_03_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_S_VM_03_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_S_VM_03_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_03_0_VM1_SHIFT)
#define GPIO_S_VM_03_0_VM1_RANGE                        1:0
#define GPIO_S_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_S_VM_03_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_03_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_03_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_03_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_03_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_03_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_03_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_S_VM_03_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_03_0_VM2_SHIFT)
#define GPIO_S_VM_03_0_VM2_RANGE                        3:2
#define GPIO_S_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_S_VM_03_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_03_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_03_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_03_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_03_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_03_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_03_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_S_VM_03_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_03_0_VM3_SHIFT)
#define GPIO_S_VM_03_0_VM3_RANGE                        5:4
#define GPIO_S_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_S_VM_03_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_03_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_03_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_03_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_03_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_03_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_03_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_S_VM_03_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_03_0_VM4_SHIFT)
#define GPIO_S_VM_03_0_VM4_RANGE                        7:6
#define GPIO_S_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_S_VM_03_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_03_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_03_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_03_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_03_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_03_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_03_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_S_VM_03_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_03_0_VM5_SHIFT)
#define GPIO_S_VM_03_0_VM5_RANGE                        9:8
#define GPIO_S_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_S_VM_03_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_03_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_03_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_03_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_03_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_03_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_03_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_S_VM_03_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_03_0_VM6_SHIFT)
#define GPIO_S_VM_03_0_VM6_RANGE                        11:10
#define GPIO_S_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_S_VM_03_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_03_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_03_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_03_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_03_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_03_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_03_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_S_VM_03_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_03_0_VM7_SHIFT)
#define GPIO_S_VM_03_0_VM7_RANGE                        13:12
#define GPIO_S_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_S_VM_03_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_03_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_03_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_03_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_03_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_03_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_03_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_S_VM_03_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_03_0_VM8_SHIFT)
#define GPIO_S_VM_03_0_VM8_RANGE                        15:14
#define GPIO_S_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_S_VM_03_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_03_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_03_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_03_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_03_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_03_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_S_SCR_03_0
#define GPIO_S_SCR_03_0                 _MK_ADDR_CONST(0x30dc)
#define GPIO_S_SCR_03_0_SECURE                  0x0
#define GPIO_S_SCR_03_0_DUAL                    0x0
#define GPIO_S_SCR_03_0_SCR                     0
#define GPIO_S_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_S_SCR_03_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_S_SCR_03_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_S_SCR_03_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_S_SCR_03_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_S_SCR_03_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_S_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_S_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_S_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_S_SCR_03_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_03_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_03_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_S_SCR_03_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_S_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_S_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_S_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_S_SCR_03_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_03_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_03_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_S_SCR_03_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_S_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_S_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_S_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_S_SCR_03_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_03_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_03_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_S_SCR_03_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_S_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_S_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_S_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_S_SCR_03_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_S_SCR_03_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_03_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_S_SCR_03_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_03_0_PR7_SHIFT)
#define GPIO_S_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_S_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_S_SCR_03_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_03_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_03_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_S_SCR_03_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_03_0_PR6_SHIFT)
#define GPIO_S_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_S_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_S_SCR_03_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_03_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_03_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_S_SCR_03_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_03_0_PR5_SHIFT)
#define GPIO_S_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_S_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_S_SCR_03_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_03_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_03_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_S_SCR_03_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_03_0_PR4_SHIFT)
#define GPIO_S_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_S_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_S_SCR_03_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_03_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_03_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_S_SCR_03_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_03_0_PR3_SHIFT)
#define GPIO_S_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_S_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_S_SCR_03_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_03_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_03_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_S_SCR_03_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_03_0_PR2_SHIFT)
#define GPIO_S_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_S_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_S_SCR_03_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_03_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_03_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_S_SCR_03_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_03_0_PR1_SHIFT)
#define GPIO_S_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_S_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_S_SCR_03_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_03_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_03_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_S_SCR_03_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_03_0_PR0_SHIFT)
#define GPIO_S_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_S_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_S_SCR_03_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_03_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_03_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_S_SCR_03_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_03_0_G7W_SHIFT)
#define GPIO_S_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_S_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_S_SCR_03_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_03_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_03_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_S_SCR_03_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_03_0_G6W_SHIFT)
#define GPIO_S_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_S_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_S_SCR_03_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_03_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_03_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_S_SCR_03_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_03_0_G5W_SHIFT)
#define GPIO_S_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_S_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_S_SCR_03_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_03_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_03_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_S_SCR_03_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_03_0_G4W_SHIFT)
#define GPIO_S_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_S_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_S_SCR_03_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_03_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_03_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_S_SCR_03_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_03_0_G3W_SHIFT)
#define GPIO_S_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_S_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_S_SCR_03_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_03_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_03_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_S_SCR_03_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_03_0_G2W_SHIFT)
#define GPIO_S_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_S_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_S_SCR_03_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_03_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_03_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_S_SCR_03_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_03_0_G1W_SHIFT)
#define GPIO_S_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_S_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_S_SCR_03_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_03_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_03_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_S_SCR_03_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_03_0_G0W_SHIFT)
#define GPIO_S_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_S_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_S_SCR_03_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_03_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_03_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_S_SCR_03_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_03_0_G7R_SHIFT)
#define GPIO_S_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_S_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_S_SCR_03_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_03_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_03_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_S_SCR_03_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_03_0_G6R_SHIFT)
#define GPIO_S_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_S_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_S_SCR_03_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_03_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_03_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_S_SCR_03_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_03_0_G5R_SHIFT)
#define GPIO_S_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_S_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_S_SCR_03_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_03_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_03_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_S_SCR_03_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_03_0_G4R_SHIFT)
#define GPIO_S_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_S_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_S_SCR_03_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_03_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_03_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_S_SCR_03_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_03_0_G3R_SHIFT)
#define GPIO_S_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_S_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_S_SCR_03_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_03_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_03_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_S_SCR_03_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_03_0_G2R_SHIFT)
#define GPIO_S_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_S_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_S_SCR_03_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_03_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_03_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_S_SCR_03_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_03_0_G1R_SHIFT)
#define GPIO_S_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_S_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_S_SCR_03_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_03_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_03_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_S_SCR_03_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_03_0_G0R_SHIFT)
#define GPIO_S_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_S_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_S_SCR_03_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_03_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_03_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_S_VM_04_0
#define GPIO_S_VM_04_0                  _MK_ADDR_CONST(0x30e0)
#define GPIO_S_VM_04_0_SECURE                   0x0
#define GPIO_S_VM_04_0_DUAL                     0x0
#define GPIO_S_VM_04_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_S_VM_04_0_WORD_COUNT                       0x1
#define GPIO_S_VM_04_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_S_VM_04_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_S_VM_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_S_VM_04_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_S_VM_04_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_S_VM_04_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_S_VM_04_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_04_0_VM1_SHIFT)
#define GPIO_S_VM_04_0_VM1_RANGE                        1:0
#define GPIO_S_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_S_VM_04_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_04_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_04_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_04_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_04_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_04_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_04_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_S_VM_04_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_04_0_VM2_SHIFT)
#define GPIO_S_VM_04_0_VM2_RANGE                        3:2
#define GPIO_S_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_S_VM_04_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_04_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_04_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_04_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_04_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_04_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_04_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_S_VM_04_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_04_0_VM3_SHIFT)
#define GPIO_S_VM_04_0_VM3_RANGE                        5:4
#define GPIO_S_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_S_VM_04_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_04_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_04_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_04_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_04_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_04_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_04_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_S_VM_04_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_04_0_VM4_SHIFT)
#define GPIO_S_VM_04_0_VM4_RANGE                        7:6
#define GPIO_S_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_S_VM_04_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_04_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_04_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_04_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_04_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_04_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_04_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_S_VM_04_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_04_0_VM5_SHIFT)
#define GPIO_S_VM_04_0_VM5_RANGE                        9:8
#define GPIO_S_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_S_VM_04_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_04_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_04_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_04_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_04_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_04_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_04_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_S_VM_04_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_04_0_VM6_SHIFT)
#define GPIO_S_VM_04_0_VM6_RANGE                        11:10
#define GPIO_S_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_S_VM_04_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_04_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_04_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_04_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_04_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_04_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_04_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_S_VM_04_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_04_0_VM7_SHIFT)
#define GPIO_S_VM_04_0_VM7_RANGE                        13:12
#define GPIO_S_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_S_VM_04_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_04_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_04_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_04_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_04_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_04_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_04_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_S_VM_04_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_04_0_VM8_SHIFT)
#define GPIO_S_VM_04_0_VM8_RANGE                        15:14
#define GPIO_S_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_S_VM_04_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_04_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_04_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_04_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_04_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_04_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_S_SCR_04_0
#define GPIO_S_SCR_04_0                 _MK_ADDR_CONST(0x30e4)
#define GPIO_S_SCR_04_0_SECURE                  0x0
#define GPIO_S_SCR_04_0_DUAL                    0x0
#define GPIO_S_SCR_04_0_SCR                     0
#define GPIO_S_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_S_SCR_04_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_S_SCR_04_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_S_SCR_04_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_S_SCR_04_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_S_SCR_04_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_S_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_S_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_S_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_S_SCR_04_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_04_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_04_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_S_SCR_04_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_S_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_S_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_S_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_S_SCR_04_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_04_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_04_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_S_SCR_04_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_S_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_S_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_S_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_S_SCR_04_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_04_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_04_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_S_SCR_04_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_S_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_S_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_S_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_S_SCR_04_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_S_SCR_04_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_04_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_S_SCR_04_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_04_0_PR7_SHIFT)
#define GPIO_S_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_S_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_S_SCR_04_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_04_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_04_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_S_SCR_04_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_04_0_PR6_SHIFT)
#define GPIO_S_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_S_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_S_SCR_04_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_04_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_04_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_S_SCR_04_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_04_0_PR5_SHIFT)
#define GPIO_S_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_S_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_S_SCR_04_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_04_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_04_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_S_SCR_04_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_04_0_PR4_SHIFT)
#define GPIO_S_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_S_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_S_SCR_04_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_04_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_04_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_S_SCR_04_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_04_0_PR3_SHIFT)
#define GPIO_S_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_S_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_S_SCR_04_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_04_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_04_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_S_SCR_04_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_04_0_PR2_SHIFT)
#define GPIO_S_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_S_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_S_SCR_04_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_04_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_04_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_S_SCR_04_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_04_0_PR1_SHIFT)
#define GPIO_S_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_S_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_S_SCR_04_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_04_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_04_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_S_SCR_04_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_04_0_PR0_SHIFT)
#define GPIO_S_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_S_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_S_SCR_04_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_04_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_04_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_S_SCR_04_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_04_0_G7W_SHIFT)
#define GPIO_S_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_S_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_S_SCR_04_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_04_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_04_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_S_SCR_04_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_04_0_G6W_SHIFT)
#define GPIO_S_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_S_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_S_SCR_04_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_04_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_04_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_S_SCR_04_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_04_0_G5W_SHIFT)
#define GPIO_S_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_S_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_S_SCR_04_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_04_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_04_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_S_SCR_04_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_04_0_G4W_SHIFT)
#define GPIO_S_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_S_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_S_SCR_04_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_04_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_04_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_S_SCR_04_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_04_0_G3W_SHIFT)
#define GPIO_S_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_S_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_S_SCR_04_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_04_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_04_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_S_SCR_04_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_04_0_G2W_SHIFT)
#define GPIO_S_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_S_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_S_SCR_04_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_04_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_04_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_S_SCR_04_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_04_0_G1W_SHIFT)
#define GPIO_S_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_S_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_S_SCR_04_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_04_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_04_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_S_SCR_04_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_04_0_G0W_SHIFT)
#define GPIO_S_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_S_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_S_SCR_04_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_04_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_04_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_S_SCR_04_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_04_0_G7R_SHIFT)
#define GPIO_S_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_S_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_S_SCR_04_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_04_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_04_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_S_SCR_04_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_04_0_G6R_SHIFT)
#define GPIO_S_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_S_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_S_SCR_04_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_04_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_04_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_S_SCR_04_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_04_0_G5R_SHIFT)
#define GPIO_S_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_S_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_S_SCR_04_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_04_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_04_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_S_SCR_04_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_04_0_G4R_SHIFT)
#define GPIO_S_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_S_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_S_SCR_04_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_04_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_04_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_S_SCR_04_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_04_0_G3R_SHIFT)
#define GPIO_S_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_S_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_S_SCR_04_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_04_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_04_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_S_SCR_04_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_04_0_G2R_SHIFT)
#define GPIO_S_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_S_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_S_SCR_04_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_04_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_04_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_S_SCR_04_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_04_0_G1R_SHIFT)
#define GPIO_S_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_S_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_S_SCR_04_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_04_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_04_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_S_SCR_04_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_04_0_G0R_SHIFT)
#define GPIO_S_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_S_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_S_SCR_04_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_04_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_04_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_S_VM_05_0
#define GPIO_S_VM_05_0                  _MK_ADDR_CONST(0x30e8)
#define GPIO_S_VM_05_0_SECURE                   0x0
#define GPIO_S_VM_05_0_DUAL                     0x0
#define GPIO_S_VM_05_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_S_VM_05_0_WORD_COUNT                       0x1
#define GPIO_S_VM_05_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_S_VM_05_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_S_VM_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_S_VM_05_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_S_VM_05_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_S_VM_05_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_S_VM_05_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_05_0_VM1_SHIFT)
#define GPIO_S_VM_05_0_VM1_RANGE                        1:0
#define GPIO_S_VM_05_0_VM1_WOFFSET                      0x0
#define GPIO_S_VM_05_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_05_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_05_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_05_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_05_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_05_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_05_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_S_VM_05_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_05_0_VM2_SHIFT)
#define GPIO_S_VM_05_0_VM2_RANGE                        3:2
#define GPIO_S_VM_05_0_VM2_WOFFSET                      0x0
#define GPIO_S_VM_05_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_05_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_05_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_05_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_05_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_05_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_05_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_S_VM_05_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_05_0_VM3_SHIFT)
#define GPIO_S_VM_05_0_VM3_RANGE                        5:4
#define GPIO_S_VM_05_0_VM3_WOFFSET                      0x0
#define GPIO_S_VM_05_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_05_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_05_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_05_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_05_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_05_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_05_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_S_VM_05_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_05_0_VM4_SHIFT)
#define GPIO_S_VM_05_0_VM4_RANGE                        7:6
#define GPIO_S_VM_05_0_VM4_WOFFSET                      0x0
#define GPIO_S_VM_05_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_05_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_05_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_05_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_05_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_05_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_05_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_S_VM_05_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_05_0_VM5_SHIFT)
#define GPIO_S_VM_05_0_VM5_RANGE                        9:8
#define GPIO_S_VM_05_0_VM5_WOFFSET                      0x0
#define GPIO_S_VM_05_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_05_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_05_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_05_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_05_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_05_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_05_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_S_VM_05_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_05_0_VM6_SHIFT)
#define GPIO_S_VM_05_0_VM6_RANGE                        11:10
#define GPIO_S_VM_05_0_VM6_WOFFSET                      0x0
#define GPIO_S_VM_05_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_05_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_05_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_05_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_05_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_05_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_05_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_S_VM_05_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_05_0_VM7_SHIFT)
#define GPIO_S_VM_05_0_VM7_RANGE                        13:12
#define GPIO_S_VM_05_0_VM7_WOFFSET                      0x0
#define GPIO_S_VM_05_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_05_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_05_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_05_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_05_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_05_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_05_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_S_VM_05_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_05_0_VM8_SHIFT)
#define GPIO_S_VM_05_0_VM8_RANGE                        15:14
#define GPIO_S_VM_05_0_VM8_WOFFSET                      0x0
#define GPIO_S_VM_05_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_05_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_05_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_05_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_05_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_05_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_S_SCR_05_0
#define GPIO_S_SCR_05_0                 _MK_ADDR_CONST(0x30ec)
#define GPIO_S_SCR_05_0_SECURE                  0x0
#define GPIO_S_SCR_05_0_DUAL                    0x0
#define GPIO_S_SCR_05_0_SCR                     0
#define GPIO_S_SCR_05_0_WORD_COUNT                      0x1
#define GPIO_S_SCR_05_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_S_SCR_05_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_S_SCR_05_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_S_SCR_05_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_S_SCR_05_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_S_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_S_SCR_05_0_SEC_LCK_RANGE                   29:29
#define GPIO_S_SCR_05_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_S_SCR_05_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_05_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_05_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_S_SCR_05_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_S_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_S_SCR_05_0_SEC_WEN_RANGE                   28:28
#define GPIO_S_SCR_05_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_S_SCR_05_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_05_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_05_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_S_SCR_05_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_S_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_S_SCR_05_0_SEC_REN_RANGE                   27:27
#define GPIO_S_SCR_05_0_SEC_REN_WOFFSET                 0x0
#define GPIO_S_SCR_05_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_05_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_05_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_S_SCR_05_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_S_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_S_SCR_05_0_SEC_OWNER_RANGE                 26:24
#define GPIO_S_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_S_SCR_05_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_S_SCR_05_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_05_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_S_SCR_05_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_05_0_PR7_SHIFT)
#define GPIO_S_SCR_05_0_PR7_RANGE                       23:23
#define GPIO_S_SCR_05_0_PR7_WOFFSET                     0x0
#define GPIO_S_SCR_05_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_05_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_05_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_S_SCR_05_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_05_0_PR6_SHIFT)
#define GPIO_S_SCR_05_0_PR6_RANGE                       22:22
#define GPIO_S_SCR_05_0_PR6_WOFFSET                     0x0
#define GPIO_S_SCR_05_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_05_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_05_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_S_SCR_05_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_05_0_PR5_SHIFT)
#define GPIO_S_SCR_05_0_PR5_RANGE                       21:21
#define GPIO_S_SCR_05_0_PR5_WOFFSET                     0x0
#define GPIO_S_SCR_05_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_05_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_05_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_S_SCR_05_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_05_0_PR4_SHIFT)
#define GPIO_S_SCR_05_0_PR4_RANGE                       20:20
#define GPIO_S_SCR_05_0_PR4_WOFFSET                     0x0
#define GPIO_S_SCR_05_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_05_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_05_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_S_SCR_05_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_05_0_PR3_SHIFT)
#define GPIO_S_SCR_05_0_PR3_RANGE                       19:19
#define GPIO_S_SCR_05_0_PR3_WOFFSET                     0x0
#define GPIO_S_SCR_05_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_05_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_05_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_S_SCR_05_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_05_0_PR2_SHIFT)
#define GPIO_S_SCR_05_0_PR2_RANGE                       18:18
#define GPIO_S_SCR_05_0_PR2_WOFFSET                     0x0
#define GPIO_S_SCR_05_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_05_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_05_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_S_SCR_05_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_05_0_PR1_SHIFT)
#define GPIO_S_SCR_05_0_PR1_RANGE                       17:17
#define GPIO_S_SCR_05_0_PR1_WOFFSET                     0x0
#define GPIO_S_SCR_05_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_05_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_05_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_S_SCR_05_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_05_0_PR0_SHIFT)
#define GPIO_S_SCR_05_0_PR0_RANGE                       16:16
#define GPIO_S_SCR_05_0_PR0_WOFFSET                     0x0
#define GPIO_S_SCR_05_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_05_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_05_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_S_SCR_05_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_05_0_G7W_SHIFT)
#define GPIO_S_SCR_05_0_G7W_RANGE                       15:15
#define GPIO_S_SCR_05_0_G7W_WOFFSET                     0x0
#define GPIO_S_SCR_05_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_05_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_05_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_S_SCR_05_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_05_0_G6W_SHIFT)
#define GPIO_S_SCR_05_0_G6W_RANGE                       14:14
#define GPIO_S_SCR_05_0_G6W_WOFFSET                     0x0
#define GPIO_S_SCR_05_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_05_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_05_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_S_SCR_05_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_05_0_G5W_SHIFT)
#define GPIO_S_SCR_05_0_G5W_RANGE                       13:13
#define GPIO_S_SCR_05_0_G5W_WOFFSET                     0x0
#define GPIO_S_SCR_05_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_05_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_05_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_S_SCR_05_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_05_0_G4W_SHIFT)
#define GPIO_S_SCR_05_0_G4W_RANGE                       12:12
#define GPIO_S_SCR_05_0_G4W_WOFFSET                     0x0
#define GPIO_S_SCR_05_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_05_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_05_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_S_SCR_05_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_05_0_G3W_SHIFT)
#define GPIO_S_SCR_05_0_G3W_RANGE                       11:11
#define GPIO_S_SCR_05_0_G3W_WOFFSET                     0x0
#define GPIO_S_SCR_05_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_05_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_05_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_S_SCR_05_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_05_0_G2W_SHIFT)
#define GPIO_S_SCR_05_0_G2W_RANGE                       10:10
#define GPIO_S_SCR_05_0_G2W_WOFFSET                     0x0
#define GPIO_S_SCR_05_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_05_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_05_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_S_SCR_05_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_05_0_G1W_SHIFT)
#define GPIO_S_SCR_05_0_G1W_RANGE                       9:9
#define GPIO_S_SCR_05_0_G1W_WOFFSET                     0x0
#define GPIO_S_SCR_05_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_05_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_05_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_S_SCR_05_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_05_0_G0W_SHIFT)
#define GPIO_S_SCR_05_0_G0W_RANGE                       8:8
#define GPIO_S_SCR_05_0_G0W_WOFFSET                     0x0
#define GPIO_S_SCR_05_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_05_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_05_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_S_SCR_05_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_05_0_G7R_SHIFT)
#define GPIO_S_SCR_05_0_G7R_RANGE                       7:7
#define GPIO_S_SCR_05_0_G7R_WOFFSET                     0x0
#define GPIO_S_SCR_05_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_05_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_05_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_S_SCR_05_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_05_0_G6R_SHIFT)
#define GPIO_S_SCR_05_0_G6R_RANGE                       6:6
#define GPIO_S_SCR_05_0_G6R_WOFFSET                     0x0
#define GPIO_S_SCR_05_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_05_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_05_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_S_SCR_05_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_05_0_G5R_SHIFT)
#define GPIO_S_SCR_05_0_G5R_RANGE                       5:5
#define GPIO_S_SCR_05_0_G5R_WOFFSET                     0x0
#define GPIO_S_SCR_05_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_05_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_05_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_S_SCR_05_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_05_0_G4R_SHIFT)
#define GPIO_S_SCR_05_0_G4R_RANGE                       4:4
#define GPIO_S_SCR_05_0_G4R_WOFFSET                     0x0
#define GPIO_S_SCR_05_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_05_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_05_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_S_SCR_05_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_05_0_G3R_SHIFT)
#define GPIO_S_SCR_05_0_G3R_RANGE                       3:3
#define GPIO_S_SCR_05_0_G3R_WOFFSET                     0x0
#define GPIO_S_SCR_05_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_05_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_05_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_S_SCR_05_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_05_0_G2R_SHIFT)
#define GPIO_S_SCR_05_0_G2R_RANGE                       2:2
#define GPIO_S_SCR_05_0_G2R_WOFFSET                     0x0
#define GPIO_S_SCR_05_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_05_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_05_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_S_SCR_05_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_05_0_G1R_SHIFT)
#define GPIO_S_SCR_05_0_G1R_RANGE                       1:1
#define GPIO_S_SCR_05_0_G1R_WOFFSET                     0x0
#define GPIO_S_SCR_05_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_05_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_05_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_S_SCR_05_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_05_0_G0R_SHIFT)
#define GPIO_S_SCR_05_0_G0R_RANGE                       0:0
#define GPIO_S_SCR_05_0_G0R_WOFFSET                     0x0
#define GPIO_S_SCR_05_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_05_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_05_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_S_VM_06_0
#define GPIO_S_VM_06_0                  _MK_ADDR_CONST(0x30f0)
#define GPIO_S_VM_06_0_SECURE                   0x0
#define GPIO_S_VM_06_0_DUAL                     0x0
#define GPIO_S_VM_06_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_S_VM_06_0_WORD_COUNT                       0x1
#define GPIO_S_VM_06_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_S_VM_06_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_S_VM_06_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_06_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_S_VM_06_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_S_VM_06_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_S_VM_06_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_S_VM_06_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_06_0_VM1_SHIFT)
#define GPIO_S_VM_06_0_VM1_RANGE                        1:0
#define GPIO_S_VM_06_0_VM1_WOFFSET                      0x0
#define GPIO_S_VM_06_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_06_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_06_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_06_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_06_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_06_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_06_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_S_VM_06_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_06_0_VM2_SHIFT)
#define GPIO_S_VM_06_0_VM2_RANGE                        3:2
#define GPIO_S_VM_06_0_VM2_WOFFSET                      0x0
#define GPIO_S_VM_06_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_06_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_06_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_06_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_06_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_06_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_06_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_S_VM_06_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_06_0_VM3_SHIFT)
#define GPIO_S_VM_06_0_VM3_RANGE                        5:4
#define GPIO_S_VM_06_0_VM3_WOFFSET                      0x0
#define GPIO_S_VM_06_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_06_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_06_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_06_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_06_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_06_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_06_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_S_VM_06_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_06_0_VM4_SHIFT)
#define GPIO_S_VM_06_0_VM4_RANGE                        7:6
#define GPIO_S_VM_06_0_VM4_WOFFSET                      0x0
#define GPIO_S_VM_06_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_06_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_06_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_06_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_06_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_06_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_06_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_S_VM_06_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_06_0_VM5_SHIFT)
#define GPIO_S_VM_06_0_VM5_RANGE                        9:8
#define GPIO_S_VM_06_0_VM5_WOFFSET                      0x0
#define GPIO_S_VM_06_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_06_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_06_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_06_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_06_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_06_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_06_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_S_VM_06_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_06_0_VM6_SHIFT)
#define GPIO_S_VM_06_0_VM6_RANGE                        11:10
#define GPIO_S_VM_06_0_VM6_WOFFSET                      0x0
#define GPIO_S_VM_06_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_06_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_06_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_06_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_06_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_06_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_06_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_S_VM_06_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_06_0_VM7_SHIFT)
#define GPIO_S_VM_06_0_VM7_RANGE                        13:12
#define GPIO_S_VM_06_0_VM7_WOFFSET                      0x0
#define GPIO_S_VM_06_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_06_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_06_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_06_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_06_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_06_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_06_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_S_VM_06_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_06_0_VM8_SHIFT)
#define GPIO_S_VM_06_0_VM8_RANGE                        15:14
#define GPIO_S_VM_06_0_VM8_WOFFSET                      0x0
#define GPIO_S_VM_06_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_06_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_06_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_06_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_06_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_06_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_S_SCR_06_0
#define GPIO_S_SCR_06_0                 _MK_ADDR_CONST(0x30f4)
#define GPIO_S_SCR_06_0_SECURE                  0x0
#define GPIO_S_SCR_06_0_DUAL                    0x0
#define GPIO_S_SCR_06_0_SCR                     0
#define GPIO_S_SCR_06_0_WORD_COUNT                      0x1
#define GPIO_S_SCR_06_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_S_SCR_06_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_S_SCR_06_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_S_SCR_06_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_S_SCR_06_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_S_SCR_06_0_SEC_LCK_SHIFT)
#define GPIO_S_SCR_06_0_SEC_LCK_RANGE                   29:29
#define GPIO_S_SCR_06_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_S_SCR_06_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_06_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_06_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_S_SCR_06_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_S_SCR_06_0_SEC_WEN_SHIFT)
#define GPIO_S_SCR_06_0_SEC_WEN_RANGE                   28:28
#define GPIO_S_SCR_06_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_S_SCR_06_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_06_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_06_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_S_SCR_06_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_S_SCR_06_0_SEC_REN_SHIFT)
#define GPIO_S_SCR_06_0_SEC_REN_RANGE                   27:27
#define GPIO_S_SCR_06_0_SEC_REN_WOFFSET                 0x0
#define GPIO_S_SCR_06_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_06_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_06_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_S_SCR_06_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_S_SCR_06_0_SEC_OWNER_SHIFT)
#define GPIO_S_SCR_06_0_SEC_OWNER_RANGE                 26:24
#define GPIO_S_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_S_SCR_06_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_S_SCR_06_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_06_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_S_SCR_06_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_06_0_PR7_SHIFT)
#define GPIO_S_SCR_06_0_PR7_RANGE                       23:23
#define GPIO_S_SCR_06_0_PR7_WOFFSET                     0x0
#define GPIO_S_SCR_06_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_06_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_06_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_S_SCR_06_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_06_0_PR6_SHIFT)
#define GPIO_S_SCR_06_0_PR6_RANGE                       22:22
#define GPIO_S_SCR_06_0_PR6_WOFFSET                     0x0
#define GPIO_S_SCR_06_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_06_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_06_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_S_SCR_06_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_06_0_PR5_SHIFT)
#define GPIO_S_SCR_06_0_PR5_RANGE                       21:21
#define GPIO_S_SCR_06_0_PR5_WOFFSET                     0x0
#define GPIO_S_SCR_06_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_06_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_06_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_S_SCR_06_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_06_0_PR4_SHIFT)
#define GPIO_S_SCR_06_0_PR4_RANGE                       20:20
#define GPIO_S_SCR_06_0_PR4_WOFFSET                     0x0
#define GPIO_S_SCR_06_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_06_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_06_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_S_SCR_06_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_06_0_PR3_SHIFT)
#define GPIO_S_SCR_06_0_PR3_RANGE                       19:19
#define GPIO_S_SCR_06_0_PR3_WOFFSET                     0x0
#define GPIO_S_SCR_06_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_06_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_06_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_S_SCR_06_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_06_0_PR2_SHIFT)
#define GPIO_S_SCR_06_0_PR2_RANGE                       18:18
#define GPIO_S_SCR_06_0_PR2_WOFFSET                     0x0
#define GPIO_S_SCR_06_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_06_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_06_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_S_SCR_06_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_06_0_PR1_SHIFT)
#define GPIO_S_SCR_06_0_PR1_RANGE                       17:17
#define GPIO_S_SCR_06_0_PR1_WOFFSET                     0x0
#define GPIO_S_SCR_06_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_06_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_06_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_S_SCR_06_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_06_0_PR0_SHIFT)
#define GPIO_S_SCR_06_0_PR0_RANGE                       16:16
#define GPIO_S_SCR_06_0_PR0_WOFFSET                     0x0
#define GPIO_S_SCR_06_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_06_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_06_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_S_SCR_06_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_06_0_G7W_SHIFT)
#define GPIO_S_SCR_06_0_G7W_RANGE                       15:15
#define GPIO_S_SCR_06_0_G7W_WOFFSET                     0x0
#define GPIO_S_SCR_06_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_06_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_06_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_S_SCR_06_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_06_0_G6W_SHIFT)
#define GPIO_S_SCR_06_0_G6W_RANGE                       14:14
#define GPIO_S_SCR_06_0_G6W_WOFFSET                     0x0
#define GPIO_S_SCR_06_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_06_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_06_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_S_SCR_06_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_06_0_G5W_SHIFT)
#define GPIO_S_SCR_06_0_G5W_RANGE                       13:13
#define GPIO_S_SCR_06_0_G5W_WOFFSET                     0x0
#define GPIO_S_SCR_06_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_06_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_06_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_S_SCR_06_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_06_0_G4W_SHIFT)
#define GPIO_S_SCR_06_0_G4W_RANGE                       12:12
#define GPIO_S_SCR_06_0_G4W_WOFFSET                     0x0
#define GPIO_S_SCR_06_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_06_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_06_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_S_SCR_06_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_06_0_G3W_SHIFT)
#define GPIO_S_SCR_06_0_G3W_RANGE                       11:11
#define GPIO_S_SCR_06_0_G3W_WOFFSET                     0x0
#define GPIO_S_SCR_06_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_06_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_06_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_S_SCR_06_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_06_0_G2W_SHIFT)
#define GPIO_S_SCR_06_0_G2W_RANGE                       10:10
#define GPIO_S_SCR_06_0_G2W_WOFFSET                     0x0
#define GPIO_S_SCR_06_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_06_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_06_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_S_SCR_06_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_06_0_G1W_SHIFT)
#define GPIO_S_SCR_06_0_G1W_RANGE                       9:9
#define GPIO_S_SCR_06_0_G1W_WOFFSET                     0x0
#define GPIO_S_SCR_06_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_06_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_06_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_S_SCR_06_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_06_0_G0W_SHIFT)
#define GPIO_S_SCR_06_0_G0W_RANGE                       8:8
#define GPIO_S_SCR_06_0_G0W_WOFFSET                     0x0
#define GPIO_S_SCR_06_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_06_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_06_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_S_SCR_06_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_06_0_G7R_SHIFT)
#define GPIO_S_SCR_06_0_G7R_RANGE                       7:7
#define GPIO_S_SCR_06_0_G7R_WOFFSET                     0x0
#define GPIO_S_SCR_06_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_06_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_06_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_S_SCR_06_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_06_0_G6R_SHIFT)
#define GPIO_S_SCR_06_0_G6R_RANGE                       6:6
#define GPIO_S_SCR_06_0_G6R_WOFFSET                     0x0
#define GPIO_S_SCR_06_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_06_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_06_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_S_SCR_06_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_06_0_G5R_SHIFT)
#define GPIO_S_SCR_06_0_G5R_RANGE                       5:5
#define GPIO_S_SCR_06_0_G5R_WOFFSET                     0x0
#define GPIO_S_SCR_06_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_06_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_06_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_S_SCR_06_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_06_0_G4R_SHIFT)
#define GPIO_S_SCR_06_0_G4R_RANGE                       4:4
#define GPIO_S_SCR_06_0_G4R_WOFFSET                     0x0
#define GPIO_S_SCR_06_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_06_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_06_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_S_SCR_06_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_06_0_G3R_SHIFT)
#define GPIO_S_SCR_06_0_G3R_RANGE                       3:3
#define GPIO_S_SCR_06_0_G3R_WOFFSET                     0x0
#define GPIO_S_SCR_06_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_06_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_06_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_S_SCR_06_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_06_0_G2R_SHIFT)
#define GPIO_S_SCR_06_0_G2R_RANGE                       2:2
#define GPIO_S_SCR_06_0_G2R_WOFFSET                     0x0
#define GPIO_S_SCR_06_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_06_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_06_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_S_SCR_06_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_06_0_G1R_SHIFT)
#define GPIO_S_SCR_06_0_G1R_RANGE                       1:1
#define GPIO_S_SCR_06_0_G1R_WOFFSET                     0x0
#define GPIO_S_SCR_06_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_06_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_06_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_S_SCR_06_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_06_0_G0R_SHIFT)
#define GPIO_S_SCR_06_0_G0R_RANGE                       0:0
#define GPIO_S_SCR_06_0_G0R_WOFFSET                     0x0
#define GPIO_S_SCR_06_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_06_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_06_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_S_VM_07_0
#define GPIO_S_VM_07_0                  _MK_ADDR_CONST(0x30f8)
#define GPIO_S_VM_07_0_SECURE                   0x0
#define GPIO_S_VM_07_0_DUAL                     0x0
#define GPIO_S_VM_07_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_S_VM_07_0_WORD_COUNT                       0x1
#define GPIO_S_VM_07_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_S_VM_07_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_S_VM_07_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_07_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_S_VM_07_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_S_VM_07_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_S_VM_07_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_S_VM_07_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_07_0_VM1_SHIFT)
#define GPIO_S_VM_07_0_VM1_RANGE                        1:0
#define GPIO_S_VM_07_0_VM1_WOFFSET                      0x0
#define GPIO_S_VM_07_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_07_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_07_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_07_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_07_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_07_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_07_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_S_VM_07_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_07_0_VM2_SHIFT)
#define GPIO_S_VM_07_0_VM2_RANGE                        3:2
#define GPIO_S_VM_07_0_VM2_WOFFSET                      0x0
#define GPIO_S_VM_07_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_07_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_07_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_07_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_07_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_07_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_07_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_S_VM_07_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_07_0_VM3_SHIFT)
#define GPIO_S_VM_07_0_VM3_RANGE                        5:4
#define GPIO_S_VM_07_0_VM3_WOFFSET                      0x0
#define GPIO_S_VM_07_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_07_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_07_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_07_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_07_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_07_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_07_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_S_VM_07_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_07_0_VM4_SHIFT)
#define GPIO_S_VM_07_0_VM4_RANGE                        7:6
#define GPIO_S_VM_07_0_VM4_WOFFSET                      0x0
#define GPIO_S_VM_07_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_07_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_07_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_07_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_07_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_07_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_07_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_S_VM_07_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_07_0_VM5_SHIFT)
#define GPIO_S_VM_07_0_VM5_RANGE                        9:8
#define GPIO_S_VM_07_0_VM5_WOFFSET                      0x0
#define GPIO_S_VM_07_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_07_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_07_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_07_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_07_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_07_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_07_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_S_VM_07_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_07_0_VM6_SHIFT)
#define GPIO_S_VM_07_0_VM6_RANGE                        11:10
#define GPIO_S_VM_07_0_VM6_WOFFSET                      0x0
#define GPIO_S_VM_07_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_07_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_07_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_07_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_07_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_07_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_07_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_S_VM_07_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_07_0_VM7_SHIFT)
#define GPIO_S_VM_07_0_VM7_RANGE                        13:12
#define GPIO_S_VM_07_0_VM7_WOFFSET                      0x0
#define GPIO_S_VM_07_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_07_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_07_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_07_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_07_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_07_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_S_VM_07_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_S_VM_07_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_S_VM_07_0_VM8_SHIFT)
#define GPIO_S_VM_07_0_VM8_RANGE                        15:14
#define GPIO_S_VM_07_0_VM8_WOFFSET                      0x0
#define GPIO_S_VM_07_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_S_VM_07_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_S_VM_07_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_VM_07_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_VM_07_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_VM_07_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_S_SCR_07_0
#define GPIO_S_SCR_07_0                 _MK_ADDR_CONST(0x30fc)
#define GPIO_S_SCR_07_0_SECURE                  0x0
#define GPIO_S_SCR_07_0_DUAL                    0x0
#define GPIO_S_SCR_07_0_SCR                     0
#define GPIO_S_SCR_07_0_WORD_COUNT                      0x1
#define GPIO_S_SCR_07_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_S_SCR_07_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_S_SCR_07_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_S_SCR_07_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_S_SCR_07_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_S_SCR_07_0_SEC_LCK_SHIFT)
#define GPIO_S_SCR_07_0_SEC_LCK_RANGE                   29:29
#define GPIO_S_SCR_07_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_S_SCR_07_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_07_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_07_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_S_SCR_07_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_S_SCR_07_0_SEC_WEN_SHIFT)
#define GPIO_S_SCR_07_0_SEC_WEN_RANGE                   28:28
#define GPIO_S_SCR_07_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_S_SCR_07_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_07_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_07_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_S_SCR_07_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_S_SCR_07_0_SEC_REN_SHIFT)
#define GPIO_S_SCR_07_0_SEC_REN_RANGE                   27:27
#define GPIO_S_SCR_07_0_SEC_REN_WOFFSET                 0x0
#define GPIO_S_SCR_07_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_07_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_07_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_S_SCR_07_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_S_SCR_07_0_SEC_OWNER_SHIFT)
#define GPIO_S_SCR_07_0_SEC_OWNER_RANGE                 26:24
#define GPIO_S_SCR_07_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_S_SCR_07_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_S_SCR_07_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_07_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_S_SCR_07_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_07_0_PR7_SHIFT)
#define GPIO_S_SCR_07_0_PR7_RANGE                       23:23
#define GPIO_S_SCR_07_0_PR7_WOFFSET                     0x0
#define GPIO_S_SCR_07_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_07_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_07_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_S_SCR_07_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_07_0_PR6_SHIFT)
#define GPIO_S_SCR_07_0_PR6_RANGE                       22:22
#define GPIO_S_SCR_07_0_PR6_WOFFSET                     0x0
#define GPIO_S_SCR_07_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_07_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_07_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_S_SCR_07_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_07_0_PR5_SHIFT)
#define GPIO_S_SCR_07_0_PR5_RANGE                       21:21
#define GPIO_S_SCR_07_0_PR5_WOFFSET                     0x0
#define GPIO_S_SCR_07_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_07_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_07_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_S_SCR_07_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_07_0_PR4_SHIFT)
#define GPIO_S_SCR_07_0_PR4_RANGE                       20:20
#define GPIO_S_SCR_07_0_PR4_WOFFSET                     0x0
#define GPIO_S_SCR_07_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_07_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_07_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_S_SCR_07_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_07_0_PR3_SHIFT)
#define GPIO_S_SCR_07_0_PR3_RANGE                       19:19
#define GPIO_S_SCR_07_0_PR3_WOFFSET                     0x0
#define GPIO_S_SCR_07_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_07_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_07_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_S_SCR_07_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_07_0_PR2_SHIFT)
#define GPIO_S_SCR_07_0_PR2_RANGE                       18:18
#define GPIO_S_SCR_07_0_PR2_WOFFSET                     0x0
#define GPIO_S_SCR_07_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_07_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_07_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_S_SCR_07_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_07_0_PR1_SHIFT)
#define GPIO_S_SCR_07_0_PR1_RANGE                       17:17
#define GPIO_S_SCR_07_0_PR1_WOFFSET                     0x0
#define GPIO_S_SCR_07_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_07_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_07_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_S_SCR_07_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_07_0_PR0_SHIFT)
#define GPIO_S_SCR_07_0_PR0_RANGE                       16:16
#define GPIO_S_SCR_07_0_PR0_WOFFSET                     0x0
#define GPIO_S_SCR_07_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_07_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_07_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_S_SCR_07_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_07_0_G7W_SHIFT)
#define GPIO_S_SCR_07_0_G7W_RANGE                       15:15
#define GPIO_S_SCR_07_0_G7W_WOFFSET                     0x0
#define GPIO_S_SCR_07_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_07_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_07_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_S_SCR_07_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_07_0_G6W_SHIFT)
#define GPIO_S_SCR_07_0_G6W_RANGE                       14:14
#define GPIO_S_SCR_07_0_G6W_WOFFSET                     0x0
#define GPIO_S_SCR_07_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_07_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_07_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_S_SCR_07_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_07_0_G5W_SHIFT)
#define GPIO_S_SCR_07_0_G5W_RANGE                       13:13
#define GPIO_S_SCR_07_0_G5W_WOFFSET                     0x0
#define GPIO_S_SCR_07_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_07_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_07_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_S_SCR_07_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_07_0_G4W_SHIFT)
#define GPIO_S_SCR_07_0_G4W_RANGE                       12:12
#define GPIO_S_SCR_07_0_G4W_WOFFSET                     0x0
#define GPIO_S_SCR_07_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_07_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_07_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_S_SCR_07_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_07_0_G3W_SHIFT)
#define GPIO_S_SCR_07_0_G3W_RANGE                       11:11
#define GPIO_S_SCR_07_0_G3W_WOFFSET                     0x0
#define GPIO_S_SCR_07_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_07_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_07_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_S_SCR_07_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_07_0_G2W_SHIFT)
#define GPIO_S_SCR_07_0_G2W_RANGE                       10:10
#define GPIO_S_SCR_07_0_G2W_WOFFSET                     0x0
#define GPIO_S_SCR_07_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_07_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_07_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_S_SCR_07_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_07_0_G1W_SHIFT)
#define GPIO_S_SCR_07_0_G1W_RANGE                       9:9
#define GPIO_S_SCR_07_0_G1W_WOFFSET                     0x0
#define GPIO_S_SCR_07_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_07_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_07_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_S_SCR_07_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_07_0_G0W_SHIFT)
#define GPIO_S_SCR_07_0_G0W_RANGE                       8:8
#define GPIO_S_SCR_07_0_G0W_WOFFSET                     0x0
#define GPIO_S_SCR_07_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_07_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_07_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_S_SCR_07_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_07_0_G7R_SHIFT)
#define GPIO_S_SCR_07_0_G7R_RANGE                       7:7
#define GPIO_S_SCR_07_0_G7R_WOFFSET                     0x0
#define GPIO_S_SCR_07_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_07_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_07_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_S_SCR_07_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_07_0_G6R_SHIFT)
#define GPIO_S_SCR_07_0_G6R_RANGE                       6:6
#define GPIO_S_SCR_07_0_G6R_WOFFSET                     0x0
#define GPIO_S_SCR_07_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_07_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_07_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_S_SCR_07_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_07_0_G5R_SHIFT)
#define GPIO_S_SCR_07_0_G5R_RANGE                       5:5
#define GPIO_S_SCR_07_0_G5R_WOFFSET                     0x0
#define GPIO_S_SCR_07_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_07_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_07_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_S_SCR_07_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_07_0_G4R_SHIFT)
#define GPIO_S_SCR_07_0_G4R_RANGE                       4:4
#define GPIO_S_SCR_07_0_G4R_WOFFSET                     0x0
#define GPIO_S_SCR_07_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_07_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_07_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_S_SCR_07_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_07_0_G3R_SHIFT)
#define GPIO_S_SCR_07_0_G3R_RANGE                       3:3
#define GPIO_S_SCR_07_0_G3R_WOFFSET                     0x0
#define GPIO_S_SCR_07_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_07_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_07_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_S_SCR_07_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_07_0_G2R_SHIFT)
#define GPIO_S_SCR_07_0_G2R_RANGE                       2:2
#define GPIO_S_SCR_07_0_G2R_WOFFSET                     0x0
#define GPIO_S_SCR_07_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_07_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_07_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_S_SCR_07_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_07_0_G1R_SHIFT)
#define GPIO_S_SCR_07_0_G1R_RANGE                       1:1
#define GPIO_S_SCR_07_0_G1R_WOFFSET                     0x0
#define GPIO_S_SCR_07_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_07_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_S_SCR_07_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_S_SCR_07_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_SCR_07_0_G0R_SHIFT)
#define GPIO_S_SCR_07_0_G0R_RANGE                       0:0
#define GPIO_S_SCR_07_0_G0R_WOFFSET                     0x0
#define GPIO_S_SCR_07_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_SCR_07_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_SCR_07_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_T_VM_00_0
#define GPIO_T_VM_00_0                  _MK_ADDR_CONST(0x3100)
#define GPIO_T_VM_00_0_SECURE                   0x0
#define GPIO_T_VM_00_0_DUAL                     0x0
#define GPIO_T_VM_00_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_T_VM_00_0_WORD_COUNT                       0x1
#define GPIO_T_VM_00_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_T_VM_00_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_T_VM_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_T_VM_00_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_T_VM_00_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_T_VM_00_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_T_VM_00_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_00_0_VM1_SHIFT)
#define GPIO_T_VM_00_0_VM1_RANGE                        1:0
#define GPIO_T_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_T_VM_00_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_00_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_00_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_00_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_00_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_00_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_00_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_T_VM_00_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_00_0_VM2_SHIFT)
#define GPIO_T_VM_00_0_VM2_RANGE                        3:2
#define GPIO_T_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_T_VM_00_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_00_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_00_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_00_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_00_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_00_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_00_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_T_VM_00_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_00_0_VM3_SHIFT)
#define GPIO_T_VM_00_0_VM3_RANGE                        5:4
#define GPIO_T_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_T_VM_00_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_00_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_00_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_00_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_00_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_00_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_00_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_T_VM_00_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_00_0_VM4_SHIFT)
#define GPIO_T_VM_00_0_VM4_RANGE                        7:6
#define GPIO_T_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_T_VM_00_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_00_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_00_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_00_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_00_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_00_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_00_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_T_VM_00_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_00_0_VM5_SHIFT)
#define GPIO_T_VM_00_0_VM5_RANGE                        9:8
#define GPIO_T_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_T_VM_00_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_00_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_00_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_00_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_00_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_00_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_00_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_T_VM_00_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_00_0_VM6_SHIFT)
#define GPIO_T_VM_00_0_VM6_RANGE                        11:10
#define GPIO_T_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_T_VM_00_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_00_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_00_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_00_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_00_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_00_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_00_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_T_VM_00_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_00_0_VM7_SHIFT)
#define GPIO_T_VM_00_0_VM7_RANGE                        13:12
#define GPIO_T_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_T_VM_00_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_00_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_00_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_00_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_00_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_00_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_00_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_T_VM_00_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_00_0_VM8_SHIFT)
#define GPIO_T_VM_00_0_VM8_RANGE                        15:14
#define GPIO_T_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_T_VM_00_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_00_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_00_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_00_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_00_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_00_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_T_SCR_00_0
#define GPIO_T_SCR_00_0                 _MK_ADDR_CONST(0x3104)
#define GPIO_T_SCR_00_0_SECURE                  0x0
#define GPIO_T_SCR_00_0_DUAL                    0x0
#define GPIO_T_SCR_00_0_SCR                     0
#define GPIO_T_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_T_SCR_00_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_T_SCR_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_T_SCR_00_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_T_SCR_00_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_T_SCR_00_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_T_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_T_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_T_SCR_00_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_00_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_00_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_T_SCR_00_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_T_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_T_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_T_SCR_00_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_00_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_00_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_T_SCR_00_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_T_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_T_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_T_SCR_00_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_00_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_00_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_T_SCR_00_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_T_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_T_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_T_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_T_SCR_00_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_T_SCR_00_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_00_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_T_SCR_00_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_00_0_PR7_SHIFT)
#define GPIO_T_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_T_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_T_SCR_00_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_00_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_00_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_T_SCR_00_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_00_0_PR6_SHIFT)
#define GPIO_T_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_T_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_T_SCR_00_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_00_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_00_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_T_SCR_00_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_00_0_PR5_SHIFT)
#define GPIO_T_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_T_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_T_SCR_00_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_00_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_00_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_T_SCR_00_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_00_0_PR4_SHIFT)
#define GPIO_T_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_T_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_T_SCR_00_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_00_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_00_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_T_SCR_00_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_00_0_PR3_SHIFT)
#define GPIO_T_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_T_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_T_SCR_00_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_00_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_00_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_T_SCR_00_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_00_0_PR2_SHIFT)
#define GPIO_T_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_T_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_T_SCR_00_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_00_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_00_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_T_SCR_00_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_00_0_PR1_SHIFT)
#define GPIO_T_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_T_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_T_SCR_00_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_00_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_00_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_T_SCR_00_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_00_0_PR0_SHIFT)
#define GPIO_T_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_T_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_T_SCR_00_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_00_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_00_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_T_SCR_00_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_00_0_G7W_SHIFT)
#define GPIO_T_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_T_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_T_SCR_00_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_00_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_00_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_T_SCR_00_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_00_0_G6W_SHIFT)
#define GPIO_T_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_T_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_T_SCR_00_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_00_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_00_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_T_SCR_00_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_00_0_G5W_SHIFT)
#define GPIO_T_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_T_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_T_SCR_00_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_00_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_00_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_T_SCR_00_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_00_0_G4W_SHIFT)
#define GPIO_T_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_T_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_T_SCR_00_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_00_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_00_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_T_SCR_00_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_00_0_G3W_SHIFT)
#define GPIO_T_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_T_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_T_SCR_00_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_00_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_00_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_T_SCR_00_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_00_0_G2W_SHIFT)
#define GPIO_T_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_T_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_T_SCR_00_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_00_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_00_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_T_SCR_00_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_00_0_G1W_SHIFT)
#define GPIO_T_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_T_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_T_SCR_00_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_00_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_00_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_T_SCR_00_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_00_0_G0W_SHIFT)
#define GPIO_T_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_T_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_T_SCR_00_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_00_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_00_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_T_SCR_00_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_00_0_G7R_SHIFT)
#define GPIO_T_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_T_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_T_SCR_00_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_00_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_00_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_T_SCR_00_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_00_0_G6R_SHIFT)
#define GPIO_T_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_T_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_T_SCR_00_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_00_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_00_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_T_SCR_00_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_00_0_G5R_SHIFT)
#define GPIO_T_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_T_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_T_SCR_00_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_00_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_00_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_T_SCR_00_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_00_0_G4R_SHIFT)
#define GPIO_T_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_T_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_T_SCR_00_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_00_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_00_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_T_SCR_00_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_00_0_G3R_SHIFT)
#define GPIO_T_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_T_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_T_SCR_00_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_00_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_00_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_T_SCR_00_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_00_0_G2R_SHIFT)
#define GPIO_T_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_T_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_T_SCR_00_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_00_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_00_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_T_SCR_00_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_00_0_G1R_SHIFT)
#define GPIO_T_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_T_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_T_SCR_00_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_00_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_00_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_T_SCR_00_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_00_0_G0R_SHIFT)
#define GPIO_T_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_T_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_T_SCR_00_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_00_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_00_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_T_VM_01_0
#define GPIO_T_VM_01_0                  _MK_ADDR_CONST(0x3108)
#define GPIO_T_VM_01_0_SECURE                   0x0
#define GPIO_T_VM_01_0_DUAL                     0x0
#define GPIO_T_VM_01_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_T_VM_01_0_WORD_COUNT                       0x1
#define GPIO_T_VM_01_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_T_VM_01_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_T_VM_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_T_VM_01_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_T_VM_01_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_T_VM_01_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_T_VM_01_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_01_0_VM1_SHIFT)
#define GPIO_T_VM_01_0_VM1_RANGE                        1:0
#define GPIO_T_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_T_VM_01_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_01_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_01_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_01_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_01_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_01_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_01_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_T_VM_01_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_01_0_VM2_SHIFT)
#define GPIO_T_VM_01_0_VM2_RANGE                        3:2
#define GPIO_T_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_T_VM_01_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_01_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_01_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_01_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_01_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_01_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_01_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_T_VM_01_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_01_0_VM3_SHIFT)
#define GPIO_T_VM_01_0_VM3_RANGE                        5:4
#define GPIO_T_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_T_VM_01_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_01_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_01_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_01_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_01_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_01_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_01_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_T_VM_01_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_01_0_VM4_SHIFT)
#define GPIO_T_VM_01_0_VM4_RANGE                        7:6
#define GPIO_T_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_T_VM_01_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_01_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_01_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_01_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_01_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_01_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_01_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_T_VM_01_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_01_0_VM5_SHIFT)
#define GPIO_T_VM_01_0_VM5_RANGE                        9:8
#define GPIO_T_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_T_VM_01_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_01_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_01_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_01_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_01_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_01_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_01_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_T_VM_01_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_01_0_VM6_SHIFT)
#define GPIO_T_VM_01_0_VM6_RANGE                        11:10
#define GPIO_T_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_T_VM_01_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_01_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_01_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_01_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_01_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_01_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_01_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_T_VM_01_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_01_0_VM7_SHIFT)
#define GPIO_T_VM_01_0_VM7_RANGE                        13:12
#define GPIO_T_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_T_VM_01_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_01_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_01_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_01_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_01_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_01_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_01_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_T_VM_01_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_01_0_VM8_SHIFT)
#define GPIO_T_VM_01_0_VM8_RANGE                        15:14
#define GPIO_T_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_T_VM_01_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_01_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_01_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_01_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_01_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_01_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_T_SCR_01_0
#define GPIO_T_SCR_01_0                 _MK_ADDR_CONST(0x310c)
#define GPIO_T_SCR_01_0_SECURE                  0x0
#define GPIO_T_SCR_01_0_DUAL                    0x0
#define GPIO_T_SCR_01_0_SCR                     0
#define GPIO_T_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_T_SCR_01_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_T_SCR_01_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_T_SCR_01_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_T_SCR_01_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_T_SCR_01_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_T_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_T_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_T_SCR_01_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_01_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_01_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_T_SCR_01_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_T_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_T_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_T_SCR_01_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_01_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_01_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_T_SCR_01_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_T_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_T_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_T_SCR_01_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_01_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_01_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_T_SCR_01_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_T_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_T_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_T_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_T_SCR_01_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_T_SCR_01_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_01_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_T_SCR_01_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_01_0_PR7_SHIFT)
#define GPIO_T_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_T_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_T_SCR_01_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_01_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_01_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_T_SCR_01_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_01_0_PR6_SHIFT)
#define GPIO_T_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_T_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_T_SCR_01_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_01_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_01_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_T_SCR_01_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_01_0_PR5_SHIFT)
#define GPIO_T_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_T_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_T_SCR_01_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_01_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_01_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_T_SCR_01_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_01_0_PR4_SHIFT)
#define GPIO_T_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_T_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_T_SCR_01_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_01_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_01_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_T_SCR_01_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_01_0_PR3_SHIFT)
#define GPIO_T_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_T_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_T_SCR_01_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_01_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_01_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_T_SCR_01_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_01_0_PR2_SHIFT)
#define GPIO_T_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_T_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_T_SCR_01_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_01_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_01_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_T_SCR_01_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_01_0_PR1_SHIFT)
#define GPIO_T_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_T_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_T_SCR_01_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_01_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_01_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_T_SCR_01_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_01_0_PR0_SHIFT)
#define GPIO_T_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_T_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_T_SCR_01_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_01_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_01_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_T_SCR_01_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_01_0_G7W_SHIFT)
#define GPIO_T_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_T_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_T_SCR_01_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_01_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_01_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_T_SCR_01_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_01_0_G6W_SHIFT)
#define GPIO_T_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_T_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_T_SCR_01_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_01_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_01_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_T_SCR_01_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_01_0_G5W_SHIFT)
#define GPIO_T_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_T_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_T_SCR_01_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_01_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_01_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_T_SCR_01_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_01_0_G4W_SHIFT)
#define GPIO_T_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_T_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_T_SCR_01_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_01_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_01_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_T_SCR_01_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_01_0_G3W_SHIFT)
#define GPIO_T_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_T_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_T_SCR_01_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_01_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_01_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_T_SCR_01_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_01_0_G2W_SHIFT)
#define GPIO_T_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_T_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_T_SCR_01_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_01_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_01_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_T_SCR_01_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_01_0_G1W_SHIFT)
#define GPIO_T_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_T_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_T_SCR_01_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_01_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_01_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_T_SCR_01_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_01_0_G0W_SHIFT)
#define GPIO_T_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_T_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_T_SCR_01_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_01_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_01_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_T_SCR_01_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_01_0_G7R_SHIFT)
#define GPIO_T_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_T_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_T_SCR_01_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_01_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_01_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_T_SCR_01_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_01_0_G6R_SHIFT)
#define GPIO_T_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_T_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_T_SCR_01_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_01_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_01_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_T_SCR_01_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_01_0_G5R_SHIFT)
#define GPIO_T_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_T_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_T_SCR_01_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_01_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_01_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_T_SCR_01_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_01_0_G4R_SHIFT)
#define GPIO_T_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_T_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_T_SCR_01_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_01_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_01_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_T_SCR_01_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_01_0_G3R_SHIFT)
#define GPIO_T_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_T_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_T_SCR_01_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_01_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_01_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_T_SCR_01_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_01_0_G2R_SHIFT)
#define GPIO_T_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_T_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_T_SCR_01_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_01_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_01_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_T_SCR_01_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_01_0_G1R_SHIFT)
#define GPIO_T_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_T_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_T_SCR_01_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_01_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_01_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_T_SCR_01_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_01_0_G0R_SHIFT)
#define GPIO_T_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_T_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_T_SCR_01_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_01_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_01_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_T_VM_02_0
#define GPIO_T_VM_02_0                  _MK_ADDR_CONST(0x3110)
#define GPIO_T_VM_02_0_SECURE                   0x0
#define GPIO_T_VM_02_0_DUAL                     0x0
#define GPIO_T_VM_02_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_T_VM_02_0_WORD_COUNT                       0x1
#define GPIO_T_VM_02_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_T_VM_02_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_T_VM_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_T_VM_02_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_T_VM_02_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_T_VM_02_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_T_VM_02_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_02_0_VM1_SHIFT)
#define GPIO_T_VM_02_0_VM1_RANGE                        1:0
#define GPIO_T_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_T_VM_02_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_02_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_02_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_02_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_02_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_02_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_02_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_T_VM_02_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_02_0_VM2_SHIFT)
#define GPIO_T_VM_02_0_VM2_RANGE                        3:2
#define GPIO_T_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_T_VM_02_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_02_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_02_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_02_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_02_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_02_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_02_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_T_VM_02_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_02_0_VM3_SHIFT)
#define GPIO_T_VM_02_0_VM3_RANGE                        5:4
#define GPIO_T_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_T_VM_02_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_02_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_02_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_02_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_02_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_02_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_02_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_T_VM_02_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_02_0_VM4_SHIFT)
#define GPIO_T_VM_02_0_VM4_RANGE                        7:6
#define GPIO_T_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_T_VM_02_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_02_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_02_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_02_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_02_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_02_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_02_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_T_VM_02_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_02_0_VM5_SHIFT)
#define GPIO_T_VM_02_0_VM5_RANGE                        9:8
#define GPIO_T_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_T_VM_02_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_02_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_02_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_02_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_02_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_02_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_02_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_T_VM_02_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_02_0_VM6_SHIFT)
#define GPIO_T_VM_02_0_VM6_RANGE                        11:10
#define GPIO_T_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_T_VM_02_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_02_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_02_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_02_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_02_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_02_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_02_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_T_VM_02_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_02_0_VM7_SHIFT)
#define GPIO_T_VM_02_0_VM7_RANGE                        13:12
#define GPIO_T_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_T_VM_02_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_02_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_02_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_02_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_02_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_02_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_02_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_T_VM_02_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_02_0_VM8_SHIFT)
#define GPIO_T_VM_02_0_VM8_RANGE                        15:14
#define GPIO_T_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_T_VM_02_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_02_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_02_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_02_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_02_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_02_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_T_SCR_02_0
#define GPIO_T_SCR_02_0                 _MK_ADDR_CONST(0x3114)
#define GPIO_T_SCR_02_0_SECURE                  0x0
#define GPIO_T_SCR_02_0_DUAL                    0x0
#define GPIO_T_SCR_02_0_SCR                     0
#define GPIO_T_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_T_SCR_02_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_T_SCR_02_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_T_SCR_02_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_T_SCR_02_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_T_SCR_02_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_T_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_T_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_T_SCR_02_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_02_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_02_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_T_SCR_02_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_T_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_T_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_T_SCR_02_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_02_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_02_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_T_SCR_02_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_T_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_T_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_T_SCR_02_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_02_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_02_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_T_SCR_02_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_T_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_T_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_T_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_T_SCR_02_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_T_SCR_02_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_02_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_T_SCR_02_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_02_0_PR7_SHIFT)
#define GPIO_T_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_T_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_T_SCR_02_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_02_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_02_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_T_SCR_02_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_02_0_PR6_SHIFT)
#define GPIO_T_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_T_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_T_SCR_02_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_02_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_02_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_T_SCR_02_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_02_0_PR5_SHIFT)
#define GPIO_T_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_T_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_T_SCR_02_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_02_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_02_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_T_SCR_02_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_02_0_PR4_SHIFT)
#define GPIO_T_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_T_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_T_SCR_02_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_02_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_02_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_T_SCR_02_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_02_0_PR3_SHIFT)
#define GPIO_T_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_T_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_T_SCR_02_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_02_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_02_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_T_SCR_02_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_02_0_PR2_SHIFT)
#define GPIO_T_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_T_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_T_SCR_02_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_02_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_02_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_T_SCR_02_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_02_0_PR1_SHIFT)
#define GPIO_T_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_T_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_T_SCR_02_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_02_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_02_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_T_SCR_02_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_02_0_PR0_SHIFT)
#define GPIO_T_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_T_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_T_SCR_02_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_02_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_02_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_T_SCR_02_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_02_0_G7W_SHIFT)
#define GPIO_T_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_T_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_T_SCR_02_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_02_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_02_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_T_SCR_02_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_02_0_G6W_SHIFT)
#define GPIO_T_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_T_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_T_SCR_02_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_02_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_02_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_T_SCR_02_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_02_0_G5W_SHIFT)
#define GPIO_T_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_T_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_T_SCR_02_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_02_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_02_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_T_SCR_02_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_02_0_G4W_SHIFT)
#define GPIO_T_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_T_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_T_SCR_02_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_02_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_02_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_T_SCR_02_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_02_0_G3W_SHIFT)
#define GPIO_T_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_T_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_T_SCR_02_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_02_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_02_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_T_SCR_02_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_02_0_G2W_SHIFT)
#define GPIO_T_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_T_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_T_SCR_02_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_02_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_02_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_T_SCR_02_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_02_0_G1W_SHIFT)
#define GPIO_T_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_T_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_T_SCR_02_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_02_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_02_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_T_SCR_02_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_02_0_G0W_SHIFT)
#define GPIO_T_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_T_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_T_SCR_02_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_02_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_02_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_T_SCR_02_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_02_0_G7R_SHIFT)
#define GPIO_T_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_T_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_T_SCR_02_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_02_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_02_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_T_SCR_02_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_02_0_G6R_SHIFT)
#define GPIO_T_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_T_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_T_SCR_02_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_02_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_02_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_T_SCR_02_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_02_0_G5R_SHIFT)
#define GPIO_T_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_T_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_T_SCR_02_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_02_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_02_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_T_SCR_02_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_02_0_G4R_SHIFT)
#define GPIO_T_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_T_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_T_SCR_02_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_02_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_02_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_T_SCR_02_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_02_0_G3R_SHIFT)
#define GPIO_T_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_T_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_T_SCR_02_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_02_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_02_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_T_SCR_02_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_02_0_G2R_SHIFT)
#define GPIO_T_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_T_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_T_SCR_02_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_02_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_02_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_T_SCR_02_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_02_0_G1R_SHIFT)
#define GPIO_T_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_T_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_T_SCR_02_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_02_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_02_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_T_SCR_02_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_02_0_G0R_SHIFT)
#define GPIO_T_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_T_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_T_SCR_02_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_02_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_02_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_T_VM_03_0
#define GPIO_T_VM_03_0                  _MK_ADDR_CONST(0x3118)
#define GPIO_T_VM_03_0_SECURE                   0x0
#define GPIO_T_VM_03_0_DUAL                     0x0
#define GPIO_T_VM_03_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_T_VM_03_0_WORD_COUNT                       0x1
#define GPIO_T_VM_03_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_T_VM_03_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_T_VM_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_T_VM_03_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_T_VM_03_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_T_VM_03_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_T_VM_03_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_03_0_VM1_SHIFT)
#define GPIO_T_VM_03_0_VM1_RANGE                        1:0
#define GPIO_T_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_T_VM_03_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_03_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_03_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_03_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_03_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_03_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_03_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_T_VM_03_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_03_0_VM2_SHIFT)
#define GPIO_T_VM_03_0_VM2_RANGE                        3:2
#define GPIO_T_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_T_VM_03_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_03_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_03_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_03_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_03_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_03_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_03_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_T_VM_03_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_03_0_VM3_SHIFT)
#define GPIO_T_VM_03_0_VM3_RANGE                        5:4
#define GPIO_T_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_T_VM_03_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_03_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_03_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_03_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_03_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_03_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_03_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_T_VM_03_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_03_0_VM4_SHIFT)
#define GPIO_T_VM_03_0_VM4_RANGE                        7:6
#define GPIO_T_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_T_VM_03_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_03_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_03_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_03_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_03_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_03_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_03_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_T_VM_03_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_03_0_VM5_SHIFT)
#define GPIO_T_VM_03_0_VM5_RANGE                        9:8
#define GPIO_T_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_T_VM_03_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_03_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_03_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_03_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_03_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_03_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_03_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_T_VM_03_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_03_0_VM6_SHIFT)
#define GPIO_T_VM_03_0_VM6_RANGE                        11:10
#define GPIO_T_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_T_VM_03_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_03_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_03_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_03_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_03_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_03_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_03_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_T_VM_03_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_03_0_VM7_SHIFT)
#define GPIO_T_VM_03_0_VM7_RANGE                        13:12
#define GPIO_T_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_T_VM_03_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_03_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_03_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_03_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_03_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_03_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_03_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_T_VM_03_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_03_0_VM8_SHIFT)
#define GPIO_T_VM_03_0_VM8_RANGE                        15:14
#define GPIO_T_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_T_VM_03_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_03_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_03_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_03_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_03_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_03_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_T_SCR_03_0
#define GPIO_T_SCR_03_0                 _MK_ADDR_CONST(0x311c)
#define GPIO_T_SCR_03_0_SECURE                  0x0
#define GPIO_T_SCR_03_0_DUAL                    0x0
#define GPIO_T_SCR_03_0_SCR                     0
#define GPIO_T_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_T_SCR_03_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_T_SCR_03_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_T_SCR_03_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_T_SCR_03_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_T_SCR_03_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_T_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_T_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_T_SCR_03_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_03_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_03_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_T_SCR_03_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_T_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_T_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_T_SCR_03_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_03_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_03_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_T_SCR_03_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_T_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_T_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_T_SCR_03_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_03_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_03_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_T_SCR_03_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_T_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_T_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_T_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_T_SCR_03_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_T_SCR_03_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_03_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_T_SCR_03_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_03_0_PR7_SHIFT)
#define GPIO_T_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_T_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_T_SCR_03_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_03_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_03_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_T_SCR_03_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_03_0_PR6_SHIFT)
#define GPIO_T_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_T_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_T_SCR_03_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_03_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_03_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_T_SCR_03_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_03_0_PR5_SHIFT)
#define GPIO_T_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_T_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_T_SCR_03_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_03_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_03_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_T_SCR_03_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_03_0_PR4_SHIFT)
#define GPIO_T_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_T_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_T_SCR_03_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_03_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_03_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_T_SCR_03_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_03_0_PR3_SHIFT)
#define GPIO_T_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_T_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_T_SCR_03_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_03_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_03_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_T_SCR_03_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_03_0_PR2_SHIFT)
#define GPIO_T_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_T_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_T_SCR_03_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_03_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_03_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_T_SCR_03_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_03_0_PR1_SHIFT)
#define GPIO_T_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_T_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_T_SCR_03_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_03_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_03_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_T_SCR_03_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_03_0_PR0_SHIFT)
#define GPIO_T_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_T_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_T_SCR_03_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_03_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_03_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_T_SCR_03_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_03_0_G7W_SHIFT)
#define GPIO_T_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_T_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_T_SCR_03_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_03_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_03_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_T_SCR_03_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_03_0_G6W_SHIFT)
#define GPIO_T_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_T_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_T_SCR_03_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_03_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_03_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_T_SCR_03_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_03_0_G5W_SHIFT)
#define GPIO_T_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_T_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_T_SCR_03_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_03_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_03_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_T_SCR_03_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_03_0_G4W_SHIFT)
#define GPIO_T_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_T_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_T_SCR_03_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_03_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_03_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_T_SCR_03_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_03_0_G3W_SHIFT)
#define GPIO_T_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_T_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_T_SCR_03_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_03_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_03_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_T_SCR_03_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_03_0_G2W_SHIFT)
#define GPIO_T_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_T_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_T_SCR_03_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_03_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_03_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_T_SCR_03_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_03_0_G1W_SHIFT)
#define GPIO_T_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_T_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_T_SCR_03_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_03_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_03_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_T_SCR_03_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_03_0_G0W_SHIFT)
#define GPIO_T_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_T_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_T_SCR_03_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_03_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_03_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_T_SCR_03_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_03_0_G7R_SHIFT)
#define GPIO_T_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_T_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_T_SCR_03_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_03_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_03_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_T_SCR_03_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_03_0_G6R_SHIFT)
#define GPIO_T_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_T_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_T_SCR_03_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_03_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_03_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_T_SCR_03_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_03_0_G5R_SHIFT)
#define GPIO_T_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_T_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_T_SCR_03_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_03_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_03_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_T_SCR_03_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_03_0_G4R_SHIFT)
#define GPIO_T_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_T_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_T_SCR_03_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_03_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_03_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_T_SCR_03_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_03_0_G3R_SHIFT)
#define GPIO_T_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_T_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_T_SCR_03_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_03_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_03_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_T_SCR_03_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_03_0_G2R_SHIFT)
#define GPIO_T_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_T_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_T_SCR_03_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_03_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_03_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_T_SCR_03_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_03_0_G1R_SHIFT)
#define GPIO_T_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_T_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_T_SCR_03_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_03_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_03_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_T_SCR_03_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_03_0_G0R_SHIFT)
#define GPIO_T_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_T_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_T_SCR_03_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_03_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_03_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_T_VM_04_0
#define GPIO_T_VM_04_0                  _MK_ADDR_CONST(0x3120)
#define GPIO_T_VM_04_0_SECURE                   0x0
#define GPIO_T_VM_04_0_DUAL                     0x0
#define GPIO_T_VM_04_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_T_VM_04_0_WORD_COUNT                       0x1
#define GPIO_T_VM_04_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_T_VM_04_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_T_VM_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_T_VM_04_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_T_VM_04_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_T_VM_04_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_T_VM_04_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_04_0_VM1_SHIFT)
#define GPIO_T_VM_04_0_VM1_RANGE                        1:0
#define GPIO_T_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_T_VM_04_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_04_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_04_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_04_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_04_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_04_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_04_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_T_VM_04_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_04_0_VM2_SHIFT)
#define GPIO_T_VM_04_0_VM2_RANGE                        3:2
#define GPIO_T_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_T_VM_04_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_04_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_04_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_04_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_04_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_04_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_04_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_T_VM_04_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_04_0_VM3_SHIFT)
#define GPIO_T_VM_04_0_VM3_RANGE                        5:4
#define GPIO_T_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_T_VM_04_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_04_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_04_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_04_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_04_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_04_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_04_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_T_VM_04_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_04_0_VM4_SHIFT)
#define GPIO_T_VM_04_0_VM4_RANGE                        7:6
#define GPIO_T_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_T_VM_04_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_04_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_04_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_04_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_04_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_04_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_04_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_T_VM_04_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_04_0_VM5_SHIFT)
#define GPIO_T_VM_04_0_VM5_RANGE                        9:8
#define GPIO_T_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_T_VM_04_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_04_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_04_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_04_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_04_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_04_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_04_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_T_VM_04_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_04_0_VM6_SHIFT)
#define GPIO_T_VM_04_0_VM6_RANGE                        11:10
#define GPIO_T_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_T_VM_04_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_04_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_04_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_04_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_04_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_04_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_04_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_T_VM_04_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_04_0_VM7_SHIFT)
#define GPIO_T_VM_04_0_VM7_RANGE                        13:12
#define GPIO_T_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_T_VM_04_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_04_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_04_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_04_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_04_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_04_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_04_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_T_VM_04_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_04_0_VM8_SHIFT)
#define GPIO_T_VM_04_0_VM8_RANGE                        15:14
#define GPIO_T_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_T_VM_04_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_04_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_04_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_04_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_04_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_04_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_T_SCR_04_0
#define GPIO_T_SCR_04_0                 _MK_ADDR_CONST(0x3124)
#define GPIO_T_SCR_04_0_SECURE                  0x0
#define GPIO_T_SCR_04_0_DUAL                    0x0
#define GPIO_T_SCR_04_0_SCR                     0
#define GPIO_T_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_T_SCR_04_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_T_SCR_04_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_T_SCR_04_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_T_SCR_04_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_T_SCR_04_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_T_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_T_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_T_SCR_04_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_04_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_04_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_T_SCR_04_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_T_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_T_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_T_SCR_04_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_04_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_04_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_T_SCR_04_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_T_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_T_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_T_SCR_04_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_04_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_04_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_T_SCR_04_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_T_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_T_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_T_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_T_SCR_04_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_T_SCR_04_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_04_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_T_SCR_04_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_04_0_PR7_SHIFT)
#define GPIO_T_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_T_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_T_SCR_04_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_04_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_04_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_T_SCR_04_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_04_0_PR6_SHIFT)
#define GPIO_T_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_T_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_T_SCR_04_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_04_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_04_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_T_SCR_04_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_04_0_PR5_SHIFT)
#define GPIO_T_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_T_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_T_SCR_04_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_04_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_04_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_T_SCR_04_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_04_0_PR4_SHIFT)
#define GPIO_T_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_T_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_T_SCR_04_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_04_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_04_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_T_SCR_04_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_04_0_PR3_SHIFT)
#define GPIO_T_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_T_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_T_SCR_04_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_04_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_04_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_T_SCR_04_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_04_0_PR2_SHIFT)
#define GPIO_T_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_T_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_T_SCR_04_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_04_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_04_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_T_SCR_04_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_04_0_PR1_SHIFT)
#define GPIO_T_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_T_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_T_SCR_04_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_04_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_04_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_T_SCR_04_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_04_0_PR0_SHIFT)
#define GPIO_T_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_T_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_T_SCR_04_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_04_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_04_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_T_SCR_04_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_04_0_G7W_SHIFT)
#define GPIO_T_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_T_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_T_SCR_04_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_04_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_04_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_T_SCR_04_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_04_0_G6W_SHIFT)
#define GPIO_T_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_T_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_T_SCR_04_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_04_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_04_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_T_SCR_04_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_04_0_G5W_SHIFT)
#define GPIO_T_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_T_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_T_SCR_04_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_04_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_04_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_T_SCR_04_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_04_0_G4W_SHIFT)
#define GPIO_T_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_T_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_T_SCR_04_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_04_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_04_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_T_SCR_04_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_04_0_G3W_SHIFT)
#define GPIO_T_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_T_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_T_SCR_04_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_04_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_04_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_T_SCR_04_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_04_0_G2W_SHIFT)
#define GPIO_T_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_T_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_T_SCR_04_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_04_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_04_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_T_SCR_04_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_04_0_G1W_SHIFT)
#define GPIO_T_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_T_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_T_SCR_04_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_04_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_04_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_T_SCR_04_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_04_0_G0W_SHIFT)
#define GPIO_T_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_T_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_T_SCR_04_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_04_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_04_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_T_SCR_04_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_04_0_G7R_SHIFT)
#define GPIO_T_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_T_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_T_SCR_04_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_04_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_04_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_T_SCR_04_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_04_0_G6R_SHIFT)
#define GPIO_T_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_T_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_T_SCR_04_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_04_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_04_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_T_SCR_04_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_04_0_G5R_SHIFT)
#define GPIO_T_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_T_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_T_SCR_04_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_04_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_04_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_T_SCR_04_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_04_0_G4R_SHIFT)
#define GPIO_T_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_T_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_T_SCR_04_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_04_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_04_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_T_SCR_04_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_04_0_G3R_SHIFT)
#define GPIO_T_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_T_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_T_SCR_04_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_04_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_04_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_T_SCR_04_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_04_0_G2R_SHIFT)
#define GPIO_T_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_T_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_T_SCR_04_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_04_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_04_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_T_SCR_04_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_04_0_G1R_SHIFT)
#define GPIO_T_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_T_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_T_SCR_04_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_04_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_04_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_T_SCR_04_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_04_0_G0R_SHIFT)
#define GPIO_T_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_T_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_T_SCR_04_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_04_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_04_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_T_VM_05_0
#define GPIO_T_VM_05_0                  _MK_ADDR_CONST(0x3128)
#define GPIO_T_VM_05_0_SECURE                   0x0
#define GPIO_T_VM_05_0_DUAL                     0x0
#define GPIO_T_VM_05_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_T_VM_05_0_WORD_COUNT                       0x1
#define GPIO_T_VM_05_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_T_VM_05_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_T_VM_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_T_VM_05_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_T_VM_05_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_T_VM_05_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_T_VM_05_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_05_0_VM1_SHIFT)
#define GPIO_T_VM_05_0_VM1_RANGE                        1:0
#define GPIO_T_VM_05_0_VM1_WOFFSET                      0x0
#define GPIO_T_VM_05_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_05_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_05_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_05_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_05_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_05_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_05_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_T_VM_05_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_05_0_VM2_SHIFT)
#define GPIO_T_VM_05_0_VM2_RANGE                        3:2
#define GPIO_T_VM_05_0_VM2_WOFFSET                      0x0
#define GPIO_T_VM_05_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_05_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_05_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_05_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_05_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_05_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_05_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_T_VM_05_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_05_0_VM3_SHIFT)
#define GPIO_T_VM_05_0_VM3_RANGE                        5:4
#define GPIO_T_VM_05_0_VM3_WOFFSET                      0x0
#define GPIO_T_VM_05_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_05_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_05_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_05_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_05_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_05_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_05_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_T_VM_05_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_05_0_VM4_SHIFT)
#define GPIO_T_VM_05_0_VM4_RANGE                        7:6
#define GPIO_T_VM_05_0_VM4_WOFFSET                      0x0
#define GPIO_T_VM_05_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_05_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_05_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_05_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_05_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_05_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_05_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_T_VM_05_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_05_0_VM5_SHIFT)
#define GPIO_T_VM_05_0_VM5_RANGE                        9:8
#define GPIO_T_VM_05_0_VM5_WOFFSET                      0x0
#define GPIO_T_VM_05_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_05_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_05_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_05_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_05_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_05_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_05_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_T_VM_05_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_05_0_VM6_SHIFT)
#define GPIO_T_VM_05_0_VM6_RANGE                        11:10
#define GPIO_T_VM_05_0_VM6_WOFFSET                      0x0
#define GPIO_T_VM_05_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_05_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_05_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_05_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_05_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_05_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_05_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_T_VM_05_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_05_0_VM7_SHIFT)
#define GPIO_T_VM_05_0_VM7_RANGE                        13:12
#define GPIO_T_VM_05_0_VM7_WOFFSET                      0x0
#define GPIO_T_VM_05_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_05_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_05_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_05_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_05_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_05_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_05_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_T_VM_05_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_05_0_VM8_SHIFT)
#define GPIO_T_VM_05_0_VM8_RANGE                        15:14
#define GPIO_T_VM_05_0_VM8_WOFFSET                      0x0
#define GPIO_T_VM_05_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_05_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_05_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_05_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_05_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_05_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_T_SCR_05_0
#define GPIO_T_SCR_05_0                 _MK_ADDR_CONST(0x312c)
#define GPIO_T_SCR_05_0_SECURE                  0x0
#define GPIO_T_SCR_05_0_DUAL                    0x0
#define GPIO_T_SCR_05_0_SCR                     0
#define GPIO_T_SCR_05_0_WORD_COUNT                      0x1
#define GPIO_T_SCR_05_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_T_SCR_05_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_T_SCR_05_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_T_SCR_05_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_T_SCR_05_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_T_SCR_05_0_SEC_LCK_RANGE                   29:29
#define GPIO_T_SCR_05_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_T_SCR_05_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_05_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_05_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_T_SCR_05_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_T_SCR_05_0_SEC_WEN_RANGE                   28:28
#define GPIO_T_SCR_05_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_T_SCR_05_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_05_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_05_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_T_SCR_05_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_T_SCR_05_0_SEC_REN_RANGE                   27:27
#define GPIO_T_SCR_05_0_SEC_REN_WOFFSET                 0x0
#define GPIO_T_SCR_05_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_05_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_05_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_T_SCR_05_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_T_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_T_SCR_05_0_SEC_OWNER_RANGE                 26:24
#define GPIO_T_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_T_SCR_05_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_T_SCR_05_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_05_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_T_SCR_05_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_05_0_PR7_SHIFT)
#define GPIO_T_SCR_05_0_PR7_RANGE                       23:23
#define GPIO_T_SCR_05_0_PR7_WOFFSET                     0x0
#define GPIO_T_SCR_05_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_05_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_05_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_T_SCR_05_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_05_0_PR6_SHIFT)
#define GPIO_T_SCR_05_0_PR6_RANGE                       22:22
#define GPIO_T_SCR_05_0_PR6_WOFFSET                     0x0
#define GPIO_T_SCR_05_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_05_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_05_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_T_SCR_05_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_05_0_PR5_SHIFT)
#define GPIO_T_SCR_05_0_PR5_RANGE                       21:21
#define GPIO_T_SCR_05_0_PR5_WOFFSET                     0x0
#define GPIO_T_SCR_05_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_05_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_05_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_T_SCR_05_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_05_0_PR4_SHIFT)
#define GPIO_T_SCR_05_0_PR4_RANGE                       20:20
#define GPIO_T_SCR_05_0_PR4_WOFFSET                     0x0
#define GPIO_T_SCR_05_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_05_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_05_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_T_SCR_05_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_05_0_PR3_SHIFT)
#define GPIO_T_SCR_05_0_PR3_RANGE                       19:19
#define GPIO_T_SCR_05_0_PR3_WOFFSET                     0x0
#define GPIO_T_SCR_05_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_05_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_05_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_T_SCR_05_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_05_0_PR2_SHIFT)
#define GPIO_T_SCR_05_0_PR2_RANGE                       18:18
#define GPIO_T_SCR_05_0_PR2_WOFFSET                     0x0
#define GPIO_T_SCR_05_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_05_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_05_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_T_SCR_05_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_05_0_PR1_SHIFT)
#define GPIO_T_SCR_05_0_PR1_RANGE                       17:17
#define GPIO_T_SCR_05_0_PR1_WOFFSET                     0x0
#define GPIO_T_SCR_05_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_05_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_05_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_T_SCR_05_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_05_0_PR0_SHIFT)
#define GPIO_T_SCR_05_0_PR0_RANGE                       16:16
#define GPIO_T_SCR_05_0_PR0_WOFFSET                     0x0
#define GPIO_T_SCR_05_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_05_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_05_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_T_SCR_05_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_05_0_G7W_SHIFT)
#define GPIO_T_SCR_05_0_G7W_RANGE                       15:15
#define GPIO_T_SCR_05_0_G7W_WOFFSET                     0x0
#define GPIO_T_SCR_05_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_05_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_05_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_T_SCR_05_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_05_0_G6W_SHIFT)
#define GPIO_T_SCR_05_0_G6W_RANGE                       14:14
#define GPIO_T_SCR_05_0_G6W_WOFFSET                     0x0
#define GPIO_T_SCR_05_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_05_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_05_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_T_SCR_05_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_05_0_G5W_SHIFT)
#define GPIO_T_SCR_05_0_G5W_RANGE                       13:13
#define GPIO_T_SCR_05_0_G5W_WOFFSET                     0x0
#define GPIO_T_SCR_05_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_05_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_05_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_T_SCR_05_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_05_0_G4W_SHIFT)
#define GPIO_T_SCR_05_0_G4W_RANGE                       12:12
#define GPIO_T_SCR_05_0_G4W_WOFFSET                     0x0
#define GPIO_T_SCR_05_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_05_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_05_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_T_SCR_05_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_05_0_G3W_SHIFT)
#define GPIO_T_SCR_05_0_G3W_RANGE                       11:11
#define GPIO_T_SCR_05_0_G3W_WOFFSET                     0x0
#define GPIO_T_SCR_05_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_05_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_05_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_T_SCR_05_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_05_0_G2W_SHIFT)
#define GPIO_T_SCR_05_0_G2W_RANGE                       10:10
#define GPIO_T_SCR_05_0_G2W_WOFFSET                     0x0
#define GPIO_T_SCR_05_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_05_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_05_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_T_SCR_05_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_05_0_G1W_SHIFT)
#define GPIO_T_SCR_05_0_G1W_RANGE                       9:9
#define GPIO_T_SCR_05_0_G1W_WOFFSET                     0x0
#define GPIO_T_SCR_05_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_05_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_05_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_T_SCR_05_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_05_0_G0W_SHIFT)
#define GPIO_T_SCR_05_0_G0W_RANGE                       8:8
#define GPIO_T_SCR_05_0_G0W_WOFFSET                     0x0
#define GPIO_T_SCR_05_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_05_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_05_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_T_SCR_05_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_05_0_G7R_SHIFT)
#define GPIO_T_SCR_05_0_G7R_RANGE                       7:7
#define GPIO_T_SCR_05_0_G7R_WOFFSET                     0x0
#define GPIO_T_SCR_05_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_05_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_05_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_T_SCR_05_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_05_0_G6R_SHIFT)
#define GPIO_T_SCR_05_0_G6R_RANGE                       6:6
#define GPIO_T_SCR_05_0_G6R_WOFFSET                     0x0
#define GPIO_T_SCR_05_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_05_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_05_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_T_SCR_05_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_05_0_G5R_SHIFT)
#define GPIO_T_SCR_05_0_G5R_RANGE                       5:5
#define GPIO_T_SCR_05_0_G5R_WOFFSET                     0x0
#define GPIO_T_SCR_05_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_05_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_05_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_T_SCR_05_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_05_0_G4R_SHIFT)
#define GPIO_T_SCR_05_0_G4R_RANGE                       4:4
#define GPIO_T_SCR_05_0_G4R_WOFFSET                     0x0
#define GPIO_T_SCR_05_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_05_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_05_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_T_SCR_05_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_05_0_G3R_SHIFT)
#define GPIO_T_SCR_05_0_G3R_RANGE                       3:3
#define GPIO_T_SCR_05_0_G3R_WOFFSET                     0x0
#define GPIO_T_SCR_05_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_05_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_05_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_T_SCR_05_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_05_0_G2R_SHIFT)
#define GPIO_T_SCR_05_0_G2R_RANGE                       2:2
#define GPIO_T_SCR_05_0_G2R_WOFFSET                     0x0
#define GPIO_T_SCR_05_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_05_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_05_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_T_SCR_05_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_05_0_G1R_SHIFT)
#define GPIO_T_SCR_05_0_G1R_RANGE                       1:1
#define GPIO_T_SCR_05_0_G1R_WOFFSET                     0x0
#define GPIO_T_SCR_05_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_05_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_05_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_T_SCR_05_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_05_0_G0R_SHIFT)
#define GPIO_T_SCR_05_0_G0R_RANGE                       0:0
#define GPIO_T_SCR_05_0_G0R_WOFFSET                     0x0
#define GPIO_T_SCR_05_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_05_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_05_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_T_VM_06_0
#define GPIO_T_VM_06_0                  _MK_ADDR_CONST(0x3130)
#define GPIO_T_VM_06_0_SECURE                   0x0
#define GPIO_T_VM_06_0_DUAL                     0x0
#define GPIO_T_VM_06_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_T_VM_06_0_WORD_COUNT                       0x1
#define GPIO_T_VM_06_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_T_VM_06_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_T_VM_06_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_06_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_T_VM_06_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_T_VM_06_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_T_VM_06_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_T_VM_06_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_06_0_VM1_SHIFT)
#define GPIO_T_VM_06_0_VM1_RANGE                        1:0
#define GPIO_T_VM_06_0_VM1_WOFFSET                      0x0
#define GPIO_T_VM_06_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_06_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_06_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_06_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_06_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_06_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_06_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_T_VM_06_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_06_0_VM2_SHIFT)
#define GPIO_T_VM_06_0_VM2_RANGE                        3:2
#define GPIO_T_VM_06_0_VM2_WOFFSET                      0x0
#define GPIO_T_VM_06_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_06_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_06_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_06_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_06_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_06_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_06_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_T_VM_06_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_06_0_VM3_SHIFT)
#define GPIO_T_VM_06_0_VM3_RANGE                        5:4
#define GPIO_T_VM_06_0_VM3_WOFFSET                      0x0
#define GPIO_T_VM_06_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_06_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_06_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_06_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_06_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_06_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_06_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_T_VM_06_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_06_0_VM4_SHIFT)
#define GPIO_T_VM_06_0_VM4_RANGE                        7:6
#define GPIO_T_VM_06_0_VM4_WOFFSET                      0x0
#define GPIO_T_VM_06_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_06_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_06_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_06_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_06_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_06_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_06_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_T_VM_06_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_06_0_VM5_SHIFT)
#define GPIO_T_VM_06_0_VM5_RANGE                        9:8
#define GPIO_T_VM_06_0_VM5_WOFFSET                      0x0
#define GPIO_T_VM_06_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_06_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_06_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_06_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_06_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_06_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_06_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_T_VM_06_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_06_0_VM6_SHIFT)
#define GPIO_T_VM_06_0_VM6_RANGE                        11:10
#define GPIO_T_VM_06_0_VM6_WOFFSET                      0x0
#define GPIO_T_VM_06_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_06_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_06_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_06_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_06_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_06_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_06_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_T_VM_06_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_06_0_VM7_SHIFT)
#define GPIO_T_VM_06_0_VM7_RANGE                        13:12
#define GPIO_T_VM_06_0_VM7_WOFFSET                      0x0
#define GPIO_T_VM_06_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_06_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_06_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_06_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_06_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_06_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_06_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_T_VM_06_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_06_0_VM8_SHIFT)
#define GPIO_T_VM_06_0_VM8_RANGE                        15:14
#define GPIO_T_VM_06_0_VM8_WOFFSET                      0x0
#define GPIO_T_VM_06_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_06_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_06_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_06_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_06_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_06_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_T_SCR_06_0
#define GPIO_T_SCR_06_0                 _MK_ADDR_CONST(0x3134)
#define GPIO_T_SCR_06_0_SECURE                  0x0
#define GPIO_T_SCR_06_0_DUAL                    0x0
#define GPIO_T_SCR_06_0_SCR                     0
#define GPIO_T_SCR_06_0_WORD_COUNT                      0x1
#define GPIO_T_SCR_06_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_T_SCR_06_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_T_SCR_06_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_T_SCR_06_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_T_SCR_06_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_SCR_06_0_SEC_LCK_SHIFT)
#define GPIO_T_SCR_06_0_SEC_LCK_RANGE                   29:29
#define GPIO_T_SCR_06_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_T_SCR_06_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_06_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_06_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_T_SCR_06_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_SCR_06_0_SEC_WEN_SHIFT)
#define GPIO_T_SCR_06_0_SEC_WEN_RANGE                   28:28
#define GPIO_T_SCR_06_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_T_SCR_06_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_06_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_06_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_T_SCR_06_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_SCR_06_0_SEC_REN_SHIFT)
#define GPIO_T_SCR_06_0_SEC_REN_RANGE                   27:27
#define GPIO_T_SCR_06_0_SEC_REN_WOFFSET                 0x0
#define GPIO_T_SCR_06_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_06_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_06_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_T_SCR_06_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_T_SCR_06_0_SEC_OWNER_SHIFT)
#define GPIO_T_SCR_06_0_SEC_OWNER_RANGE                 26:24
#define GPIO_T_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_T_SCR_06_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_T_SCR_06_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_06_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_T_SCR_06_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_06_0_PR7_SHIFT)
#define GPIO_T_SCR_06_0_PR7_RANGE                       23:23
#define GPIO_T_SCR_06_0_PR7_WOFFSET                     0x0
#define GPIO_T_SCR_06_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_06_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_06_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_T_SCR_06_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_06_0_PR6_SHIFT)
#define GPIO_T_SCR_06_0_PR6_RANGE                       22:22
#define GPIO_T_SCR_06_0_PR6_WOFFSET                     0x0
#define GPIO_T_SCR_06_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_06_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_06_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_T_SCR_06_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_06_0_PR5_SHIFT)
#define GPIO_T_SCR_06_0_PR5_RANGE                       21:21
#define GPIO_T_SCR_06_0_PR5_WOFFSET                     0x0
#define GPIO_T_SCR_06_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_06_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_06_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_T_SCR_06_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_06_0_PR4_SHIFT)
#define GPIO_T_SCR_06_0_PR4_RANGE                       20:20
#define GPIO_T_SCR_06_0_PR4_WOFFSET                     0x0
#define GPIO_T_SCR_06_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_06_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_06_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_T_SCR_06_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_06_0_PR3_SHIFT)
#define GPIO_T_SCR_06_0_PR3_RANGE                       19:19
#define GPIO_T_SCR_06_0_PR3_WOFFSET                     0x0
#define GPIO_T_SCR_06_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_06_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_06_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_T_SCR_06_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_06_0_PR2_SHIFT)
#define GPIO_T_SCR_06_0_PR2_RANGE                       18:18
#define GPIO_T_SCR_06_0_PR2_WOFFSET                     0x0
#define GPIO_T_SCR_06_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_06_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_06_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_T_SCR_06_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_06_0_PR1_SHIFT)
#define GPIO_T_SCR_06_0_PR1_RANGE                       17:17
#define GPIO_T_SCR_06_0_PR1_WOFFSET                     0x0
#define GPIO_T_SCR_06_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_06_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_06_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_T_SCR_06_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_06_0_PR0_SHIFT)
#define GPIO_T_SCR_06_0_PR0_RANGE                       16:16
#define GPIO_T_SCR_06_0_PR0_WOFFSET                     0x0
#define GPIO_T_SCR_06_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_06_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_06_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_T_SCR_06_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_06_0_G7W_SHIFT)
#define GPIO_T_SCR_06_0_G7W_RANGE                       15:15
#define GPIO_T_SCR_06_0_G7W_WOFFSET                     0x0
#define GPIO_T_SCR_06_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_06_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_06_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_T_SCR_06_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_06_0_G6W_SHIFT)
#define GPIO_T_SCR_06_0_G6W_RANGE                       14:14
#define GPIO_T_SCR_06_0_G6W_WOFFSET                     0x0
#define GPIO_T_SCR_06_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_06_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_06_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_T_SCR_06_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_06_0_G5W_SHIFT)
#define GPIO_T_SCR_06_0_G5W_RANGE                       13:13
#define GPIO_T_SCR_06_0_G5W_WOFFSET                     0x0
#define GPIO_T_SCR_06_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_06_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_06_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_T_SCR_06_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_06_0_G4W_SHIFT)
#define GPIO_T_SCR_06_0_G4W_RANGE                       12:12
#define GPIO_T_SCR_06_0_G4W_WOFFSET                     0x0
#define GPIO_T_SCR_06_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_06_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_06_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_T_SCR_06_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_06_0_G3W_SHIFT)
#define GPIO_T_SCR_06_0_G3W_RANGE                       11:11
#define GPIO_T_SCR_06_0_G3W_WOFFSET                     0x0
#define GPIO_T_SCR_06_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_06_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_06_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_T_SCR_06_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_06_0_G2W_SHIFT)
#define GPIO_T_SCR_06_0_G2W_RANGE                       10:10
#define GPIO_T_SCR_06_0_G2W_WOFFSET                     0x0
#define GPIO_T_SCR_06_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_06_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_06_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_T_SCR_06_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_06_0_G1W_SHIFT)
#define GPIO_T_SCR_06_0_G1W_RANGE                       9:9
#define GPIO_T_SCR_06_0_G1W_WOFFSET                     0x0
#define GPIO_T_SCR_06_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_06_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_06_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_T_SCR_06_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_06_0_G0W_SHIFT)
#define GPIO_T_SCR_06_0_G0W_RANGE                       8:8
#define GPIO_T_SCR_06_0_G0W_WOFFSET                     0x0
#define GPIO_T_SCR_06_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_06_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_06_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_T_SCR_06_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_06_0_G7R_SHIFT)
#define GPIO_T_SCR_06_0_G7R_RANGE                       7:7
#define GPIO_T_SCR_06_0_G7R_WOFFSET                     0x0
#define GPIO_T_SCR_06_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_06_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_06_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_T_SCR_06_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_06_0_G6R_SHIFT)
#define GPIO_T_SCR_06_0_G6R_RANGE                       6:6
#define GPIO_T_SCR_06_0_G6R_WOFFSET                     0x0
#define GPIO_T_SCR_06_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_06_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_06_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_T_SCR_06_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_06_0_G5R_SHIFT)
#define GPIO_T_SCR_06_0_G5R_RANGE                       5:5
#define GPIO_T_SCR_06_0_G5R_WOFFSET                     0x0
#define GPIO_T_SCR_06_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_06_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_06_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_T_SCR_06_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_06_0_G4R_SHIFT)
#define GPIO_T_SCR_06_0_G4R_RANGE                       4:4
#define GPIO_T_SCR_06_0_G4R_WOFFSET                     0x0
#define GPIO_T_SCR_06_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_06_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_06_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_T_SCR_06_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_06_0_G3R_SHIFT)
#define GPIO_T_SCR_06_0_G3R_RANGE                       3:3
#define GPIO_T_SCR_06_0_G3R_WOFFSET                     0x0
#define GPIO_T_SCR_06_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_06_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_06_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_T_SCR_06_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_06_0_G2R_SHIFT)
#define GPIO_T_SCR_06_0_G2R_RANGE                       2:2
#define GPIO_T_SCR_06_0_G2R_WOFFSET                     0x0
#define GPIO_T_SCR_06_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_06_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_06_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_T_SCR_06_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_06_0_G1R_SHIFT)
#define GPIO_T_SCR_06_0_G1R_RANGE                       1:1
#define GPIO_T_SCR_06_0_G1R_WOFFSET                     0x0
#define GPIO_T_SCR_06_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_06_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_06_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_T_SCR_06_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_06_0_G0R_SHIFT)
#define GPIO_T_SCR_06_0_G0R_RANGE                       0:0
#define GPIO_T_SCR_06_0_G0R_WOFFSET                     0x0
#define GPIO_T_SCR_06_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_06_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_06_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_T_VM_07_0
#define GPIO_T_VM_07_0                  _MK_ADDR_CONST(0x3138)
#define GPIO_T_VM_07_0_SECURE                   0x0
#define GPIO_T_VM_07_0_DUAL                     0x0
#define GPIO_T_VM_07_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_T_VM_07_0_WORD_COUNT                       0x1
#define GPIO_T_VM_07_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_T_VM_07_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_T_VM_07_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_07_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_T_VM_07_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_T_VM_07_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_T_VM_07_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_T_VM_07_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_07_0_VM1_SHIFT)
#define GPIO_T_VM_07_0_VM1_RANGE                        1:0
#define GPIO_T_VM_07_0_VM1_WOFFSET                      0x0
#define GPIO_T_VM_07_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_07_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_07_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_07_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_07_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_07_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_07_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_T_VM_07_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_07_0_VM2_SHIFT)
#define GPIO_T_VM_07_0_VM2_RANGE                        3:2
#define GPIO_T_VM_07_0_VM2_WOFFSET                      0x0
#define GPIO_T_VM_07_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_07_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_07_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_07_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_07_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_07_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_07_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_T_VM_07_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_07_0_VM3_SHIFT)
#define GPIO_T_VM_07_0_VM3_RANGE                        5:4
#define GPIO_T_VM_07_0_VM3_WOFFSET                      0x0
#define GPIO_T_VM_07_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_07_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_07_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_07_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_07_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_07_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_07_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_T_VM_07_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_07_0_VM4_SHIFT)
#define GPIO_T_VM_07_0_VM4_RANGE                        7:6
#define GPIO_T_VM_07_0_VM4_WOFFSET                      0x0
#define GPIO_T_VM_07_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_07_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_07_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_07_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_07_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_07_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_07_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_T_VM_07_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_07_0_VM5_SHIFT)
#define GPIO_T_VM_07_0_VM5_RANGE                        9:8
#define GPIO_T_VM_07_0_VM5_WOFFSET                      0x0
#define GPIO_T_VM_07_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_07_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_07_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_07_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_07_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_07_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_07_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_T_VM_07_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_07_0_VM6_SHIFT)
#define GPIO_T_VM_07_0_VM6_RANGE                        11:10
#define GPIO_T_VM_07_0_VM6_WOFFSET                      0x0
#define GPIO_T_VM_07_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_07_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_07_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_07_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_07_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_07_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_07_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_T_VM_07_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_07_0_VM7_SHIFT)
#define GPIO_T_VM_07_0_VM7_RANGE                        13:12
#define GPIO_T_VM_07_0_VM7_WOFFSET                      0x0
#define GPIO_T_VM_07_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_07_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_07_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_07_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_07_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_07_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_T_VM_07_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_T_VM_07_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_T_VM_07_0_VM8_SHIFT)
#define GPIO_T_VM_07_0_VM8_RANGE                        15:14
#define GPIO_T_VM_07_0_VM8_WOFFSET                      0x0
#define GPIO_T_VM_07_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_T_VM_07_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_T_VM_07_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_VM_07_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_VM_07_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_VM_07_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_T_SCR_07_0
#define GPIO_T_SCR_07_0                 _MK_ADDR_CONST(0x313c)
#define GPIO_T_SCR_07_0_SECURE                  0x0
#define GPIO_T_SCR_07_0_DUAL                    0x0
#define GPIO_T_SCR_07_0_SCR                     0
#define GPIO_T_SCR_07_0_WORD_COUNT                      0x1
#define GPIO_T_SCR_07_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_T_SCR_07_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_T_SCR_07_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_T_SCR_07_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_T_SCR_07_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_SCR_07_0_SEC_LCK_SHIFT)
#define GPIO_T_SCR_07_0_SEC_LCK_RANGE                   29:29
#define GPIO_T_SCR_07_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_T_SCR_07_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_07_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_07_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_T_SCR_07_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_SCR_07_0_SEC_WEN_SHIFT)
#define GPIO_T_SCR_07_0_SEC_WEN_RANGE                   28:28
#define GPIO_T_SCR_07_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_T_SCR_07_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_07_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_07_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_T_SCR_07_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_SCR_07_0_SEC_REN_SHIFT)
#define GPIO_T_SCR_07_0_SEC_REN_RANGE                   27:27
#define GPIO_T_SCR_07_0_SEC_REN_WOFFSET                 0x0
#define GPIO_T_SCR_07_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_07_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_07_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_T_SCR_07_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_T_SCR_07_0_SEC_OWNER_SHIFT)
#define GPIO_T_SCR_07_0_SEC_OWNER_RANGE                 26:24
#define GPIO_T_SCR_07_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_T_SCR_07_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_T_SCR_07_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_07_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_T_SCR_07_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_07_0_PR7_SHIFT)
#define GPIO_T_SCR_07_0_PR7_RANGE                       23:23
#define GPIO_T_SCR_07_0_PR7_WOFFSET                     0x0
#define GPIO_T_SCR_07_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_07_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_07_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_T_SCR_07_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_07_0_PR6_SHIFT)
#define GPIO_T_SCR_07_0_PR6_RANGE                       22:22
#define GPIO_T_SCR_07_0_PR6_WOFFSET                     0x0
#define GPIO_T_SCR_07_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_07_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_07_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_T_SCR_07_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_07_0_PR5_SHIFT)
#define GPIO_T_SCR_07_0_PR5_RANGE                       21:21
#define GPIO_T_SCR_07_0_PR5_WOFFSET                     0x0
#define GPIO_T_SCR_07_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_07_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_07_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_T_SCR_07_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_07_0_PR4_SHIFT)
#define GPIO_T_SCR_07_0_PR4_RANGE                       20:20
#define GPIO_T_SCR_07_0_PR4_WOFFSET                     0x0
#define GPIO_T_SCR_07_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_07_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_07_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_T_SCR_07_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_07_0_PR3_SHIFT)
#define GPIO_T_SCR_07_0_PR3_RANGE                       19:19
#define GPIO_T_SCR_07_0_PR3_WOFFSET                     0x0
#define GPIO_T_SCR_07_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_07_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_07_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_T_SCR_07_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_07_0_PR2_SHIFT)
#define GPIO_T_SCR_07_0_PR2_RANGE                       18:18
#define GPIO_T_SCR_07_0_PR2_WOFFSET                     0x0
#define GPIO_T_SCR_07_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_07_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_07_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_T_SCR_07_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_07_0_PR1_SHIFT)
#define GPIO_T_SCR_07_0_PR1_RANGE                       17:17
#define GPIO_T_SCR_07_0_PR1_WOFFSET                     0x0
#define GPIO_T_SCR_07_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_07_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_07_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_T_SCR_07_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_07_0_PR0_SHIFT)
#define GPIO_T_SCR_07_0_PR0_RANGE                       16:16
#define GPIO_T_SCR_07_0_PR0_WOFFSET                     0x0
#define GPIO_T_SCR_07_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_07_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_07_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_T_SCR_07_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_07_0_G7W_SHIFT)
#define GPIO_T_SCR_07_0_G7W_RANGE                       15:15
#define GPIO_T_SCR_07_0_G7W_WOFFSET                     0x0
#define GPIO_T_SCR_07_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_07_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_07_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_T_SCR_07_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_07_0_G6W_SHIFT)
#define GPIO_T_SCR_07_0_G6W_RANGE                       14:14
#define GPIO_T_SCR_07_0_G6W_WOFFSET                     0x0
#define GPIO_T_SCR_07_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_07_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_07_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_T_SCR_07_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_07_0_G5W_SHIFT)
#define GPIO_T_SCR_07_0_G5W_RANGE                       13:13
#define GPIO_T_SCR_07_0_G5W_WOFFSET                     0x0
#define GPIO_T_SCR_07_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_07_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_07_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_T_SCR_07_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_07_0_G4W_SHIFT)
#define GPIO_T_SCR_07_0_G4W_RANGE                       12:12
#define GPIO_T_SCR_07_0_G4W_WOFFSET                     0x0
#define GPIO_T_SCR_07_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_07_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_07_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_T_SCR_07_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_07_0_G3W_SHIFT)
#define GPIO_T_SCR_07_0_G3W_RANGE                       11:11
#define GPIO_T_SCR_07_0_G3W_WOFFSET                     0x0
#define GPIO_T_SCR_07_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_07_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_07_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_T_SCR_07_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_07_0_G2W_SHIFT)
#define GPIO_T_SCR_07_0_G2W_RANGE                       10:10
#define GPIO_T_SCR_07_0_G2W_WOFFSET                     0x0
#define GPIO_T_SCR_07_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_07_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_07_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_T_SCR_07_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_07_0_G1W_SHIFT)
#define GPIO_T_SCR_07_0_G1W_RANGE                       9:9
#define GPIO_T_SCR_07_0_G1W_WOFFSET                     0x0
#define GPIO_T_SCR_07_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_07_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_07_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_T_SCR_07_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_07_0_G0W_SHIFT)
#define GPIO_T_SCR_07_0_G0W_RANGE                       8:8
#define GPIO_T_SCR_07_0_G0W_WOFFSET                     0x0
#define GPIO_T_SCR_07_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_07_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_07_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_T_SCR_07_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_07_0_G7R_SHIFT)
#define GPIO_T_SCR_07_0_G7R_RANGE                       7:7
#define GPIO_T_SCR_07_0_G7R_WOFFSET                     0x0
#define GPIO_T_SCR_07_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_07_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_07_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_T_SCR_07_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_07_0_G6R_SHIFT)
#define GPIO_T_SCR_07_0_G6R_RANGE                       6:6
#define GPIO_T_SCR_07_0_G6R_WOFFSET                     0x0
#define GPIO_T_SCR_07_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_07_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_07_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_T_SCR_07_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_07_0_G5R_SHIFT)
#define GPIO_T_SCR_07_0_G5R_RANGE                       5:5
#define GPIO_T_SCR_07_0_G5R_WOFFSET                     0x0
#define GPIO_T_SCR_07_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_07_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_07_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_T_SCR_07_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_07_0_G4R_SHIFT)
#define GPIO_T_SCR_07_0_G4R_RANGE                       4:4
#define GPIO_T_SCR_07_0_G4R_WOFFSET                     0x0
#define GPIO_T_SCR_07_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_07_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_07_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_T_SCR_07_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_07_0_G3R_SHIFT)
#define GPIO_T_SCR_07_0_G3R_RANGE                       3:3
#define GPIO_T_SCR_07_0_G3R_WOFFSET                     0x0
#define GPIO_T_SCR_07_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_07_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_07_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_T_SCR_07_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_07_0_G2R_SHIFT)
#define GPIO_T_SCR_07_0_G2R_RANGE                       2:2
#define GPIO_T_SCR_07_0_G2R_WOFFSET                     0x0
#define GPIO_T_SCR_07_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_07_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_07_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_T_SCR_07_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_07_0_G1R_SHIFT)
#define GPIO_T_SCR_07_0_G1R_RANGE                       1:1
#define GPIO_T_SCR_07_0_G1R_WOFFSET                     0x0
#define GPIO_T_SCR_07_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_07_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_T_SCR_07_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_T_SCR_07_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_SCR_07_0_G0R_SHIFT)
#define GPIO_T_SCR_07_0_G0R_RANGE                       0:0
#define GPIO_T_SCR_07_0_G0R_WOFFSET                     0x0
#define GPIO_T_SCR_07_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_SCR_07_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_SCR_07_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_U_VM_00_0
#define GPIO_U_VM_00_0                  _MK_ADDR_CONST(0x3140)
#define GPIO_U_VM_00_0_SECURE                   0x0
#define GPIO_U_VM_00_0_DUAL                     0x0
#define GPIO_U_VM_00_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_U_VM_00_0_WORD_COUNT                       0x1
#define GPIO_U_VM_00_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_U_VM_00_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_U_VM_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_U_VM_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_U_VM_00_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_U_VM_00_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_U_VM_00_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_U_VM_00_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_U_VM_00_0_VM1_SHIFT)
#define GPIO_U_VM_00_0_VM1_RANGE                        1:0
#define GPIO_U_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_U_VM_00_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_U_VM_00_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_U_VM_00_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_U_VM_00_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_U_VM_00_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_U_VM_00_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_U_VM_00_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_U_VM_00_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_U_VM_00_0_VM2_SHIFT)
#define GPIO_U_VM_00_0_VM2_RANGE                        3:2
#define GPIO_U_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_U_VM_00_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_U_VM_00_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_U_VM_00_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_U_VM_00_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_U_VM_00_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_U_VM_00_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_U_VM_00_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_U_VM_00_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_U_VM_00_0_VM3_SHIFT)
#define GPIO_U_VM_00_0_VM3_RANGE                        5:4
#define GPIO_U_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_U_VM_00_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_U_VM_00_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_U_VM_00_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_U_VM_00_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_U_VM_00_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_U_VM_00_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_U_VM_00_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_U_VM_00_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_U_VM_00_0_VM4_SHIFT)
#define GPIO_U_VM_00_0_VM4_RANGE                        7:6
#define GPIO_U_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_U_VM_00_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_U_VM_00_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_U_VM_00_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_U_VM_00_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_U_VM_00_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_U_VM_00_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_U_VM_00_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_U_VM_00_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_U_VM_00_0_VM5_SHIFT)
#define GPIO_U_VM_00_0_VM5_RANGE                        9:8
#define GPIO_U_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_U_VM_00_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_U_VM_00_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_U_VM_00_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_U_VM_00_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_U_VM_00_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_U_VM_00_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_U_VM_00_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_U_VM_00_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_U_VM_00_0_VM6_SHIFT)
#define GPIO_U_VM_00_0_VM6_RANGE                        11:10
#define GPIO_U_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_U_VM_00_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_U_VM_00_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_U_VM_00_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_U_VM_00_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_U_VM_00_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_U_VM_00_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_U_VM_00_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_U_VM_00_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_U_VM_00_0_VM7_SHIFT)
#define GPIO_U_VM_00_0_VM7_RANGE                        13:12
#define GPIO_U_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_U_VM_00_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_U_VM_00_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_U_VM_00_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_U_VM_00_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_U_VM_00_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_U_VM_00_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_U_VM_00_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_U_VM_00_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_U_VM_00_0_VM8_SHIFT)
#define GPIO_U_VM_00_0_VM8_RANGE                        15:14
#define GPIO_U_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_U_VM_00_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_U_VM_00_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_U_VM_00_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_U_VM_00_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_U_VM_00_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_U_VM_00_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_U_SCR_00_0
#define GPIO_U_SCR_00_0                 _MK_ADDR_CONST(0x3144)
#define GPIO_U_SCR_00_0_SECURE                  0x0
#define GPIO_U_SCR_00_0_DUAL                    0x0
#define GPIO_U_SCR_00_0_SCR                     0
#define GPIO_U_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_U_SCR_00_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_U_SCR_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_U_SCR_00_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_U_SCR_00_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_U_SCR_00_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_U_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_U_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_U_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_U_SCR_00_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_U_SCR_00_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_U_SCR_00_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_U_SCR_00_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_U_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_U_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_U_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_U_SCR_00_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_U_SCR_00_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_U_SCR_00_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_U_SCR_00_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_U_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_U_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_U_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_U_SCR_00_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_U_SCR_00_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_U_SCR_00_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_U_SCR_00_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_U_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_U_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_U_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_U_SCR_00_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_U_SCR_00_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_U_SCR_00_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_U_SCR_00_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_U_SCR_00_0_PR7_SHIFT)
#define GPIO_U_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_U_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_U_SCR_00_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_U_SCR_00_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_U_SCR_00_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_U_SCR_00_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_U_SCR_00_0_PR6_SHIFT)
#define GPIO_U_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_U_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_U_SCR_00_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_U_SCR_00_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_U_SCR_00_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_U_SCR_00_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_U_SCR_00_0_PR5_SHIFT)
#define GPIO_U_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_U_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_U_SCR_00_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_U_SCR_00_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_U_SCR_00_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_U_SCR_00_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_U_SCR_00_0_PR4_SHIFT)
#define GPIO_U_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_U_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_U_SCR_00_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_U_SCR_00_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_U_SCR_00_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_U_SCR_00_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_U_SCR_00_0_PR3_SHIFT)
#define GPIO_U_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_U_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_U_SCR_00_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_U_SCR_00_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_U_SCR_00_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_U_SCR_00_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_U_SCR_00_0_PR2_SHIFT)
#define GPIO_U_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_U_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_U_SCR_00_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_U_SCR_00_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_U_SCR_00_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_U_SCR_00_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_U_SCR_00_0_PR1_SHIFT)
#define GPIO_U_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_U_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_U_SCR_00_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_U_SCR_00_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_U_SCR_00_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_U_SCR_00_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_U_SCR_00_0_PR0_SHIFT)
#define GPIO_U_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_U_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_U_SCR_00_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_U_SCR_00_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_U_SCR_00_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_U_SCR_00_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_U_SCR_00_0_G7W_SHIFT)
#define GPIO_U_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_U_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_U_SCR_00_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_U_SCR_00_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_U_SCR_00_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_U_SCR_00_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_U_SCR_00_0_G6W_SHIFT)
#define GPIO_U_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_U_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_U_SCR_00_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_U_SCR_00_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_U_SCR_00_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_U_SCR_00_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_U_SCR_00_0_G5W_SHIFT)
#define GPIO_U_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_U_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_U_SCR_00_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_U_SCR_00_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_U_SCR_00_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_U_SCR_00_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_U_SCR_00_0_G4W_SHIFT)
#define GPIO_U_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_U_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_U_SCR_00_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_U_SCR_00_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_U_SCR_00_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_U_SCR_00_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_U_SCR_00_0_G3W_SHIFT)
#define GPIO_U_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_U_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_U_SCR_00_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_U_SCR_00_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_U_SCR_00_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_U_SCR_00_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_U_SCR_00_0_G2W_SHIFT)
#define GPIO_U_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_U_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_U_SCR_00_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_U_SCR_00_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_U_SCR_00_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_U_SCR_00_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_U_SCR_00_0_G1W_SHIFT)
#define GPIO_U_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_U_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_U_SCR_00_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_U_SCR_00_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_U_SCR_00_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_U_SCR_00_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_U_SCR_00_0_G0W_SHIFT)
#define GPIO_U_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_U_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_U_SCR_00_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_U_SCR_00_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_U_SCR_00_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_U_SCR_00_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_U_SCR_00_0_G7R_SHIFT)
#define GPIO_U_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_U_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_U_SCR_00_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_U_SCR_00_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_U_SCR_00_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_U_SCR_00_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_U_SCR_00_0_G6R_SHIFT)
#define GPIO_U_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_U_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_U_SCR_00_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_U_SCR_00_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_U_SCR_00_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_U_SCR_00_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_U_SCR_00_0_G5R_SHIFT)
#define GPIO_U_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_U_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_U_SCR_00_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_U_SCR_00_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_U_SCR_00_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_U_SCR_00_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_U_SCR_00_0_G4R_SHIFT)
#define GPIO_U_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_U_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_U_SCR_00_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_U_SCR_00_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_U_SCR_00_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_U_SCR_00_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_U_SCR_00_0_G3R_SHIFT)
#define GPIO_U_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_U_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_U_SCR_00_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_U_SCR_00_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_U_SCR_00_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_U_SCR_00_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_U_SCR_00_0_G2R_SHIFT)
#define GPIO_U_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_U_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_U_SCR_00_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_U_SCR_00_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_U_SCR_00_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_U_SCR_00_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_U_SCR_00_0_G1R_SHIFT)
#define GPIO_U_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_U_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_U_SCR_00_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_U_SCR_00_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_U_SCR_00_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_U_SCR_00_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_U_SCR_00_0_G0R_SHIFT)
#define GPIO_U_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_U_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_U_SCR_00_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_U_SCR_00_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_U_SCR_00_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Reserved address 0x3148

// Reserved address 0x314c

// Reserved address 0x3150

// Reserved address 0x3154

// Reserved address 0x3158

// Reserved address 0x315c

// Reserved address 0x3160

// Reserved address 0x3164

// Reserved address 0x3168

// Reserved address 0x316c

// Reserved address 0x3170

// Reserved address 0x3174

// Reserved address 0x3178

// Reserved address 0x317c

// Register GPIO_CTL3_VM_SCR_0
#define GPIO_CTL3_VM_SCR_0                      _MK_ADDR_CONST(0x3800)
#define GPIO_CTL3_VM_SCR_0_SECURE                       0x0
#define GPIO_CTL3_VM_SCR_0_DUAL                         0x0
#define GPIO_CTL3_VM_SCR_0_SCR                  0
#define GPIO_CTL3_VM_SCR_0_WORD_COUNT                   0x1
#define GPIO_CTL3_VM_SCR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_RESET_MASK                   _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL3_VM_SCR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_READ_MASK                    _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL3_VM_SCR_0_WRITE_MASK                   _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL3_VM_SCR_0_SEC_LCK_SHIFT                        _MK_SHIFT_CONST(29)
#define GPIO_CTL3_VM_SCR_0_SEC_LCK_FIELD                        _MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_SEC_LCK_SHIFT)
#define GPIO_CTL3_VM_SCR_0_SEC_LCK_RANGE                        29:29
#define GPIO_CTL3_VM_SCR_0_SEC_LCK_WOFFSET                      0x0
#define GPIO_CTL3_VM_SCR_0_SEC_LCK_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_SEC_LCK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_SEC_LCK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_SEC_LCK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_SEC_LCK_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_CTL3_VM_SCR_0_SEC_WEN_SHIFT                        _MK_SHIFT_CONST(28)
#define GPIO_CTL3_VM_SCR_0_SEC_WEN_FIELD                        _MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_SEC_WEN_SHIFT)
#define GPIO_CTL3_VM_SCR_0_SEC_WEN_RANGE                        28:28
#define GPIO_CTL3_VM_SCR_0_SEC_WEN_WOFFSET                      0x0
#define GPIO_CTL3_VM_SCR_0_SEC_WEN_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_SEC_WEN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_SEC_WEN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_SEC_WEN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_SEC_WEN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_CTL3_VM_SCR_0_SEC_REN_SHIFT                        _MK_SHIFT_CONST(27)
#define GPIO_CTL3_VM_SCR_0_SEC_REN_FIELD                        _MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_SEC_REN_SHIFT)
#define GPIO_CTL3_VM_SCR_0_SEC_REN_RANGE                        27:27
#define GPIO_CTL3_VM_SCR_0_SEC_REN_WOFFSET                      0x0
#define GPIO_CTL3_VM_SCR_0_SEC_REN_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_SEC_REN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_SEC_REN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_SEC_REN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_SEC_REN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_SEC_REN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_CTL3_VM_SCR_0_SEC_OWNER_SHIFT                      _MK_SHIFT_CONST(24)
#define GPIO_CTL3_VM_SCR_0_SEC_OWNER_FIELD                      _MK_FIELD_CONST(0x7, GPIO_CTL3_VM_SCR_0_SEC_OWNER_SHIFT)
#define GPIO_CTL3_VM_SCR_0_SEC_OWNER_RANGE                      26:24
#define GPIO_CTL3_VM_SCR_0_SEC_OWNER_WOFFSET                    0x0
#define GPIO_CTL3_VM_SCR_0_SEC_OWNER_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_SEC_OWNER_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
#define GPIO_CTL3_VM_SCR_0_SEC_OWNER_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_SEC_OWNER_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_CTL3_VM_SCR_0_PR7_SHIFT                    _MK_SHIFT_CONST(23)
#define GPIO_CTL3_VM_SCR_0_PR7_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_PR7_SHIFT)
#define GPIO_CTL3_VM_SCR_0_PR7_RANGE                    23:23
#define GPIO_CTL3_VM_SCR_0_PR7_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_PR7_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR7_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_PR7_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR7_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR7_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR7_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL3_VM_SCR_0_PR6_SHIFT                    _MK_SHIFT_CONST(22)
#define GPIO_CTL3_VM_SCR_0_PR6_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_PR6_SHIFT)
#define GPIO_CTL3_VM_SCR_0_PR6_RANGE                    22:22
#define GPIO_CTL3_VM_SCR_0_PR6_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_PR6_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR6_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_PR6_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR6_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR6_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL3_VM_SCR_0_PR5_SHIFT                    _MK_SHIFT_CONST(21)
#define GPIO_CTL3_VM_SCR_0_PR5_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_PR5_SHIFT)
#define GPIO_CTL3_VM_SCR_0_PR5_RANGE                    21:21
#define GPIO_CTL3_VM_SCR_0_PR5_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_PR5_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR5_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_PR5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR5_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR5_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL3_VM_SCR_0_PR4_SHIFT                    _MK_SHIFT_CONST(20)
#define GPIO_CTL3_VM_SCR_0_PR4_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_PR4_SHIFT)
#define GPIO_CTL3_VM_SCR_0_PR4_RANGE                    20:20
#define GPIO_CTL3_VM_SCR_0_PR4_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_PR4_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR4_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_PR4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR4_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR4_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL3_VM_SCR_0_PR3_SHIFT                    _MK_SHIFT_CONST(19)
#define GPIO_CTL3_VM_SCR_0_PR3_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_PR3_SHIFT)
#define GPIO_CTL3_VM_SCR_0_PR3_RANGE                    19:19
#define GPIO_CTL3_VM_SCR_0_PR3_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_PR3_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_PR3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR3_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR3_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL3_VM_SCR_0_PR2_SHIFT                    _MK_SHIFT_CONST(18)
#define GPIO_CTL3_VM_SCR_0_PR2_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_PR2_SHIFT)
#define GPIO_CTL3_VM_SCR_0_PR2_RANGE                    18:18
#define GPIO_CTL3_VM_SCR_0_PR2_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_PR2_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_PR2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR2_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR2_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL3_VM_SCR_0_PR1_SHIFT                    _MK_SHIFT_CONST(17)
#define GPIO_CTL3_VM_SCR_0_PR1_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_PR1_SHIFT)
#define GPIO_CTL3_VM_SCR_0_PR1_RANGE                    17:17
#define GPIO_CTL3_VM_SCR_0_PR1_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_PR1_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_PR1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR1_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR1_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL3_VM_SCR_0_PR0_SHIFT                    _MK_SHIFT_CONST(16)
#define GPIO_CTL3_VM_SCR_0_PR0_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_PR0_SHIFT)
#define GPIO_CTL3_VM_SCR_0_PR0_RANGE                    16:16
#define GPIO_CTL3_VM_SCR_0_PR0_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_PR0_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_PR0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR0_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR0_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL3_VM_SCR_0_G7W_SHIFT                    _MK_SHIFT_CONST(15)
#define GPIO_CTL3_VM_SCR_0_G7W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G7W_SHIFT)
#define GPIO_CTL3_VM_SCR_0_G7W_RANGE                    15:15
#define GPIO_CTL3_VM_SCR_0_G7W_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_G7W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G7W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_G7W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G7W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G7W_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G7W_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL3_VM_SCR_0_G6W_SHIFT                    _MK_SHIFT_CONST(14)
#define GPIO_CTL3_VM_SCR_0_G6W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G6W_SHIFT)
#define GPIO_CTL3_VM_SCR_0_G6W_RANGE                    14:14
#define GPIO_CTL3_VM_SCR_0_G6W_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_G6W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G6W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_G6W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G6W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G6W_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G6W_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL3_VM_SCR_0_G5W_SHIFT                    _MK_SHIFT_CONST(13)
#define GPIO_CTL3_VM_SCR_0_G5W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G5W_SHIFT)
#define GPIO_CTL3_VM_SCR_0_G5W_RANGE                    13:13
#define GPIO_CTL3_VM_SCR_0_G5W_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_G5W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G5W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_G5W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G5W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G5W_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G5W_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL3_VM_SCR_0_G4W_SHIFT                    _MK_SHIFT_CONST(12)
#define GPIO_CTL3_VM_SCR_0_G4W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G4W_SHIFT)
#define GPIO_CTL3_VM_SCR_0_G4W_RANGE                    12:12
#define GPIO_CTL3_VM_SCR_0_G4W_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_G4W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G4W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_G4W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G4W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G4W_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G4W_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL3_VM_SCR_0_G3W_SHIFT                    _MK_SHIFT_CONST(11)
#define GPIO_CTL3_VM_SCR_0_G3W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G3W_SHIFT)
#define GPIO_CTL3_VM_SCR_0_G3W_RANGE                    11:11
#define GPIO_CTL3_VM_SCR_0_G3W_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_G3W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G3W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_G3W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G3W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G3W_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G3W_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL3_VM_SCR_0_G2W_SHIFT                    _MK_SHIFT_CONST(10)
#define GPIO_CTL3_VM_SCR_0_G2W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G2W_SHIFT)
#define GPIO_CTL3_VM_SCR_0_G2W_RANGE                    10:10
#define GPIO_CTL3_VM_SCR_0_G2W_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_G2W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G2W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_G2W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G2W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G2W_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G2W_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL3_VM_SCR_0_G1W_SHIFT                    _MK_SHIFT_CONST(9)
#define GPIO_CTL3_VM_SCR_0_G1W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G1W_SHIFT)
#define GPIO_CTL3_VM_SCR_0_G1W_RANGE                    9:9
#define GPIO_CTL3_VM_SCR_0_G1W_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_G1W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G1W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_G1W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G1W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G1W_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G1W_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL3_VM_SCR_0_G0W_SHIFT                    _MK_SHIFT_CONST(8)
#define GPIO_CTL3_VM_SCR_0_G0W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G0W_SHIFT)
#define GPIO_CTL3_VM_SCR_0_G0W_RANGE                    8:8
#define GPIO_CTL3_VM_SCR_0_G0W_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_G0W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G0W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_G0W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G0W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G0W_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G0W_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL3_VM_SCR_0_G7R_SHIFT                    _MK_SHIFT_CONST(7)
#define GPIO_CTL3_VM_SCR_0_G7R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G7R_SHIFT)
#define GPIO_CTL3_VM_SCR_0_G7R_RANGE                    7:7
#define GPIO_CTL3_VM_SCR_0_G7R_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_G7R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G7R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_G7R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G7R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G7R_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G7R_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL3_VM_SCR_0_G6R_SHIFT                    _MK_SHIFT_CONST(6)
#define GPIO_CTL3_VM_SCR_0_G6R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G6R_SHIFT)
#define GPIO_CTL3_VM_SCR_0_G6R_RANGE                    6:6
#define GPIO_CTL3_VM_SCR_0_G6R_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_G6R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G6R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_G6R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G6R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G6R_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G6R_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL3_VM_SCR_0_G5R_SHIFT                    _MK_SHIFT_CONST(5)
#define GPIO_CTL3_VM_SCR_0_G5R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G5R_SHIFT)
#define GPIO_CTL3_VM_SCR_0_G5R_RANGE                    5:5
#define GPIO_CTL3_VM_SCR_0_G5R_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_G5R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G5R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_G5R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G5R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G5R_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G5R_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL3_VM_SCR_0_G4R_SHIFT                    _MK_SHIFT_CONST(4)
#define GPIO_CTL3_VM_SCR_0_G4R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G4R_SHIFT)
#define GPIO_CTL3_VM_SCR_0_G4R_RANGE                    4:4
#define GPIO_CTL3_VM_SCR_0_G4R_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_G4R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G4R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_G4R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G4R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G4R_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G4R_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL3_VM_SCR_0_G3R_SHIFT                    _MK_SHIFT_CONST(3)
#define GPIO_CTL3_VM_SCR_0_G3R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G3R_SHIFT)
#define GPIO_CTL3_VM_SCR_0_G3R_RANGE                    3:3
#define GPIO_CTL3_VM_SCR_0_G3R_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_G3R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G3R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_G3R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G3R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G3R_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G3R_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL3_VM_SCR_0_G2R_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_CTL3_VM_SCR_0_G2R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G2R_SHIFT)
#define GPIO_CTL3_VM_SCR_0_G2R_RANGE                    2:2
#define GPIO_CTL3_VM_SCR_0_G2R_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_G2R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G2R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_G2R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G2R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G2R_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G2R_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL3_VM_SCR_0_G1R_SHIFT                    _MK_SHIFT_CONST(1)
#define GPIO_CTL3_VM_SCR_0_G1R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G1R_SHIFT)
#define GPIO_CTL3_VM_SCR_0_G1R_RANGE                    1:1
#define GPIO_CTL3_VM_SCR_0_G1R_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_G1R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G1R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_G1R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G1R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G1R_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G1R_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL3_VM_SCR_0_G0R_SHIFT                    _MK_SHIFT_CONST(0)
#define GPIO_CTL3_VM_SCR_0_G0R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G0R_SHIFT)
#define GPIO_CTL3_VM_SCR_0_G0R_RANGE                    0:0
#define GPIO_CTL3_VM_SCR_0_G0R_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_G0R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G0R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_G0R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G0R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G0R_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G0R_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0                     _MK_ADDR_CONST(0x3804)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SECURE                      0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_DUAL                        0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SCR                         0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_WORD_COUNT                  0x1
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_RESET_MASK                  _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_READ_MASK                   _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_WRITE_MASK                  _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SHIFT                       _MK_SHIFT_CONST(29)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_RANGE                       29:29
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_WOFFSET                     0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SHIFT                       _MK_SHIFT_CONST(28)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_RANGE                       28:28
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_WOFFSET                     0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SHIFT                       _MK_SHIFT_CONST(27)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_RANGE                       27:27
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_WOFFSET                     0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SHIFT                     _MK_SHIFT_CONST(24)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_FIELD                     _MK_FIELD_CONST(0x7, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_RANGE                     26:24
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_WOFFSET                   0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR7_SHIFT                   _MK_SHIFT_CONST(23)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR7_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR7_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR7_RANGE                   23:23
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR7_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR7_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR7_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR7_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR7_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR7_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR7_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR6_SHIFT                   _MK_SHIFT_CONST(22)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR6_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR6_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR6_RANGE                   22:22
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR6_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR6_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR6_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR6_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR6_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR6_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR6_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR5_SHIFT                   _MK_SHIFT_CONST(21)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR5_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR5_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR5_RANGE                   21:21
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR5_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR5_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR5_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR5_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR5_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR5_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR5_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR4_SHIFT                   _MK_SHIFT_CONST(20)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR4_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR4_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR4_RANGE                   20:20
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR4_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR4_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR4_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR4_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR4_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR3_SHIFT                   _MK_SHIFT_CONST(19)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR3_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR3_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR3_RANGE                   19:19
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR3_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR3_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR3_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR3_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR2_SHIFT                   _MK_SHIFT_CONST(18)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR2_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR2_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR2_RANGE                   18:18
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR2_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR2_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR2_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR2_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR1_SHIFT                   _MK_SHIFT_CONST(17)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR1_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR1_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR1_RANGE                   17:17
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR1_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR1_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR1_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR1_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR0_SHIFT                   _MK_SHIFT_CONST(16)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR0_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR0_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR0_RANGE                   16:16
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR0_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR0_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR0_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR0_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7W_SHIFT                   _MK_SHIFT_CONST(15)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7W_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7W_RANGE                   15:15
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7W_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6W_SHIFT                   _MK_SHIFT_CONST(14)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6W_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6W_RANGE                   14:14
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6W_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5W_SHIFT                   _MK_SHIFT_CONST(13)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5W_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5W_RANGE                   13:13
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5W_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4W_SHIFT                   _MK_SHIFT_CONST(12)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4W_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4W_RANGE                   12:12
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4W_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3W_SHIFT                   _MK_SHIFT_CONST(11)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3W_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3W_RANGE                   11:11
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3W_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2W_SHIFT                   _MK_SHIFT_CONST(10)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2W_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2W_RANGE                   10:10
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2W_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1W_SHIFT                   _MK_SHIFT_CONST(9)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1W_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1W_RANGE                   9:9
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1W_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0W_SHIFT                   _MK_SHIFT_CONST(8)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0W_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0W_RANGE                   8:8
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0W_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7R_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7R_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7R_RANGE                   7:7
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7R_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6R_SHIFT                   _MK_SHIFT_CONST(6)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6R_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6R_RANGE                   6:6
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6R_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5R_SHIFT                   _MK_SHIFT_CONST(5)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5R_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5R_RANGE                   5:5
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5R_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4R_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4R_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4R_RANGE                   4:4
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4R_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3R_SHIFT                   _MK_SHIFT_CONST(3)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3R_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3R_RANGE                   3:3
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3R_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2R_SHIFT                   _MK_SHIFT_CONST(2)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2R_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2R_RANGE                   2:2
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2R_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1R_SHIFT                   _MK_SHIFT_CONST(1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1R_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1R_RANGE                   1:1
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1R_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0R_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0R_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0R_RANGE                   0:0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0R_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_CTL3_INTERRUPT_STATUS_VM_0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0                 _MK_ADDR_CONST(0x3808)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_SECURE                  0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_DUAL                    0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_SCR                     GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_WORD_COUNT                      0x1
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_RESET_MASK                      _MK_MASK_CONST(0xff)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_READ_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_FIELD                  _MK_FIELD_CONST(0xff, GPIO_CTL3_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_RANGE                  7:0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_WOFFSET                        0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register GPIO_CTL3_SCR_0
#define GPIO_CTL3_SCR_0                 _MK_ADDR_CONST(0x380c)
#define GPIO_CTL3_SCR_0_SECURE                  0x0
#define GPIO_CTL3_SCR_0_DUAL                    0x0
#define GPIO_CTL3_SCR_0_SCR                     0
#define GPIO_CTL3_SCR_0_WORD_COUNT                      0x1
#define GPIO_CTL3_SCR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL3_SCR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL3_SCR_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL3_SCR_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_CTL3_SCR_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_SEC_LCK_SHIFT)
#define GPIO_CTL3_SCR_0_SEC_LCK_RANGE                   29:29
#define GPIO_CTL3_SCR_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_CTL3_SCR_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL3_SCR_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_CTL3_SCR_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_SEC_WEN_SHIFT)
#define GPIO_CTL3_SCR_0_SEC_WEN_RANGE                   28:28
#define GPIO_CTL3_SCR_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_CTL3_SCR_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL3_SCR_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_CTL3_SCR_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_SEC_REN_SHIFT)
#define GPIO_CTL3_SCR_0_SEC_REN_RANGE                   27:27
#define GPIO_CTL3_SCR_0_SEC_REN_WOFFSET                 0x0
#define GPIO_CTL3_SCR_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL3_SCR_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_CTL3_SCR_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_CTL3_SCR_0_SEC_OWNER_SHIFT)
#define GPIO_CTL3_SCR_0_SEC_OWNER_RANGE                 26:24
#define GPIO_CTL3_SCR_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_CTL3_SCR_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_CTL3_SCR_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_CTL3_SCR_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_CTL3_SCR_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_PR7_SHIFT)
#define GPIO_CTL3_SCR_0_PR7_RANGE                       23:23
#define GPIO_CTL3_SCR_0_PR7_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL3_SCR_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_CTL3_SCR_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_PR6_SHIFT)
#define GPIO_CTL3_SCR_0_PR6_RANGE                       22:22
#define GPIO_CTL3_SCR_0_PR6_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL3_SCR_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_CTL3_SCR_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_PR5_SHIFT)
#define GPIO_CTL3_SCR_0_PR5_RANGE                       21:21
#define GPIO_CTL3_SCR_0_PR5_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL3_SCR_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_CTL3_SCR_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_PR4_SHIFT)
#define GPIO_CTL3_SCR_0_PR4_RANGE                       20:20
#define GPIO_CTL3_SCR_0_PR4_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL3_SCR_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_CTL3_SCR_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_PR3_SHIFT)
#define GPIO_CTL3_SCR_0_PR3_RANGE                       19:19
#define GPIO_CTL3_SCR_0_PR3_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL3_SCR_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_CTL3_SCR_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_PR2_SHIFT)
#define GPIO_CTL3_SCR_0_PR2_RANGE                       18:18
#define GPIO_CTL3_SCR_0_PR2_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL3_SCR_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_CTL3_SCR_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_PR1_SHIFT)
#define GPIO_CTL3_SCR_0_PR1_RANGE                       17:17
#define GPIO_CTL3_SCR_0_PR1_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL3_SCR_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_CTL3_SCR_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_PR0_SHIFT)
#define GPIO_CTL3_SCR_0_PR0_RANGE                       16:16
#define GPIO_CTL3_SCR_0_PR0_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL3_SCR_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_CTL3_SCR_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G7W_SHIFT)
#define GPIO_CTL3_SCR_0_G7W_RANGE                       15:15
#define GPIO_CTL3_SCR_0_G7W_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL3_SCR_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_CTL3_SCR_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G6W_SHIFT)
#define GPIO_CTL3_SCR_0_G6W_RANGE                       14:14
#define GPIO_CTL3_SCR_0_G6W_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL3_SCR_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_CTL3_SCR_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G5W_SHIFT)
#define GPIO_CTL3_SCR_0_G5W_RANGE                       13:13
#define GPIO_CTL3_SCR_0_G5W_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL3_SCR_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_CTL3_SCR_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G4W_SHIFT)
#define GPIO_CTL3_SCR_0_G4W_RANGE                       12:12
#define GPIO_CTL3_SCR_0_G4W_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL3_SCR_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_CTL3_SCR_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G3W_SHIFT)
#define GPIO_CTL3_SCR_0_G3W_RANGE                       11:11
#define GPIO_CTL3_SCR_0_G3W_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL3_SCR_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_CTL3_SCR_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G2W_SHIFT)
#define GPIO_CTL3_SCR_0_G2W_RANGE                       10:10
#define GPIO_CTL3_SCR_0_G2W_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL3_SCR_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_CTL3_SCR_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G1W_SHIFT)
#define GPIO_CTL3_SCR_0_G1W_RANGE                       9:9
#define GPIO_CTL3_SCR_0_G1W_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL3_SCR_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_CTL3_SCR_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G0W_SHIFT)
#define GPIO_CTL3_SCR_0_G0W_RANGE                       8:8
#define GPIO_CTL3_SCR_0_G0W_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL3_SCR_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_CTL3_SCR_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G7R_SHIFT)
#define GPIO_CTL3_SCR_0_G7R_RANGE                       7:7
#define GPIO_CTL3_SCR_0_G7R_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL3_SCR_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_CTL3_SCR_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G6R_SHIFT)
#define GPIO_CTL3_SCR_0_G6R_RANGE                       6:6
#define GPIO_CTL3_SCR_0_G6R_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL3_SCR_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_CTL3_SCR_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G5R_SHIFT)
#define GPIO_CTL3_SCR_0_G5R_RANGE                       5:5
#define GPIO_CTL3_SCR_0_G5R_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL3_SCR_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_CTL3_SCR_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G4R_SHIFT)
#define GPIO_CTL3_SCR_0_G4R_RANGE                       4:4
#define GPIO_CTL3_SCR_0_G4R_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL3_SCR_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_CTL3_SCR_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G3R_SHIFT)
#define GPIO_CTL3_SCR_0_G3R_RANGE                       3:3
#define GPIO_CTL3_SCR_0_G3R_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL3_SCR_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_CTL3_SCR_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G2R_SHIFT)
#define GPIO_CTL3_SCR_0_G2R_RANGE                       2:2
#define GPIO_CTL3_SCR_0_G2R_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL3_SCR_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_CTL3_SCR_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G1R_SHIFT)
#define GPIO_CTL3_SCR_0_G1R_RANGE                       1:1
#define GPIO_CTL3_SCR_0_G1R_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL3_SCR_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_CTL3_SCR_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G0R_SHIFT)
#define GPIO_CTL3_SCR_0_G0R_RANGE                       0:0
#define GPIO_CTL3_SCR_0_G0R_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_CTL3_ICG_EN_OVERRIDE_0
#define GPIO_CTL3_ICG_EN_OVERRIDE_0                     _MK_ADDR_CONST(0x3810)
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_SECURE                      0x0
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_DUAL                        0x0
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_WORD_COUNT                  0x1
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_FIELD                  _MK_FIELD_CONST(0x1, GPIO_CTL3_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SHIFT)
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_RANGE                  0:0
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_WOFFSET                        0x0
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register GPIO_K_INT0_ROUTE_MAPPING_0
#define GPIO_K_INT0_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x3814)
#define GPIO_K_INT0_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_K_INT0_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_K_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_K_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_K_INT0_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_K_INT0_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_K_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_K_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_INT0_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_K_INT0_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_K_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_K_INT0_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_K_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_K_INT0_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_K_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_K_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_K_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_K_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_K_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_K_INT1_ROUTE_MAPPING_0
#define GPIO_K_INT1_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x3818)
#define GPIO_K_INT1_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_K_INT1_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_K_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_K_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_K_INT1_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_K_INT1_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_K_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_K_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_INT1_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_K_INT1_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_K_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_K_INT1_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_K_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_K_INT1_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_K_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_K_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_K_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_K_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_K_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_K_INT2_ROUTE_MAPPING_0
#define GPIO_K_INT2_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x381c)
#define GPIO_K_INT2_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_K_INT2_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_K_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_K_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_K_INT2_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_K_INT2_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_K_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_K_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_INT2_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_K_INT2_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_K_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_K_INT2_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_K_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_K_INT2_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_K_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_K_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_K_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_K_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_K_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_K_INT3_ROUTE_MAPPING_0
#define GPIO_K_INT3_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x3820)
#define GPIO_K_INT3_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_K_INT3_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_K_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_K_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_K_INT3_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_K_INT3_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_K_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_K_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_INT3_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_K_INT3_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_K_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_K_INT3_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_K_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_K_INT3_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_K_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_K_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_K_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_K_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_K_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_K_INT4_ROUTE_MAPPING_0
#define GPIO_K_INT4_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x3824)
#define GPIO_K_INT4_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_K_INT4_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_K_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_K_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_K_INT4_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_K_INT4_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_K_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_K_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_INT4_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_K_INT4_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_K_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_K_INT4_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_K_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_K_INT4_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_K_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_K_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_K_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_K_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_K_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_K_INT5_ROUTE_MAPPING_0
#define GPIO_K_INT5_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x3828)
#define GPIO_K_INT5_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_K_INT5_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_K_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_K_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_K_INT5_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_K_INT5_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_K_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_K_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_INT5_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_K_INT5_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_K_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_K_INT5_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_K_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_K_INT5_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_K_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_K_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_K_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_K_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_K_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_K_INT6_ROUTE_MAPPING_0
#define GPIO_K_INT6_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x382c)
#define GPIO_K_INT6_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_K_INT6_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_K_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_K_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_K_INT6_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_K_INT6_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_K_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_K_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_INT6_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_K_INT6_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_K_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_K_INT6_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_K_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_K_INT6_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_K_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_K_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_K_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_K_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_K_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_K_INT7_ROUTE_MAPPING_0
#define GPIO_K_INT7_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x3830)
#define GPIO_K_INT7_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_K_INT7_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_K_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_K_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_K_INT7_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_K_INT7_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_K_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_K_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_INT7_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_K_INT7_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_K_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_K_INT7_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_K_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_K_INT7_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_K_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_K_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_K_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_K_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_K_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_L_INT0_ROUTE_MAPPING_0
#define GPIO_L_INT0_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x3834)
#define GPIO_L_INT0_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_L_INT0_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_L_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_L_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_L_INT0_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_L_INT0_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_L_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_L_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_INT0_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xf)
#define GPIO_L_INT0_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_L_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_L_INT0_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xf, GPIO_L_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_L_INT0_ROUTE_MAPPING_0_VAL_RANGE                   3:0
#define GPIO_L_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_L_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define GPIO_L_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_L_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_L_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_L_INT1_ROUTE_MAPPING_0
#define GPIO_L_INT1_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x3838)
#define GPIO_L_INT1_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_L_INT1_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_L_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_L_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_L_INT1_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_L_INT1_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_L_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_L_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_INT1_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xf)
#define GPIO_L_INT1_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_L_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_L_INT1_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xf, GPIO_L_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_L_INT1_ROUTE_MAPPING_0_VAL_RANGE                   3:0
#define GPIO_L_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_L_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define GPIO_L_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_L_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_L_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_L_INT2_ROUTE_MAPPING_0
#define GPIO_L_INT2_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x383c)
#define GPIO_L_INT2_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_L_INT2_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_L_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_L_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_L_INT2_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_L_INT2_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_L_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_L_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_INT2_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xf)
#define GPIO_L_INT2_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_L_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_L_INT2_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xf, GPIO_L_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_L_INT2_ROUTE_MAPPING_0_VAL_RANGE                   3:0
#define GPIO_L_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_L_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define GPIO_L_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_L_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_L_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_L_INT3_ROUTE_MAPPING_0
#define GPIO_L_INT3_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x3840)
#define GPIO_L_INT3_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_L_INT3_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_L_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_L_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_L_INT3_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_L_INT3_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_L_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_L_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_INT3_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xf)
#define GPIO_L_INT3_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_L_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_L_INT3_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xf, GPIO_L_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_L_INT3_ROUTE_MAPPING_0_VAL_RANGE                   3:0
#define GPIO_L_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_L_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define GPIO_L_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_L_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_L_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_L_INT4_ROUTE_MAPPING_0
#define GPIO_L_INT4_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x3844)
#define GPIO_L_INT4_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_L_INT4_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_L_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_L_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_L_INT4_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_L_INT4_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_L_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_L_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_INT4_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xf)
#define GPIO_L_INT4_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_L_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_L_INT4_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xf, GPIO_L_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_L_INT4_ROUTE_MAPPING_0_VAL_RANGE                   3:0
#define GPIO_L_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_L_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define GPIO_L_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_L_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_L_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_L_INT5_ROUTE_MAPPING_0
#define GPIO_L_INT5_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x3848)
#define GPIO_L_INT5_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_L_INT5_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_L_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_L_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_L_INT5_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_L_INT5_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_L_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_L_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_INT5_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xf)
#define GPIO_L_INT5_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_L_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_L_INT5_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xf, GPIO_L_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_L_INT5_ROUTE_MAPPING_0_VAL_RANGE                   3:0
#define GPIO_L_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_L_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define GPIO_L_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_L_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_L_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_L_INT6_ROUTE_MAPPING_0
#define GPIO_L_INT6_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x384c)
#define GPIO_L_INT6_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_L_INT6_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_L_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_L_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_L_INT6_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_L_INT6_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_L_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_L_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_INT6_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xf)
#define GPIO_L_INT6_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_L_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_L_INT6_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xf, GPIO_L_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_L_INT6_ROUTE_MAPPING_0_VAL_RANGE                   3:0
#define GPIO_L_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_L_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define GPIO_L_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_L_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_L_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_L_INT7_ROUTE_MAPPING_0
#define GPIO_L_INT7_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x3850)
#define GPIO_L_INT7_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_L_INT7_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_L_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_L_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_L_INT7_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_L_INT7_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_L_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_L_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_INT7_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xf)
#define GPIO_L_INT7_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_L_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_L_INT7_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xf, GPIO_L_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_L_INT7_ROUTE_MAPPING_0_VAL_RANGE                   3:0
#define GPIO_L_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_L_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define GPIO_L_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_L_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_L_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_FF_INT0_ROUTE_MAPPING_0
#define GPIO_FF_INT0_ROUTE_MAPPING_0                    _MK_ADDR_CONST(0x3854)
#define GPIO_FF_INT0_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_FF_INT0_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_FF_INT0_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
#define GPIO_FF_INT0_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_FF_INT0_ROUTE_MAPPING_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_FF_INT0_ROUTE_MAPPING_0_RESET_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_FF_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_FF_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_INT0_ROUTE_MAPPING_0_READ_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_FF_INT0_ROUTE_MAPPING_0_WRITE_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_FF_INT0_ROUTE_MAPPING_0_VAL_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_FF_INT0_ROUTE_MAPPING_0_VAL_FIELD                  _MK_FIELD_CONST(0x3, GPIO_FF_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_FF_INT0_ROUTE_MAPPING_0_VAL_RANGE                  1:0
#define GPIO_FF_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_FF_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_FF_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define GPIO_FF_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_FF_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_FF_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_FF_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register GPIO_FF_INT1_ROUTE_MAPPING_0
#define GPIO_FF_INT1_ROUTE_MAPPING_0                    _MK_ADDR_CONST(0x3858)
#define GPIO_FF_INT1_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_FF_INT1_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_FF_INT1_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
#define GPIO_FF_INT1_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_FF_INT1_ROUTE_MAPPING_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_FF_INT1_ROUTE_MAPPING_0_RESET_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_FF_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_FF_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_INT1_ROUTE_MAPPING_0_READ_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_FF_INT1_ROUTE_MAPPING_0_WRITE_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_FF_INT1_ROUTE_MAPPING_0_VAL_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_FF_INT1_ROUTE_MAPPING_0_VAL_FIELD                  _MK_FIELD_CONST(0x3, GPIO_FF_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_FF_INT1_ROUTE_MAPPING_0_VAL_RANGE                  1:0
#define GPIO_FF_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_FF_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_FF_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define GPIO_FF_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_FF_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_FF_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_FF_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register GPIO_FF_INT2_ROUTE_MAPPING_0
#define GPIO_FF_INT2_ROUTE_MAPPING_0                    _MK_ADDR_CONST(0x385c)
#define GPIO_FF_INT2_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_FF_INT2_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_FF_INT2_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
#define GPIO_FF_INT2_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_FF_INT2_ROUTE_MAPPING_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_FF_INT2_ROUTE_MAPPING_0_RESET_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_FF_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_FF_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_INT2_ROUTE_MAPPING_0_READ_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_FF_INT2_ROUTE_MAPPING_0_WRITE_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_FF_INT2_ROUTE_MAPPING_0_VAL_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_FF_INT2_ROUTE_MAPPING_0_VAL_FIELD                  _MK_FIELD_CONST(0x3, GPIO_FF_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_FF_INT2_ROUTE_MAPPING_0_VAL_RANGE                  1:0
#define GPIO_FF_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_FF_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_FF_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define GPIO_FF_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_FF_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_FF_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_FF_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register GPIO_FF_INT3_ROUTE_MAPPING_0
#define GPIO_FF_INT3_ROUTE_MAPPING_0                    _MK_ADDR_CONST(0x3860)
#define GPIO_FF_INT3_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_FF_INT3_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_FF_INT3_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
#define GPIO_FF_INT3_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_FF_INT3_ROUTE_MAPPING_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_FF_INT3_ROUTE_MAPPING_0_RESET_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_FF_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_FF_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_INT3_ROUTE_MAPPING_0_READ_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_FF_INT3_ROUTE_MAPPING_0_WRITE_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_FF_INT3_ROUTE_MAPPING_0_VAL_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_FF_INT3_ROUTE_MAPPING_0_VAL_FIELD                  _MK_FIELD_CONST(0x3, GPIO_FF_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_FF_INT3_ROUTE_MAPPING_0_VAL_RANGE                  1:0
#define GPIO_FF_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_FF_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_FF_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define GPIO_FF_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_FF_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_FF_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_FF_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register GPIO_FF_INT4_ROUTE_MAPPING_0
#define GPIO_FF_INT4_ROUTE_MAPPING_0                    _MK_ADDR_CONST(0x3864)
#define GPIO_FF_INT4_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_FF_INT4_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_FF_INT4_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
#define GPIO_FF_INT4_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_FF_INT4_ROUTE_MAPPING_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_FF_INT4_ROUTE_MAPPING_0_RESET_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_FF_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_FF_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_INT4_ROUTE_MAPPING_0_READ_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_FF_INT4_ROUTE_MAPPING_0_WRITE_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_FF_INT4_ROUTE_MAPPING_0_VAL_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_FF_INT4_ROUTE_MAPPING_0_VAL_FIELD                  _MK_FIELD_CONST(0x3, GPIO_FF_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_FF_INT4_ROUTE_MAPPING_0_VAL_RANGE                  1:0
#define GPIO_FF_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_FF_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_FF_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define GPIO_FF_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_FF_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_FF_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_FF_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register GPIO_FF_INT5_ROUTE_MAPPING_0
#define GPIO_FF_INT5_ROUTE_MAPPING_0                    _MK_ADDR_CONST(0x3868)
#define GPIO_FF_INT5_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_FF_INT5_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_FF_INT5_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
#define GPIO_FF_INT5_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_FF_INT5_ROUTE_MAPPING_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_FF_INT5_ROUTE_MAPPING_0_RESET_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_FF_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_FF_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_INT5_ROUTE_MAPPING_0_READ_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_FF_INT5_ROUTE_MAPPING_0_WRITE_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_FF_INT5_ROUTE_MAPPING_0_VAL_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_FF_INT5_ROUTE_MAPPING_0_VAL_FIELD                  _MK_FIELD_CONST(0x3, GPIO_FF_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_FF_INT5_ROUTE_MAPPING_0_VAL_RANGE                  1:0
#define GPIO_FF_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_FF_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_FF_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define GPIO_FF_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_FF_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_FF_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_FF_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register GPIO_FF_INT6_ROUTE_MAPPING_0
#define GPIO_FF_INT6_ROUTE_MAPPING_0                    _MK_ADDR_CONST(0x386c)
#define GPIO_FF_INT6_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_FF_INT6_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_FF_INT6_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
#define GPIO_FF_INT6_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_FF_INT6_ROUTE_MAPPING_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_FF_INT6_ROUTE_MAPPING_0_RESET_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_FF_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_FF_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_INT6_ROUTE_MAPPING_0_READ_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_FF_INT6_ROUTE_MAPPING_0_WRITE_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_FF_INT6_ROUTE_MAPPING_0_VAL_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_FF_INT6_ROUTE_MAPPING_0_VAL_FIELD                  _MK_FIELD_CONST(0x3, GPIO_FF_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_FF_INT6_ROUTE_MAPPING_0_VAL_RANGE                  1:0
#define GPIO_FF_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_FF_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_FF_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define GPIO_FF_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_FF_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_FF_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_FF_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register GPIO_FF_INT7_ROUTE_MAPPING_0
#define GPIO_FF_INT7_ROUTE_MAPPING_0                    _MK_ADDR_CONST(0x3870)
#define GPIO_FF_INT7_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_FF_INT7_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_FF_INT7_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
#define GPIO_FF_INT7_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_FF_INT7_ROUTE_MAPPING_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_FF_INT7_ROUTE_MAPPING_0_RESET_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_FF_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_FF_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_INT7_ROUTE_MAPPING_0_READ_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_FF_INT7_ROUTE_MAPPING_0_WRITE_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_FF_INT7_ROUTE_MAPPING_0_VAL_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_FF_INT7_ROUTE_MAPPING_0_VAL_FIELD                  _MK_FIELD_CONST(0x3, GPIO_FF_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_FF_INT7_ROUTE_MAPPING_0_VAL_RANGE                  1:0
#define GPIO_FF_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_FF_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_FF_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define GPIO_FF_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_FF_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_FF_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_FF_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register GPIO_S_INT0_ROUTE_MAPPING_0
#define GPIO_S_INT0_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x3874)
#define GPIO_S_INT0_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_S_INT0_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_S_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_S_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_S_INT0_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_S_INT0_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_S_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_S_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_INT0_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_S_INT0_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_S_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_S_INT0_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_S_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_S_INT0_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_S_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_S_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_S_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_S_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_S_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_S_INT1_ROUTE_MAPPING_0
#define GPIO_S_INT1_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x3878)
#define GPIO_S_INT1_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_S_INT1_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_S_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_S_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_S_INT1_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_S_INT1_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_S_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_S_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_INT1_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_S_INT1_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_S_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_S_INT1_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_S_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_S_INT1_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_S_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_S_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_S_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_S_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_S_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_S_INT2_ROUTE_MAPPING_0
#define GPIO_S_INT2_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x387c)
#define GPIO_S_INT2_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_S_INT2_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_S_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_S_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_S_INT2_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_S_INT2_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_S_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_S_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_INT2_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_S_INT2_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_S_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_S_INT2_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_S_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_S_INT2_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_S_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_S_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_S_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_S_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_S_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_S_INT3_ROUTE_MAPPING_0
#define GPIO_S_INT3_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x3880)
#define GPIO_S_INT3_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_S_INT3_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_S_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_S_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_S_INT3_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_S_INT3_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_S_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_S_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_INT3_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_S_INT3_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_S_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_S_INT3_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_S_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_S_INT3_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_S_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_S_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_S_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_S_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_S_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_S_INT4_ROUTE_MAPPING_0
#define GPIO_S_INT4_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x3884)
#define GPIO_S_INT4_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_S_INT4_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_S_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_S_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_S_INT4_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_S_INT4_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_S_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_S_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_INT4_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_S_INT4_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_S_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_S_INT4_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_S_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_S_INT4_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_S_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_S_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_S_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_S_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_S_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_S_INT5_ROUTE_MAPPING_0
#define GPIO_S_INT5_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x3888)
#define GPIO_S_INT5_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_S_INT5_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_S_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_S_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_S_INT5_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_S_INT5_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_S_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_S_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_INT5_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_S_INT5_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_S_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_S_INT5_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_S_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_S_INT5_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_S_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_S_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_S_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_S_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_S_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_S_INT6_ROUTE_MAPPING_0
#define GPIO_S_INT6_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x388c)
#define GPIO_S_INT6_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_S_INT6_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_S_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_S_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_S_INT6_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_S_INT6_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_S_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_S_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_INT6_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_S_INT6_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_S_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_S_INT6_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_S_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_S_INT6_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_S_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_S_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_S_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_S_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_S_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_S_INT7_ROUTE_MAPPING_0
#define GPIO_S_INT7_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x3890)
#define GPIO_S_INT7_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_S_INT7_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_S_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_S_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_S_INT7_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_S_INT7_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_S_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_S_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_INT7_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_S_INT7_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_S_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_S_INT7_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_S_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_S_INT7_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_S_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_S_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_S_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_S_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_S_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_T_INT0_ROUTE_MAPPING_0
#define GPIO_T_INT0_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x3894)
#define GPIO_T_INT0_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_T_INT0_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_T_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_T_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_T_INT0_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_T_INT0_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_T_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_T_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_INT0_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_T_INT0_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_T_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_T_INT0_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_T_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_T_INT0_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_T_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_T_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_T_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_T_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_T_INT1_ROUTE_MAPPING_0
#define GPIO_T_INT1_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x3898)
#define GPIO_T_INT1_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_T_INT1_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_T_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_T_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_T_INT1_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_T_INT1_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_T_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_T_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_INT1_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_T_INT1_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_T_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_T_INT1_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_T_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_T_INT1_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_T_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_T_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_T_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_T_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_T_INT2_ROUTE_MAPPING_0
#define GPIO_T_INT2_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x389c)
#define GPIO_T_INT2_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_T_INT2_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_T_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_T_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_T_INT2_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_T_INT2_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_T_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_T_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_INT2_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_T_INT2_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_T_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_T_INT2_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_T_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_T_INT2_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_T_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_T_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_T_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_T_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_T_INT3_ROUTE_MAPPING_0
#define GPIO_T_INT3_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x38a0)
#define GPIO_T_INT3_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_T_INT3_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_T_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_T_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_T_INT3_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_T_INT3_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_T_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_T_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_INT3_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_T_INT3_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_T_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_T_INT3_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_T_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_T_INT3_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_T_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_T_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_T_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_T_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_T_INT4_ROUTE_MAPPING_0
#define GPIO_T_INT4_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x38a4)
#define GPIO_T_INT4_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_T_INT4_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_T_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_T_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_T_INT4_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_T_INT4_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_T_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_T_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_INT4_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_T_INT4_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_T_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_T_INT4_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_T_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_T_INT4_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_T_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_T_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_T_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_T_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_T_INT5_ROUTE_MAPPING_0
#define GPIO_T_INT5_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x38a8)
#define GPIO_T_INT5_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_T_INT5_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_T_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_T_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_T_INT5_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_T_INT5_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_T_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_T_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_INT5_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_T_INT5_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_T_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_T_INT5_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_T_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_T_INT5_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_T_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_T_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_T_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_T_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_T_INT6_ROUTE_MAPPING_0
#define GPIO_T_INT6_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x38ac)
#define GPIO_T_INT6_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_T_INT6_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_T_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_T_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_T_INT6_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_T_INT6_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_T_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_T_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_INT6_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_T_INT6_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_T_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_T_INT6_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_T_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_T_INT6_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_T_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_T_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_T_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_T_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_T_INT7_ROUTE_MAPPING_0
#define GPIO_T_INT7_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x38b0)
#define GPIO_T_INT7_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_T_INT7_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_T_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_T_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_T_INT7_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_T_INT7_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_T_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_T_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_INT7_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_T_INT7_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_T_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_T_INT7_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_T_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_T_INT7_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_T_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_T_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_T_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_T_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_U_INT0_ROUTE_MAPPING_0
#define GPIO_U_INT0_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x38b4)
#define GPIO_U_INT0_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_U_INT0_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_U_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_U_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_U_INT0_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_U_INT0_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_U_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_U_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_U_INT0_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_U_INT0_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_U_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_U_INT0_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_U_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_U_INT0_ROUTE_MAPPING_0_VAL_RANGE                   0:0
#define GPIO_U_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_U_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_U_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_U_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_U_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_U_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_U_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_U_INT1_ROUTE_MAPPING_0
#define GPIO_U_INT1_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x38b8)
#define GPIO_U_INT1_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_U_INT1_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_U_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_U_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_U_INT1_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_U_INT1_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_U_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_U_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_U_INT1_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_U_INT1_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_U_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_U_INT1_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_U_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_U_INT1_ROUTE_MAPPING_0_VAL_RANGE                   0:0
#define GPIO_U_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_U_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_U_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_U_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_U_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_U_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_U_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_U_INT2_ROUTE_MAPPING_0
#define GPIO_U_INT2_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x38bc)
#define GPIO_U_INT2_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_U_INT2_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_U_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_U_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_U_INT2_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_U_INT2_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_U_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_U_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_U_INT2_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_U_INT2_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_U_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_U_INT2_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_U_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_U_INT2_ROUTE_MAPPING_0_VAL_RANGE                   0:0
#define GPIO_U_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_U_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_U_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_U_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_U_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_U_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_U_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_U_INT3_ROUTE_MAPPING_0
#define GPIO_U_INT3_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x38c0)
#define GPIO_U_INT3_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_U_INT3_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_U_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_U_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_U_INT3_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_U_INT3_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_U_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_U_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_U_INT3_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_U_INT3_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_U_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_U_INT3_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_U_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_U_INT3_ROUTE_MAPPING_0_VAL_RANGE                   0:0
#define GPIO_U_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_U_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_U_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_U_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_U_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_U_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_U_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_U_INT4_ROUTE_MAPPING_0
#define GPIO_U_INT4_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x38c4)
#define GPIO_U_INT4_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_U_INT4_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_U_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_U_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_U_INT4_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_U_INT4_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_U_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_U_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_U_INT4_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_U_INT4_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_U_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_U_INT4_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_U_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_U_INT4_ROUTE_MAPPING_0_VAL_RANGE                   0:0
#define GPIO_U_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_U_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_U_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_U_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_U_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_U_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_U_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_U_INT5_ROUTE_MAPPING_0
#define GPIO_U_INT5_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x38c8)
#define GPIO_U_INT5_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_U_INT5_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_U_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_U_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_U_INT5_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_U_INT5_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_U_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_U_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_U_INT5_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_U_INT5_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_U_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_U_INT5_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_U_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_U_INT5_ROUTE_MAPPING_0_VAL_RANGE                   0:0
#define GPIO_U_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_U_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_U_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_U_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_U_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_U_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_U_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_U_INT6_ROUTE_MAPPING_0
#define GPIO_U_INT6_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x38cc)
#define GPIO_U_INT6_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_U_INT6_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_U_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_U_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_U_INT6_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_U_INT6_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_U_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_U_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_U_INT6_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_U_INT6_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_U_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_U_INT6_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_U_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_U_INT6_ROUTE_MAPPING_0_VAL_RANGE                   0:0
#define GPIO_U_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_U_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_U_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_U_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_U_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_U_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_U_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_U_INT7_ROUTE_MAPPING_0
#define GPIO_U_INT7_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x38d0)
#define GPIO_U_INT7_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_U_INT7_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_U_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_U_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_U_INT7_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_U_INT7_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_U_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_U_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_U_INT7_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_U_INT7_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_U_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_U_INT7_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_U_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_U_INT7_ROUTE_MAPPING_0_VAL_RANGE                   0:0
#define GPIO_U_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_U_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_U_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_U_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_U_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_U_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_U_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_CTL3_SPARE_0
#define GPIO_CTL3_SPARE_0                       _MK_ADDR_CONST(0x38d4)
#define GPIO_CTL3_SPARE_0_SECURE                        0x0
#define GPIO_CTL3_SPARE_0_DUAL                  0x0
#define GPIO_CTL3_SPARE_0_SCR                   0
#define GPIO_CTL3_SPARE_0_WORD_COUNT                    0x1
#define GPIO_CTL3_SPARE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SPARE_0_RESET_MASK                    _MK_MASK_CONST(0xffff)
#define GPIO_CTL3_SPARE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SPARE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SPARE_0_READ_MASK                     _MK_MASK_CONST(0xffff)
#define GPIO_CTL3_SPARE_0_WRITE_MASK                    _MK_MASK_CONST(0xffff)
#define GPIO_CTL3_SPARE_0_SPARE_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_CTL3_SPARE_0_SPARE_FIELD                   _MK_FIELD_CONST(0xffff, GPIO_CTL3_SPARE_0_SPARE_SHIFT)
#define GPIO_CTL3_SPARE_0_SPARE_RANGE                   15:0
#define GPIO_CTL3_SPARE_0_SPARE_WOFFSET                 0x0
#define GPIO_CTL3_SPARE_0_SPARE_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SPARE_0_SPARE_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define GPIO_CTL3_SPARE_0_SPARE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SPARE_0_SPARE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SPARE_0_SPARE_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL3_SPARE_0_SPARE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_G_VM_00_0
#define GPIO_G_VM_00_0                  _MK_ADDR_CONST(0x4000)
#define GPIO_G_VM_00_0_SECURE                   0x0
#define GPIO_G_VM_00_0_DUAL                     0x0
#define GPIO_G_VM_00_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_G_VM_00_0_WORD_COUNT                       0x1
#define GPIO_G_VM_00_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_00_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_00_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_00_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_G_VM_00_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_00_0_VM1_SHIFT)
#define GPIO_G_VM_00_0_VM1_RANGE                        1:0
#define GPIO_G_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_G_VM_00_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_00_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_00_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_00_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_G_VM_00_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_00_0_VM2_SHIFT)
#define GPIO_G_VM_00_0_VM2_RANGE                        3:2
#define GPIO_G_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_G_VM_00_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_00_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_00_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_00_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_G_VM_00_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_00_0_VM3_SHIFT)
#define GPIO_G_VM_00_0_VM3_RANGE                        5:4
#define GPIO_G_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_G_VM_00_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_00_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_00_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_00_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_G_VM_00_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_00_0_VM4_SHIFT)
#define GPIO_G_VM_00_0_VM4_RANGE                        7:6
#define GPIO_G_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_G_VM_00_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_00_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_00_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_00_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_G_VM_00_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_00_0_VM5_SHIFT)
#define GPIO_G_VM_00_0_VM5_RANGE                        9:8
#define GPIO_G_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_G_VM_00_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_00_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_00_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_00_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_G_VM_00_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_00_0_VM6_SHIFT)
#define GPIO_G_VM_00_0_VM6_RANGE                        11:10
#define GPIO_G_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_G_VM_00_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_00_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_00_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_00_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_G_VM_00_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_00_0_VM7_SHIFT)
#define GPIO_G_VM_00_0_VM7_RANGE                        13:12
#define GPIO_G_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_G_VM_00_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_00_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_00_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_00_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_G_VM_00_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_00_0_VM8_SHIFT)
#define GPIO_G_VM_00_0_VM8_RANGE                        15:14
#define GPIO_G_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_G_VM_00_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_00_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_00_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_G_SCR_00_0
#define GPIO_G_SCR_00_0                 _MK_ADDR_CONST(0x4004)
#define GPIO_G_SCR_00_0_SECURE                  0x0
#define GPIO_G_SCR_00_0_DUAL                    0x0
#define GPIO_G_SCR_00_0_SCR                     0
#define GPIO_G_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_G_SCR_00_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_00_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_00_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_G_SCR_00_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_G_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_G_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_G_SCR_00_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_00_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_G_SCR_00_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_G_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_G_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_G_SCR_00_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_00_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_G_SCR_00_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_G_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_G_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_G_SCR_00_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_00_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_G_SCR_00_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_G_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_G_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_G_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_G_SCR_00_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_G_SCR_00_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_00_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_G_SCR_00_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_PR7_SHIFT)
#define GPIO_G_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_G_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_00_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_G_SCR_00_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_PR6_SHIFT)
#define GPIO_G_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_G_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_00_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_G_SCR_00_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_PR5_SHIFT)
#define GPIO_G_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_G_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_00_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_G_SCR_00_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_PR4_SHIFT)
#define GPIO_G_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_G_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_00_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_G_SCR_00_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_PR3_SHIFT)
#define GPIO_G_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_G_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_00_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_G_SCR_00_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_PR2_SHIFT)
#define GPIO_G_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_G_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_00_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_G_SCR_00_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_PR1_SHIFT)
#define GPIO_G_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_G_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_00_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_G_SCR_00_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_PR0_SHIFT)
#define GPIO_G_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_G_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_00_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_G_SCR_00_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G7W_SHIFT)
#define GPIO_G_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_G_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_00_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_G_SCR_00_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G6W_SHIFT)
#define GPIO_G_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_G_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_00_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_G_SCR_00_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G5W_SHIFT)
#define GPIO_G_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_G_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_00_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_G_SCR_00_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G4W_SHIFT)
#define GPIO_G_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_G_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_00_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_G_SCR_00_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G3W_SHIFT)
#define GPIO_G_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_G_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_00_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_G_SCR_00_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G2W_SHIFT)
#define GPIO_G_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_G_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_00_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_G_SCR_00_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G1W_SHIFT)
#define GPIO_G_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_G_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_00_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_G_SCR_00_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G0W_SHIFT)
#define GPIO_G_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_G_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_00_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_G_SCR_00_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G7R_SHIFT)
#define GPIO_G_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_G_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_00_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_G_SCR_00_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G6R_SHIFT)
#define GPIO_G_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_G_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_00_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_G_SCR_00_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G5R_SHIFT)
#define GPIO_G_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_G_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_00_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_G_SCR_00_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G4R_SHIFT)
#define GPIO_G_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_G_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_00_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_G_SCR_00_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G3R_SHIFT)
#define GPIO_G_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_G_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_00_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_G_SCR_00_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G2R_SHIFT)
#define GPIO_G_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_G_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_00_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_G_SCR_00_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G1R_SHIFT)
#define GPIO_G_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_G_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_00_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_G_SCR_00_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G0R_SHIFT)
#define GPIO_G_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_G_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_G_VM_01_0
#define GPIO_G_VM_01_0                  _MK_ADDR_CONST(0x4008)
#define GPIO_G_VM_01_0_SECURE                   0x0
#define GPIO_G_VM_01_0_DUAL                     0x0
#define GPIO_G_VM_01_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_G_VM_01_0_WORD_COUNT                       0x1
#define GPIO_G_VM_01_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_01_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_01_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_01_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_G_VM_01_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_01_0_VM1_SHIFT)
#define GPIO_G_VM_01_0_VM1_RANGE                        1:0
#define GPIO_G_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_G_VM_01_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_01_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_01_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_01_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_G_VM_01_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_01_0_VM2_SHIFT)
#define GPIO_G_VM_01_0_VM2_RANGE                        3:2
#define GPIO_G_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_G_VM_01_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_01_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_01_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_01_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_G_VM_01_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_01_0_VM3_SHIFT)
#define GPIO_G_VM_01_0_VM3_RANGE                        5:4
#define GPIO_G_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_G_VM_01_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_01_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_01_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_01_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_G_VM_01_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_01_0_VM4_SHIFT)
#define GPIO_G_VM_01_0_VM4_RANGE                        7:6
#define GPIO_G_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_G_VM_01_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_01_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_01_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_01_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_G_VM_01_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_01_0_VM5_SHIFT)
#define GPIO_G_VM_01_0_VM5_RANGE                        9:8
#define GPIO_G_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_G_VM_01_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_01_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_01_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_01_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_G_VM_01_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_01_0_VM6_SHIFT)
#define GPIO_G_VM_01_0_VM6_RANGE                        11:10
#define GPIO_G_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_G_VM_01_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_01_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_01_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_01_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_G_VM_01_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_01_0_VM7_SHIFT)
#define GPIO_G_VM_01_0_VM7_RANGE                        13:12
#define GPIO_G_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_G_VM_01_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_01_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_01_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_01_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_G_VM_01_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_01_0_VM8_SHIFT)
#define GPIO_G_VM_01_0_VM8_RANGE                        15:14
#define GPIO_G_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_G_VM_01_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_01_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_01_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_G_SCR_01_0
#define GPIO_G_SCR_01_0                 _MK_ADDR_CONST(0x400c)
#define GPIO_G_SCR_01_0_SECURE                  0x0
#define GPIO_G_SCR_01_0_DUAL                    0x0
#define GPIO_G_SCR_01_0_SCR                     0
#define GPIO_G_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_G_SCR_01_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_01_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_01_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_01_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_G_SCR_01_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_G_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_G_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_G_SCR_01_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_01_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_G_SCR_01_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_G_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_G_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_G_SCR_01_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_01_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_G_SCR_01_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_G_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_G_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_G_SCR_01_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_01_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_G_SCR_01_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_G_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_G_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_G_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_G_SCR_01_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_G_SCR_01_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_01_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_G_SCR_01_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_PR7_SHIFT)
#define GPIO_G_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_G_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_01_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_G_SCR_01_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_PR6_SHIFT)
#define GPIO_G_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_G_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_01_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_G_SCR_01_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_PR5_SHIFT)
#define GPIO_G_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_G_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_01_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_G_SCR_01_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_PR4_SHIFT)
#define GPIO_G_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_G_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_01_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_G_SCR_01_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_PR3_SHIFT)
#define GPIO_G_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_G_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_01_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_G_SCR_01_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_PR2_SHIFT)
#define GPIO_G_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_G_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_01_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_G_SCR_01_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_PR1_SHIFT)
#define GPIO_G_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_G_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_01_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_G_SCR_01_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_PR0_SHIFT)
#define GPIO_G_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_G_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_01_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_G_SCR_01_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G7W_SHIFT)
#define GPIO_G_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_G_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_01_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_G_SCR_01_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G6W_SHIFT)
#define GPIO_G_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_G_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_01_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_G_SCR_01_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G5W_SHIFT)
#define GPIO_G_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_G_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_01_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_G_SCR_01_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G4W_SHIFT)
#define GPIO_G_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_G_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_01_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_G_SCR_01_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G3W_SHIFT)
#define GPIO_G_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_G_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_01_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_G_SCR_01_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G2W_SHIFT)
#define GPIO_G_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_G_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_01_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_G_SCR_01_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G1W_SHIFT)
#define GPIO_G_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_G_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_01_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_G_SCR_01_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G0W_SHIFT)
#define GPIO_G_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_G_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_01_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_G_SCR_01_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G7R_SHIFT)
#define GPIO_G_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_G_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_01_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_G_SCR_01_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G6R_SHIFT)
#define GPIO_G_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_G_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_01_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_G_SCR_01_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G5R_SHIFT)
#define GPIO_G_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_G_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_01_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_G_SCR_01_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G4R_SHIFT)
#define GPIO_G_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_G_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_01_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_G_SCR_01_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G3R_SHIFT)
#define GPIO_G_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_G_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_01_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_G_SCR_01_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G2R_SHIFT)
#define GPIO_G_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_G_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_01_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_G_SCR_01_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G1R_SHIFT)
#define GPIO_G_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_G_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_01_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_G_SCR_01_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G0R_SHIFT)
#define GPIO_G_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_G_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_G_VM_02_0
#define GPIO_G_VM_02_0                  _MK_ADDR_CONST(0x4010)
#define GPIO_G_VM_02_0_SECURE                   0x0
#define GPIO_G_VM_02_0_DUAL                     0x0
#define GPIO_G_VM_02_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_G_VM_02_0_WORD_COUNT                       0x1
#define GPIO_G_VM_02_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_02_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_02_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_02_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_G_VM_02_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_02_0_VM1_SHIFT)
#define GPIO_G_VM_02_0_VM1_RANGE                        1:0
#define GPIO_G_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_G_VM_02_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_02_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_02_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_02_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_G_VM_02_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_02_0_VM2_SHIFT)
#define GPIO_G_VM_02_0_VM2_RANGE                        3:2
#define GPIO_G_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_G_VM_02_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_02_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_02_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_02_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_G_VM_02_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_02_0_VM3_SHIFT)
#define GPIO_G_VM_02_0_VM3_RANGE                        5:4
#define GPIO_G_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_G_VM_02_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_02_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_02_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_02_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_G_VM_02_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_02_0_VM4_SHIFT)
#define GPIO_G_VM_02_0_VM4_RANGE                        7:6
#define GPIO_G_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_G_VM_02_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_02_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_02_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_02_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_G_VM_02_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_02_0_VM5_SHIFT)
#define GPIO_G_VM_02_0_VM5_RANGE                        9:8
#define GPIO_G_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_G_VM_02_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_02_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_02_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_02_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_G_VM_02_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_02_0_VM6_SHIFT)
#define GPIO_G_VM_02_0_VM6_RANGE                        11:10
#define GPIO_G_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_G_VM_02_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_02_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_02_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_02_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_G_VM_02_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_02_0_VM7_SHIFT)
#define GPIO_G_VM_02_0_VM7_RANGE                        13:12
#define GPIO_G_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_G_VM_02_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_02_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_02_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_02_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_G_VM_02_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_02_0_VM8_SHIFT)
#define GPIO_G_VM_02_0_VM8_RANGE                        15:14
#define GPIO_G_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_G_VM_02_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_02_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_02_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_G_SCR_02_0
#define GPIO_G_SCR_02_0                 _MK_ADDR_CONST(0x4014)
#define GPIO_G_SCR_02_0_SECURE                  0x0
#define GPIO_G_SCR_02_0_DUAL                    0x0
#define GPIO_G_SCR_02_0_SCR                     0
#define GPIO_G_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_G_SCR_02_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_02_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_02_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_02_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_G_SCR_02_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_G_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_G_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_G_SCR_02_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_02_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_G_SCR_02_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_G_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_G_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_G_SCR_02_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_02_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_G_SCR_02_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_G_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_G_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_G_SCR_02_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_02_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_G_SCR_02_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_G_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_G_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_G_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_G_SCR_02_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_G_SCR_02_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_02_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_G_SCR_02_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_PR7_SHIFT)
#define GPIO_G_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_G_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_02_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_G_SCR_02_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_PR6_SHIFT)
#define GPIO_G_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_G_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_02_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_G_SCR_02_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_PR5_SHIFT)
#define GPIO_G_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_G_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_02_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_G_SCR_02_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_PR4_SHIFT)
#define GPIO_G_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_G_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_02_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_G_SCR_02_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_PR3_SHIFT)
#define GPIO_G_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_G_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_02_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_G_SCR_02_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_PR2_SHIFT)
#define GPIO_G_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_G_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_02_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_G_SCR_02_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_PR1_SHIFT)
#define GPIO_G_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_G_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_02_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_G_SCR_02_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_PR0_SHIFT)
#define GPIO_G_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_G_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_02_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_G_SCR_02_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G7W_SHIFT)
#define GPIO_G_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_G_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_02_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_G_SCR_02_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G6W_SHIFT)
#define GPIO_G_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_G_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_02_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_G_SCR_02_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G5W_SHIFT)
#define GPIO_G_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_G_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_02_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_G_SCR_02_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G4W_SHIFT)
#define GPIO_G_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_G_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_02_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_G_SCR_02_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G3W_SHIFT)
#define GPIO_G_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_G_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_02_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_G_SCR_02_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G2W_SHIFT)
#define GPIO_G_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_G_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_02_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_G_SCR_02_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G1W_SHIFT)
#define GPIO_G_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_G_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_02_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_G_SCR_02_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G0W_SHIFT)
#define GPIO_G_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_G_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_02_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_G_SCR_02_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G7R_SHIFT)
#define GPIO_G_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_G_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_02_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_G_SCR_02_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G6R_SHIFT)
#define GPIO_G_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_G_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_02_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_G_SCR_02_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G5R_SHIFT)
#define GPIO_G_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_G_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_02_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_G_SCR_02_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G4R_SHIFT)
#define GPIO_G_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_G_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_02_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_G_SCR_02_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G3R_SHIFT)
#define GPIO_G_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_G_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_02_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_G_SCR_02_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G2R_SHIFT)
#define GPIO_G_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_G_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_02_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_G_SCR_02_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G1R_SHIFT)
#define GPIO_G_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_G_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_02_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_G_SCR_02_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G0R_SHIFT)
#define GPIO_G_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_G_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_G_VM_03_0
#define GPIO_G_VM_03_0                  _MK_ADDR_CONST(0x4018)
#define GPIO_G_VM_03_0_SECURE                   0x0
#define GPIO_G_VM_03_0_DUAL                     0x0
#define GPIO_G_VM_03_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_G_VM_03_0_WORD_COUNT                       0x1
#define GPIO_G_VM_03_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_03_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_03_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_03_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_G_VM_03_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_03_0_VM1_SHIFT)
#define GPIO_G_VM_03_0_VM1_RANGE                        1:0
#define GPIO_G_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_G_VM_03_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_03_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_03_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_03_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_G_VM_03_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_03_0_VM2_SHIFT)
#define GPIO_G_VM_03_0_VM2_RANGE                        3:2
#define GPIO_G_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_G_VM_03_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_03_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_03_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_03_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_G_VM_03_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_03_0_VM3_SHIFT)
#define GPIO_G_VM_03_0_VM3_RANGE                        5:4
#define GPIO_G_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_G_VM_03_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_03_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_03_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_03_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_G_VM_03_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_03_0_VM4_SHIFT)
#define GPIO_G_VM_03_0_VM4_RANGE                        7:6
#define GPIO_G_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_G_VM_03_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_03_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_03_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_03_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_G_VM_03_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_03_0_VM5_SHIFT)
#define GPIO_G_VM_03_0_VM5_RANGE                        9:8
#define GPIO_G_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_G_VM_03_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_03_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_03_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_03_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_G_VM_03_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_03_0_VM6_SHIFT)
#define GPIO_G_VM_03_0_VM6_RANGE                        11:10
#define GPIO_G_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_G_VM_03_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_03_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_03_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_03_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_G_VM_03_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_03_0_VM7_SHIFT)
#define GPIO_G_VM_03_0_VM7_RANGE                        13:12
#define GPIO_G_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_G_VM_03_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_03_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_03_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_03_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_G_VM_03_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_03_0_VM8_SHIFT)
#define GPIO_G_VM_03_0_VM8_RANGE                        15:14
#define GPIO_G_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_G_VM_03_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_03_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_03_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_G_SCR_03_0
#define GPIO_G_SCR_03_0                 _MK_ADDR_CONST(0x401c)
#define GPIO_G_SCR_03_0_SECURE                  0x0
#define GPIO_G_SCR_03_0_DUAL                    0x0
#define GPIO_G_SCR_03_0_SCR                     0
#define GPIO_G_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_G_SCR_03_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_03_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_03_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_03_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_G_SCR_03_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_G_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_G_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_G_SCR_03_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_03_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_G_SCR_03_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_G_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_G_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_G_SCR_03_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_03_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_G_SCR_03_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_G_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_G_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_G_SCR_03_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_03_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_G_SCR_03_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_G_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_G_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_G_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_G_SCR_03_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_G_SCR_03_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_03_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_G_SCR_03_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_PR7_SHIFT)
#define GPIO_G_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_G_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_03_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_G_SCR_03_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_PR6_SHIFT)
#define GPIO_G_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_G_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_03_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_G_SCR_03_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_PR5_SHIFT)
#define GPIO_G_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_G_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_03_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_G_SCR_03_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_PR4_SHIFT)
#define GPIO_G_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_G_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_03_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_G_SCR_03_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_PR3_SHIFT)
#define GPIO_G_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_G_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_03_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_G_SCR_03_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_PR2_SHIFT)
#define GPIO_G_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_G_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_03_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_G_SCR_03_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_PR1_SHIFT)
#define GPIO_G_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_G_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_03_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_G_SCR_03_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_PR0_SHIFT)
#define GPIO_G_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_G_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_03_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_G_SCR_03_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G7W_SHIFT)
#define GPIO_G_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_G_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_03_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_G_SCR_03_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G6W_SHIFT)
#define GPIO_G_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_G_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_03_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_G_SCR_03_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G5W_SHIFT)
#define GPIO_G_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_G_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_03_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_G_SCR_03_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G4W_SHIFT)
#define GPIO_G_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_G_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_03_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_G_SCR_03_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G3W_SHIFT)
#define GPIO_G_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_G_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_03_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_G_SCR_03_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G2W_SHIFT)
#define GPIO_G_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_G_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_03_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_G_SCR_03_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G1W_SHIFT)
#define GPIO_G_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_G_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_03_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_G_SCR_03_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G0W_SHIFT)
#define GPIO_G_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_G_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_03_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_G_SCR_03_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G7R_SHIFT)
#define GPIO_G_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_G_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_03_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_G_SCR_03_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G6R_SHIFT)
#define GPIO_G_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_G_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_03_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_G_SCR_03_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G5R_SHIFT)
#define GPIO_G_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_G_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_03_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_G_SCR_03_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G4R_SHIFT)
#define GPIO_G_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_G_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_03_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_G_SCR_03_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G3R_SHIFT)
#define GPIO_G_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_G_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_03_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_G_SCR_03_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G2R_SHIFT)
#define GPIO_G_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_G_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_03_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_G_SCR_03_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G1R_SHIFT)
#define GPIO_G_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_G_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_03_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_G_SCR_03_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G0R_SHIFT)
#define GPIO_G_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_G_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_G_VM_04_0
#define GPIO_G_VM_04_0                  _MK_ADDR_CONST(0x4020)
#define GPIO_G_VM_04_0_SECURE                   0x0
#define GPIO_G_VM_04_0_DUAL                     0x0
#define GPIO_G_VM_04_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_G_VM_04_0_WORD_COUNT                       0x1
#define GPIO_G_VM_04_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_04_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_04_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_04_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_G_VM_04_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_04_0_VM1_SHIFT)
#define GPIO_G_VM_04_0_VM1_RANGE                        1:0
#define GPIO_G_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_G_VM_04_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_04_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_04_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_04_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_G_VM_04_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_04_0_VM2_SHIFT)
#define GPIO_G_VM_04_0_VM2_RANGE                        3:2
#define GPIO_G_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_G_VM_04_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_04_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_04_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_04_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_G_VM_04_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_04_0_VM3_SHIFT)
#define GPIO_G_VM_04_0_VM3_RANGE                        5:4
#define GPIO_G_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_G_VM_04_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_04_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_04_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_04_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_G_VM_04_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_04_0_VM4_SHIFT)
#define GPIO_G_VM_04_0_VM4_RANGE                        7:6
#define GPIO_G_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_G_VM_04_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_04_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_04_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_04_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_G_VM_04_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_04_0_VM5_SHIFT)
#define GPIO_G_VM_04_0_VM5_RANGE                        9:8
#define GPIO_G_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_G_VM_04_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_04_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_04_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_04_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_G_VM_04_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_04_0_VM6_SHIFT)
#define GPIO_G_VM_04_0_VM6_RANGE                        11:10
#define GPIO_G_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_G_VM_04_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_04_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_04_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_04_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_G_VM_04_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_04_0_VM7_SHIFT)
#define GPIO_G_VM_04_0_VM7_RANGE                        13:12
#define GPIO_G_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_G_VM_04_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_04_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_04_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_04_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_G_VM_04_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_04_0_VM8_SHIFT)
#define GPIO_G_VM_04_0_VM8_RANGE                        15:14
#define GPIO_G_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_G_VM_04_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_04_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_04_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_G_SCR_04_0
#define GPIO_G_SCR_04_0                 _MK_ADDR_CONST(0x4024)
#define GPIO_G_SCR_04_0_SECURE                  0x0
#define GPIO_G_SCR_04_0_DUAL                    0x0
#define GPIO_G_SCR_04_0_SCR                     0
#define GPIO_G_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_G_SCR_04_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_04_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_04_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_04_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_G_SCR_04_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_G_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_G_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_G_SCR_04_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_04_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_G_SCR_04_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_G_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_G_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_G_SCR_04_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_04_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_G_SCR_04_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_G_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_G_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_G_SCR_04_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_04_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_G_SCR_04_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_G_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_G_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_G_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_G_SCR_04_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_G_SCR_04_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_04_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_G_SCR_04_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_PR7_SHIFT)
#define GPIO_G_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_G_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_04_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_G_SCR_04_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_PR6_SHIFT)
#define GPIO_G_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_G_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_04_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_G_SCR_04_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_PR5_SHIFT)
#define GPIO_G_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_G_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_04_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_G_SCR_04_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_PR4_SHIFT)
#define GPIO_G_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_G_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_04_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_G_SCR_04_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_PR3_SHIFT)
#define GPIO_G_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_G_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_04_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_G_SCR_04_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_PR2_SHIFT)
#define GPIO_G_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_G_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_04_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_G_SCR_04_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_PR1_SHIFT)
#define GPIO_G_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_G_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_04_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_G_SCR_04_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_PR0_SHIFT)
#define GPIO_G_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_G_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_04_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_G_SCR_04_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G7W_SHIFT)
#define GPIO_G_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_G_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_04_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_G_SCR_04_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G6W_SHIFT)
#define GPIO_G_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_G_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_04_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_G_SCR_04_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G5W_SHIFT)
#define GPIO_G_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_G_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_04_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_G_SCR_04_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G4W_SHIFT)
#define GPIO_G_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_G_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_04_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_G_SCR_04_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G3W_SHIFT)
#define GPIO_G_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_G_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_04_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_G_SCR_04_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G2W_SHIFT)
#define GPIO_G_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_G_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_04_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_G_SCR_04_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G1W_SHIFT)
#define GPIO_G_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_G_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_04_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_G_SCR_04_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G0W_SHIFT)
#define GPIO_G_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_G_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_04_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_G_SCR_04_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G7R_SHIFT)
#define GPIO_G_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_G_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_04_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_G_SCR_04_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G6R_SHIFT)
#define GPIO_G_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_G_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_04_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_G_SCR_04_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G5R_SHIFT)
#define GPIO_G_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_G_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_04_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_G_SCR_04_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G4R_SHIFT)
#define GPIO_G_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_G_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_04_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_G_SCR_04_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G3R_SHIFT)
#define GPIO_G_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_G_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_04_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_G_SCR_04_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G2R_SHIFT)
#define GPIO_G_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_G_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_04_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_G_SCR_04_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G1R_SHIFT)
#define GPIO_G_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_G_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_04_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_G_SCR_04_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G0R_SHIFT)
#define GPIO_G_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_G_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_G_VM_05_0
#define GPIO_G_VM_05_0                  _MK_ADDR_CONST(0x4028)
#define GPIO_G_VM_05_0_SECURE                   0x0
#define GPIO_G_VM_05_0_DUAL                     0x0
#define GPIO_G_VM_05_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_G_VM_05_0_WORD_COUNT                       0x1
#define GPIO_G_VM_05_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_05_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_05_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_05_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_G_VM_05_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_05_0_VM1_SHIFT)
#define GPIO_G_VM_05_0_VM1_RANGE                        1:0
#define GPIO_G_VM_05_0_VM1_WOFFSET                      0x0
#define GPIO_G_VM_05_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_05_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_05_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_05_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_G_VM_05_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_05_0_VM2_SHIFT)
#define GPIO_G_VM_05_0_VM2_RANGE                        3:2
#define GPIO_G_VM_05_0_VM2_WOFFSET                      0x0
#define GPIO_G_VM_05_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_05_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_05_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_05_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_G_VM_05_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_05_0_VM3_SHIFT)
#define GPIO_G_VM_05_0_VM3_RANGE                        5:4
#define GPIO_G_VM_05_0_VM3_WOFFSET                      0x0
#define GPIO_G_VM_05_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_05_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_05_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_05_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_G_VM_05_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_05_0_VM4_SHIFT)
#define GPIO_G_VM_05_0_VM4_RANGE                        7:6
#define GPIO_G_VM_05_0_VM4_WOFFSET                      0x0
#define GPIO_G_VM_05_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_05_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_05_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_05_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_G_VM_05_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_05_0_VM5_SHIFT)
#define GPIO_G_VM_05_0_VM5_RANGE                        9:8
#define GPIO_G_VM_05_0_VM5_WOFFSET                      0x0
#define GPIO_G_VM_05_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_05_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_05_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_05_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_G_VM_05_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_05_0_VM6_SHIFT)
#define GPIO_G_VM_05_0_VM6_RANGE                        11:10
#define GPIO_G_VM_05_0_VM6_WOFFSET                      0x0
#define GPIO_G_VM_05_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_05_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_05_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_05_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_G_VM_05_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_05_0_VM7_SHIFT)
#define GPIO_G_VM_05_0_VM7_RANGE                        13:12
#define GPIO_G_VM_05_0_VM7_WOFFSET                      0x0
#define GPIO_G_VM_05_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_05_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_05_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_05_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_G_VM_05_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_05_0_VM8_SHIFT)
#define GPIO_G_VM_05_0_VM8_RANGE                        15:14
#define GPIO_G_VM_05_0_VM8_WOFFSET                      0x0
#define GPIO_G_VM_05_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_05_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_05_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_G_SCR_05_0
#define GPIO_G_SCR_05_0                 _MK_ADDR_CONST(0x402c)
#define GPIO_G_SCR_05_0_SECURE                  0x0
#define GPIO_G_SCR_05_0_DUAL                    0x0
#define GPIO_G_SCR_05_0_SCR                     0
#define GPIO_G_SCR_05_0_WORD_COUNT                      0x1
#define GPIO_G_SCR_05_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_05_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_05_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_05_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_G_SCR_05_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_G_SCR_05_0_SEC_LCK_RANGE                   29:29
#define GPIO_G_SCR_05_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_G_SCR_05_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_05_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_G_SCR_05_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_G_SCR_05_0_SEC_WEN_RANGE                   28:28
#define GPIO_G_SCR_05_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_G_SCR_05_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_05_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_G_SCR_05_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_G_SCR_05_0_SEC_REN_RANGE                   27:27
#define GPIO_G_SCR_05_0_SEC_REN_WOFFSET                 0x0
#define GPIO_G_SCR_05_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_05_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_G_SCR_05_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_G_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_G_SCR_05_0_SEC_OWNER_RANGE                 26:24
#define GPIO_G_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_G_SCR_05_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_G_SCR_05_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_05_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_G_SCR_05_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_PR7_SHIFT)
#define GPIO_G_SCR_05_0_PR7_RANGE                       23:23
#define GPIO_G_SCR_05_0_PR7_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_05_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_G_SCR_05_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_PR6_SHIFT)
#define GPIO_G_SCR_05_0_PR6_RANGE                       22:22
#define GPIO_G_SCR_05_0_PR6_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_05_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_G_SCR_05_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_PR5_SHIFT)
#define GPIO_G_SCR_05_0_PR5_RANGE                       21:21
#define GPIO_G_SCR_05_0_PR5_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_05_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_G_SCR_05_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_PR4_SHIFT)
#define GPIO_G_SCR_05_0_PR4_RANGE                       20:20
#define GPIO_G_SCR_05_0_PR4_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_05_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_G_SCR_05_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_PR3_SHIFT)
#define GPIO_G_SCR_05_0_PR3_RANGE                       19:19
#define GPIO_G_SCR_05_0_PR3_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_05_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_G_SCR_05_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_PR2_SHIFT)
#define GPIO_G_SCR_05_0_PR2_RANGE                       18:18
#define GPIO_G_SCR_05_0_PR2_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_05_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_G_SCR_05_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_PR1_SHIFT)
#define GPIO_G_SCR_05_0_PR1_RANGE                       17:17
#define GPIO_G_SCR_05_0_PR1_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_05_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_G_SCR_05_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_PR0_SHIFT)
#define GPIO_G_SCR_05_0_PR0_RANGE                       16:16
#define GPIO_G_SCR_05_0_PR0_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_05_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_G_SCR_05_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G7W_SHIFT)
#define GPIO_G_SCR_05_0_G7W_RANGE                       15:15
#define GPIO_G_SCR_05_0_G7W_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_05_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_G_SCR_05_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G6W_SHIFT)
#define GPIO_G_SCR_05_0_G6W_RANGE                       14:14
#define GPIO_G_SCR_05_0_G6W_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_05_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_G_SCR_05_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G5W_SHIFT)
#define GPIO_G_SCR_05_0_G5W_RANGE                       13:13
#define GPIO_G_SCR_05_0_G5W_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_05_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_G_SCR_05_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G4W_SHIFT)
#define GPIO_G_SCR_05_0_G4W_RANGE                       12:12
#define GPIO_G_SCR_05_0_G4W_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_05_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_G_SCR_05_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G3W_SHIFT)
#define GPIO_G_SCR_05_0_G3W_RANGE                       11:11
#define GPIO_G_SCR_05_0_G3W_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_05_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_G_SCR_05_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G2W_SHIFT)
#define GPIO_G_SCR_05_0_G2W_RANGE                       10:10
#define GPIO_G_SCR_05_0_G2W_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_05_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_G_SCR_05_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G1W_SHIFT)
#define GPIO_G_SCR_05_0_G1W_RANGE                       9:9
#define GPIO_G_SCR_05_0_G1W_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_05_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_G_SCR_05_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G0W_SHIFT)
#define GPIO_G_SCR_05_0_G0W_RANGE                       8:8
#define GPIO_G_SCR_05_0_G0W_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_05_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_G_SCR_05_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G7R_SHIFT)
#define GPIO_G_SCR_05_0_G7R_RANGE                       7:7
#define GPIO_G_SCR_05_0_G7R_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_05_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_G_SCR_05_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G6R_SHIFT)
#define GPIO_G_SCR_05_0_G6R_RANGE                       6:6
#define GPIO_G_SCR_05_0_G6R_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_05_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_G_SCR_05_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G5R_SHIFT)
#define GPIO_G_SCR_05_0_G5R_RANGE                       5:5
#define GPIO_G_SCR_05_0_G5R_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_05_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_G_SCR_05_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G4R_SHIFT)
#define GPIO_G_SCR_05_0_G4R_RANGE                       4:4
#define GPIO_G_SCR_05_0_G4R_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_05_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_G_SCR_05_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G3R_SHIFT)
#define GPIO_G_SCR_05_0_G3R_RANGE                       3:3
#define GPIO_G_SCR_05_0_G3R_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_05_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_G_SCR_05_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G2R_SHIFT)
#define GPIO_G_SCR_05_0_G2R_RANGE                       2:2
#define GPIO_G_SCR_05_0_G2R_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_05_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_G_SCR_05_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G1R_SHIFT)
#define GPIO_G_SCR_05_0_G1R_RANGE                       1:1
#define GPIO_G_SCR_05_0_G1R_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_05_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_G_SCR_05_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G0R_SHIFT)
#define GPIO_G_SCR_05_0_G0R_RANGE                       0:0
#define GPIO_G_SCR_05_0_G0R_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_G_VM_06_0
#define GPIO_G_VM_06_0                  _MK_ADDR_CONST(0x4030)
#define GPIO_G_VM_06_0_SECURE                   0x0
#define GPIO_G_VM_06_0_DUAL                     0x0
#define GPIO_G_VM_06_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_G_VM_06_0_WORD_COUNT                       0x1
#define GPIO_G_VM_06_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_06_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_06_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_06_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_VM_06_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_06_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_06_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_G_VM_06_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_06_0_VM1_SHIFT)
#define GPIO_G_VM_06_0_VM1_RANGE                        1:0
#define GPIO_G_VM_06_0_VM1_WOFFSET                      0x0
#define GPIO_G_VM_06_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_06_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_06_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_06_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_06_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_06_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_06_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_G_VM_06_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_06_0_VM2_SHIFT)
#define GPIO_G_VM_06_0_VM2_RANGE                        3:2
#define GPIO_G_VM_06_0_VM2_WOFFSET                      0x0
#define GPIO_G_VM_06_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_06_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_06_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_06_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_06_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_06_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_06_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_G_VM_06_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_06_0_VM3_SHIFT)
#define GPIO_G_VM_06_0_VM3_RANGE                        5:4
#define GPIO_G_VM_06_0_VM3_WOFFSET                      0x0
#define GPIO_G_VM_06_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_06_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_06_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_06_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_06_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_06_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_06_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_G_VM_06_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_06_0_VM4_SHIFT)
#define GPIO_G_VM_06_0_VM4_RANGE                        7:6
#define GPIO_G_VM_06_0_VM4_WOFFSET                      0x0
#define GPIO_G_VM_06_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_06_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_06_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_06_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_06_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_06_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_06_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_G_VM_06_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_06_0_VM5_SHIFT)
#define GPIO_G_VM_06_0_VM5_RANGE                        9:8
#define GPIO_G_VM_06_0_VM5_WOFFSET                      0x0
#define GPIO_G_VM_06_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_06_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_06_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_06_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_06_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_06_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_06_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_G_VM_06_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_06_0_VM6_SHIFT)
#define GPIO_G_VM_06_0_VM6_RANGE                        11:10
#define GPIO_G_VM_06_0_VM6_WOFFSET                      0x0
#define GPIO_G_VM_06_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_06_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_06_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_06_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_06_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_06_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_06_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_G_VM_06_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_06_0_VM7_SHIFT)
#define GPIO_G_VM_06_0_VM7_RANGE                        13:12
#define GPIO_G_VM_06_0_VM7_WOFFSET                      0x0
#define GPIO_G_VM_06_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_06_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_06_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_06_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_06_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_06_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_06_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_G_VM_06_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_06_0_VM8_SHIFT)
#define GPIO_G_VM_06_0_VM8_RANGE                        15:14
#define GPIO_G_VM_06_0_VM8_WOFFSET                      0x0
#define GPIO_G_VM_06_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_06_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_06_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_06_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_06_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_06_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_G_SCR_06_0
#define GPIO_G_SCR_06_0                 _MK_ADDR_CONST(0x4034)
#define GPIO_G_SCR_06_0_SECURE                  0x0
#define GPIO_G_SCR_06_0_DUAL                    0x0
#define GPIO_G_SCR_06_0_SCR                     0
#define GPIO_G_SCR_06_0_WORD_COUNT                      0x1
#define GPIO_G_SCR_06_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_06_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_06_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_06_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_G_SCR_06_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_SEC_LCK_SHIFT)
#define GPIO_G_SCR_06_0_SEC_LCK_RANGE                   29:29
#define GPIO_G_SCR_06_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_G_SCR_06_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_06_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_06_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_G_SCR_06_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_SEC_WEN_SHIFT)
#define GPIO_G_SCR_06_0_SEC_WEN_RANGE                   28:28
#define GPIO_G_SCR_06_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_G_SCR_06_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_06_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_06_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_G_SCR_06_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_SEC_REN_SHIFT)
#define GPIO_G_SCR_06_0_SEC_REN_RANGE                   27:27
#define GPIO_G_SCR_06_0_SEC_REN_WOFFSET                 0x0
#define GPIO_G_SCR_06_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_06_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_06_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_G_SCR_06_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_G_SCR_06_0_SEC_OWNER_SHIFT)
#define GPIO_G_SCR_06_0_SEC_OWNER_RANGE                 26:24
#define GPIO_G_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_G_SCR_06_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_G_SCR_06_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_06_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_G_SCR_06_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_PR7_SHIFT)
#define GPIO_G_SCR_06_0_PR7_RANGE                       23:23
#define GPIO_G_SCR_06_0_PR7_WOFFSET                     0x0
#define GPIO_G_SCR_06_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_06_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_06_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_G_SCR_06_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_PR6_SHIFT)
#define GPIO_G_SCR_06_0_PR6_RANGE                       22:22
#define GPIO_G_SCR_06_0_PR6_WOFFSET                     0x0
#define GPIO_G_SCR_06_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_06_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_06_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_G_SCR_06_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_PR5_SHIFT)
#define GPIO_G_SCR_06_0_PR5_RANGE                       21:21
#define GPIO_G_SCR_06_0_PR5_WOFFSET                     0x0
#define GPIO_G_SCR_06_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_06_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_06_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_G_SCR_06_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_PR4_SHIFT)
#define GPIO_G_SCR_06_0_PR4_RANGE                       20:20
#define GPIO_G_SCR_06_0_PR4_WOFFSET                     0x0
#define GPIO_G_SCR_06_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_06_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_06_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_G_SCR_06_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_PR3_SHIFT)
#define GPIO_G_SCR_06_0_PR3_RANGE                       19:19
#define GPIO_G_SCR_06_0_PR3_WOFFSET                     0x0
#define GPIO_G_SCR_06_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_06_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_06_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_G_SCR_06_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_PR2_SHIFT)
#define GPIO_G_SCR_06_0_PR2_RANGE                       18:18
#define GPIO_G_SCR_06_0_PR2_WOFFSET                     0x0
#define GPIO_G_SCR_06_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_06_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_06_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_G_SCR_06_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_PR1_SHIFT)
#define GPIO_G_SCR_06_0_PR1_RANGE                       17:17
#define GPIO_G_SCR_06_0_PR1_WOFFSET                     0x0
#define GPIO_G_SCR_06_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_06_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_06_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_G_SCR_06_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_PR0_SHIFT)
#define GPIO_G_SCR_06_0_PR0_RANGE                       16:16
#define GPIO_G_SCR_06_0_PR0_WOFFSET                     0x0
#define GPIO_G_SCR_06_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_06_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_06_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_G_SCR_06_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_G7W_SHIFT)
#define GPIO_G_SCR_06_0_G7W_RANGE                       15:15
#define GPIO_G_SCR_06_0_G7W_WOFFSET                     0x0
#define GPIO_G_SCR_06_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_06_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_06_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_G_SCR_06_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_G6W_SHIFT)
#define GPIO_G_SCR_06_0_G6W_RANGE                       14:14
#define GPIO_G_SCR_06_0_G6W_WOFFSET                     0x0
#define GPIO_G_SCR_06_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_06_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_06_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_G_SCR_06_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_G5W_SHIFT)
#define GPIO_G_SCR_06_0_G5W_RANGE                       13:13
#define GPIO_G_SCR_06_0_G5W_WOFFSET                     0x0
#define GPIO_G_SCR_06_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_06_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_06_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_G_SCR_06_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_G4W_SHIFT)
#define GPIO_G_SCR_06_0_G4W_RANGE                       12:12
#define GPIO_G_SCR_06_0_G4W_WOFFSET                     0x0
#define GPIO_G_SCR_06_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_06_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_06_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_G_SCR_06_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_G3W_SHIFT)
#define GPIO_G_SCR_06_0_G3W_RANGE                       11:11
#define GPIO_G_SCR_06_0_G3W_WOFFSET                     0x0
#define GPIO_G_SCR_06_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_06_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_06_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_G_SCR_06_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_G2W_SHIFT)
#define GPIO_G_SCR_06_0_G2W_RANGE                       10:10
#define GPIO_G_SCR_06_0_G2W_WOFFSET                     0x0
#define GPIO_G_SCR_06_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_06_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_06_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_G_SCR_06_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_G1W_SHIFT)
#define GPIO_G_SCR_06_0_G1W_RANGE                       9:9
#define GPIO_G_SCR_06_0_G1W_WOFFSET                     0x0
#define GPIO_G_SCR_06_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_06_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_06_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_G_SCR_06_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_G0W_SHIFT)
#define GPIO_G_SCR_06_0_G0W_RANGE                       8:8
#define GPIO_G_SCR_06_0_G0W_WOFFSET                     0x0
#define GPIO_G_SCR_06_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_06_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_06_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_G_SCR_06_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_G7R_SHIFT)
#define GPIO_G_SCR_06_0_G7R_RANGE                       7:7
#define GPIO_G_SCR_06_0_G7R_WOFFSET                     0x0
#define GPIO_G_SCR_06_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_06_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_06_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_G_SCR_06_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_G6R_SHIFT)
#define GPIO_G_SCR_06_0_G6R_RANGE                       6:6
#define GPIO_G_SCR_06_0_G6R_WOFFSET                     0x0
#define GPIO_G_SCR_06_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_06_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_06_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_G_SCR_06_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_G5R_SHIFT)
#define GPIO_G_SCR_06_0_G5R_RANGE                       5:5
#define GPIO_G_SCR_06_0_G5R_WOFFSET                     0x0
#define GPIO_G_SCR_06_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_06_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_06_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_G_SCR_06_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_G4R_SHIFT)
#define GPIO_G_SCR_06_0_G4R_RANGE                       4:4
#define GPIO_G_SCR_06_0_G4R_WOFFSET                     0x0
#define GPIO_G_SCR_06_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_06_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_06_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_G_SCR_06_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_G3R_SHIFT)
#define GPIO_G_SCR_06_0_G3R_RANGE                       3:3
#define GPIO_G_SCR_06_0_G3R_WOFFSET                     0x0
#define GPIO_G_SCR_06_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_06_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_06_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_G_SCR_06_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_G2R_SHIFT)
#define GPIO_G_SCR_06_0_G2R_RANGE                       2:2
#define GPIO_G_SCR_06_0_G2R_WOFFSET                     0x0
#define GPIO_G_SCR_06_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_06_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_06_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_G_SCR_06_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_G1R_SHIFT)
#define GPIO_G_SCR_06_0_G1R_RANGE                       1:1
#define GPIO_G_SCR_06_0_G1R_WOFFSET                     0x0
#define GPIO_G_SCR_06_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_06_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_06_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_G_SCR_06_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_G0R_SHIFT)
#define GPIO_G_SCR_06_0_G0R_RANGE                       0:0
#define GPIO_G_SCR_06_0_G0R_WOFFSET                     0x0
#define GPIO_G_SCR_06_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_06_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_G_VM_07_0
#define GPIO_G_VM_07_0                  _MK_ADDR_CONST(0x4038)
#define GPIO_G_VM_07_0_SECURE                   0x0
#define GPIO_G_VM_07_0_DUAL                     0x0
#define GPIO_G_VM_07_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_G_VM_07_0_WORD_COUNT                       0x1
#define GPIO_G_VM_07_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_07_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_07_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_07_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_VM_07_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_07_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_G_VM_07_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_G_VM_07_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_07_0_VM1_SHIFT)
#define GPIO_G_VM_07_0_VM1_RANGE                        1:0
#define GPIO_G_VM_07_0_VM1_WOFFSET                      0x0
#define GPIO_G_VM_07_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_07_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_07_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_07_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_07_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_07_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_07_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_G_VM_07_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_07_0_VM2_SHIFT)
#define GPIO_G_VM_07_0_VM2_RANGE                        3:2
#define GPIO_G_VM_07_0_VM2_WOFFSET                      0x0
#define GPIO_G_VM_07_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_07_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_07_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_07_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_07_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_07_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_07_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_G_VM_07_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_07_0_VM3_SHIFT)
#define GPIO_G_VM_07_0_VM3_RANGE                        5:4
#define GPIO_G_VM_07_0_VM3_WOFFSET                      0x0
#define GPIO_G_VM_07_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_07_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_07_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_07_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_07_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_07_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_07_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_G_VM_07_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_07_0_VM4_SHIFT)
#define GPIO_G_VM_07_0_VM4_RANGE                        7:6
#define GPIO_G_VM_07_0_VM4_WOFFSET                      0x0
#define GPIO_G_VM_07_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_07_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_07_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_07_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_07_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_07_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_07_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_G_VM_07_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_07_0_VM5_SHIFT)
#define GPIO_G_VM_07_0_VM5_RANGE                        9:8
#define GPIO_G_VM_07_0_VM5_WOFFSET                      0x0
#define GPIO_G_VM_07_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_07_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_07_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_07_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_07_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_07_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_07_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_G_VM_07_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_07_0_VM6_SHIFT)
#define GPIO_G_VM_07_0_VM6_RANGE                        11:10
#define GPIO_G_VM_07_0_VM6_WOFFSET                      0x0
#define GPIO_G_VM_07_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_07_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_07_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_07_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_07_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_07_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_07_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_G_VM_07_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_07_0_VM7_SHIFT)
#define GPIO_G_VM_07_0_VM7_RANGE                        13:12
#define GPIO_G_VM_07_0_VM7_WOFFSET                      0x0
#define GPIO_G_VM_07_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_07_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_07_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_07_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_07_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_07_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_G_VM_07_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_G_VM_07_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_G_VM_07_0_VM8_SHIFT)
#define GPIO_G_VM_07_0_VM8_RANGE                        15:14
#define GPIO_G_VM_07_0_VM8_WOFFSET                      0x0
#define GPIO_G_VM_07_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_G_VM_07_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_G_VM_07_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_VM_07_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_VM_07_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_VM_07_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_G_SCR_07_0
#define GPIO_G_SCR_07_0                 _MK_ADDR_CONST(0x403c)
#define GPIO_G_SCR_07_0_SECURE                  0x0
#define GPIO_G_SCR_07_0_DUAL                    0x0
#define GPIO_G_SCR_07_0_SCR                     0
#define GPIO_G_SCR_07_0_WORD_COUNT                      0x1
#define GPIO_G_SCR_07_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_07_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_07_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_07_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_G_SCR_07_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_SEC_LCK_SHIFT)
#define GPIO_G_SCR_07_0_SEC_LCK_RANGE                   29:29
#define GPIO_G_SCR_07_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_G_SCR_07_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_07_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_07_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_G_SCR_07_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_SEC_WEN_SHIFT)
#define GPIO_G_SCR_07_0_SEC_WEN_RANGE                   28:28
#define GPIO_G_SCR_07_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_G_SCR_07_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_07_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_07_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_G_SCR_07_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_SEC_REN_SHIFT)
#define GPIO_G_SCR_07_0_SEC_REN_RANGE                   27:27
#define GPIO_G_SCR_07_0_SEC_REN_WOFFSET                 0x0
#define GPIO_G_SCR_07_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_07_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_07_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_G_SCR_07_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_G_SCR_07_0_SEC_OWNER_SHIFT)
#define GPIO_G_SCR_07_0_SEC_OWNER_RANGE                 26:24
#define GPIO_G_SCR_07_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_G_SCR_07_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_G_SCR_07_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_07_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_G_SCR_07_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_PR7_SHIFT)
#define GPIO_G_SCR_07_0_PR7_RANGE                       23:23
#define GPIO_G_SCR_07_0_PR7_WOFFSET                     0x0
#define GPIO_G_SCR_07_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_07_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_07_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_G_SCR_07_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_PR6_SHIFT)
#define GPIO_G_SCR_07_0_PR6_RANGE                       22:22
#define GPIO_G_SCR_07_0_PR6_WOFFSET                     0x0
#define GPIO_G_SCR_07_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_07_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_07_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_G_SCR_07_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_PR5_SHIFT)
#define GPIO_G_SCR_07_0_PR5_RANGE                       21:21
#define GPIO_G_SCR_07_0_PR5_WOFFSET                     0x0
#define GPIO_G_SCR_07_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_07_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_07_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_G_SCR_07_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_PR4_SHIFT)
#define GPIO_G_SCR_07_0_PR4_RANGE                       20:20
#define GPIO_G_SCR_07_0_PR4_WOFFSET                     0x0
#define GPIO_G_SCR_07_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_07_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_07_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_G_SCR_07_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_PR3_SHIFT)
#define GPIO_G_SCR_07_0_PR3_RANGE                       19:19
#define GPIO_G_SCR_07_0_PR3_WOFFSET                     0x0
#define GPIO_G_SCR_07_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_07_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_07_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_G_SCR_07_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_PR2_SHIFT)
#define GPIO_G_SCR_07_0_PR2_RANGE                       18:18
#define GPIO_G_SCR_07_0_PR2_WOFFSET                     0x0
#define GPIO_G_SCR_07_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_07_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_07_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_G_SCR_07_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_PR1_SHIFT)
#define GPIO_G_SCR_07_0_PR1_RANGE                       17:17
#define GPIO_G_SCR_07_0_PR1_WOFFSET                     0x0
#define GPIO_G_SCR_07_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_07_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_07_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_G_SCR_07_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_PR0_SHIFT)
#define GPIO_G_SCR_07_0_PR0_RANGE                       16:16
#define GPIO_G_SCR_07_0_PR0_WOFFSET                     0x0
#define GPIO_G_SCR_07_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_07_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_07_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_G_SCR_07_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_G7W_SHIFT)
#define GPIO_G_SCR_07_0_G7W_RANGE                       15:15
#define GPIO_G_SCR_07_0_G7W_WOFFSET                     0x0
#define GPIO_G_SCR_07_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_07_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_07_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_G_SCR_07_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_G6W_SHIFT)
#define GPIO_G_SCR_07_0_G6W_RANGE                       14:14
#define GPIO_G_SCR_07_0_G6W_WOFFSET                     0x0
#define GPIO_G_SCR_07_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_07_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_07_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_G_SCR_07_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_G5W_SHIFT)
#define GPIO_G_SCR_07_0_G5W_RANGE                       13:13
#define GPIO_G_SCR_07_0_G5W_WOFFSET                     0x0
#define GPIO_G_SCR_07_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_07_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_07_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_G_SCR_07_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_G4W_SHIFT)
#define GPIO_G_SCR_07_0_G4W_RANGE                       12:12
#define GPIO_G_SCR_07_0_G4W_WOFFSET                     0x0
#define GPIO_G_SCR_07_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_07_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_07_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_G_SCR_07_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_G3W_SHIFT)
#define GPIO_G_SCR_07_0_G3W_RANGE                       11:11
#define GPIO_G_SCR_07_0_G3W_WOFFSET                     0x0
#define GPIO_G_SCR_07_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_07_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_07_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_G_SCR_07_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_G2W_SHIFT)
#define GPIO_G_SCR_07_0_G2W_RANGE                       10:10
#define GPIO_G_SCR_07_0_G2W_WOFFSET                     0x0
#define GPIO_G_SCR_07_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_07_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_07_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_G_SCR_07_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_G1W_SHIFT)
#define GPIO_G_SCR_07_0_G1W_RANGE                       9:9
#define GPIO_G_SCR_07_0_G1W_WOFFSET                     0x0
#define GPIO_G_SCR_07_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_07_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_07_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_G_SCR_07_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_G0W_SHIFT)
#define GPIO_G_SCR_07_0_G0W_RANGE                       8:8
#define GPIO_G_SCR_07_0_G0W_WOFFSET                     0x0
#define GPIO_G_SCR_07_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_07_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_07_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_G_SCR_07_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_G7R_SHIFT)
#define GPIO_G_SCR_07_0_G7R_RANGE                       7:7
#define GPIO_G_SCR_07_0_G7R_WOFFSET                     0x0
#define GPIO_G_SCR_07_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_07_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_07_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_G_SCR_07_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_G6R_SHIFT)
#define GPIO_G_SCR_07_0_G6R_RANGE                       6:6
#define GPIO_G_SCR_07_0_G6R_WOFFSET                     0x0
#define GPIO_G_SCR_07_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_07_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_07_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_G_SCR_07_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_G5R_SHIFT)
#define GPIO_G_SCR_07_0_G5R_RANGE                       5:5
#define GPIO_G_SCR_07_0_G5R_WOFFSET                     0x0
#define GPIO_G_SCR_07_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_07_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_07_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_G_SCR_07_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_G4R_SHIFT)
#define GPIO_G_SCR_07_0_G4R_RANGE                       4:4
#define GPIO_G_SCR_07_0_G4R_WOFFSET                     0x0
#define GPIO_G_SCR_07_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_07_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_07_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_G_SCR_07_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_G3R_SHIFT)
#define GPIO_G_SCR_07_0_G3R_RANGE                       3:3
#define GPIO_G_SCR_07_0_G3R_WOFFSET                     0x0
#define GPIO_G_SCR_07_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_07_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_07_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_G_SCR_07_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_G2R_SHIFT)
#define GPIO_G_SCR_07_0_G2R_RANGE                       2:2
#define GPIO_G_SCR_07_0_G2R_WOFFSET                     0x0
#define GPIO_G_SCR_07_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_07_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_07_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_G_SCR_07_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_G1R_SHIFT)
#define GPIO_G_SCR_07_0_G1R_RANGE                       1:1
#define GPIO_G_SCR_07_0_G1R_WOFFSET                     0x0
#define GPIO_G_SCR_07_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_07_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_G_SCR_07_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_G_SCR_07_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_G0R_SHIFT)
#define GPIO_G_SCR_07_0_G0R_RANGE                       0:0
#define GPIO_G_SCR_07_0_G0R_WOFFSET                     0x0
#define GPIO_G_SCR_07_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_SCR_07_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_H_VM_00_0
#define GPIO_H_VM_00_0                  _MK_ADDR_CONST(0x4040)
#define GPIO_H_VM_00_0_SECURE                   0x0
#define GPIO_H_VM_00_0_DUAL                     0x0
#define GPIO_H_VM_00_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_H_VM_00_0_WORD_COUNT                       0x1
#define GPIO_H_VM_00_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_00_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_00_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_00_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_H_VM_00_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_00_0_VM1_SHIFT)
#define GPIO_H_VM_00_0_VM1_RANGE                        1:0
#define GPIO_H_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_H_VM_00_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_00_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_00_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_00_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_H_VM_00_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_00_0_VM2_SHIFT)
#define GPIO_H_VM_00_0_VM2_RANGE                        3:2
#define GPIO_H_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_H_VM_00_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_00_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_00_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_00_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_H_VM_00_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_00_0_VM3_SHIFT)
#define GPIO_H_VM_00_0_VM3_RANGE                        5:4
#define GPIO_H_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_H_VM_00_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_00_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_00_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_00_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_H_VM_00_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_00_0_VM4_SHIFT)
#define GPIO_H_VM_00_0_VM4_RANGE                        7:6
#define GPIO_H_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_H_VM_00_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_00_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_00_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_00_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_H_VM_00_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_00_0_VM5_SHIFT)
#define GPIO_H_VM_00_0_VM5_RANGE                        9:8
#define GPIO_H_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_H_VM_00_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_00_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_00_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_00_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_H_VM_00_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_00_0_VM6_SHIFT)
#define GPIO_H_VM_00_0_VM6_RANGE                        11:10
#define GPIO_H_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_H_VM_00_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_00_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_00_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_00_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_H_VM_00_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_00_0_VM7_SHIFT)
#define GPIO_H_VM_00_0_VM7_RANGE                        13:12
#define GPIO_H_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_H_VM_00_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_00_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_00_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_00_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_H_VM_00_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_00_0_VM8_SHIFT)
#define GPIO_H_VM_00_0_VM8_RANGE                        15:14
#define GPIO_H_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_H_VM_00_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_00_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_00_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_H_SCR_00_0
#define GPIO_H_SCR_00_0                 _MK_ADDR_CONST(0x4044)
#define GPIO_H_SCR_00_0_SECURE                  0x0
#define GPIO_H_SCR_00_0_DUAL                    0x0
#define GPIO_H_SCR_00_0_SCR                     0
#define GPIO_H_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_H_SCR_00_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_00_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_00_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_H_SCR_00_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_H_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_H_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_H_SCR_00_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_00_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_H_SCR_00_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_H_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_H_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_H_SCR_00_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_00_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_H_SCR_00_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_H_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_H_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_H_SCR_00_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_00_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_H_SCR_00_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_H_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_H_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_H_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_H_SCR_00_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_H_SCR_00_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_00_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_H_SCR_00_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_PR7_SHIFT)
#define GPIO_H_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_H_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_00_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_H_SCR_00_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_PR6_SHIFT)
#define GPIO_H_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_H_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_00_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_H_SCR_00_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_PR5_SHIFT)
#define GPIO_H_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_H_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_00_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_H_SCR_00_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_PR4_SHIFT)
#define GPIO_H_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_H_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_00_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_H_SCR_00_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_PR3_SHIFT)
#define GPIO_H_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_H_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_00_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_H_SCR_00_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_PR2_SHIFT)
#define GPIO_H_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_H_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_00_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_H_SCR_00_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_PR1_SHIFT)
#define GPIO_H_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_H_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_00_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_H_SCR_00_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_PR0_SHIFT)
#define GPIO_H_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_H_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_00_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_H_SCR_00_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G7W_SHIFT)
#define GPIO_H_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_H_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_00_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_H_SCR_00_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G6W_SHIFT)
#define GPIO_H_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_H_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_00_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_H_SCR_00_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G5W_SHIFT)
#define GPIO_H_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_H_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_00_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_H_SCR_00_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G4W_SHIFT)
#define GPIO_H_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_H_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_00_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_H_SCR_00_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G3W_SHIFT)
#define GPIO_H_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_H_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_00_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_H_SCR_00_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G2W_SHIFT)
#define GPIO_H_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_H_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_00_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_H_SCR_00_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G1W_SHIFT)
#define GPIO_H_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_H_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_00_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_H_SCR_00_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G0W_SHIFT)
#define GPIO_H_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_H_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_00_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_H_SCR_00_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G7R_SHIFT)
#define GPIO_H_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_H_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_00_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_H_SCR_00_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G6R_SHIFT)
#define GPIO_H_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_H_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_00_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_H_SCR_00_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G5R_SHIFT)
#define GPIO_H_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_H_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_00_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_H_SCR_00_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G4R_SHIFT)
#define GPIO_H_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_H_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_00_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_H_SCR_00_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G3R_SHIFT)
#define GPIO_H_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_H_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_00_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_H_SCR_00_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G2R_SHIFT)
#define GPIO_H_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_H_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_00_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_H_SCR_00_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G1R_SHIFT)
#define GPIO_H_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_H_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_00_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_H_SCR_00_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G0R_SHIFT)
#define GPIO_H_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_H_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_H_VM_01_0
#define GPIO_H_VM_01_0                  _MK_ADDR_CONST(0x4048)
#define GPIO_H_VM_01_0_SECURE                   0x0
#define GPIO_H_VM_01_0_DUAL                     0x0
#define GPIO_H_VM_01_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_H_VM_01_0_WORD_COUNT                       0x1
#define GPIO_H_VM_01_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_01_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_01_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_01_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_H_VM_01_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_01_0_VM1_SHIFT)
#define GPIO_H_VM_01_0_VM1_RANGE                        1:0
#define GPIO_H_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_H_VM_01_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_01_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_01_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_01_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_H_VM_01_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_01_0_VM2_SHIFT)
#define GPIO_H_VM_01_0_VM2_RANGE                        3:2
#define GPIO_H_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_H_VM_01_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_01_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_01_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_01_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_H_VM_01_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_01_0_VM3_SHIFT)
#define GPIO_H_VM_01_0_VM3_RANGE                        5:4
#define GPIO_H_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_H_VM_01_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_01_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_01_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_01_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_H_VM_01_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_01_0_VM4_SHIFT)
#define GPIO_H_VM_01_0_VM4_RANGE                        7:6
#define GPIO_H_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_H_VM_01_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_01_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_01_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_01_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_H_VM_01_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_01_0_VM5_SHIFT)
#define GPIO_H_VM_01_0_VM5_RANGE                        9:8
#define GPIO_H_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_H_VM_01_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_01_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_01_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_01_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_H_VM_01_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_01_0_VM6_SHIFT)
#define GPIO_H_VM_01_0_VM6_RANGE                        11:10
#define GPIO_H_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_H_VM_01_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_01_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_01_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_01_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_H_VM_01_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_01_0_VM7_SHIFT)
#define GPIO_H_VM_01_0_VM7_RANGE                        13:12
#define GPIO_H_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_H_VM_01_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_01_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_01_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_01_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_H_VM_01_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_01_0_VM8_SHIFT)
#define GPIO_H_VM_01_0_VM8_RANGE                        15:14
#define GPIO_H_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_H_VM_01_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_01_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_01_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_H_SCR_01_0
#define GPIO_H_SCR_01_0                 _MK_ADDR_CONST(0x404c)
#define GPIO_H_SCR_01_0_SECURE                  0x0
#define GPIO_H_SCR_01_0_DUAL                    0x0
#define GPIO_H_SCR_01_0_SCR                     0
#define GPIO_H_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_H_SCR_01_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_01_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_01_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_01_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_H_SCR_01_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_H_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_H_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_H_SCR_01_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_01_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_H_SCR_01_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_H_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_H_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_H_SCR_01_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_01_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_H_SCR_01_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_H_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_H_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_H_SCR_01_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_01_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_H_SCR_01_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_H_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_H_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_H_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_H_SCR_01_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_H_SCR_01_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_01_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_H_SCR_01_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_PR7_SHIFT)
#define GPIO_H_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_H_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_01_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_H_SCR_01_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_PR6_SHIFT)
#define GPIO_H_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_H_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_01_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_H_SCR_01_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_PR5_SHIFT)
#define GPIO_H_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_H_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_01_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_H_SCR_01_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_PR4_SHIFT)
#define GPIO_H_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_H_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_01_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_H_SCR_01_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_PR3_SHIFT)
#define GPIO_H_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_H_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_01_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_H_SCR_01_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_PR2_SHIFT)
#define GPIO_H_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_H_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_01_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_H_SCR_01_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_PR1_SHIFT)
#define GPIO_H_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_H_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_01_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_H_SCR_01_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_PR0_SHIFT)
#define GPIO_H_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_H_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_01_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_H_SCR_01_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G7W_SHIFT)
#define GPIO_H_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_H_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_01_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_H_SCR_01_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G6W_SHIFT)
#define GPIO_H_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_H_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_01_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_H_SCR_01_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G5W_SHIFT)
#define GPIO_H_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_H_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_01_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_H_SCR_01_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G4W_SHIFT)
#define GPIO_H_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_H_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_01_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_H_SCR_01_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G3W_SHIFT)
#define GPIO_H_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_H_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_01_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_H_SCR_01_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G2W_SHIFT)
#define GPIO_H_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_H_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_01_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_H_SCR_01_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G1W_SHIFT)
#define GPIO_H_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_H_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_01_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_H_SCR_01_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G0W_SHIFT)
#define GPIO_H_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_H_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_01_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_H_SCR_01_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G7R_SHIFT)
#define GPIO_H_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_H_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_01_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_H_SCR_01_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G6R_SHIFT)
#define GPIO_H_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_H_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_01_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_H_SCR_01_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G5R_SHIFT)
#define GPIO_H_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_H_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_01_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_H_SCR_01_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G4R_SHIFT)
#define GPIO_H_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_H_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_01_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_H_SCR_01_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G3R_SHIFT)
#define GPIO_H_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_H_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_01_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_H_SCR_01_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G2R_SHIFT)
#define GPIO_H_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_H_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_01_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_H_SCR_01_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G1R_SHIFT)
#define GPIO_H_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_H_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_01_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_H_SCR_01_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G0R_SHIFT)
#define GPIO_H_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_H_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_H_VM_02_0
#define GPIO_H_VM_02_0                  _MK_ADDR_CONST(0x4050)
#define GPIO_H_VM_02_0_SECURE                   0x0
#define GPIO_H_VM_02_0_DUAL                     0x0
#define GPIO_H_VM_02_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_H_VM_02_0_WORD_COUNT                       0x1
#define GPIO_H_VM_02_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_02_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_02_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_02_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_H_VM_02_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_02_0_VM1_SHIFT)
#define GPIO_H_VM_02_0_VM1_RANGE                        1:0
#define GPIO_H_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_H_VM_02_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_02_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_02_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_02_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_H_VM_02_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_02_0_VM2_SHIFT)
#define GPIO_H_VM_02_0_VM2_RANGE                        3:2
#define GPIO_H_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_H_VM_02_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_02_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_02_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_02_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_H_VM_02_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_02_0_VM3_SHIFT)
#define GPIO_H_VM_02_0_VM3_RANGE                        5:4
#define GPIO_H_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_H_VM_02_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_02_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_02_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_02_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_H_VM_02_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_02_0_VM4_SHIFT)
#define GPIO_H_VM_02_0_VM4_RANGE                        7:6
#define GPIO_H_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_H_VM_02_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_02_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_02_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_02_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_H_VM_02_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_02_0_VM5_SHIFT)
#define GPIO_H_VM_02_0_VM5_RANGE                        9:8
#define GPIO_H_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_H_VM_02_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_02_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_02_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_02_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_H_VM_02_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_02_0_VM6_SHIFT)
#define GPIO_H_VM_02_0_VM6_RANGE                        11:10
#define GPIO_H_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_H_VM_02_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_02_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_02_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_02_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_H_VM_02_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_02_0_VM7_SHIFT)
#define GPIO_H_VM_02_0_VM7_RANGE                        13:12
#define GPIO_H_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_H_VM_02_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_02_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_02_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_02_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_H_VM_02_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_02_0_VM8_SHIFT)
#define GPIO_H_VM_02_0_VM8_RANGE                        15:14
#define GPIO_H_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_H_VM_02_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_02_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_02_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_H_SCR_02_0
#define GPIO_H_SCR_02_0                 _MK_ADDR_CONST(0x4054)
#define GPIO_H_SCR_02_0_SECURE                  0x0
#define GPIO_H_SCR_02_0_DUAL                    0x0
#define GPIO_H_SCR_02_0_SCR                     0
#define GPIO_H_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_H_SCR_02_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_02_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_02_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_02_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_H_SCR_02_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_H_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_H_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_H_SCR_02_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_02_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_H_SCR_02_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_H_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_H_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_H_SCR_02_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_02_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_H_SCR_02_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_H_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_H_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_H_SCR_02_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_02_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_H_SCR_02_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_H_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_H_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_H_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_H_SCR_02_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_H_SCR_02_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_02_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_H_SCR_02_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_PR7_SHIFT)
#define GPIO_H_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_H_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_02_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_H_SCR_02_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_PR6_SHIFT)
#define GPIO_H_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_H_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_02_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_H_SCR_02_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_PR5_SHIFT)
#define GPIO_H_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_H_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_02_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_H_SCR_02_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_PR4_SHIFT)
#define GPIO_H_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_H_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_02_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_H_SCR_02_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_PR3_SHIFT)
#define GPIO_H_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_H_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_02_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_H_SCR_02_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_PR2_SHIFT)
#define GPIO_H_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_H_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_02_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_H_SCR_02_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_PR1_SHIFT)
#define GPIO_H_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_H_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_02_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_H_SCR_02_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_PR0_SHIFT)
#define GPIO_H_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_H_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_02_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_H_SCR_02_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G7W_SHIFT)
#define GPIO_H_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_H_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_02_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_H_SCR_02_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G6W_SHIFT)
#define GPIO_H_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_H_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_02_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_H_SCR_02_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G5W_SHIFT)
#define GPIO_H_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_H_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_02_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_H_SCR_02_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G4W_SHIFT)
#define GPIO_H_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_H_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_02_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_H_SCR_02_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G3W_SHIFT)
#define GPIO_H_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_H_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_02_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_H_SCR_02_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G2W_SHIFT)
#define GPIO_H_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_H_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_02_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_H_SCR_02_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G1W_SHIFT)
#define GPIO_H_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_H_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_02_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_H_SCR_02_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G0W_SHIFT)
#define GPIO_H_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_H_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_02_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_H_SCR_02_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G7R_SHIFT)
#define GPIO_H_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_H_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_02_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_H_SCR_02_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G6R_SHIFT)
#define GPIO_H_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_H_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_02_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_H_SCR_02_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G5R_SHIFT)
#define GPIO_H_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_H_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_02_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_H_SCR_02_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G4R_SHIFT)
#define GPIO_H_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_H_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_02_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_H_SCR_02_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G3R_SHIFT)
#define GPIO_H_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_H_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_02_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_H_SCR_02_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G2R_SHIFT)
#define GPIO_H_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_H_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_02_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_H_SCR_02_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G1R_SHIFT)
#define GPIO_H_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_H_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_02_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_H_SCR_02_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G0R_SHIFT)
#define GPIO_H_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_H_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_H_VM_03_0
#define GPIO_H_VM_03_0                  _MK_ADDR_CONST(0x4058)
#define GPIO_H_VM_03_0_SECURE                   0x0
#define GPIO_H_VM_03_0_DUAL                     0x0
#define GPIO_H_VM_03_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_H_VM_03_0_WORD_COUNT                       0x1
#define GPIO_H_VM_03_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_03_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_03_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_03_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_H_VM_03_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_03_0_VM1_SHIFT)
#define GPIO_H_VM_03_0_VM1_RANGE                        1:0
#define GPIO_H_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_H_VM_03_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_03_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_03_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_03_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_H_VM_03_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_03_0_VM2_SHIFT)
#define GPIO_H_VM_03_0_VM2_RANGE                        3:2
#define GPIO_H_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_H_VM_03_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_03_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_03_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_03_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_H_VM_03_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_03_0_VM3_SHIFT)
#define GPIO_H_VM_03_0_VM3_RANGE                        5:4
#define GPIO_H_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_H_VM_03_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_03_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_03_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_03_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_H_VM_03_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_03_0_VM4_SHIFT)
#define GPIO_H_VM_03_0_VM4_RANGE                        7:6
#define GPIO_H_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_H_VM_03_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_03_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_03_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_03_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_H_VM_03_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_03_0_VM5_SHIFT)
#define GPIO_H_VM_03_0_VM5_RANGE                        9:8
#define GPIO_H_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_H_VM_03_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_03_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_03_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_03_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_H_VM_03_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_03_0_VM6_SHIFT)
#define GPIO_H_VM_03_0_VM6_RANGE                        11:10
#define GPIO_H_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_H_VM_03_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_03_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_03_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_03_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_H_VM_03_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_03_0_VM7_SHIFT)
#define GPIO_H_VM_03_0_VM7_RANGE                        13:12
#define GPIO_H_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_H_VM_03_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_03_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_03_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_03_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_H_VM_03_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_03_0_VM8_SHIFT)
#define GPIO_H_VM_03_0_VM8_RANGE                        15:14
#define GPIO_H_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_H_VM_03_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_03_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_03_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_H_SCR_03_0
#define GPIO_H_SCR_03_0                 _MK_ADDR_CONST(0x405c)
#define GPIO_H_SCR_03_0_SECURE                  0x0
#define GPIO_H_SCR_03_0_DUAL                    0x0
#define GPIO_H_SCR_03_0_SCR                     0
#define GPIO_H_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_H_SCR_03_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_03_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_03_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_03_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_H_SCR_03_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_H_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_H_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_H_SCR_03_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_03_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_H_SCR_03_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_H_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_H_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_H_SCR_03_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_03_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_H_SCR_03_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_H_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_H_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_H_SCR_03_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_03_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_H_SCR_03_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_H_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_H_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_H_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_H_SCR_03_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_H_SCR_03_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_03_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_H_SCR_03_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_PR7_SHIFT)
#define GPIO_H_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_H_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_03_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_H_SCR_03_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_PR6_SHIFT)
#define GPIO_H_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_H_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_03_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_H_SCR_03_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_PR5_SHIFT)
#define GPIO_H_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_H_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_03_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_H_SCR_03_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_PR4_SHIFT)
#define GPIO_H_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_H_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_03_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_H_SCR_03_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_PR3_SHIFT)
#define GPIO_H_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_H_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_03_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_H_SCR_03_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_PR2_SHIFT)
#define GPIO_H_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_H_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_03_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_H_SCR_03_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_PR1_SHIFT)
#define GPIO_H_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_H_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_03_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_H_SCR_03_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_PR0_SHIFT)
#define GPIO_H_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_H_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_03_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_H_SCR_03_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G7W_SHIFT)
#define GPIO_H_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_H_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_03_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_H_SCR_03_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G6W_SHIFT)
#define GPIO_H_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_H_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_03_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_H_SCR_03_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G5W_SHIFT)
#define GPIO_H_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_H_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_03_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_H_SCR_03_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G4W_SHIFT)
#define GPIO_H_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_H_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_03_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_H_SCR_03_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G3W_SHIFT)
#define GPIO_H_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_H_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_03_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_H_SCR_03_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G2W_SHIFT)
#define GPIO_H_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_H_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_03_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_H_SCR_03_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G1W_SHIFT)
#define GPIO_H_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_H_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_03_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_H_SCR_03_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G0W_SHIFT)
#define GPIO_H_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_H_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_03_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_H_SCR_03_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G7R_SHIFT)
#define GPIO_H_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_H_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_03_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_H_SCR_03_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G6R_SHIFT)
#define GPIO_H_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_H_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_03_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_H_SCR_03_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G5R_SHIFT)
#define GPIO_H_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_H_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_03_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_H_SCR_03_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G4R_SHIFT)
#define GPIO_H_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_H_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_03_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_H_SCR_03_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G3R_SHIFT)
#define GPIO_H_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_H_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_03_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_H_SCR_03_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G2R_SHIFT)
#define GPIO_H_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_H_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_03_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_H_SCR_03_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G1R_SHIFT)
#define GPIO_H_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_H_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_03_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_H_SCR_03_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G0R_SHIFT)
#define GPIO_H_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_H_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_H_VM_04_0
#define GPIO_H_VM_04_0                  _MK_ADDR_CONST(0x4060)
#define GPIO_H_VM_04_0_SECURE                   0x0
#define GPIO_H_VM_04_0_DUAL                     0x0
#define GPIO_H_VM_04_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_H_VM_04_0_WORD_COUNT                       0x1
#define GPIO_H_VM_04_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_04_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_04_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_04_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_H_VM_04_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_04_0_VM1_SHIFT)
#define GPIO_H_VM_04_0_VM1_RANGE                        1:0
#define GPIO_H_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_H_VM_04_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_04_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_04_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_04_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_H_VM_04_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_04_0_VM2_SHIFT)
#define GPIO_H_VM_04_0_VM2_RANGE                        3:2
#define GPIO_H_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_H_VM_04_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_04_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_04_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_04_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_H_VM_04_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_04_0_VM3_SHIFT)
#define GPIO_H_VM_04_0_VM3_RANGE                        5:4
#define GPIO_H_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_H_VM_04_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_04_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_04_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_04_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_H_VM_04_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_04_0_VM4_SHIFT)
#define GPIO_H_VM_04_0_VM4_RANGE                        7:6
#define GPIO_H_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_H_VM_04_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_04_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_04_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_04_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_H_VM_04_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_04_0_VM5_SHIFT)
#define GPIO_H_VM_04_0_VM5_RANGE                        9:8
#define GPIO_H_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_H_VM_04_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_04_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_04_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_04_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_H_VM_04_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_04_0_VM6_SHIFT)
#define GPIO_H_VM_04_0_VM6_RANGE                        11:10
#define GPIO_H_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_H_VM_04_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_04_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_04_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_04_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_H_VM_04_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_04_0_VM7_SHIFT)
#define GPIO_H_VM_04_0_VM7_RANGE                        13:12
#define GPIO_H_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_H_VM_04_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_04_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_04_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_04_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_H_VM_04_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_04_0_VM8_SHIFT)
#define GPIO_H_VM_04_0_VM8_RANGE                        15:14
#define GPIO_H_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_H_VM_04_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_04_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_04_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_H_SCR_04_0
#define GPIO_H_SCR_04_0                 _MK_ADDR_CONST(0x4064)
#define GPIO_H_SCR_04_0_SECURE                  0x0
#define GPIO_H_SCR_04_0_DUAL                    0x0
#define GPIO_H_SCR_04_0_SCR                     0
#define GPIO_H_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_H_SCR_04_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_04_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_04_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_04_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_H_SCR_04_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_H_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_H_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_H_SCR_04_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_04_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_H_SCR_04_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_H_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_H_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_H_SCR_04_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_04_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_H_SCR_04_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_H_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_H_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_H_SCR_04_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_04_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_H_SCR_04_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_H_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_H_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_H_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_H_SCR_04_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_H_SCR_04_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_04_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_H_SCR_04_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_PR7_SHIFT)
#define GPIO_H_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_H_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_04_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_H_SCR_04_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_PR6_SHIFT)
#define GPIO_H_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_H_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_04_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_H_SCR_04_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_PR5_SHIFT)
#define GPIO_H_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_H_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_04_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_H_SCR_04_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_PR4_SHIFT)
#define GPIO_H_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_H_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_04_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_H_SCR_04_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_PR3_SHIFT)
#define GPIO_H_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_H_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_04_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_H_SCR_04_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_PR2_SHIFT)
#define GPIO_H_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_H_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_04_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_H_SCR_04_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_PR1_SHIFT)
#define GPIO_H_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_H_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_04_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_H_SCR_04_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_PR0_SHIFT)
#define GPIO_H_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_H_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_04_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_H_SCR_04_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G7W_SHIFT)
#define GPIO_H_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_H_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_04_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_H_SCR_04_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G6W_SHIFT)
#define GPIO_H_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_H_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_04_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_H_SCR_04_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G5W_SHIFT)
#define GPIO_H_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_H_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_04_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_H_SCR_04_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G4W_SHIFT)
#define GPIO_H_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_H_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_04_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_H_SCR_04_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G3W_SHIFT)
#define GPIO_H_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_H_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_04_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_H_SCR_04_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G2W_SHIFT)
#define GPIO_H_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_H_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_04_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_H_SCR_04_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G1W_SHIFT)
#define GPIO_H_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_H_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_04_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_H_SCR_04_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G0W_SHIFT)
#define GPIO_H_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_H_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_04_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_H_SCR_04_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G7R_SHIFT)
#define GPIO_H_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_H_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_04_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_H_SCR_04_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G6R_SHIFT)
#define GPIO_H_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_H_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_04_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_H_SCR_04_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G5R_SHIFT)
#define GPIO_H_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_H_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_04_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_H_SCR_04_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G4R_SHIFT)
#define GPIO_H_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_H_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_04_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_H_SCR_04_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G3R_SHIFT)
#define GPIO_H_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_H_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_04_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_H_SCR_04_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G2R_SHIFT)
#define GPIO_H_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_H_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_04_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_H_SCR_04_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G1R_SHIFT)
#define GPIO_H_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_H_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_04_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_H_SCR_04_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G0R_SHIFT)
#define GPIO_H_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_H_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_H_VM_05_0
#define GPIO_H_VM_05_0                  _MK_ADDR_CONST(0x4068)
#define GPIO_H_VM_05_0_SECURE                   0x0
#define GPIO_H_VM_05_0_DUAL                     0x0
#define GPIO_H_VM_05_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_H_VM_05_0_WORD_COUNT                       0x1
#define GPIO_H_VM_05_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_05_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_05_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_05_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_H_VM_05_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_05_0_VM1_SHIFT)
#define GPIO_H_VM_05_0_VM1_RANGE                        1:0
#define GPIO_H_VM_05_0_VM1_WOFFSET                      0x0
#define GPIO_H_VM_05_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_05_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_05_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_05_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_H_VM_05_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_05_0_VM2_SHIFT)
#define GPIO_H_VM_05_0_VM2_RANGE                        3:2
#define GPIO_H_VM_05_0_VM2_WOFFSET                      0x0
#define GPIO_H_VM_05_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_05_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_05_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_05_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_H_VM_05_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_05_0_VM3_SHIFT)
#define GPIO_H_VM_05_0_VM3_RANGE                        5:4
#define GPIO_H_VM_05_0_VM3_WOFFSET                      0x0
#define GPIO_H_VM_05_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_05_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_05_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_05_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_H_VM_05_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_05_0_VM4_SHIFT)
#define GPIO_H_VM_05_0_VM4_RANGE                        7:6
#define GPIO_H_VM_05_0_VM4_WOFFSET                      0x0
#define GPIO_H_VM_05_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_05_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_05_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_05_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_H_VM_05_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_05_0_VM5_SHIFT)
#define GPIO_H_VM_05_0_VM5_RANGE                        9:8
#define GPIO_H_VM_05_0_VM5_WOFFSET                      0x0
#define GPIO_H_VM_05_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_05_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_05_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_05_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_H_VM_05_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_05_0_VM6_SHIFT)
#define GPIO_H_VM_05_0_VM6_RANGE                        11:10
#define GPIO_H_VM_05_0_VM6_WOFFSET                      0x0
#define GPIO_H_VM_05_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_05_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_05_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_05_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_H_VM_05_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_05_0_VM7_SHIFT)
#define GPIO_H_VM_05_0_VM7_RANGE                        13:12
#define GPIO_H_VM_05_0_VM7_WOFFSET                      0x0
#define GPIO_H_VM_05_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_05_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_05_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_05_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_H_VM_05_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_05_0_VM8_SHIFT)
#define GPIO_H_VM_05_0_VM8_RANGE                        15:14
#define GPIO_H_VM_05_0_VM8_WOFFSET                      0x0
#define GPIO_H_VM_05_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_05_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_05_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_H_SCR_05_0
#define GPIO_H_SCR_05_0                 _MK_ADDR_CONST(0x406c)
#define GPIO_H_SCR_05_0_SECURE                  0x0
#define GPIO_H_SCR_05_0_DUAL                    0x0
#define GPIO_H_SCR_05_0_SCR                     0
#define GPIO_H_SCR_05_0_WORD_COUNT                      0x1
#define GPIO_H_SCR_05_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_05_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_05_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_05_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_H_SCR_05_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_H_SCR_05_0_SEC_LCK_RANGE                   29:29
#define GPIO_H_SCR_05_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_H_SCR_05_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_05_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_H_SCR_05_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_H_SCR_05_0_SEC_WEN_RANGE                   28:28
#define GPIO_H_SCR_05_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_H_SCR_05_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_05_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_H_SCR_05_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_H_SCR_05_0_SEC_REN_RANGE                   27:27
#define GPIO_H_SCR_05_0_SEC_REN_WOFFSET                 0x0
#define GPIO_H_SCR_05_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_05_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_H_SCR_05_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_H_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_H_SCR_05_0_SEC_OWNER_RANGE                 26:24
#define GPIO_H_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_H_SCR_05_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_H_SCR_05_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_05_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_H_SCR_05_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_PR7_SHIFT)
#define GPIO_H_SCR_05_0_PR7_RANGE                       23:23
#define GPIO_H_SCR_05_0_PR7_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_05_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_H_SCR_05_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_PR6_SHIFT)
#define GPIO_H_SCR_05_0_PR6_RANGE                       22:22
#define GPIO_H_SCR_05_0_PR6_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_05_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_H_SCR_05_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_PR5_SHIFT)
#define GPIO_H_SCR_05_0_PR5_RANGE                       21:21
#define GPIO_H_SCR_05_0_PR5_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_05_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_H_SCR_05_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_PR4_SHIFT)
#define GPIO_H_SCR_05_0_PR4_RANGE                       20:20
#define GPIO_H_SCR_05_0_PR4_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_05_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_H_SCR_05_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_PR3_SHIFT)
#define GPIO_H_SCR_05_0_PR3_RANGE                       19:19
#define GPIO_H_SCR_05_0_PR3_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_05_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_H_SCR_05_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_PR2_SHIFT)
#define GPIO_H_SCR_05_0_PR2_RANGE                       18:18
#define GPIO_H_SCR_05_0_PR2_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_05_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_H_SCR_05_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_PR1_SHIFT)
#define GPIO_H_SCR_05_0_PR1_RANGE                       17:17
#define GPIO_H_SCR_05_0_PR1_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_05_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_H_SCR_05_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_PR0_SHIFT)
#define GPIO_H_SCR_05_0_PR0_RANGE                       16:16
#define GPIO_H_SCR_05_0_PR0_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_05_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_H_SCR_05_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G7W_SHIFT)
#define GPIO_H_SCR_05_0_G7W_RANGE                       15:15
#define GPIO_H_SCR_05_0_G7W_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_05_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_H_SCR_05_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G6W_SHIFT)
#define GPIO_H_SCR_05_0_G6W_RANGE                       14:14
#define GPIO_H_SCR_05_0_G6W_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_05_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_H_SCR_05_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G5W_SHIFT)
#define GPIO_H_SCR_05_0_G5W_RANGE                       13:13
#define GPIO_H_SCR_05_0_G5W_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_05_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_H_SCR_05_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G4W_SHIFT)
#define GPIO_H_SCR_05_0_G4W_RANGE                       12:12
#define GPIO_H_SCR_05_0_G4W_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_05_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_H_SCR_05_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G3W_SHIFT)
#define GPIO_H_SCR_05_0_G3W_RANGE                       11:11
#define GPIO_H_SCR_05_0_G3W_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_05_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_H_SCR_05_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G2W_SHIFT)
#define GPIO_H_SCR_05_0_G2W_RANGE                       10:10
#define GPIO_H_SCR_05_0_G2W_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_05_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_H_SCR_05_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G1W_SHIFT)
#define GPIO_H_SCR_05_0_G1W_RANGE                       9:9
#define GPIO_H_SCR_05_0_G1W_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_05_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_H_SCR_05_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G0W_SHIFT)
#define GPIO_H_SCR_05_0_G0W_RANGE                       8:8
#define GPIO_H_SCR_05_0_G0W_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_05_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_H_SCR_05_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G7R_SHIFT)
#define GPIO_H_SCR_05_0_G7R_RANGE                       7:7
#define GPIO_H_SCR_05_0_G7R_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_05_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_H_SCR_05_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G6R_SHIFT)
#define GPIO_H_SCR_05_0_G6R_RANGE                       6:6
#define GPIO_H_SCR_05_0_G6R_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_05_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_H_SCR_05_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G5R_SHIFT)
#define GPIO_H_SCR_05_0_G5R_RANGE                       5:5
#define GPIO_H_SCR_05_0_G5R_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_05_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_H_SCR_05_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G4R_SHIFT)
#define GPIO_H_SCR_05_0_G4R_RANGE                       4:4
#define GPIO_H_SCR_05_0_G4R_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_05_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_H_SCR_05_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G3R_SHIFT)
#define GPIO_H_SCR_05_0_G3R_RANGE                       3:3
#define GPIO_H_SCR_05_0_G3R_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_05_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_H_SCR_05_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G2R_SHIFT)
#define GPIO_H_SCR_05_0_G2R_RANGE                       2:2
#define GPIO_H_SCR_05_0_G2R_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_05_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_H_SCR_05_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G1R_SHIFT)
#define GPIO_H_SCR_05_0_G1R_RANGE                       1:1
#define GPIO_H_SCR_05_0_G1R_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_05_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_H_SCR_05_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G0R_SHIFT)
#define GPIO_H_SCR_05_0_G0R_RANGE                       0:0
#define GPIO_H_SCR_05_0_G0R_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_H_VM_06_0
#define GPIO_H_VM_06_0                  _MK_ADDR_CONST(0x4070)
#define GPIO_H_VM_06_0_SECURE                   0x0
#define GPIO_H_VM_06_0_DUAL                     0x0
#define GPIO_H_VM_06_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_H_VM_06_0_WORD_COUNT                       0x1
#define GPIO_H_VM_06_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_06_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_06_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_06_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_06_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_H_VM_06_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_06_0_VM1_SHIFT)
#define GPIO_H_VM_06_0_VM1_RANGE                        1:0
#define GPIO_H_VM_06_0_VM1_WOFFSET                      0x0
#define GPIO_H_VM_06_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_06_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_06_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_06_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_H_VM_06_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_06_0_VM2_SHIFT)
#define GPIO_H_VM_06_0_VM2_RANGE                        3:2
#define GPIO_H_VM_06_0_VM2_WOFFSET                      0x0
#define GPIO_H_VM_06_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_06_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_06_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_06_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_H_VM_06_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_06_0_VM3_SHIFT)
#define GPIO_H_VM_06_0_VM3_RANGE                        5:4
#define GPIO_H_VM_06_0_VM3_WOFFSET                      0x0
#define GPIO_H_VM_06_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_06_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_06_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_06_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_H_VM_06_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_06_0_VM4_SHIFT)
#define GPIO_H_VM_06_0_VM4_RANGE                        7:6
#define GPIO_H_VM_06_0_VM4_WOFFSET                      0x0
#define GPIO_H_VM_06_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_06_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_06_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_06_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_H_VM_06_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_06_0_VM5_SHIFT)
#define GPIO_H_VM_06_0_VM5_RANGE                        9:8
#define GPIO_H_VM_06_0_VM5_WOFFSET                      0x0
#define GPIO_H_VM_06_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_06_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_06_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_06_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_H_VM_06_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_06_0_VM6_SHIFT)
#define GPIO_H_VM_06_0_VM6_RANGE                        11:10
#define GPIO_H_VM_06_0_VM6_WOFFSET                      0x0
#define GPIO_H_VM_06_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_06_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_06_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_06_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_H_VM_06_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_06_0_VM7_SHIFT)
#define GPIO_H_VM_06_0_VM7_RANGE                        13:12
#define GPIO_H_VM_06_0_VM7_WOFFSET                      0x0
#define GPIO_H_VM_06_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_06_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_06_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_06_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_H_VM_06_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_06_0_VM8_SHIFT)
#define GPIO_H_VM_06_0_VM8_RANGE                        15:14
#define GPIO_H_VM_06_0_VM8_WOFFSET                      0x0
#define GPIO_H_VM_06_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_06_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_06_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_H_SCR_06_0
#define GPIO_H_SCR_06_0                 _MK_ADDR_CONST(0x4074)
#define GPIO_H_SCR_06_0_SECURE                  0x0
#define GPIO_H_SCR_06_0_DUAL                    0x0
#define GPIO_H_SCR_06_0_SCR                     0
#define GPIO_H_SCR_06_0_WORD_COUNT                      0x1
#define GPIO_H_SCR_06_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_06_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_06_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_06_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_H_SCR_06_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_SEC_LCK_SHIFT)
#define GPIO_H_SCR_06_0_SEC_LCK_RANGE                   29:29
#define GPIO_H_SCR_06_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_H_SCR_06_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_06_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_H_SCR_06_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_SEC_WEN_SHIFT)
#define GPIO_H_SCR_06_0_SEC_WEN_RANGE                   28:28
#define GPIO_H_SCR_06_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_H_SCR_06_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_06_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_H_SCR_06_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_SEC_REN_SHIFT)
#define GPIO_H_SCR_06_0_SEC_REN_RANGE                   27:27
#define GPIO_H_SCR_06_0_SEC_REN_WOFFSET                 0x0
#define GPIO_H_SCR_06_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_06_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_H_SCR_06_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_H_SCR_06_0_SEC_OWNER_SHIFT)
#define GPIO_H_SCR_06_0_SEC_OWNER_RANGE                 26:24
#define GPIO_H_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_H_SCR_06_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_H_SCR_06_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_06_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_H_SCR_06_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_PR7_SHIFT)
#define GPIO_H_SCR_06_0_PR7_RANGE                       23:23
#define GPIO_H_SCR_06_0_PR7_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_06_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_H_SCR_06_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_PR6_SHIFT)
#define GPIO_H_SCR_06_0_PR6_RANGE                       22:22
#define GPIO_H_SCR_06_0_PR6_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_06_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_H_SCR_06_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_PR5_SHIFT)
#define GPIO_H_SCR_06_0_PR5_RANGE                       21:21
#define GPIO_H_SCR_06_0_PR5_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_06_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_H_SCR_06_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_PR4_SHIFT)
#define GPIO_H_SCR_06_0_PR4_RANGE                       20:20
#define GPIO_H_SCR_06_0_PR4_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_06_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_H_SCR_06_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_PR3_SHIFT)
#define GPIO_H_SCR_06_0_PR3_RANGE                       19:19
#define GPIO_H_SCR_06_0_PR3_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_06_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_H_SCR_06_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_PR2_SHIFT)
#define GPIO_H_SCR_06_0_PR2_RANGE                       18:18
#define GPIO_H_SCR_06_0_PR2_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_06_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_H_SCR_06_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_PR1_SHIFT)
#define GPIO_H_SCR_06_0_PR1_RANGE                       17:17
#define GPIO_H_SCR_06_0_PR1_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_06_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_H_SCR_06_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_PR0_SHIFT)
#define GPIO_H_SCR_06_0_PR0_RANGE                       16:16
#define GPIO_H_SCR_06_0_PR0_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_06_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_H_SCR_06_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G7W_SHIFT)
#define GPIO_H_SCR_06_0_G7W_RANGE                       15:15
#define GPIO_H_SCR_06_0_G7W_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_06_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_H_SCR_06_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G6W_SHIFT)
#define GPIO_H_SCR_06_0_G6W_RANGE                       14:14
#define GPIO_H_SCR_06_0_G6W_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_06_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_H_SCR_06_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G5W_SHIFT)
#define GPIO_H_SCR_06_0_G5W_RANGE                       13:13
#define GPIO_H_SCR_06_0_G5W_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_06_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_H_SCR_06_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G4W_SHIFT)
#define GPIO_H_SCR_06_0_G4W_RANGE                       12:12
#define GPIO_H_SCR_06_0_G4W_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_06_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_H_SCR_06_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G3W_SHIFT)
#define GPIO_H_SCR_06_0_G3W_RANGE                       11:11
#define GPIO_H_SCR_06_0_G3W_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_06_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_H_SCR_06_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G2W_SHIFT)
#define GPIO_H_SCR_06_0_G2W_RANGE                       10:10
#define GPIO_H_SCR_06_0_G2W_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_06_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_H_SCR_06_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G1W_SHIFT)
#define GPIO_H_SCR_06_0_G1W_RANGE                       9:9
#define GPIO_H_SCR_06_0_G1W_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_06_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_H_SCR_06_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G0W_SHIFT)
#define GPIO_H_SCR_06_0_G0W_RANGE                       8:8
#define GPIO_H_SCR_06_0_G0W_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_06_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_H_SCR_06_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G7R_SHIFT)
#define GPIO_H_SCR_06_0_G7R_RANGE                       7:7
#define GPIO_H_SCR_06_0_G7R_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_06_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_H_SCR_06_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G6R_SHIFT)
#define GPIO_H_SCR_06_0_G6R_RANGE                       6:6
#define GPIO_H_SCR_06_0_G6R_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_06_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_H_SCR_06_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G5R_SHIFT)
#define GPIO_H_SCR_06_0_G5R_RANGE                       5:5
#define GPIO_H_SCR_06_0_G5R_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_06_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_H_SCR_06_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G4R_SHIFT)
#define GPIO_H_SCR_06_0_G4R_RANGE                       4:4
#define GPIO_H_SCR_06_0_G4R_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_06_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_H_SCR_06_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G3R_SHIFT)
#define GPIO_H_SCR_06_0_G3R_RANGE                       3:3
#define GPIO_H_SCR_06_0_G3R_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_06_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_H_SCR_06_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G2R_SHIFT)
#define GPIO_H_SCR_06_0_G2R_RANGE                       2:2
#define GPIO_H_SCR_06_0_G2R_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_06_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_H_SCR_06_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G1R_SHIFT)
#define GPIO_H_SCR_06_0_G1R_RANGE                       1:1
#define GPIO_H_SCR_06_0_G1R_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_06_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_H_SCR_06_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G0R_SHIFT)
#define GPIO_H_SCR_06_0_G0R_RANGE                       0:0
#define GPIO_H_SCR_06_0_G0R_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_H_VM_07_0
#define GPIO_H_VM_07_0                  _MK_ADDR_CONST(0x4078)
#define GPIO_H_VM_07_0_SECURE                   0x0
#define GPIO_H_VM_07_0_DUAL                     0x0
#define GPIO_H_VM_07_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_H_VM_07_0_WORD_COUNT                       0x1
#define GPIO_H_VM_07_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_07_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_07_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_07_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_VM_07_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_07_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_H_VM_07_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_H_VM_07_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_07_0_VM1_SHIFT)
#define GPIO_H_VM_07_0_VM1_RANGE                        1:0
#define GPIO_H_VM_07_0_VM1_WOFFSET                      0x0
#define GPIO_H_VM_07_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_07_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_07_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_07_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_07_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_07_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_07_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_H_VM_07_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_07_0_VM2_SHIFT)
#define GPIO_H_VM_07_0_VM2_RANGE                        3:2
#define GPIO_H_VM_07_0_VM2_WOFFSET                      0x0
#define GPIO_H_VM_07_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_07_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_07_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_07_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_07_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_07_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_07_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_H_VM_07_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_07_0_VM3_SHIFT)
#define GPIO_H_VM_07_0_VM3_RANGE                        5:4
#define GPIO_H_VM_07_0_VM3_WOFFSET                      0x0
#define GPIO_H_VM_07_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_07_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_07_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_07_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_07_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_07_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_07_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_H_VM_07_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_07_0_VM4_SHIFT)
#define GPIO_H_VM_07_0_VM4_RANGE                        7:6
#define GPIO_H_VM_07_0_VM4_WOFFSET                      0x0
#define GPIO_H_VM_07_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_07_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_07_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_07_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_07_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_07_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_07_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_H_VM_07_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_07_0_VM5_SHIFT)
#define GPIO_H_VM_07_0_VM5_RANGE                        9:8
#define GPIO_H_VM_07_0_VM5_WOFFSET                      0x0
#define GPIO_H_VM_07_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_07_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_07_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_07_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_07_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_07_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_07_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_H_VM_07_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_07_0_VM6_SHIFT)
#define GPIO_H_VM_07_0_VM6_RANGE                        11:10
#define GPIO_H_VM_07_0_VM6_WOFFSET                      0x0
#define GPIO_H_VM_07_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_07_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_07_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_07_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_07_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_07_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_07_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_H_VM_07_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_07_0_VM7_SHIFT)
#define GPIO_H_VM_07_0_VM7_RANGE                        13:12
#define GPIO_H_VM_07_0_VM7_WOFFSET                      0x0
#define GPIO_H_VM_07_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_07_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_07_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_07_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_07_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_07_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_H_VM_07_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_H_VM_07_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_H_VM_07_0_VM8_SHIFT)
#define GPIO_H_VM_07_0_VM8_RANGE                        15:14
#define GPIO_H_VM_07_0_VM8_WOFFSET                      0x0
#define GPIO_H_VM_07_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_H_VM_07_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_H_VM_07_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_VM_07_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_VM_07_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_VM_07_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_H_SCR_07_0
#define GPIO_H_SCR_07_0                 _MK_ADDR_CONST(0x407c)
#define GPIO_H_SCR_07_0_SECURE                  0x0
#define GPIO_H_SCR_07_0_DUAL                    0x0
#define GPIO_H_SCR_07_0_SCR                     0
#define GPIO_H_SCR_07_0_WORD_COUNT                      0x1
#define GPIO_H_SCR_07_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_07_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_07_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_07_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_H_SCR_07_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_SEC_LCK_SHIFT)
#define GPIO_H_SCR_07_0_SEC_LCK_RANGE                   29:29
#define GPIO_H_SCR_07_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_H_SCR_07_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_07_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_07_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_H_SCR_07_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_SEC_WEN_SHIFT)
#define GPIO_H_SCR_07_0_SEC_WEN_RANGE                   28:28
#define GPIO_H_SCR_07_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_H_SCR_07_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_07_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_07_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_H_SCR_07_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_SEC_REN_SHIFT)
#define GPIO_H_SCR_07_0_SEC_REN_RANGE                   27:27
#define GPIO_H_SCR_07_0_SEC_REN_WOFFSET                 0x0
#define GPIO_H_SCR_07_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_07_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_07_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_H_SCR_07_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_H_SCR_07_0_SEC_OWNER_SHIFT)
#define GPIO_H_SCR_07_0_SEC_OWNER_RANGE                 26:24
#define GPIO_H_SCR_07_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_H_SCR_07_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_H_SCR_07_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_07_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_H_SCR_07_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_PR7_SHIFT)
#define GPIO_H_SCR_07_0_PR7_RANGE                       23:23
#define GPIO_H_SCR_07_0_PR7_WOFFSET                     0x0
#define GPIO_H_SCR_07_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_07_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_07_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_H_SCR_07_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_PR6_SHIFT)
#define GPIO_H_SCR_07_0_PR6_RANGE                       22:22
#define GPIO_H_SCR_07_0_PR6_WOFFSET                     0x0
#define GPIO_H_SCR_07_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_07_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_07_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_H_SCR_07_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_PR5_SHIFT)
#define GPIO_H_SCR_07_0_PR5_RANGE                       21:21
#define GPIO_H_SCR_07_0_PR5_WOFFSET                     0x0
#define GPIO_H_SCR_07_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_07_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_07_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_H_SCR_07_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_PR4_SHIFT)
#define GPIO_H_SCR_07_0_PR4_RANGE                       20:20
#define GPIO_H_SCR_07_0_PR4_WOFFSET                     0x0
#define GPIO_H_SCR_07_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_07_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_07_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_H_SCR_07_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_PR3_SHIFT)
#define GPIO_H_SCR_07_0_PR3_RANGE                       19:19
#define GPIO_H_SCR_07_0_PR3_WOFFSET                     0x0
#define GPIO_H_SCR_07_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_07_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_07_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_H_SCR_07_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_PR2_SHIFT)
#define GPIO_H_SCR_07_0_PR2_RANGE                       18:18
#define GPIO_H_SCR_07_0_PR2_WOFFSET                     0x0
#define GPIO_H_SCR_07_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_07_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_07_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_H_SCR_07_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_PR1_SHIFT)
#define GPIO_H_SCR_07_0_PR1_RANGE                       17:17
#define GPIO_H_SCR_07_0_PR1_WOFFSET                     0x0
#define GPIO_H_SCR_07_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_07_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_07_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_H_SCR_07_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_PR0_SHIFT)
#define GPIO_H_SCR_07_0_PR0_RANGE                       16:16
#define GPIO_H_SCR_07_0_PR0_WOFFSET                     0x0
#define GPIO_H_SCR_07_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_07_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_07_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_H_SCR_07_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_G7W_SHIFT)
#define GPIO_H_SCR_07_0_G7W_RANGE                       15:15
#define GPIO_H_SCR_07_0_G7W_WOFFSET                     0x0
#define GPIO_H_SCR_07_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_07_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_07_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_H_SCR_07_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_G6W_SHIFT)
#define GPIO_H_SCR_07_0_G6W_RANGE                       14:14
#define GPIO_H_SCR_07_0_G6W_WOFFSET                     0x0
#define GPIO_H_SCR_07_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_07_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_07_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_H_SCR_07_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_G5W_SHIFT)
#define GPIO_H_SCR_07_0_G5W_RANGE                       13:13
#define GPIO_H_SCR_07_0_G5W_WOFFSET                     0x0
#define GPIO_H_SCR_07_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_07_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_07_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_H_SCR_07_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_G4W_SHIFT)
#define GPIO_H_SCR_07_0_G4W_RANGE                       12:12
#define GPIO_H_SCR_07_0_G4W_WOFFSET                     0x0
#define GPIO_H_SCR_07_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_07_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_07_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_H_SCR_07_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_G3W_SHIFT)
#define GPIO_H_SCR_07_0_G3W_RANGE                       11:11
#define GPIO_H_SCR_07_0_G3W_WOFFSET                     0x0
#define GPIO_H_SCR_07_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_07_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_07_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_H_SCR_07_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_G2W_SHIFT)
#define GPIO_H_SCR_07_0_G2W_RANGE                       10:10
#define GPIO_H_SCR_07_0_G2W_WOFFSET                     0x0
#define GPIO_H_SCR_07_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_07_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_07_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_H_SCR_07_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_G1W_SHIFT)
#define GPIO_H_SCR_07_0_G1W_RANGE                       9:9
#define GPIO_H_SCR_07_0_G1W_WOFFSET                     0x0
#define GPIO_H_SCR_07_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_07_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_07_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_H_SCR_07_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_G0W_SHIFT)
#define GPIO_H_SCR_07_0_G0W_RANGE                       8:8
#define GPIO_H_SCR_07_0_G0W_WOFFSET                     0x0
#define GPIO_H_SCR_07_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_07_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_07_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_H_SCR_07_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_G7R_SHIFT)
#define GPIO_H_SCR_07_0_G7R_RANGE                       7:7
#define GPIO_H_SCR_07_0_G7R_WOFFSET                     0x0
#define GPIO_H_SCR_07_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_07_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_07_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_H_SCR_07_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_G6R_SHIFT)
#define GPIO_H_SCR_07_0_G6R_RANGE                       6:6
#define GPIO_H_SCR_07_0_G6R_WOFFSET                     0x0
#define GPIO_H_SCR_07_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_07_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_07_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_H_SCR_07_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_G5R_SHIFT)
#define GPIO_H_SCR_07_0_G5R_RANGE                       5:5
#define GPIO_H_SCR_07_0_G5R_WOFFSET                     0x0
#define GPIO_H_SCR_07_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_07_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_07_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_H_SCR_07_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_G4R_SHIFT)
#define GPIO_H_SCR_07_0_G4R_RANGE                       4:4
#define GPIO_H_SCR_07_0_G4R_WOFFSET                     0x0
#define GPIO_H_SCR_07_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_07_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_07_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_H_SCR_07_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_G3R_SHIFT)
#define GPIO_H_SCR_07_0_G3R_RANGE                       3:3
#define GPIO_H_SCR_07_0_G3R_WOFFSET                     0x0
#define GPIO_H_SCR_07_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_07_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_07_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_H_SCR_07_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_G2R_SHIFT)
#define GPIO_H_SCR_07_0_G2R_RANGE                       2:2
#define GPIO_H_SCR_07_0_G2R_WOFFSET                     0x0
#define GPIO_H_SCR_07_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_07_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_07_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_H_SCR_07_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_G1R_SHIFT)
#define GPIO_H_SCR_07_0_G1R_RANGE                       1:1
#define GPIO_H_SCR_07_0_G1R_WOFFSET                     0x0
#define GPIO_H_SCR_07_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_07_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_H_SCR_07_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_H_SCR_07_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_G0R_SHIFT)
#define GPIO_H_SCR_07_0_G0R_RANGE                       0:0
#define GPIO_H_SCR_07_0_G0R_WOFFSET                     0x0
#define GPIO_H_SCR_07_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_SCR_07_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_I_VM_00_0
#define GPIO_I_VM_00_0                  _MK_ADDR_CONST(0x4080)
#define GPIO_I_VM_00_0_SECURE                   0x0
#define GPIO_I_VM_00_0_DUAL                     0x0
#define GPIO_I_VM_00_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_I_VM_00_0_WORD_COUNT                       0x1
#define GPIO_I_VM_00_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_I_VM_00_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_I_VM_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_I_VM_00_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_I_VM_00_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_I_VM_00_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_00_0_VM1_SHIFT)
#define GPIO_I_VM_00_0_VM1_RANGE                        1:0
#define GPIO_I_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_I_VM_00_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_00_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_00_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_I_VM_00_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_I_VM_00_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_00_0_VM2_SHIFT)
#define GPIO_I_VM_00_0_VM2_RANGE                        3:2
#define GPIO_I_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_I_VM_00_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_00_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_00_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_I_VM_00_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_I_VM_00_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_00_0_VM3_SHIFT)
#define GPIO_I_VM_00_0_VM3_RANGE                        5:4
#define GPIO_I_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_I_VM_00_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_00_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_00_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_I_VM_00_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_I_VM_00_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_00_0_VM4_SHIFT)
#define GPIO_I_VM_00_0_VM4_RANGE                        7:6
#define GPIO_I_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_I_VM_00_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_00_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_00_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_I_VM_00_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_I_VM_00_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_00_0_VM5_SHIFT)
#define GPIO_I_VM_00_0_VM5_RANGE                        9:8
#define GPIO_I_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_I_VM_00_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_00_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_00_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_I_VM_00_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_I_VM_00_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_00_0_VM6_SHIFT)
#define GPIO_I_VM_00_0_VM6_RANGE                        11:10
#define GPIO_I_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_I_VM_00_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_00_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_00_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_I_VM_00_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_I_VM_00_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_00_0_VM7_SHIFT)
#define GPIO_I_VM_00_0_VM7_RANGE                        13:12
#define GPIO_I_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_I_VM_00_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_00_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_00_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_I_VM_00_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_I_VM_00_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_00_0_VM8_SHIFT)
#define GPIO_I_VM_00_0_VM8_RANGE                        15:14
#define GPIO_I_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_I_VM_00_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_00_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_00_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_I_SCR_00_0
#define GPIO_I_SCR_00_0                 _MK_ADDR_CONST(0x4084)
#define GPIO_I_SCR_00_0_SECURE                  0x0
#define GPIO_I_SCR_00_0_DUAL                    0x0
#define GPIO_I_SCR_00_0_SCR                     0
#define GPIO_I_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_I_SCR_00_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_00_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_00_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_I_SCR_00_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_I_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_I_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_I_SCR_00_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_00_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_I_SCR_00_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_I_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_I_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_I_SCR_00_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_00_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_I_SCR_00_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_I_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_I_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_I_SCR_00_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_00_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_I_SCR_00_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_I_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_I_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_I_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_I_SCR_00_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_I_SCR_00_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_00_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_I_SCR_00_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_PR7_SHIFT)
#define GPIO_I_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_I_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_00_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_I_SCR_00_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_PR6_SHIFT)
#define GPIO_I_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_I_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_00_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_I_SCR_00_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_PR5_SHIFT)
#define GPIO_I_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_I_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_00_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_I_SCR_00_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_PR4_SHIFT)
#define GPIO_I_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_I_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_00_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_I_SCR_00_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_PR3_SHIFT)
#define GPIO_I_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_I_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_00_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_I_SCR_00_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_PR2_SHIFT)
#define GPIO_I_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_I_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_00_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_I_SCR_00_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_PR1_SHIFT)
#define GPIO_I_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_I_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_00_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_I_SCR_00_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_PR0_SHIFT)
#define GPIO_I_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_I_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_00_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_I_SCR_00_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G7W_SHIFT)
#define GPIO_I_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_I_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_00_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_I_SCR_00_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G6W_SHIFT)
#define GPIO_I_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_I_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_00_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_I_SCR_00_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G5W_SHIFT)
#define GPIO_I_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_I_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_00_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_I_SCR_00_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G4W_SHIFT)
#define GPIO_I_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_I_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_00_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_I_SCR_00_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G3W_SHIFT)
#define GPIO_I_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_I_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_00_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_I_SCR_00_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G2W_SHIFT)
#define GPIO_I_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_I_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_00_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_I_SCR_00_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G1W_SHIFT)
#define GPIO_I_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_I_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_00_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_I_SCR_00_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G0W_SHIFT)
#define GPIO_I_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_I_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_00_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_I_SCR_00_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G7R_SHIFT)
#define GPIO_I_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_I_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_00_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_I_SCR_00_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G6R_SHIFT)
#define GPIO_I_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_I_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_00_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_I_SCR_00_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G5R_SHIFT)
#define GPIO_I_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_I_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_00_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_I_SCR_00_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G4R_SHIFT)
#define GPIO_I_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_I_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_00_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_I_SCR_00_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G3R_SHIFT)
#define GPIO_I_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_I_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_00_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_I_SCR_00_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G2R_SHIFT)
#define GPIO_I_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_I_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_00_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_I_SCR_00_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G1R_SHIFT)
#define GPIO_I_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_I_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_00_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_I_SCR_00_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G0R_SHIFT)
#define GPIO_I_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_I_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_I_VM_01_0
#define GPIO_I_VM_01_0                  _MK_ADDR_CONST(0x4088)
#define GPIO_I_VM_01_0_SECURE                   0x0
#define GPIO_I_VM_01_0_DUAL                     0x0
#define GPIO_I_VM_01_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_I_VM_01_0_WORD_COUNT                       0x1
#define GPIO_I_VM_01_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_I_VM_01_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_I_VM_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_I_VM_01_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_I_VM_01_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_I_VM_01_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_01_0_VM1_SHIFT)
#define GPIO_I_VM_01_0_VM1_RANGE                        1:0
#define GPIO_I_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_I_VM_01_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_01_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_01_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_I_VM_01_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_I_VM_01_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_01_0_VM2_SHIFT)
#define GPIO_I_VM_01_0_VM2_RANGE                        3:2
#define GPIO_I_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_I_VM_01_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_01_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_01_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_I_VM_01_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_I_VM_01_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_01_0_VM3_SHIFT)
#define GPIO_I_VM_01_0_VM3_RANGE                        5:4
#define GPIO_I_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_I_VM_01_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_01_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_01_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_I_VM_01_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_I_VM_01_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_01_0_VM4_SHIFT)
#define GPIO_I_VM_01_0_VM4_RANGE                        7:6
#define GPIO_I_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_I_VM_01_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_01_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_01_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_I_VM_01_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_I_VM_01_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_01_0_VM5_SHIFT)
#define GPIO_I_VM_01_0_VM5_RANGE                        9:8
#define GPIO_I_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_I_VM_01_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_01_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_01_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_I_VM_01_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_I_VM_01_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_01_0_VM6_SHIFT)
#define GPIO_I_VM_01_0_VM6_RANGE                        11:10
#define GPIO_I_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_I_VM_01_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_01_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_01_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_I_VM_01_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_I_VM_01_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_01_0_VM7_SHIFT)
#define GPIO_I_VM_01_0_VM7_RANGE                        13:12
#define GPIO_I_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_I_VM_01_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_01_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_01_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_I_VM_01_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_I_VM_01_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_01_0_VM8_SHIFT)
#define GPIO_I_VM_01_0_VM8_RANGE                        15:14
#define GPIO_I_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_I_VM_01_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_01_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_01_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_I_SCR_01_0
#define GPIO_I_SCR_01_0                 _MK_ADDR_CONST(0x408c)
#define GPIO_I_SCR_01_0_SECURE                  0x0
#define GPIO_I_SCR_01_0_DUAL                    0x0
#define GPIO_I_SCR_01_0_SCR                     0
#define GPIO_I_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_I_SCR_01_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_01_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_01_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_01_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_I_SCR_01_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_I_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_I_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_I_SCR_01_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_01_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_I_SCR_01_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_I_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_I_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_I_SCR_01_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_01_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_I_SCR_01_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_I_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_I_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_I_SCR_01_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_01_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_I_SCR_01_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_I_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_I_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_I_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_I_SCR_01_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_I_SCR_01_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_01_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_I_SCR_01_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_PR7_SHIFT)
#define GPIO_I_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_I_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_01_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_I_SCR_01_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_PR6_SHIFT)
#define GPIO_I_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_I_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_01_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_I_SCR_01_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_PR5_SHIFT)
#define GPIO_I_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_I_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_01_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_I_SCR_01_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_PR4_SHIFT)
#define GPIO_I_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_I_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_01_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_I_SCR_01_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_PR3_SHIFT)
#define GPIO_I_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_I_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_01_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_I_SCR_01_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_PR2_SHIFT)
#define GPIO_I_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_I_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_01_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_I_SCR_01_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_PR1_SHIFT)
#define GPIO_I_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_I_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_01_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_I_SCR_01_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_PR0_SHIFT)
#define GPIO_I_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_I_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_01_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_I_SCR_01_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G7W_SHIFT)
#define GPIO_I_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_I_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_01_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_I_SCR_01_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G6W_SHIFT)
#define GPIO_I_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_I_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_01_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_I_SCR_01_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G5W_SHIFT)
#define GPIO_I_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_I_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_01_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_I_SCR_01_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G4W_SHIFT)
#define GPIO_I_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_I_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_01_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_I_SCR_01_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G3W_SHIFT)
#define GPIO_I_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_I_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_01_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_I_SCR_01_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G2W_SHIFT)
#define GPIO_I_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_I_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_01_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_I_SCR_01_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G1W_SHIFT)
#define GPIO_I_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_I_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_01_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_I_SCR_01_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G0W_SHIFT)
#define GPIO_I_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_I_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_01_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_I_SCR_01_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G7R_SHIFT)
#define GPIO_I_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_I_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_01_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_I_SCR_01_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G6R_SHIFT)
#define GPIO_I_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_I_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_01_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_I_SCR_01_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G5R_SHIFT)
#define GPIO_I_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_I_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_01_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_I_SCR_01_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G4R_SHIFT)
#define GPIO_I_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_I_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_01_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_I_SCR_01_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G3R_SHIFT)
#define GPIO_I_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_I_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_01_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_I_SCR_01_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G2R_SHIFT)
#define GPIO_I_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_I_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_01_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_I_SCR_01_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G1R_SHIFT)
#define GPIO_I_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_I_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_01_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_I_SCR_01_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G0R_SHIFT)
#define GPIO_I_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_I_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_I_VM_02_0
#define GPIO_I_VM_02_0                  _MK_ADDR_CONST(0x4090)
#define GPIO_I_VM_02_0_SECURE                   0x0
#define GPIO_I_VM_02_0_DUAL                     0x0
#define GPIO_I_VM_02_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_I_VM_02_0_WORD_COUNT                       0x1
#define GPIO_I_VM_02_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_I_VM_02_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_I_VM_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_I_VM_02_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_I_VM_02_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_I_VM_02_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_02_0_VM1_SHIFT)
#define GPIO_I_VM_02_0_VM1_RANGE                        1:0
#define GPIO_I_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_I_VM_02_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_02_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_02_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_I_VM_02_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_I_VM_02_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_02_0_VM2_SHIFT)
#define GPIO_I_VM_02_0_VM2_RANGE                        3:2
#define GPIO_I_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_I_VM_02_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_02_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_02_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_I_VM_02_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_I_VM_02_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_02_0_VM3_SHIFT)
#define GPIO_I_VM_02_0_VM3_RANGE                        5:4
#define GPIO_I_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_I_VM_02_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_02_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_02_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_I_VM_02_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_I_VM_02_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_02_0_VM4_SHIFT)
#define GPIO_I_VM_02_0_VM4_RANGE                        7:6
#define GPIO_I_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_I_VM_02_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_02_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_02_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_I_VM_02_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_I_VM_02_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_02_0_VM5_SHIFT)
#define GPIO_I_VM_02_0_VM5_RANGE                        9:8
#define GPIO_I_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_I_VM_02_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_02_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_02_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_I_VM_02_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_I_VM_02_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_02_0_VM6_SHIFT)
#define GPIO_I_VM_02_0_VM6_RANGE                        11:10
#define GPIO_I_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_I_VM_02_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_02_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_02_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_I_VM_02_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_I_VM_02_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_02_0_VM7_SHIFT)
#define GPIO_I_VM_02_0_VM7_RANGE                        13:12
#define GPIO_I_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_I_VM_02_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_02_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_02_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_I_VM_02_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_I_VM_02_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_02_0_VM8_SHIFT)
#define GPIO_I_VM_02_0_VM8_RANGE                        15:14
#define GPIO_I_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_I_VM_02_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_02_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_02_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_I_SCR_02_0
#define GPIO_I_SCR_02_0                 _MK_ADDR_CONST(0x4094)
#define GPIO_I_SCR_02_0_SECURE                  0x0
#define GPIO_I_SCR_02_0_DUAL                    0x0
#define GPIO_I_SCR_02_0_SCR                     0
#define GPIO_I_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_I_SCR_02_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_02_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_02_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_02_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_I_SCR_02_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_I_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_I_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_I_SCR_02_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_02_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_I_SCR_02_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_I_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_I_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_I_SCR_02_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_02_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_I_SCR_02_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_I_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_I_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_I_SCR_02_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_02_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_I_SCR_02_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_I_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_I_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_I_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_I_SCR_02_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_I_SCR_02_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_02_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_I_SCR_02_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_PR7_SHIFT)
#define GPIO_I_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_I_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_02_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_I_SCR_02_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_PR6_SHIFT)
#define GPIO_I_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_I_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_02_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_I_SCR_02_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_PR5_SHIFT)
#define GPIO_I_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_I_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_02_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_I_SCR_02_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_PR4_SHIFT)
#define GPIO_I_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_I_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_02_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_I_SCR_02_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_PR3_SHIFT)
#define GPIO_I_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_I_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_02_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_I_SCR_02_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_PR2_SHIFT)
#define GPIO_I_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_I_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_02_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_I_SCR_02_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_PR1_SHIFT)
#define GPIO_I_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_I_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_02_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_I_SCR_02_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_PR0_SHIFT)
#define GPIO_I_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_I_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_02_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_I_SCR_02_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G7W_SHIFT)
#define GPIO_I_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_I_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_02_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_I_SCR_02_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G6W_SHIFT)
#define GPIO_I_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_I_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_02_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_I_SCR_02_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G5W_SHIFT)
#define GPIO_I_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_I_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_02_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_I_SCR_02_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G4W_SHIFT)
#define GPIO_I_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_I_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_02_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_I_SCR_02_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G3W_SHIFT)
#define GPIO_I_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_I_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_02_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_I_SCR_02_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G2W_SHIFT)
#define GPIO_I_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_I_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_02_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_I_SCR_02_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G1W_SHIFT)
#define GPIO_I_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_I_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_02_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_I_SCR_02_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G0W_SHIFT)
#define GPIO_I_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_I_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_02_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_I_SCR_02_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G7R_SHIFT)
#define GPIO_I_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_I_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_02_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_I_SCR_02_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G6R_SHIFT)
#define GPIO_I_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_I_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_02_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_I_SCR_02_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G5R_SHIFT)
#define GPIO_I_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_I_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_02_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_I_SCR_02_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G4R_SHIFT)
#define GPIO_I_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_I_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_02_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_I_SCR_02_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G3R_SHIFT)
#define GPIO_I_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_I_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_02_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_I_SCR_02_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G2R_SHIFT)
#define GPIO_I_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_I_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_02_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_I_SCR_02_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G1R_SHIFT)
#define GPIO_I_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_I_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_02_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_I_SCR_02_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G0R_SHIFT)
#define GPIO_I_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_I_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_I_VM_03_0
#define GPIO_I_VM_03_0                  _MK_ADDR_CONST(0x4098)
#define GPIO_I_VM_03_0_SECURE                   0x0
#define GPIO_I_VM_03_0_DUAL                     0x0
#define GPIO_I_VM_03_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_I_VM_03_0_WORD_COUNT                       0x1
#define GPIO_I_VM_03_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_I_VM_03_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_I_VM_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_I_VM_03_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_I_VM_03_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_I_VM_03_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_03_0_VM1_SHIFT)
#define GPIO_I_VM_03_0_VM1_RANGE                        1:0
#define GPIO_I_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_I_VM_03_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_03_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_03_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_I_VM_03_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_I_VM_03_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_03_0_VM2_SHIFT)
#define GPIO_I_VM_03_0_VM2_RANGE                        3:2
#define GPIO_I_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_I_VM_03_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_03_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_03_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_I_VM_03_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_I_VM_03_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_03_0_VM3_SHIFT)
#define GPIO_I_VM_03_0_VM3_RANGE                        5:4
#define GPIO_I_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_I_VM_03_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_03_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_03_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_I_VM_03_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_I_VM_03_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_03_0_VM4_SHIFT)
#define GPIO_I_VM_03_0_VM4_RANGE                        7:6
#define GPIO_I_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_I_VM_03_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_03_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_03_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_I_VM_03_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_I_VM_03_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_03_0_VM5_SHIFT)
#define GPIO_I_VM_03_0_VM5_RANGE                        9:8
#define GPIO_I_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_I_VM_03_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_03_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_03_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_I_VM_03_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_I_VM_03_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_03_0_VM6_SHIFT)
#define GPIO_I_VM_03_0_VM6_RANGE                        11:10
#define GPIO_I_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_I_VM_03_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_03_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_03_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_I_VM_03_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_I_VM_03_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_03_0_VM7_SHIFT)
#define GPIO_I_VM_03_0_VM7_RANGE                        13:12
#define GPIO_I_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_I_VM_03_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_03_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_03_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_I_VM_03_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_I_VM_03_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_03_0_VM8_SHIFT)
#define GPIO_I_VM_03_0_VM8_RANGE                        15:14
#define GPIO_I_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_I_VM_03_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_03_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_03_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_I_SCR_03_0
#define GPIO_I_SCR_03_0                 _MK_ADDR_CONST(0x409c)
#define GPIO_I_SCR_03_0_SECURE                  0x0
#define GPIO_I_SCR_03_0_DUAL                    0x0
#define GPIO_I_SCR_03_0_SCR                     0
#define GPIO_I_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_I_SCR_03_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_03_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_03_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_03_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_I_SCR_03_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_I_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_I_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_I_SCR_03_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_03_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_I_SCR_03_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_I_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_I_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_I_SCR_03_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_03_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_I_SCR_03_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_I_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_I_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_I_SCR_03_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_03_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_I_SCR_03_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_I_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_I_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_I_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_I_SCR_03_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_I_SCR_03_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_03_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_I_SCR_03_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_PR7_SHIFT)
#define GPIO_I_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_I_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_03_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_I_SCR_03_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_PR6_SHIFT)
#define GPIO_I_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_I_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_03_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_I_SCR_03_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_PR5_SHIFT)
#define GPIO_I_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_I_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_03_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_I_SCR_03_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_PR4_SHIFT)
#define GPIO_I_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_I_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_03_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_I_SCR_03_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_PR3_SHIFT)
#define GPIO_I_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_I_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_03_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_I_SCR_03_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_PR2_SHIFT)
#define GPIO_I_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_I_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_03_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_I_SCR_03_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_PR1_SHIFT)
#define GPIO_I_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_I_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_03_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_I_SCR_03_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_PR0_SHIFT)
#define GPIO_I_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_I_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_03_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_I_SCR_03_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G7W_SHIFT)
#define GPIO_I_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_I_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_03_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_I_SCR_03_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G6W_SHIFT)
#define GPIO_I_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_I_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_03_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_I_SCR_03_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G5W_SHIFT)
#define GPIO_I_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_I_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_03_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_I_SCR_03_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G4W_SHIFT)
#define GPIO_I_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_I_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_03_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_I_SCR_03_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G3W_SHIFT)
#define GPIO_I_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_I_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_03_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_I_SCR_03_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G2W_SHIFT)
#define GPIO_I_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_I_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_03_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_I_SCR_03_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G1W_SHIFT)
#define GPIO_I_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_I_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_03_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_I_SCR_03_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G0W_SHIFT)
#define GPIO_I_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_I_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_03_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_I_SCR_03_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G7R_SHIFT)
#define GPIO_I_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_I_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_03_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_I_SCR_03_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G6R_SHIFT)
#define GPIO_I_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_I_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_03_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_I_SCR_03_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G5R_SHIFT)
#define GPIO_I_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_I_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_03_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_I_SCR_03_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G4R_SHIFT)
#define GPIO_I_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_I_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_03_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_I_SCR_03_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G3R_SHIFT)
#define GPIO_I_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_I_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_03_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_I_SCR_03_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G2R_SHIFT)
#define GPIO_I_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_I_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_03_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_I_SCR_03_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G1R_SHIFT)
#define GPIO_I_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_I_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_03_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_I_SCR_03_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G0R_SHIFT)
#define GPIO_I_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_I_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_I_VM_04_0
#define GPIO_I_VM_04_0                  _MK_ADDR_CONST(0x40a0)
#define GPIO_I_VM_04_0_SECURE                   0x0
#define GPIO_I_VM_04_0_DUAL                     0x0
#define GPIO_I_VM_04_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_I_VM_04_0_WORD_COUNT                       0x1
#define GPIO_I_VM_04_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_I_VM_04_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_I_VM_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_I_VM_04_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_I_VM_04_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_I_VM_04_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_04_0_VM1_SHIFT)
#define GPIO_I_VM_04_0_VM1_RANGE                        1:0
#define GPIO_I_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_I_VM_04_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_04_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_04_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_I_VM_04_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_I_VM_04_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_04_0_VM2_SHIFT)
#define GPIO_I_VM_04_0_VM2_RANGE                        3:2
#define GPIO_I_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_I_VM_04_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_04_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_04_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_I_VM_04_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_I_VM_04_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_04_0_VM3_SHIFT)
#define GPIO_I_VM_04_0_VM3_RANGE                        5:4
#define GPIO_I_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_I_VM_04_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_04_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_04_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_I_VM_04_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_I_VM_04_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_04_0_VM4_SHIFT)
#define GPIO_I_VM_04_0_VM4_RANGE                        7:6
#define GPIO_I_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_I_VM_04_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_04_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_04_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_I_VM_04_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_I_VM_04_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_04_0_VM5_SHIFT)
#define GPIO_I_VM_04_0_VM5_RANGE                        9:8
#define GPIO_I_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_I_VM_04_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_04_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_04_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_I_VM_04_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_I_VM_04_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_04_0_VM6_SHIFT)
#define GPIO_I_VM_04_0_VM6_RANGE                        11:10
#define GPIO_I_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_I_VM_04_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_04_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_04_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_I_VM_04_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_I_VM_04_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_04_0_VM7_SHIFT)
#define GPIO_I_VM_04_0_VM7_RANGE                        13:12
#define GPIO_I_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_I_VM_04_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_04_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_04_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_I_VM_04_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_I_VM_04_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_I_VM_04_0_VM8_SHIFT)
#define GPIO_I_VM_04_0_VM8_RANGE                        15:14
#define GPIO_I_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_I_VM_04_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_I_VM_04_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_I_VM_04_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_I_SCR_04_0
#define GPIO_I_SCR_04_0                 _MK_ADDR_CONST(0x40a4)
#define GPIO_I_SCR_04_0_SECURE                  0x0
#define GPIO_I_SCR_04_0_DUAL                    0x0
#define GPIO_I_SCR_04_0_SCR                     0
#define GPIO_I_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_I_SCR_04_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_04_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_04_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_04_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_I_SCR_04_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_I_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_I_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_I_SCR_04_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_04_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_I_SCR_04_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_I_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_I_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_I_SCR_04_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_04_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_I_SCR_04_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_I_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_I_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_I_SCR_04_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_04_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_I_SCR_04_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_I_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_I_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_I_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_I_SCR_04_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_I_SCR_04_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_04_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_I_SCR_04_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_PR7_SHIFT)
#define GPIO_I_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_I_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_04_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_I_SCR_04_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_PR6_SHIFT)
#define GPIO_I_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_I_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_04_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_I_SCR_04_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_PR5_SHIFT)
#define GPIO_I_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_I_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_04_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_I_SCR_04_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_PR4_SHIFT)
#define GPIO_I_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_I_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_04_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_I_SCR_04_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_PR3_SHIFT)
#define GPIO_I_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_I_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_04_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_I_SCR_04_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_PR2_SHIFT)
#define GPIO_I_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_I_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_04_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_I_SCR_04_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_PR1_SHIFT)
#define GPIO_I_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_I_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_04_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_I_SCR_04_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_PR0_SHIFT)
#define GPIO_I_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_I_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_04_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_I_SCR_04_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G7W_SHIFT)
#define GPIO_I_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_I_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_04_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_I_SCR_04_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G6W_SHIFT)
#define GPIO_I_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_I_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_04_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_I_SCR_04_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G5W_SHIFT)
#define GPIO_I_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_I_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_04_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_I_SCR_04_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G4W_SHIFT)
#define GPIO_I_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_I_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_04_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_I_SCR_04_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G3W_SHIFT)
#define GPIO_I_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_I_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_04_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_I_SCR_04_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G2W_SHIFT)
#define GPIO_I_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_I_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_04_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_I_SCR_04_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G1W_SHIFT)
#define GPIO_I_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_I_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_04_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_I_SCR_04_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G0W_SHIFT)
#define GPIO_I_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_I_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_04_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_I_SCR_04_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G7R_SHIFT)
#define GPIO_I_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_I_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_04_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_I_SCR_04_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G6R_SHIFT)
#define GPIO_I_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_I_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_04_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_I_SCR_04_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G5R_SHIFT)
#define GPIO_I_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_I_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_04_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_I_SCR_04_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G4R_SHIFT)
#define GPIO_I_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_I_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_04_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_I_SCR_04_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G3R_SHIFT)
#define GPIO_I_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_I_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_04_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_I_SCR_04_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G2R_SHIFT)
#define GPIO_I_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_I_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_04_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_I_SCR_04_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G1R_SHIFT)
#define GPIO_I_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_I_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_I_SCR_04_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_I_SCR_04_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G0R_SHIFT)
#define GPIO_I_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_I_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Reserved address 0x40a8

// Reserved address 0x40ac

// Reserved address 0x40b0

// Reserved address 0x40b4

// Reserved address 0x40b8

// Reserved address 0x40bc

// Register GPIO_C_VM_00_0
#define GPIO_C_VM_00_0                  _MK_ADDR_CONST(0x40c0)
#define GPIO_C_VM_00_0_SECURE                   0x0
#define GPIO_C_VM_00_0_DUAL                     0x0
#define GPIO_C_VM_00_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_C_VM_00_0_WORD_COUNT                       0x1
#define GPIO_C_VM_00_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_00_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_00_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_00_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_C_VM_00_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_00_0_VM1_SHIFT)
#define GPIO_C_VM_00_0_VM1_RANGE                        1:0
#define GPIO_C_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_C_VM_00_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_00_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_00_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_00_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_C_VM_00_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_00_0_VM2_SHIFT)
#define GPIO_C_VM_00_0_VM2_RANGE                        3:2
#define GPIO_C_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_C_VM_00_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_00_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_00_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_00_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_C_VM_00_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_00_0_VM3_SHIFT)
#define GPIO_C_VM_00_0_VM3_RANGE                        5:4
#define GPIO_C_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_C_VM_00_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_00_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_00_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_00_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_C_VM_00_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_00_0_VM4_SHIFT)
#define GPIO_C_VM_00_0_VM4_RANGE                        7:6
#define GPIO_C_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_C_VM_00_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_00_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_00_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_00_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_C_VM_00_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_00_0_VM5_SHIFT)
#define GPIO_C_VM_00_0_VM5_RANGE                        9:8
#define GPIO_C_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_C_VM_00_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_00_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_00_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_00_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_C_VM_00_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_00_0_VM6_SHIFT)
#define GPIO_C_VM_00_0_VM6_RANGE                        11:10
#define GPIO_C_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_C_VM_00_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_00_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_00_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_00_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_C_VM_00_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_00_0_VM7_SHIFT)
#define GPIO_C_VM_00_0_VM7_RANGE                        13:12
#define GPIO_C_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_C_VM_00_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_00_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_00_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_00_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_C_VM_00_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_00_0_VM8_SHIFT)
#define GPIO_C_VM_00_0_VM8_RANGE                        15:14
#define GPIO_C_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_C_VM_00_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_00_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_00_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_C_SCR_00_0
#define GPIO_C_SCR_00_0                 _MK_ADDR_CONST(0x40c4)
#define GPIO_C_SCR_00_0_SECURE                  0x0
#define GPIO_C_SCR_00_0_DUAL                    0x0
#define GPIO_C_SCR_00_0_SCR                     0
#define GPIO_C_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_C_SCR_00_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_00_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_00_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_C_SCR_00_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_C_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_C_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_C_SCR_00_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_00_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_C_SCR_00_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_C_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_C_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_C_SCR_00_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_00_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_C_SCR_00_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_C_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_C_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_C_SCR_00_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_00_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_C_SCR_00_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_C_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_C_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_C_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_C_SCR_00_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_C_SCR_00_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_00_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_C_SCR_00_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_PR7_SHIFT)
#define GPIO_C_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_C_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_00_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_C_SCR_00_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_PR6_SHIFT)
#define GPIO_C_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_C_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_00_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_C_SCR_00_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_PR5_SHIFT)
#define GPIO_C_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_C_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_00_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_C_SCR_00_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_PR4_SHIFT)
#define GPIO_C_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_C_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_00_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_C_SCR_00_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_PR3_SHIFT)
#define GPIO_C_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_C_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_00_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_C_SCR_00_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_PR2_SHIFT)
#define GPIO_C_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_C_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_00_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_C_SCR_00_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_PR1_SHIFT)
#define GPIO_C_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_C_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_00_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_C_SCR_00_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_PR0_SHIFT)
#define GPIO_C_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_C_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_00_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_C_SCR_00_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G7W_SHIFT)
#define GPIO_C_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_C_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_00_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_C_SCR_00_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G6W_SHIFT)
#define GPIO_C_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_C_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_00_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_C_SCR_00_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G5W_SHIFT)
#define GPIO_C_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_C_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_00_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_C_SCR_00_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G4W_SHIFT)
#define GPIO_C_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_C_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_00_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_C_SCR_00_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G3W_SHIFT)
#define GPIO_C_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_C_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_00_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_C_SCR_00_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G2W_SHIFT)
#define GPIO_C_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_C_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_00_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_C_SCR_00_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G1W_SHIFT)
#define GPIO_C_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_C_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_00_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_C_SCR_00_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G0W_SHIFT)
#define GPIO_C_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_C_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_00_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_C_SCR_00_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G7R_SHIFT)
#define GPIO_C_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_C_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_00_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_C_SCR_00_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G6R_SHIFT)
#define GPIO_C_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_C_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_00_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_C_SCR_00_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G5R_SHIFT)
#define GPIO_C_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_C_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_00_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_C_SCR_00_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G4R_SHIFT)
#define GPIO_C_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_C_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_00_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_C_SCR_00_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G3R_SHIFT)
#define GPIO_C_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_C_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_00_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_C_SCR_00_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G2R_SHIFT)
#define GPIO_C_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_C_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_00_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_C_SCR_00_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G1R_SHIFT)
#define GPIO_C_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_C_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_00_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_C_SCR_00_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G0R_SHIFT)
#define GPIO_C_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_C_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_C_VM_01_0
#define GPIO_C_VM_01_0                  _MK_ADDR_CONST(0x40c8)
#define GPIO_C_VM_01_0_SECURE                   0x0
#define GPIO_C_VM_01_0_DUAL                     0x0
#define GPIO_C_VM_01_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_C_VM_01_0_WORD_COUNT                       0x1
#define GPIO_C_VM_01_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_01_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_01_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_01_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_C_VM_01_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_01_0_VM1_SHIFT)
#define GPIO_C_VM_01_0_VM1_RANGE                        1:0
#define GPIO_C_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_C_VM_01_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_01_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_01_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_01_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_C_VM_01_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_01_0_VM2_SHIFT)
#define GPIO_C_VM_01_0_VM2_RANGE                        3:2
#define GPIO_C_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_C_VM_01_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_01_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_01_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_01_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_C_VM_01_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_01_0_VM3_SHIFT)
#define GPIO_C_VM_01_0_VM3_RANGE                        5:4
#define GPIO_C_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_C_VM_01_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_01_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_01_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_01_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_C_VM_01_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_01_0_VM4_SHIFT)
#define GPIO_C_VM_01_0_VM4_RANGE                        7:6
#define GPIO_C_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_C_VM_01_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_01_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_01_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_01_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_C_VM_01_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_01_0_VM5_SHIFT)
#define GPIO_C_VM_01_0_VM5_RANGE                        9:8
#define GPIO_C_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_C_VM_01_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_01_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_01_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_01_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_C_VM_01_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_01_0_VM6_SHIFT)
#define GPIO_C_VM_01_0_VM6_RANGE                        11:10
#define GPIO_C_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_C_VM_01_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_01_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_01_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_01_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_C_VM_01_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_01_0_VM7_SHIFT)
#define GPIO_C_VM_01_0_VM7_RANGE                        13:12
#define GPIO_C_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_C_VM_01_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_01_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_01_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_01_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_C_VM_01_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_01_0_VM8_SHIFT)
#define GPIO_C_VM_01_0_VM8_RANGE                        15:14
#define GPIO_C_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_C_VM_01_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_01_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_01_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_C_SCR_01_0
#define GPIO_C_SCR_01_0                 _MK_ADDR_CONST(0x40cc)
#define GPIO_C_SCR_01_0_SECURE                  0x0
#define GPIO_C_SCR_01_0_DUAL                    0x0
#define GPIO_C_SCR_01_0_SCR                     0
#define GPIO_C_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_C_SCR_01_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_01_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_01_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_01_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_C_SCR_01_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_C_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_C_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_C_SCR_01_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_01_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_C_SCR_01_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_C_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_C_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_C_SCR_01_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_01_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_C_SCR_01_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_C_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_C_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_C_SCR_01_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_01_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_C_SCR_01_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_C_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_C_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_C_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_C_SCR_01_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_C_SCR_01_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_01_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_C_SCR_01_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_PR7_SHIFT)
#define GPIO_C_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_C_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_01_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_C_SCR_01_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_PR6_SHIFT)
#define GPIO_C_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_C_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_01_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_C_SCR_01_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_PR5_SHIFT)
#define GPIO_C_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_C_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_01_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_C_SCR_01_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_PR4_SHIFT)
#define GPIO_C_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_C_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_01_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_C_SCR_01_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_PR3_SHIFT)
#define GPIO_C_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_C_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_01_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_C_SCR_01_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_PR2_SHIFT)
#define GPIO_C_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_C_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_01_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_C_SCR_01_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_PR1_SHIFT)
#define GPIO_C_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_C_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_01_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_C_SCR_01_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_PR0_SHIFT)
#define GPIO_C_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_C_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_01_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_C_SCR_01_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G7W_SHIFT)
#define GPIO_C_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_C_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_01_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_C_SCR_01_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G6W_SHIFT)
#define GPIO_C_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_C_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_01_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_C_SCR_01_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G5W_SHIFT)
#define GPIO_C_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_C_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_01_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_C_SCR_01_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G4W_SHIFT)
#define GPIO_C_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_C_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_01_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_C_SCR_01_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G3W_SHIFT)
#define GPIO_C_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_C_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_01_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_C_SCR_01_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G2W_SHIFT)
#define GPIO_C_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_C_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_01_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_C_SCR_01_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G1W_SHIFT)
#define GPIO_C_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_C_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_01_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_C_SCR_01_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G0W_SHIFT)
#define GPIO_C_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_C_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_01_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_C_SCR_01_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G7R_SHIFT)
#define GPIO_C_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_C_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_01_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_C_SCR_01_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G6R_SHIFT)
#define GPIO_C_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_C_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_01_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_C_SCR_01_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G5R_SHIFT)
#define GPIO_C_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_C_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_01_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_C_SCR_01_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G4R_SHIFT)
#define GPIO_C_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_C_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_01_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_C_SCR_01_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G3R_SHIFT)
#define GPIO_C_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_C_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_01_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_C_SCR_01_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G2R_SHIFT)
#define GPIO_C_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_C_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_01_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_C_SCR_01_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G1R_SHIFT)
#define GPIO_C_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_C_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_01_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_C_SCR_01_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G0R_SHIFT)
#define GPIO_C_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_C_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_C_VM_02_0
#define GPIO_C_VM_02_0                  _MK_ADDR_CONST(0x40d0)
#define GPIO_C_VM_02_0_SECURE                   0x0
#define GPIO_C_VM_02_0_DUAL                     0x0
#define GPIO_C_VM_02_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_C_VM_02_0_WORD_COUNT                       0x1
#define GPIO_C_VM_02_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_02_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_02_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_02_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_C_VM_02_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_02_0_VM1_SHIFT)
#define GPIO_C_VM_02_0_VM1_RANGE                        1:0
#define GPIO_C_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_C_VM_02_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_02_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_02_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_02_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_C_VM_02_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_02_0_VM2_SHIFT)
#define GPIO_C_VM_02_0_VM2_RANGE                        3:2
#define GPIO_C_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_C_VM_02_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_02_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_02_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_02_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_C_VM_02_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_02_0_VM3_SHIFT)
#define GPIO_C_VM_02_0_VM3_RANGE                        5:4
#define GPIO_C_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_C_VM_02_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_02_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_02_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_02_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_C_VM_02_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_02_0_VM4_SHIFT)
#define GPIO_C_VM_02_0_VM4_RANGE                        7:6
#define GPIO_C_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_C_VM_02_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_02_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_02_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_02_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_C_VM_02_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_02_0_VM5_SHIFT)
#define GPIO_C_VM_02_0_VM5_RANGE                        9:8
#define GPIO_C_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_C_VM_02_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_02_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_02_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_02_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_C_VM_02_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_02_0_VM6_SHIFT)
#define GPIO_C_VM_02_0_VM6_RANGE                        11:10
#define GPIO_C_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_C_VM_02_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_02_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_02_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_02_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_C_VM_02_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_02_0_VM7_SHIFT)
#define GPIO_C_VM_02_0_VM7_RANGE                        13:12
#define GPIO_C_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_C_VM_02_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_02_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_02_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_02_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_C_VM_02_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_02_0_VM8_SHIFT)
#define GPIO_C_VM_02_0_VM8_RANGE                        15:14
#define GPIO_C_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_C_VM_02_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_02_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_02_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_C_SCR_02_0
#define GPIO_C_SCR_02_0                 _MK_ADDR_CONST(0x40d4)
#define GPIO_C_SCR_02_0_SECURE                  0x0
#define GPIO_C_SCR_02_0_DUAL                    0x0
#define GPIO_C_SCR_02_0_SCR                     0
#define GPIO_C_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_C_SCR_02_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_02_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_02_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_02_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_C_SCR_02_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_C_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_C_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_C_SCR_02_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_02_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_C_SCR_02_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_C_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_C_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_C_SCR_02_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_02_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_C_SCR_02_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_C_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_C_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_C_SCR_02_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_02_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_C_SCR_02_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_C_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_C_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_C_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_C_SCR_02_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_C_SCR_02_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_02_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_C_SCR_02_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_PR7_SHIFT)
#define GPIO_C_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_C_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_02_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_C_SCR_02_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_PR6_SHIFT)
#define GPIO_C_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_C_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_02_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_C_SCR_02_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_PR5_SHIFT)
#define GPIO_C_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_C_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_02_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_C_SCR_02_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_PR4_SHIFT)
#define GPIO_C_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_C_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_02_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_C_SCR_02_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_PR3_SHIFT)
#define GPIO_C_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_C_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_02_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_C_SCR_02_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_PR2_SHIFT)
#define GPIO_C_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_C_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_02_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_C_SCR_02_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_PR1_SHIFT)
#define GPIO_C_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_C_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_02_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_C_SCR_02_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_PR0_SHIFT)
#define GPIO_C_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_C_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_02_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_C_SCR_02_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G7W_SHIFT)
#define GPIO_C_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_C_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_02_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_C_SCR_02_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G6W_SHIFT)
#define GPIO_C_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_C_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_02_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_C_SCR_02_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G5W_SHIFT)
#define GPIO_C_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_C_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_02_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_C_SCR_02_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G4W_SHIFT)
#define GPIO_C_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_C_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_02_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_C_SCR_02_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G3W_SHIFT)
#define GPIO_C_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_C_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_02_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_C_SCR_02_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G2W_SHIFT)
#define GPIO_C_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_C_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_02_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_C_SCR_02_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G1W_SHIFT)
#define GPIO_C_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_C_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_02_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_C_SCR_02_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G0W_SHIFT)
#define GPIO_C_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_C_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_02_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_C_SCR_02_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G7R_SHIFT)
#define GPIO_C_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_C_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_02_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_C_SCR_02_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G6R_SHIFT)
#define GPIO_C_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_C_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_02_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_C_SCR_02_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G5R_SHIFT)
#define GPIO_C_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_C_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_02_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_C_SCR_02_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G4R_SHIFT)
#define GPIO_C_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_C_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_02_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_C_SCR_02_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G3R_SHIFT)
#define GPIO_C_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_C_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_02_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_C_SCR_02_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G2R_SHIFT)
#define GPIO_C_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_C_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_02_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_C_SCR_02_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G1R_SHIFT)
#define GPIO_C_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_C_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_02_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_C_SCR_02_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G0R_SHIFT)
#define GPIO_C_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_C_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_C_VM_03_0
#define GPIO_C_VM_03_0                  _MK_ADDR_CONST(0x40d8)
#define GPIO_C_VM_03_0_SECURE                   0x0
#define GPIO_C_VM_03_0_DUAL                     0x0
#define GPIO_C_VM_03_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_C_VM_03_0_WORD_COUNT                       0x1
#define GPIO_C_VM_03_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_03_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_03_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_03_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_C_VM_03_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_03_0_VM1_SHIFT)
#define GPIO_C_VM_03_0_VM1_RANGE                        1:0
#define GPIO_C_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_C_VM_03_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_03_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_03_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_03_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_C_VM_03_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_03_0_VM2_SHIFT)
#define GPIO_C_VM_03_0_VM2_RANGE                        3:2
#define GPIO_C_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_C_VM_03_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_03_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_03_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_03_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_C_VM_03_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_03_0_VM3_SHIFT)
#define GPIO_C_VM_03_0_VM3_RANGE                        5:4
#define GPIO_C_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_C_VM_03_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_03_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_03_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_03_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_C_VM_03_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_03_0_VM4_SHIFT)
#define GPIO_C_VM_03_0_VM4_RANGE                        7:6
#define GPIO_C_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_C_VM_03_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_03_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_03_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_03_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_C_VM_03_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_03_0_VM5_SHIFT)
#define GPIO_C_VM_03_0_VM5_RANGE                        9:8
#define GPIO_C_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_C_VM_03_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_03_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_03_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_03_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_C_VM_03_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_03_0_VM6_SHIFT)
#define GPIO_C_VM_03_0_VM6_RANGE                        11:10
#define GPIO_C_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_C_VM_03_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_03_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_03_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_03_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_C_VM_03_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_03_0_VM7_SHIFT)
#define GPIO_C_VM_03_0_VM7_RANGE                        13:12
#define GPIO_C_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_C_VM_03_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_03_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_03_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_03_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_C_VM_03_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_03_0_VM8_SHIFT)
#define GPIO_C_VM_03_0_VM8_RANGE                        15:14
#define GPIO_C_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_C_VM_03_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_03_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_03_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_C_SCR_03_0
#define GPIO_C_SCR_03_0                 _MK_ADDR_CONST(0x40dc)
#define GPIO_C_SCR_03_0_SECURE                  0x0
#define GPIO_C_SCR_03_0_DUAL                    0x0
#define GPIO_C_SCR_03_0_SCR                     0
#define GPIO_C_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_C_SCR_03_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_03_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_03_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_03_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_C_SCR_03_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_C_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_C_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_C_SCR_03_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_03_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_C_SCR_03_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_C_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_C_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_C_SCR_03_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_03_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_C_SCR_03_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_C_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_C_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_C_SCR_03_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_03_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_C_SCR_03_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_C_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_C_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_C_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_C_SCR_03_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_C_SCR_03_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_03_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_C_SCR_03_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_PR7_SHIFT)
#define GPIO_C_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_C_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_03_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_C_SCR_03_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_PR6_SHIFT)
#define GPIO_C_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_C_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_03_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_C_SCR_03_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_PR5_SHIFT)
#define GPIO_C_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_C_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_03_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_C_SCR_03_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_PR4_SHIFT)
#define GPIO_C_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_C_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_03_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_C_SCR_03_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_PR3_SHIFT)
#define GPIO_C_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_C_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_03_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_C_SCR_03_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_PR2_SHIFT)
#define GPIO_C_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_C_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_03_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_C_SCR_03_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_PR1_SHIFT)
#define GPIO_C_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_C_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_03_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_C_SCR_03_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_PR0_SHIFT)
#define GPIO_C_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_C_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_03_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_C_SCR_03_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G7W_SHIFT)
#define GPIO_C_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_C_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_03_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_C_SCR_03_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G6W_SHIFT)
#define GPIO_C_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_C_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_03_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_C_SCR_03_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G5W_SHIFT)
#define GPIO_C_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_C_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_03_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_C_SCR_03_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G4W_SHIFT)
#define GPIO_C_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_C_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_03_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_C_SCR_03_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G3W_SHIFT)
#define GPIO_C_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_C_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_03_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_C_SCR_03_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G2W_SHIFT)
#define GPIO_C_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_C_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_03_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_C_SCR_03_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G1W_SHIFT)
#define GPIO_C_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_C_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_03_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_C_SCR_03_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G0W_SHIFT)
#define GPIO_C_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_C_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_03_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_C_SCR_03_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G7R_SHIFT)
#define GPIO_C_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_C_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_03_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_C_SCR_03_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G6R_SHIFT)
#define GPIO_C_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_C_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_03_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_C_SCR_03_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G5R_SHIFT)
#define GPIO_C_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_C_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_03_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_C_SCR_03_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G4R_SHIFT)
#define GPIO_C_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_C_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_03_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_C_SCR_03_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G3R_SHIFT)
#define GPIO_C_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_C_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_03_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_C_SCR_03_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G2R_SHIFT)
#define GPIO_C_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_C_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_03_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_C_SCR_03_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G1R_SHIFT)
#define GPIO_C_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_C_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_03_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_C_SCR_03_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G0R_SHIFT)
#define GPIO_C_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_C_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_C_VM_04_0
#define GPIO_C_VM_04_0                  _MK_ADDR_CONST(0x40e0)
#define GPIO_C_VM_04_0_SECURE                   0x0
#define GPIO_C_VM_04_0_DUAL                     0x0
#define GPIO_C_VM_04_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_C_VM_04_0_WORD_COUNT                       0x1
#define GPIO_C_VM_04_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_04_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_04_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_04_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_C_VM_04_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_04_0_VM1_SHIFT)
#define GPIO_C_VM_04_0_VM1_RANGE                        1:0
#define GPIO_C_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_C_VM_04_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_04_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_04_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_04_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_C_VM_04_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_04_0_VM2_SHIFT)
#define GPIO_C_VM_04_0_VM2_RANGE                        3:2
#define GPIO_C_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_C_VM_04_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_04_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_04_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_04_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_C_VM_04_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_04_0_VM3_SHIFT)
#define GPIO_C_VM_04_0_VM3_RANGE                        5:4
#define GPIO_C_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_C_VM_04_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_04_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_04_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_04_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_C_VM_04_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_04_0_VM4_SHIFT)
#define GPIO_C_VM_04_0_VM4_RANGE                        7:6
#define GPIO_C_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_C_VM_04_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_04_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_04_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_04_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_C_VM_04_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_04_0_VM5_SHIFT)
#define GPIO_C_VM_04_0_VM5_RANGE                        9:8
#define GPIO_C_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_C_VM_04_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_04_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_04_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_04_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_C_VM_04_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_04_0_VM6_SHIFT)
#define GPIO_C_VM_04_0_VM6_RANGE                        11:10
#define GPIO_C_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_C_VM_04_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_04_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_04_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_04_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_C_VM_04_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_04_0_VM7_SHIFT)
#define GPIO_C_VM_04_0_VM7_RANGE                        13:12
#define GPIO_C_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_C_VM_04_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_04_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_04_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_04_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_C_VM_04_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_04_0_VM8_SHIFT)
#define GPIO_C_VM_04_0_VM8_RANGE                        15:14
#define GPIO_C_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_C_VM_04_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_04_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_04_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_C_SCR_04_0
#define GPIO_C_SCR_04_0                 _MK_ADDR_CONST(0x40e4)
#define GPIO_C_SCR_04_0_SECURE                  0x0
#define GPIO_C_SCR_04_0_DUAL                    0x0
#define GPIO_C_SCR_04_0_SCR                     0
#define GPIO_C_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_C_SCR_04_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_04_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_04_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_04_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_C_SCR_04_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_C_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_C_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_C_SCR_04_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_04_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_C_SCR_04_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_C_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_C_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_C_SCR_04_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_04_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_C_SCR_04_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_C_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_C_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_C_SCR_04_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_04_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_C_SCR_04_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_C_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_C_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_C_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_C_SCR_04_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_C_SCR_04_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_04_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_C_SCR_04_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_PR7_SHIFT)
#define GPIO_C_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_C_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_04_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_C_SCR_04_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_PR6_SHIFT)
#define GPIO_C_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_C_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_04_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_C_SCR_04_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_PR5_SHIFT)
#define GPIO_C_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_C_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_04_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_C_SCR_04_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_PR4_SHIFT)
#define GPIO_C_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_C_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_04_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_C_SCR_04_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_PR3_SHIFT)
#define GPIO_C_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_C_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_04_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_C_SCR_04_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_PR2_SHIFT)
#define GPIO_C_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_C_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_04_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_C_SCR_04_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_PR1_SHIFT)
#define GPIO_C_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_C_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_04_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_C_SCR_04_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_PR0_SHIFT)
#define GPIO_C_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_C_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_04_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_C_SCR_04_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G7W_SHIFT)
#define GPIO_C_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_C_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_04_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_C_SCR_04_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G6W_SHIFT)
#define GPIO_C_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_C_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_04_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_C_SCR_04_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G5W_SHIFT)
#define GPIO_C_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_C_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_04_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_C_SCR_04_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G4W_SHIFT)
#define GPIO_C_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_C_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_04_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_C_SCR_04_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G3W_SHIFT)
#define GPIO_C_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_C_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_04_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_C_SCR_04_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G2W_SHIFT)
#define GPIO_C_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_C_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_04_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_C_SCR_04_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G1W_SHIFT)
#define GPIO_C_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_C_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_04_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_C_SCR_04_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G0W_SHIFT)
#define GPIO_C_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_C_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_04_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_C_SCR_04_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G7R_SHIFT)
#define GPIO_C_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_C_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_04_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_C_SCR_04_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G6R_SHIFT)
#define GPIO_C_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_C_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_04_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_C_SCR_04_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G5R_SHIFT)
#define GPIO_C_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_C_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_04_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_C_SCR_04_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G4R_SHIFT)
#define GPIO_C_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_C_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_04_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_C_SCR_04_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G3R_SHIFT)
#define GPIO_C_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_C_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_04_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_C_SCR_04_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G2R_SHIFT)
#define GPIO_C_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_C_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_04_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_C_SCR_04_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G1R_SHIFT)
#define GPIO_C_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_C_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_04_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_C_SCR_04_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G0R_SHIFT)
#define GPIO_C_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_C_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_C_VM_05_0
#define GPIO_C_VM_05_0                  _MK_ADDR_CONST(0x40e8)
#define GPIO_C_VM_05_0_SECURE                   0x0
#define GPIO_C_VM_05_0_DUAL                     0x0
#define GPIO_C_VM_05_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_C_VM_05_0_WORD_COUNT                       0x1
#define GPIO_C_VM_05_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_05_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_05_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_05_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_C_VM_05_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_05_0_VM1_SHIFT)
#define GPIO_C_VM_05_0_VM1_RANGE                        1:0
#define GPIO_C_VM_05_0_VM1_WOFFSET                      0x0
#define GPIO_C_VM_05_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_05_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_05_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_05_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_C_VM_05_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_05_0_VM2_SHIFT)
#define GPIO_C_VM_05_0_VM2_RANGE                        3:2
#define GPIO_C_VM_05_0_VM2_WOFFSET                      0x0
#define GPIO_C_VM_05_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_05_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_05_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_05_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_C_VM_05_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_05_0_VM3_SHIFT)
#define GPIO_C_VM_05_0_VM3_RANGE                        5:4
#define GPIO_C_VM_05_0_VM3_WOFFSET                      0x0
#define GPIO_C_VM_05_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_05_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_05_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_05_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_C_VM_05_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_05_0_VM4_SHIFT)
#define GPIO_C_VM_05_0_VM4_RANGE                        7:6
#define GPIO_C_VM_05_0_VM4_WOFFSET                      0x0
#define GPIO_C_VM_05_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_05_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_05_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_05_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_C_VM_05_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_05_0_VM5_SHIFT)
#define GPIO_C_VM_05_0_VM5_RANGE                        9:8
#define GPIO_C_VM_05_0_VM5_WOFFSET                      0x0
#define GPIO_C_VM_05_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_05_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_05_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_05_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_C_VM_05_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_05_0_VM6_SHIFT)
#define GPIO_C_VM_05_0_VM6_RANGE                        11:10
#define GPIO_C_VM_05_0_VM6_WOFFSET                      0x0
#define GPIO_C_VM_05_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_05_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_05_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_05_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_C_VM_05_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_05_0_VM7_SHIFT)
#define GPIO_C_VM_05_0_VM7_RANGE                        13:12
#define GPIO_C_VM_05_0_VM7_WOFFSET                      0x0
#define GPIO_C_VM_05_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_05_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_05_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_05_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_C_VM_05_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_05_0_VM8_SHIFT)
#define GPIO_C_VM_05_0_VM8_RANGE                        15:14
#define GPIO_C_VM_05_0_VM8_WOFFSET                      0x0
#define GPIO_C_VM_05_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_05_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_05_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_C_SCR_05_0
#define GPIO_C_SCR_05_0                 _MK_ADDR_CONST(0x40ec)
#define GPIO_C_SCR_05_0_SECURE                  0x0
#define GPIO_C_SCR_05_0_DUAL                    0x0
#define GPIO_C_SCR_05_0_SCR                     0
#define GPIO_C_SCR_05_0_WORD_COUNT                      0x1
#define GPIO_C_SCR_05_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_05_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_05_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_05_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_C_SCR_05_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_C_SCR_05_0_SEC_LCK_RANGE                   29:29
#define GPIO_C_SCR_05_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_C_SCR_05_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_05_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_C_SCR_05_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_C_SCR_05_0_SEC_WEN_RANGE                   28:28
#define GPIO_C_SCR_05_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_C_SCR_05_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_05_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_C_SCR_05_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_C_SCR_05_0_SEC_REN_RANGE                   27:27
#define GPIO_C_SCR_05_0_SEC_REN_WOFFSET                 0x0
#define GPIO_C_SCR_05_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_05_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_C_SCR_05_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_C_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_C_SCR_05_0_SEC_OWNER_RANGE                 26:24
#define GPIO_C_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_C_SCR_05_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_C_SCR_05_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_05_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_C_SCR_05_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_PR7_SHIFT)
#define GPIO_C_SCR_05_0_PR7_RANGE                       23:23
#define GPIO_C_SCR_05_0_PR7_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_05_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_C_SCR_05_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_PR6_SHIFT)
#define GPIO_C_SCR_05_0_PR6_RANGE                       22:22
#define GPIO_C_SCR_05_0_PR6_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_05_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_C_SCR_05_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_PR5_SHIFT)
#define GPIO_C_SCR_05_0_PR5_RANGE                       21:21
#define GPIO_C_SCR_05_0_PR5_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_05_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_C_SCR_05_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_PR4_SHIFT)
#define GPIO_C_SCR_05_0_PR4_RANGE                       20:20
#define GPIO_C_SCR_05_0_PR4_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_05_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_C_SCR_05_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_PR3_SHIFT)
#define GPIO_C_SCR_05_0_PR3_RANGE                       19:19
#define GPIO_C_SCR_05_0_PR3_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_05_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_C_SCR_05_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_PR2_SHIFT)
#define GPIO_C_SCR_05_0_PR2_RANGE                       18:18
#define GPIO_C_SCR_05_0_PR2_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_05_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_C_SCR_05_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_PR1_SHIFT)
#define GPIO_C_SCR_05_0_PR1_RANGE                       17:17
#define GPIO_C_SCR_05_0_PR1_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_05_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_C_SCR_05_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_PR0_SHIFT)
#define GPIO_C_SCR_05_0_PR0_RANGE                       16:16
#define GPIO_C_SCR_05_0_PR0_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_05_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_C_SCR_05_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G7W_SHIFT)
#define GPIO_C_SCR_05_0_G7W_RANGE                       15:15
#define GPIO_C_SCR_05_0_G7W_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_05_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_C_SCR_05_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G6W_SHIFT)
#define GPIO_C_SCR_05_0_G6W_RANGE                       14:14
#define GPIO_C_SCR_05_0_G6W_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_05_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_C_SCR_05_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G5W_SHIFT)
#define GPIO_C_SCR_05_0_G5W_RANGE                       13:13
#define GPIO_C_SCR_05_0_G5W_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_05_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_C_SCR_05_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G4W_SHIFT)
#define GPIO_C_SCR_05_0_G4W_RANGE                       12:12
#define GPIO_C_SCR_05_0_G4W_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_05_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_C_SCR_05_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G3W_SHIFT)
#define GPIO_C_SCR_05_0_G3W_RANGE                       11:11
#define GPIO_C_SCR_05_0_G3W_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_05_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_C_SCR_05_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G2W_SHIFT)
#define GPIO_C_SCR_05_0_G2W_RANGE                       10:10
#define GPIO_C_SCR_05_0_G2W_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_05_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_C_SCR_05_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G1W_SHIFT)
#define GPIO_C_SCR_05_0_G1W_RANGE                       9:9
#define GPIO_C_SCR_05_0_G1W_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_05_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_C_SCR_05_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G0W_SHIFT)
#define GPIO_C_SCR_05_0_G0W_RANGE                       8:8
#define GPIO_C_SCR_05_0_G0W_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_05_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_C_SCR_05_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G7R_SHIFT)
#define GPIO_C_SCR_05_0_G7R_RANGE                       7:7
#define GPIO_C_SCR_05_0_G7R_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_05_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_C_SCR_05_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G6R_SHIFT)
#define GPIO_C_SCR_05_0_G6R_RANGE                       6:6
#define GPIO_C_SCR_05_0_G6R_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_05_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_C_SCR_05_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G5R_SHIFT)
#define GPIO_C_SCR_05_0_G5R_RANGE                       5:5
#define GPIO_C_SCR_05_0_G5R_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_05_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_C_SCR_05_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G4R_SHIFT)
#define GPIO_C_SCR_05_0_G4R_RANGE                       4:4
#define GPIO_C_SCR_05_0_G4R_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_05_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_C_SCR_05_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G3R_SHIFT)
#define GPIO_C_SCR_05_0_G3R_RANGE                       3:3
#define GPIO_C_SCR_05_0_G3R_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_05_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_C_SCR_05_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G2R_SHIFT)
#define GPIO_C_SCR_05_0_G2R_RANGE                       2:2
#define GPIO_C_SCR_05_0_G2R_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_05_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_C_SCR_05_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G1R_SHIFT)
#define GPIO_C_SCR_05_0_G1R_RANGE                       1:1
#define GPIO_C_SCR_05_0_G1R_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_05_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_C_SCR_05_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G0R_SHIFT)
#define GPIO_C_SCR_05_0_G0R_RANGE                       0:0
#define GPIO_C_SCR_05_0_G0R_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_C_VM_06_0
#define GPIO_C_VM_06_0                  _MK_ADDR_CONST(0x40f0)
#define GPIO_C_VM_06_0_SECURE                   0x0
#define GPIO_C_VM_06_0_DUAL                     0x0
#define GPIO_C_VM_06_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_C_VM_06_0_WORD_COUNT                       0x1
#define GPIO_C_VM_06_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_06_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_06_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_06_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_06_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_C_VM_06_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_06_0_VM1_SHIFT)
#define GPIO_C_VM_06_0_VM1_RANGE                        1:0
#define GPIO_C_VM_06_0_VM1_WOFFSET                      0x0
#define GPIO_C_VM_06_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_06_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_06_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_06_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_C_VM_06_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_06_0_VM2_SHIFT)
#define GPIO_C_VM_06_0_VM2_RANGE                        3:2
#define GPIO_C_VM_06_0_VM2_WOFFSET                      0x0
#define GPIO_C_VM_06_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_06_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_06_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_06_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_C_VM_06_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_06_0_VM3_SHIFT)
#define GPIO_C_VM_06_0_VM3_RANGE                        5:4
#define GPIO_C_VM_06_0_VM3_WOFFSET                      0x0
#define GPIO_C_VM_06_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_06_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_06_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_06_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_C_VM_06_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_06_0_VM4_SHIFT)
#define GPIO_C_VM_06_0_VM4_RANGE                        7:6
#define GPIO_C_VM_06_0_VM4_WOFFSET                      0x0
#define GPIO_C_VM_06_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_06_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_06_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_06_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_C_VM_06_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_06_0_VM5_SHIFT)
#define GPIO_C_VM_06_0_VM5_RANGE                        9:8
#define GPIO_C_VM_06_0_VM5_WOFFSET                      0x0
#define GPIO_C_VM_06_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_06_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_06_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_06_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_C_VM_06_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_06_0_VM6_SHIFT)
#define GPIO_C_VM_06_0_VM6_RANGE                        11:10
#define GPIO_C_VM_06_0_VM6_WOFFSET                      0x0
#define GPIO_C_VM_06_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_06_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_06_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_06_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_C_VM_06_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_06_0_VM7_SHIFT)
#define GPIO_C_VM_06_0_VM7_RANGE                        13:12
#define GPIO_C_VM_06_0_VM7_WOFFSET                      0x0
#define GPIO_C_VM_06_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_06_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_06_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_06_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_C_VM_06_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_06_0_VM8_SHIFT)
#define GPIO_C_VM_06_0_VM8_RANGE                        15:14
#define GPIO_C_VM_06_0_VM8_WOFFSET                      0x0
#define GPIO_C_VM_06_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_06_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_06_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_C_SCR_06_0
#define GPIO_C_SCR_06_0                 _MK_ADDR_CONST(0x40f4)
#define GPIO_C_SCR_06_0_SECURE                  0x0
#define GPIO_C_SCR_06_0_DUAL                    0x0
#define GPIO_C_SCR_06_0_SCR                     0
#define GPIO_C_SCR_06_0_WORD_COUNT                      0x1
#define GPIO_C_SCR_06_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_06_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_06_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_06_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_C_SCR_06_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_SEC_LCK_SHIFT)
#define GPIO_C_SCR_06_0_SEC_LCK_RANGE                   29:29
#define GPIO_C_SCR_06_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_C_SCR_06_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_06_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_C_SCR_06_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_SEC_WEN_SHIFT)
#define GPIO_C_SCR_06_0_SEC_WEN_RANGE                   28:28
#define GPIO_C_SCR_06_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_C_SCR_06_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_06_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_C_SCR_06_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_SEC_REN_SHIFT)
#define GPIO_C_SCR_06_0_SEC_REN_RANGE                   27:27
#define GPIO_C_SCR_06_0_SEC_REN_WOFFSET                 0x0
#define GPIO_C_SCR_06_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_06_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_C_SCR_06_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_C_SCR_06_0_SEC_OWNER_SHIFT)
#define GPIO_C_SCR_06_0_SEC_OWNER_RANGE                 26:24
#define GPIO_C_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_C_SCR_06_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_C_SCR_06_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_06_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_C_SCR_06_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_PR7_SHIFT)
#define GPIO_C_SCR_06_0_PR7_RANGE                       23:23
#define GPIO_C_SCR_06_0_PR7_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_06_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_C_SCR_06_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_PR6_SHIFT)
#define GPIO_C_SCR_06_0_PR6_RANGE                       22:22
#define GPIO_C_SCR_06_0_PR6_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_06_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_C_SCR_06_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_PR5_SHIFT)
#define GPIO_C_SCR_06_0_PR5_RANGE                       21:21
#define GPIO_C_SCR_06_0_PR5_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_06_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_C_SCR_06_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_PR4_SHIFT)
#define GPIO_C_SCR_06_0_PR4_RANGE                       20:20
#define GPIO_C_SCR_06_0_PR4_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_06_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_C_SCR_06_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_PR3_SHIFT)
#define GPIO_C_SCR_06_0_PR3_RANGE                       19:19
#define GPIO_C_SCR_06_0_PR3_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_06_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_C_SCR_06_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_PR2_SHIFT)
#define GPIO_C_SCR_06_0_PR2_RANGE                       18:18
#define GPIO_C_SCR_06_0_PR2_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_06_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_C_SCR_06_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_PR1_SHIFT)
#define GPIO_C_SCR_06_0_PR1_RANGE                       17:17
#define GPIO_C_SCR_06_0_PR1_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_06_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_C_SCR_06_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_PR0_SHIFT)
#define GPIO_C_SCR_06_0_PR0_RANGE                       16:16
#define GPIO_C_SCR_06_0_PR0_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_06_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_C_SCR_06_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G7W_SHIFT)
#define GPIO_C_SCR_06_0_G7W_RANGE                       15:15
#define GPIO_C_SCR_06_0_G7W_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_06_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_C_SCR_06_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G6W_SHIFT)
#define GPIO_C_SCR_06_0_G6W_RANGE                       14:14
#define GPIO_C_SCR_06_0_G6W_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_06_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_C_SCR_06_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G5W_SHIFT)
#define GPIO_C_SCR_06_0_G5W_RANGE                       13:13
#define GPIO_C_SCR_06_0_G5W_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_06_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_C_SCR_06_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G4W_SHIFT)
#define GPIO_C_SCR_06_0_G4W_RANGE                       12:12
#define GPIO_C_SCR_06_0_G4W_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_06_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_C_SCR_06_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G3W_SHIFT)
#define GPIO_C_SCR_06_0_G3W_RANGE                       11:11
#define GPIO_C_SCR_06_0_G3W_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_06_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_C_SCR_06_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G2W_SHIFT)
#define GPIO_C_SCR_06_0_G2W_RANGE                       10:10
#define GPIO_C_SCR_06_0_G2W_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_06_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_C_SCR_06_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G1W_SHIFT)
#define GPIO_C_SCR_06_0_G1W_RANGE                       9:9
#define GPIO_C_SCR_06_0_G1W_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_06_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_C_SCR_06_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G0W_SHIFT)
#define GPIO_C_SCR_06_0_G0W_RANGE                       8:8
#define GPIO_C_SCR_06_0_G0W_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_06_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_C_SCR_06_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G7R_SHIFT)
#define GPIO_C_SCR_06_0_G7R_RANGE                       7:7
#define GPIO_C_SCR_06_0_G7R_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_06_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_C_SCR_06_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G6R_SHIFT)
#define GPIO_C_SCR_06_0_G6R_RANGE                       6:6
#define GPIO_C_SCR_06_0_G6R_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_06_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_C_SCR_06_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G5R_SHIFT)
#define GPIO_C_SCR_06_0_G5R_RANGE                       5:5
#define GPIO_C_SCR_06_0_G5R_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_06_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_C_SCR_06_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G4R_SHIFT)
#define GPIO_C_SCR_06_0_G4R_RANGE                       4:4
#define GPIO_C_SCR_06_0_G4R_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_06_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_C_SCR_06_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G3R_SHIFT)
#define GPIO_C_SCR_06_0_G3R_RANGE                       3:3
#define GPIO_C_SCR_06_0_G3R_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_06_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_C_SCR_06_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G2R_SHIFT)
#define GPIO_C_SCR_06_0_G2R_RANGE                       2:2
#define GPIO_C_SCR_06_0_G2R_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_06_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_C_SCR_06_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G1R_SHIFT)
#define GPIO_C_SCR_06_0_G1R_RANGE                       1:1
#define GPIO_C_SCR_06_0_G1R_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_06_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_C_SCR_06_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G0R_SHIFT)
#define GPIO_C_SCR_06_0_G0R_RANGE                       0:0
#define GPIO_C_SCR_06_0_G0R_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_C_VM_07_0
#define GPIO_C_VM_07_0                  _MK_ADDR_CONST(0x40f8)
#define GPIO_C_VM_07_0_SECURE                   0x0
#define GPIO_C_VM_07_0_DUAL                     0x0
#define GPIO_C_VM_07_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_C_VM_07_0_WORD_COUNT                       0x1
#define GPIO_C_VM_07_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_07_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_07_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_07_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_VM_07_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_07_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_C_VM_07_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_C_VM_07_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_07_0_VM1_SHIFT)
#define GPIO_C_VM_07_0_VM1_RANGE                        1:0
#define GPIO_C_VM_07_0_VM1_WOFFSET                      0x0
#define GPIO_C_VM_07_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_07_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_07_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_07_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_07_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_07_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_07_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_C_VM_07_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_07_0_VM2_SHIFT)
#define GPIO_C_VM_07_0_VM2_RANGE                        3:2
#define GPIO_C_VM_07_0_VM2_WOFFSET                      0x0
#define GPIO_C_VM_07_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_07_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_07_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_07_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_07_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_07_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_07_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_C_VM_07_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_07_0_VM3_SHIFT)
#define GPIO_C_VM_07_0_VM3_RANGE                        5:4
#define GPIO_C_VM_07_0_VM3_WOFFSET                      0x0
#define GPIO_C_VM_07_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_07_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_07_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_07_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_07_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_07_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_07_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_C_VM_07_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_07_0_VM4_SHIFT)
#define GPIO_C_VM_07_0_VM4_RANGE                        7:6
#define GPIO_C_VM_07_0_VM4_WOFFSET                      0x0
#define GPIO_C_VM_07_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_07_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_07_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_07_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_07_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_07_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_07_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_C_VM_07_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_07_0_VM5_SHIFT)
#define GPIO_C_VM_07_0_VM5_RANGE                        9:8
#define GPIO_C_VM_07_0_VM5_WOFFSET                      0x0
#define GPIO_C_VM_07_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_07_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_07_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_07_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_07_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_07_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_07_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_C_VM_07_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_07_0_VM6_SHIFT)
#define GPIO_C_VM_07_0_VM6_RANGE                        11:10
#define GPIO_C_VM_07_0_VM6_WOFFSET                      0x0
#define GPIO_C_VM_07_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_07_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_07_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_07_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_07_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_07_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_07_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_C_VM_07_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_07_0_VM7_SHIFT)
#define GPIO_C_VM_07_0_VM7_RANGE                        13:12
#define GPIO_C_VM_07_0_VM7_WOFFSET                      0x0
#define GPIO_C_VM_07_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_07_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_07_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_07_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_07_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_07_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_C_VM_07_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_C_VM_07_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_C_VM_07_0_VM8_SHIFT)
#define GPIO_C_VM_07_0_VM8_RANGE                        15:14
#define GPIO_C_VM_07_0_VM8_WOFFSET                      0x0
#define GPIO_C_VM_07_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_C_VM_07_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_C_VM_07_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_VM_07_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_VM_07_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_VM_07_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_C_SCR_07_0
#define GPIO_C_SCR_07_0                 _MK_ADDR_CONST(0x40fc)
#define GPIO_C_SCR_07_0_SECURE                  0x0
#define GPIO_C_SCR_07_0_DUAL                    0x0
#define GPIO_C_SCR_07_0_SCR                     0
#define GPIO_C_SCR_07_0_WORD_COUNT                      0x1
#define GPIO_C_SCR_07_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_07_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_07_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_07_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_C_SCR_07_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_SEC_LCK_SHIFT)
#define GPIO_C_SCR_07_0_SEC_LCK_RANGE                   29:29
#define GPIO_C_SCR_07_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_C_SCR_07_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_07_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_07_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_C_SCR_07_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_SEC_WEN_SHIFT)
#define GPIO_C_SCR_07_0_SEC_WEN_RANGE                   28:28
#define GPIO_C_SCR_07_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_C_SCR_07_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_07_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_07_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_C_SCR_07_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_SEC_REN_SHIFT)
#define GPIO_C_SCR_07_0_SEC_REN_RANGE                   27:27
#define GPIO_C_SCR_07_0_SEC_REN_WOFFSET                 0x0
#define GPIO_C_SCR_07_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_07_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_07_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_C_SCR_07_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_C_SCR_07_0_SEC_OWNER_SHIFT)
#define GPIO_C_SCR_07_0_SEC_OWNER_RANGE                 26:24
#define GPIO_C_SCR_07_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_C_SCR_07_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_C_SCR_07_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_07_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_C_SCR_07_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_PR7_SHIFT)
#define GPIO_C_SCR_07_0_PR7_RANGE                       23:23
#define GPIO_C_SCR_07_0_PR7_WOFFSET                     0x0
#define GPIO_C_SCR_07_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_07_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_07_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_C_SCR_07_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_PR6_SHIFT)
#define GPIO_C_SCR_07_0_PR6_RANGE                       22:22
#define GPIO_C_SCR_07_0_PR6_WOFFSET                     0x0
#define GPIO_C_SCR_07_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_07_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_07_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_C_SCR_07_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_PR5_SHIFT)
#define GPIO_C_SCR_07_0_PR5_RANGE                       21:21
#define GPIO_C_SCR_07_0_PR5_WOFFSET                     0x0
#define GPIO_C_SCR_07_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_07_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_07_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_C_SCR_07_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_PR4_SHIFT)
#define GPIO_C_SCR_07_0_PR4_RANGE                       20:20
#define GPIO_C_SCR_07_0_PR4_WOFFSET                     0x0
#define GPIO_C_SCR_07_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_07_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_07_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_C_SCR_07_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_PR3_SHIFT)
#define GPIO_C_SCR_07_0_PR3_RANGE                       19:19
#define GPIO_C_SCR_07_0_PR3_WOFFSET                     0x0
#define GPIO_C_SCR_07_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_07_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_07_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_C_SCR_07_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_PR2_SHIFT)
#define GPIO_C_SCR_07_0_PR2_RANGE                       18:18
#define GPIO_C_SCR_07_0_PR2_WOFFSET                     0x0
#define GPIO_C_SCR_07_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_07_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_07_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_C_SCR_07_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_PR1_SHIFT)
#define GPIO_C_SCR_07_0_PR1_RANGE                       17:17
#define GPIO_C_SCR_07_0_PR1_WOFFSET                     0x0
#define GPIO_C_SCR_07_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_07_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_07_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_C_SCR_07_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_PR0_SHIFT)
#define GPIO_C_SCR_07_0_PR0_RANGE                       16:16
#define GPIO_C_SCR_07_0_PR0_WOFFSET                     0x0
#define GPIO_C_SCR_07_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_07_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_07_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_C_SCR_07_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_G7W_SHIFT)
#define GPIO_C_SCR_07_0_G7W_RANGE                       15:15
#define GPIO_C_SCR_07_0_G7W_WOFFSET                     0x0
#define GPIO_C_SCR_07_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_07_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_07_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_C_SCR_07_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_G6W_SHIFT)
#define GPIO_C_SCR_07_0_G6W_RANGE                       14:14
#define GPIO_C_SCR_07_0_G6W_WOFFSET                     0x0
#define GPIO_C_SCR_07_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_07_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_07_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_C_SCR_07_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_G5W_SHIFT)
#define GPIO_C_SCR_07_0_G5W_RANGE                       13:13
#define GPIO_C_SCR_07_0_G5W_WOFFSET                     0x0
#define GPIO_C_SCR_07_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_07_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_07_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_C_SCR_07_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_G4W_SHIFT)
#define GPIO_C_SCR_07_0_G4W_RANGE                       12:12
#define GPIO_C_SCR_07_0_G4W_WOFFSET                     0x0
#define GPIO_C_SCR_07_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_07_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_07_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_C_SCR_07_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_G3W_SHIFT)
#define GPIO_C_SCR_07_0_G3W_RANGE                       11:11
#define GPIO_C_SCR_07_0_G3W_WOFFSET                     0x0
#define GPIO_C_SCR_07_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_07_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_07_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_C_SCR_07_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_G2W_SHIFT)
#define GPIO_C_SCR_07_0_G2W_RANGE                       10:10
#define GPIO_C_SCR_07_0_G2W_WOFFSET                     0x0
#define GPIO_C_SCR_07_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_07_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_07_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_C_SCR_07_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_G1W_SHIFT)
#define GPIO_C_SCR_07_0_G1W_RANGE                       9:9
#define GPIO_C_SCR_07_0_G1W_WOFFSET                     0x0
#define GPIO_C_SCR_07_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_07_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_07_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_C_SCR_07_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_G0W_SHIFT)
#define GPIO_C_SCR_07_0_G0W_RANGE                       8:8
#define GPIO_C_SCR_07_0_G0W_WOFFSET                     0x0
#define GPIO_C_SCR_07_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_07_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_07_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_C_SCR_07_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_G7R_SHIFT)
#define GPIO_C_SCR_07_0_G7R_RANGE                       7:7
#define GPIO_C_SCR_07_0_G7R_WOFFSET                     0x0
#define GPIO_C_SCR_07_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_07_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_07_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_C_SCR_07_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_G6R_SHIFT)
#define GPIO_C_SCR_07_0_G6R_RANGE                       6:6
#define GPIO_C_SCR_07_0_G6R_WOFFSET                     0x0
#define GPIO_C_SCR_07_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_07_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_07_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_C_SCR_07_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_G5R_SHIFT)
#define GPIO_C_SCR_07_0_G5R_RANGE                       5:5
#define GPIO_C_SCR_07_0_G5R_WOFFSET                     0x0
#define GPIO_C_SCR_07_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_07_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_07_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_C_SCR_07_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_G4R_SHIFT)
#define GPIO_C_SCR_07_0_G4R_RANGE                       4:4
#define GPIO_C_SCR_07_0_G4R_WOFFSET                     0x0
#define GPIO_C_SCR_07_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_07_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_07_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_C_SCR_07_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_G3R_SHIFT)
#define GPIO_C_SCR_07_0_G3R_RANGE                       3:3
#define GPIO_C_SCR_07_0_G3R_WOFFSET                     0x0
#define GPIO_C_SCR_07_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_07_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_07_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_C_SCR_07_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_G2R_SHIFT)
#define GPIO_C_SCR_07_0_G2R_RANGE                       2:2
#define GPIO_C_SCR_07_0_G2R_WOFFSET                     0x0
#define GPIO_C_SCR_07_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_07_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_07_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_C_SCR_07_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_G1R_SHIFT)
#define GPIO_C_SCR_07_0_G1R_RANGE                       1:1
#define GPIO_C_SCR_07_0_G1R_WOFFSET                     0x0
#define GPIO_C_SCR_07_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_07_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_C_SCR_07_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_C_SCR_07_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_G0R_SHIFT)
#define GPIO_C_SCR_07_0_G0R_RANGE                       0:0
#define GPIO_C_SCR_07_0_G0R_WOFFSET                     0x0
#define GPIO_C_SCR_07_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_SCR_07_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_D_VM_00_0
#define GPIO_D_VM_00_0                  _MK_ADDR_CONST(0x4100)
#define GPIO_D_VM_00_0_SECURE                   0x0
#define GPIO_D_VM_00_0_DUAL                     0x0
#define GPIO_D_VM_00_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_D_VM_00_0_WORD_COUNT                       0x1
#define GPIO_D_VM_00_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_D_VM_00_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_D_VM_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_D_VM_00_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_D_VM_00_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_D_VM_00_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_00_0_VM1_SHIFT)
#define GPIO_D_VM_00_0_VM1_RANGE                        1:0
#define GPIO_D_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_D_VM_00_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_00_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_00_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_D_VM_00_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_D_VM_00_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_00_0_VM2_SHIFT)
#define GPIO_D_VM_00_0_VM2_RANGE                        3:2
#define GPIO_D_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_D_VM_00_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_00_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_00_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_D_VM_00_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_D_VM_00_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_00_0_VM3_SHIFT)
#define GPIO_D_VM_00_0_VM3_RANGE                        5:4
#define GPIO_D_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_D_VM_00_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_00_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_00_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_D_VM_00_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_D_VM_00_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_00_0_VM4_SHIFT)
#define GPIO_D_VM_00_0_VM4_RANGE                        7:6
#define GPIO_D_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_D_VM_00_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_00_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_00_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_D_VM_00_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_D_VM_00_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_00_0_VM5_SHIFT)
#define GPIO_D_VM_00_0_VM5_RANGE                        9:8
#define GPIO_D_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_D_VM_00_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_00_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_00_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_D_VM_00_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_D_VM_00_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_00_0_VM6_SHIFT)
#define GPIO_D_VM_00_0_VM6_RANGE                        11:10
#define GPIO_D_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_D_VM_00_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_00_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_00_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_D_VM_00_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_D_VM_00_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_00_0_VM7_SHIFT)
#define GPIO_D_VM_00_0_VM7_RANGE                        13:12
#define GPIO_D_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_D_VM_00_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_00_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_00_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_D_VM_00_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_D_VM_00_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_00_0_VM8_SHIFT)
#define GPIO_D_VM_00_0_VM8_RANGE                        15:14
#define GPIO_D_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_D_VM_00_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_00_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_00_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_D_SCR_00_0
#define GPIO_D_SCR_00_0                 _MK_ADDR_CONST(0x4104)
#define GPIO_D_SCR_00_0_SECURE                  0x0
#define GPIO_D_SCR_00_0_DUAL                    0x0
#define GPIO_D_SCR_00_0_SCR                     0
#define GPIO_D_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_D_SCR_00_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_D_SCR_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_D_SCR_00_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_D_SCR_00_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_D_SCR_00_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_D_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_D_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_D_SCR_00_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_00_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_D_SCR_00_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_D_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_D_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_D_SCR_00_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_00_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_D_SCR_00_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_D_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_D_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_D_SCR_00_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_00_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_D_SCR_00_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_D_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_D_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_D_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_D_SCR_00_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_D_SCR_00_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_00_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_D_SCR_00_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_PR7_SHIFT)
#define GPIO_D_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_D_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_00_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_D_SCR_00_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_PR6_SHIFT)
#define GPIO_D_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_D_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_00_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_D_SCR_00_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_PR5_SHIFT)
#define GPIO_D_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_D_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_00_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_D_SCR_00_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_PR4_SHIFT)
#define GPIO_D_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_D_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_00_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_D_SCR_00_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_PR3_SHIFT)
#define GPIO_D_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_D_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_00_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_D_SCR_00_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_PR2_SHIFT)
#define GPIO_D_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_D_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_00_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_D_SCR_00_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_PR1_SHIFT)
#define GPIO_D_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_D_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_00_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_D_SCR_00_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_PR0_SHIFT)
#define GPIO_D_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_D_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_00_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_D_SCR_00_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G7W_SHIFT)
#define GPIO_D_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_D_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_00_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_D_SCR_00_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G6W_SHIFT)
#define GPIO_D_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_D_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_00_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_D_SCR_00_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G5W_SHIFT)
#define GPIO_D_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_D_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_00_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_D_SCR_00_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G4W_SHIFT)
#define GPIO_D_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_D_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_00_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_D_SCR_00_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G3W_SHIFT)
#define GPIO_D_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_D_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_00_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_D_SCR_00_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G2W_SHIFT)
#define GPIO_D_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_D_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_00_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_D_SCR_00_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G1W_SHIFT)
#define GPIO_D_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_D_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_00_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_D_SCR_00_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G0W_SHIFT)
#define GPIO_D_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_D_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_00_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_D_SCR_00_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G7R_SHIFT)
#define GPIO_D_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_D_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_00_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_D_SCR_00_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G6R_SHIFT)
#define GPIO_D_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_D_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_00_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_D_SCR_00_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G5R_SHIFT)
#define GPIO_D_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_D_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_00_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_D_SCR_00_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G4R_SHIFT)
#define GPIO_D_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_D_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_00_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_D_SCR_00_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G3R_SHIFT)
#define GPIO_D_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_D_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_00_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_D_SCR_00_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G2R_SHIFT)
#define GPIO_D_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_D_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_00_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_D_SCR_00_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G1R_SHIFT)
#define GPIO_D_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_D_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_00_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_D_SCR_00_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G0R_SHIFT)
#define GPIO_D_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_D_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_D_VM_01_0
#define GPIO_D_VM_01_0                  _MK_ADDR_CONST(0x4108)
#define GPIO_D_VM_01_0_SECURE                   0x0
#define GPIO_D_VM_01_0_DUAL                     0x0
#define GPIO_D_VM_01_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_D_VM_01_0_WORD_COUNT                       0x1
#define GPIO_D_VM_01_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_D_VM_01_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_D_VM_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_D_VM_01_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_D_VM_01_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_D_VM_01_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_01_0_VM1_SHIFT)
#define GPIO_D_VM_01_0_VM1_RANGE                        1:0
#define GPIO_D_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_D_VM_01_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_01_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_01_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_D_VM_01_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_D_VM_01_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_01_0_VM2_SHIFT)
#define GPIO_D_VM_01_0_VM2_RANGE                        3:2
#define GPIO_D_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_D_VM_01_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_01_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_01_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_D_VM_01_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_D_VM_01_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_01_0_VM3_SHIFT)
#define GPIO_D_VM_01_0_VM3_RANGE                        5:4
#define GPIO_D_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_D_VM_01_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_01_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_01_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_D_VM_01_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_D_VM_01_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_01_0_VM4_SHIFT)
#define GPIO_D_VM_01_0_VM4_RANGE                        7:6
#define GPIO_D_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_D_VM_01_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_01_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_01_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_D_VM_01_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_D_VM_01_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_01_0_VM5_SHIFT)
#define GPIO_D_VM_01_0_VM5_RANGE                        9:8
#define GPIO_D_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_D_VM_01_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_01_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_01_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_D_VM_01_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_D_VM_01_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_01_0_VM6_SHIFT)
#define GPIO_D_VM_01_0_VM6_RANGE                        11:10
#define GPIO_D_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_D_VM_01_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_01_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_01_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_D_VM_01_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_D_VM_01_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_01_0_VM7_SHIFT)
#define GPIO_D_VM_01_0_VM7_RANGE                        13:12
#define GPIO_D_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_D_VM_01_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_01_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_01_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_D_VM_01_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_D_VM_01_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_01_0_VM8_SHIFT)
#define GPIO_D_VM_01_0_VM8_RANGE                        15:14
#define GPIO_D_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_D_VM_01_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_01_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_01_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_D_SCR_01_0
#define GPIO_D_SCR_01_0                 _MK_ADDR_CONST(0x410c)
#define GPIO_D_SCR_01_0_SECURE                  0x0
#define GPIO_D_SCR_01_0_DUAL                    0x0
#define GPIO_D_SCR_01_0_SCR                     0
#define GPIO_D_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_D_SCR_01_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_D_SCR_01_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_D_SCR_01_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_D_SCR_01_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_D_SCR_01_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_D_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_D_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_D_SCR_01_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_01_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_D_SCR_01_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_D_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_D_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_D_SCR_01_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_01_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_D_SCR_01_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_D_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_D_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_D_SCR_01_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_01_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_D_SCR_01_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_D_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_D_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_D_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_D_SCR_01_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_D_SCR_01_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_01_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_D_SCR_01_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_PR7_SHIFT)
#define GPIO_D_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_D_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_01_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_D_SCR_01_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_PR6_SHIFT)
#define GPIO_D_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_D_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_01_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_D_SCR_01_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_PR5_SHIFT)
#define GPIO_D_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_D_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_01_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_D_SCR_01_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_PR4_SHIFT)
#define GPIO_D_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_D_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_01_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_D_SCR_01_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_PR3_SHIFT)
#define GPIO_D_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_D_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_01_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_D_SCR_01_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_PR2_SHIFT)
#define GPIO_D_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_D_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_01_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_D_SCR_01_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_PR1_SHIFT)
#define GPIO_D_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_D_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_01_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_D_SCR_01_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_PR0_SHIFT)
#define GPIO_D_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_D_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_01_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_D_SCR_01_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G7W_SHIFT)
#define GPIO_D_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_D_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_01_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_D_SCR_01_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G6W_SHIFT)
#define GPIO_D_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_D_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_01_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_D_SCR_01_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G5W_SHIFT)
#define GPIO_D_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_D_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_01_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_D_SCR_01_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G4W_SHIFT)
#define GPIO_D_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_D_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_01_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_D_SCR_01_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G3W_SHIFT)
#define GPIO_D_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_D_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_01_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_D_SCR_01_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G2W_SHIFT)
#define GPIO_D_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_D_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_01_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_D_SCR_01_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G1W_SHIFT)
#define GPIO_D_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_D_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_01_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_D_SCR_01_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G0W_SHIFT)
#define GPIO_D_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_D_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_01_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_D_SCR_01_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G7R_SHIFT)
#define GPIO_D_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_D_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_01_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_D_SCR_01_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G6R_SHIFT)
#define GPIO_D_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_D_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_01_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_D_SCR_01_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G5R_SHIFT)
#define GPIO_D_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_D_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_01_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_D_SCR_01_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G4R_SHIFT)
#define GPIO_D_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_D_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_01_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_D_SCR_01_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G3R_SHIFT)
#define GPIO_D_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_D_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_01_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_D_SCR_01_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G2R_SHIFT)
#define GPIO_D_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_D_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_01_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_D_SCR_01_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G1R_SHIFT)
#define GPIO_D_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_D_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_01_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_D_SCR_01_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G0R_SHIFT)
#define GPIO_D_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_D_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_D_VM_02_0
#define GPIO_D_VM_02_0                  _MK_ADDR_CONST(0x4110)
#define GPIO_D_VM_02_0_SECURE                   0x0
#define GPIO_D_VM_02_0_DUAL                     0x0
#define GPIO_D_VM_02_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_D_VM_02_0_WORD_COUNT                       0x1
#define GPIO_D_VM_02_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_D_VM_02_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_D_VM_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_D_VM_02_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_D_VM_02_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_D_VM_02_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_02_0_VM1_SHIFT)
#define GPIO_D_VM_02_0_VM1_RANGE                        1:0
#define GPIO_D_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_D_VM_02_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_02_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_02_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_D_VM_02_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_D_VM_02_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_02_0_VM2_SHIFT)
#define GPIO_D_VM_02_0_VM2_RANGE                        3:2
#define GPIO_D_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_D_VM_02_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_02_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_02_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_D_VM_02_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_D_VM_02_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_02_0_VM3_SHIFT)
#define GPIO_D_VM_02_0_VM3_RANGE                        5:4
#define GPIO_D_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_D_VM_02_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_02_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_02_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_D_VM_02_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_D_VM_02_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_02_0_VM4_SHIFT)
#define GPIO_D_VM_02_0_VM4_RANGE                        7:6
#define GPIO_D_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_D_VM_02_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_02_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_02_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_D_VM_02_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_D_VM_02_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_02_0_VM5_SHIFT)
#define GPIO_D_VM_02_0_VM5_RANGE                        9:8
#define GPIO_D_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_D_VM_02_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_02_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_02_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_D_VM_02_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_D_VM_02_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_02_0_VM6_SHIFT)
#define GPIO_D_VM_02_0_VM6_RANGE                        11:10
#define GPIO_D_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_D_VM_02_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_02_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_02_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_D_VM_02_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_D_VM_02_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_02_0_VM7_SHIFT)
#define GPIO_D_VM_02_0_VM7_RANGE                        13:12
#define GPIO_D_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_D_VM_02_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_02_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_02_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_D_VM_02_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_D_VM_02_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_02_0_VM8_SHIFT)
#define GPIO_D_VM_02_0_VM8_RANGE                        15:14
#define GPIO_D_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_D_VM_02_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_02_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_02_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_D_SCR_02_0
#define GPIO_D_SCR_02_0                 _MK_ADDR_CONST(0x4114)
#define GPIO_D_SCR_02_0_SECURE                  0x0
#define GPIO_D_SCR_02_0_DUAL                    0x0
#define GPIO_D_SCR_02_0_SCR                     0
#define GPIO_D_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_D_SCR_02_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_D_SCR_02_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_D_SCR_02_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_D_SCR_02_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_D_SCR_02_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_D_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_D_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_D_SCR_02_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_02_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_D_SCR_02_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_D_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_D_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_D_SCR_02_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_02_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_D_SCR_02_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_D_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_D_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_D_SCR_02_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_02_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_D_SCR_02_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_D_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_D_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_D_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_D_SCR_02_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_D_SCR_02_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_02_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_D_SCR_02_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_PR7_SHIFT)
#define GPIO_D_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_D_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_02_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_D_SCR_02_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_PR6_SHIFT)
#define GPIO_D_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_D_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_02_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_D_SCR_02_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_PR5_SHIFT)
#define GPIO_D_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_D_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_02_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_D_SCR_02_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_PR4_SHIFT)
#define GPIO_D_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_D_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_02_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_D_SCR_02_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_PR3_SHIFT)
#define GPIO_D_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_D_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_02_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_D_SCR_02_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_PR2_SHIFT)
#define GPIO_D_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_D_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_02_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_D_SCR_02_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_PR1_SHIFT)
#define GPIO_D_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_D_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_02_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_D_SCR_02_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_PR0_SHIFT)
#define GPIO_D_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_D_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_02_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_D_SCR_02_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G7W_SHIFT)
#define GPIO_D_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_D_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_02_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_D_SCR_02_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G6W_SHIFT)
#define GPIO_D_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_D_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_02_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_D_SCR_02_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G5W_SHIFT)
#define GPIO_D_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_D_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_02_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_D_SCR_02_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G4W_SHIFT)
#define GPIO_D_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_D_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_02_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_D_SCR_02_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G3W_SHIFT)
#define GPIO_D_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_D_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_02_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_D_SCR_02_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G2W_SHIFT)
#define GPIO_D_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_D_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_02_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_D_SCR_02_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G1W_SHIFT)
#define GPIO_D_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_D_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_02_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_D_SCR_02_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G0W_SHIFT)
#define GPIO_D_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_D_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_02_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_D_SCR_02_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G7R_SHIFT)
#define GPIO_D_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_D_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_02_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_D_SCR_02_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G6R_SHIFT)
#define GPIO_D_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_D_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_02_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_D_SCR_02_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G5R_SHIFT)
#define GPIO_D_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_D_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_02_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_D_SCR_02_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G4R_SHIFT)
#define GPIO_D_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_D_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_02_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_D_SCR_02_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G3R_SHIFT)
#define GPIO_D_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_D_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_02_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_D_SCR_02_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G2R_SHIFT)
#define GPIO_D_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_D_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_02_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_D_SCR_02_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G1R_SHIFT)
#define GPIO_D_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_D_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_02_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_D_SCR_02_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G0R_SHIFT)
#define GPIO_D_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_D_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_D_VM_03_0
#define GPIO_D_VM_03_0                  _MK_ADDR_CONST(0x4118)
#define GPIO_D_VM_03_0_SECURE                   0x0
#define GPIO_D_VM_03_0_DUAL                     0x0
#define GPIO_D_VM_03_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_D_VM_03_0_WORD_COUNT                       0x1
#define GPIO_D_VM_03_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_D_VM_03_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_D_VM_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_D_VM_03_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_D_VM_03_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_D_VM_03_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_03_0_VM1_SHIFT)
#define GPIO_D_VM_03_0_VM1_RANGE                        1:0
#define GPIO_D_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_D_VM_03_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_03_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_03_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_D_VM_03_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_D_VM_03_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_03_0_VM2_SHIFT)
#define GPIO_D_VM_03_0_VM2_RANGE                        3:2
#define GPIO_D_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_D_VM_03_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_03_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_03_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_D_VM_03_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_D_VM_03_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_03_0_VM3_SHIFT)
#define GPIO_D_VM_03_0_VM3_RANGE                        5:4
#define GPIO_D_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_D_VM_03_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_03_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_03_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_D_VM_03_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_D_VM_03_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_03_0_VM4_SHIFT)
#define GPIO_D_VM_03_0_VM4_RANGE                        7:6
#define GPIO_D_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_D_VM_03_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_03_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_03_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_D_VM_03_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_D_VM_03_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_03_0_VM5_SHIFT)
#define GPIO_D_VM_03_0_VM5_RANGE                        9:8
#define GPIO_D_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_D_VM_03_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_03_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_03_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_D_VM_03_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_D_VM_03_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_03_0_VM6_SHIFT)
#define GPIO_D_VM_03_0_VM6_RANGE                        11:10
#define GPIO_D_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_D_VM_03_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_03_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_03_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_D_VM_03_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_D_VM_03_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_03_0_VM7_SHIFT)
#define GPIO_D_VM_03_0_VM7_RANGE                        13:12
#define GPIO_D_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_D_VM_03_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_03_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_03_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_D_VM_03_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_D_VM_03_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_D_VM_03_0_VM8_SHIFT)
#define GPIO_D_VM_03_0_VM8_RANGE                        15:14
#define GPIO_D_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_D_VM_03_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_D_VM_03_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_D_VM_03_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_D_SCR_03_0
#define GPIO_D_SCR_03_0                 _MK_ADDR_CONST(0x411c)
#define GPIO_D_SCR_03_0_SECURE                  0x0
#define GPIO_D_SCR_03_0_DUAL                    0x0
#define GPIO_D_SCR_03_0_SCR                     0
#define GPIO_D_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_D_SCR_03_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_D_SCR_03_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_D_SCR_03_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_D_SCR_03_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_D_SCR_03_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_D_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_D_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_D_SCR_03_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_03_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_D_SCR_03_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_D_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_D_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_D_SCR_03_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_03_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_D_SCR_03_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_D_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_D_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_D_SCR_03_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_03_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_D_SCR_03_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_D_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_D_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_D_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_D_SCR_03_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_D_SCR_03_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_03_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_D_SCR_03_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_PR7_SHIFT)
#define GPIO_D_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_D_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_03_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_D_SCR_03_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_PR6_SHIFT)
#define GPIO_D_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_D_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_03_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_D_SCR_03_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_PR5_SHIFT)
#define GPIO_D_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_D_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_03_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_D_SCR_03_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_PR4_SHIFT)
#define GPIO_D_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_D_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_03_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_D_SCR_03_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_PR3_SHIFT)
#define GPIO_D_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_D_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_03_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_D_SCR_03_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_PR2_SHIFT)
#define GPIO_D_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_D_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_03_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_D_SCR_03_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_PR1_SHIFT)
#define GPIO_D_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_D_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_03_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_D_SCR_03_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_PR0_SHIFT)
#define GPIO_D_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_D_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_03_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_D_SCR_03_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G7W_SHIFT)
#define GPIO_D_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_D_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_03_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_D_SCR_03_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G6W_SHIFT)
#define GPIO_D_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_D_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_03_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_D_SCR_03_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G5W_SHIFT)
#define GPIO_D_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_D_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_03_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_D_SCR_03_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G4W_SHIFT)
#define GPIO_D_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_D_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_03_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_D_SCR_03_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G3W_SHIFT)
#define GPIO_D_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_D_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_03_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_D_SCR_03_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G2W_SHIFT)
#define GPIO_D_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_D_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_03_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_D_SCR_03_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G1W_SHIFT)
#define GPIO_D_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_D_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_03_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_D_SCR_03_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G0W_SHIFT)
#define GPIO_D_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_D_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_03_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_D_SCR_03_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G7R_SHIFT)
#define GPIO_D_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_D_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_03_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_D_SCR_03_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G6R_SHIFT)
#define GPIO_D_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_D_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_03_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_D_SCR_03_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G5R_SHIFT)
#define GPIO_D_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_D_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_03_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_D_SCR_03_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G4R_SHIFT)
#define GPIO_D_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_D_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_03_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_D_SCR_03_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G3R_SHIFT)
#define GPIO_D_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_D_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_03_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_D_SCR_03_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G2R_SHIFT)
#define GPIO_D_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_D_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_03_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_D_SCR_03_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G1R_SHIFT)
#define GPIO_D_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_D_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_D_SCR_03_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_D_SCR_03_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G0R_SHIFT)
#define GPIO_D_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_D_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Reserved address 0x4120

// Reserved address 0x4124

// Reserved address 0x4128

// Reserved address 0x412c

// Reserved address 0x4130

// Reserved address 0x4134

// Reserved address 0x4138

// Reserved address 0x413c

// Register GPIO_E_VM_00_0
#define GPIO_E_VM_00_0                  _MK_ADDR_CONST(0x4140)
#define GPIO_E_VM_00_0_SECURE                   0x0
#define GPIO_E_VM_00_0_DUAL                     0x0
#define GPIO_E_VM_00_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_E_VM_00_0_WORD_COUNT                       0x1
#define GPIO_E_VM_00_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_00_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_00_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_00_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_E_VM_00_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_00_0_VM1_SHIFT)
#define GPIO_E_VM_00_0_VM1_RANGE                        1:0
#define GPIO_E_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_E_VM_00_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_00_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_00_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_00_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_E_VM_00_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_00_0_VM2_SHIFT)
#define GPIO_E_VM_00_0_VM2_RANGE                        3:2
#define GPIO_E_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_E_VM_00_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_00_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_00_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_00_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_E_VM_00_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_00_0_VM3_SHIFT)
#define GPIO_E_VM_00_0_VM3_RANGE                        5:4
#define GPIO_E_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_E_VM_00_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_00_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_00_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_00_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_E_VM_00_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_00_0_VM4_SHIFT)
#define GPIO_E_VM_00_0_VM4_RANGE                        7:6
#define GPIO_E_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_E_VM_00_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_00_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_00_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_00_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_E_VM_00_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_00_0_VM5_SHIFT)
#define GPIO_E_VM_00_0_VM5_RANGE                        9:8
#define GPIO_E_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_E_VM_00_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_00_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_00_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_00_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_E_VM_00_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_00_0_VM6_SHIFT)
#define GPIO_E_VM_00_0_VM6_RANGE                        11:10
#define GPIO_E_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_E_VM_00_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_00_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_00_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_00_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_E_VM_00_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_00_0_VM7_SHIFT)
#define GPIO_E_VM_00_0_VM7_RANGE                        13:12
#define GPIO_E_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_E_VM_00_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_00_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_00_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_00_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_E_VM_00_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_00_0_VM8_SHIFT)
#define GPIO_E_VM_00_0_VM8_RANGE                        15:14
#define GPIO_E_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_E_VM_00_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_00_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_00_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_E_SCR_00_0
#define GPIO_E_SCR_00_0                 _MK_ADDR_CONST(0x4144)
#define GPIO_E_SCR_00_0_SECURE                  0x0
#define GPIO_E_SCR_00_0_DUAL                    0x0
#define GPIO_E_SCR_00_0_SCR                     0
#define GPIO_E_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_E_SCR_00_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_00_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_00_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_E_SCR_00_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_E_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_E_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_E_SCR_00_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_00_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_E_SCR_00_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_E_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_E_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_E_SCR_00_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_00_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_E_SCR_00_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_E_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_E_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_E_SCR_00_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_00_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_E_SCR_00_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_E_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_E_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_E_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_E_SCR_00_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_E_SCR_00_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_00_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_E_SCR_00_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_PR7_SHIFT)
#define GPIO_E_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_E_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_00_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_E_SCR_00_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_PR6_SHIFT)
#define GPIO_E_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_E_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_00_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_E_SCR_00_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_PR5_SHIFT)
#define GPIO_E_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_E_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_00_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_E_SCR_00_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_PR4_SHIFT)
#define GPIO_E_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_E_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_00_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_E_SCR_00_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_PR3_SHIFT)
#define GPIO_E_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_E_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_00_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_E_SCR_00_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_PR2_SHIFT)
#define GPIO_E_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_E_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_00_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_E_SCR_00_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_PR1_SHIFT)
#define GPIO_E_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_E_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_00_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_E_SCR_00_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_PR0_SHIFT)
#define GPIO_E_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_E_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_00_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_E_SCR_00_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G7W_SHIFT)
#define GPIO_E_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_E_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_00_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_E_SCR_00_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G6W_SHIFT)
#define GPIO_E_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_E_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_00_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_E_SCR_00_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G5W_SHIFT)
#define GPIO_E_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_E_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_00_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_E_SCR_00_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G4W_SHIFT)
#define GPIO_E_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_E_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_00_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_E_SCR_00_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G3W_SHIFT)
#define GPIO_E_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_E_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_00_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_E_SCR_00_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G2W_SHIFT)
#define GPIO_E_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_E_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_00_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_E_SCR_00_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G1W_SHIFT)
#define GPIO_E_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_E_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_00_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_E_SCR_00_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G0W_SHIFT)
#define GPIO_E_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_E_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_00_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_E_SCR_00_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G7R_SHIFT)
#define GPIO_E_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_E_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_00_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_E_SCR_00_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G6R_SHIFT)
#define GPIO_E_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_E_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_00_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_E_SCR_00_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G5R_SHIFT)
#define GPIO_E_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_E_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_00_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_E_SCR_00_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G4R_SHIFT)
#define GPIO_E_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_E_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_00_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_E_SCR_00_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G3R_SHIFT)
#define GPIO_E_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_E_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_00_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_E_SCR_00_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G2R_SHIFT)
#define GPIO_E_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_E_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_00_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_E_SCR_00_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G1R_SHIFT)
#define GPIO_E_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_E_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_00_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_E_SCR_00_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G0R_SHIFT)
#define GPIO_E_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_E_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_E_VM_01_0
#define GPIO_E_VM_01_0                  _MK_ADDR_CONST(0x4148)
#define GPIO_E_VM_01_0_SECURE                   0x0
#define GPIO_E_VM_01_0_DUAL                     0x0
#define GPIO_E_VM_01_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_E_VM_01_0_WORD_COUNT                       0x1
#define GPIO_E_VM_01_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_01_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_01_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_01_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_E_VM_01_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_01_0_VM1_SHIFT)
#define GPIO_E_VM_01_0_VM1_RANGE                        1:0
#define GPIO_E_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_E_VM_01_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_01_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_01_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_01_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_E_VM_01_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_01_0_VM2_SHIFT)
#define GPIO_E_VM_01_0_VM2_RANGE                        3:2
#define GPIO_E_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_E_VM_01_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_01_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_01_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_01_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_E_VM_01_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_01_0_VM3_SHIFT)
#define GPIO_E_VM_01_0_VM3_RANGE                        5:4
#define GPIO_E_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_E_VM_01_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_01_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_01_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_01_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_E_VM_01_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_01_0_VM4_SHIFT)
#define GPIO_E_VM_01_0_VM4_RANGE                        7:6
#define GPIO_E_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_E_VM_01_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_01_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_01_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_01_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_E_VM_01_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_01_0_VM5_SHIFT)
#define GPIO_E_VM_01_0_VM5_RANGE                        9:8
#define GPIO_E_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_E_VM_01_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_01_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_01_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_01_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_E_VM_01_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_01_0_VM6_SHIFT)
#define GPIO_E_VM_01_0_VM6_RANGE                        11:10
#define GPIO_E_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_E_VM_01_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_01_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_01_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_01_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_E_VM_01_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_01_0_VM7_SHIFT)
#define GPIO_E_VM_01_0_VM7_RANGE                        13:12
#define GPIO_E_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_E_VM_01_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_01_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_01_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_01_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_E_VM_01_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_01_0_VM8_SHIFT)
#define GPIO_E_VM_01_0_VM8_RANGE                        15:14
#define GPIO_E_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_E_VM_01_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_01_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_01_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_E_SCR_01_0
#define GPIO_E_SCR_01_0                 _MK_ADDR_CONST(0x414c)
#define GPIO_E_SCR_01_0_SECURE                  0x0
#define GPIO_E_SCR_01_0_DUAL                    0x0
#define GPIO_E_SCR_01_0_SCR                     0
#define GPIO_E_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_E_SCR_01_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_01_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_01_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_01_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_E_SCR_01_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_E_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_E_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_E_SCR_01_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_01_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_E_SCR_01_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_E_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_E_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_E_SCR_01_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_01_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_E_SCR_01_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_E_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_E_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_E_SCR_01_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_01_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_E_SCR_01_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_E_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_E_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_E_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_E_SCR_01_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_E_SCR_01_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_01_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_E_SCR_01_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_PR7_SHIFT)
#define GPIO_E_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_E_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_01_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_E_SCR_01_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_PR6_SHIFT)
#define GPIO_E_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_E_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_01_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_E_SCR_01_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_PR5_SHIFT)
#define GPIO_E_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_E_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_01_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_E_SCR_01_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_PR4_SHIFT)
#define GPIO_E_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_E_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_01_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_E_SCR_01_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_PR3_SHIFT)
#define GPIO_E_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_E_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_01_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_E_SCR_01_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_PR2_SHIFT)
#define GPIO_E_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_E_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_01_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_E_SCR_01_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_PR1_SHIFT)
#define GPIO_E_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_E_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_01_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_E_SCR_01_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_PR0_SHIFT)
#define GPIO_E_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_E_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_01_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_E_SCR_01_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G7W_SHIFT)
#define GPIO_E_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_E_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_01_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_E_SCR_01_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G6W_SHIFT)
#define GPIO_E_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_E_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_01_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_E_SCR_01_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G5W_SHIFT)
#define GPIO_E_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_E_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_01_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_E_SCR_01_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G4W_SHIFT)
#define GPIO_E_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_E_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_01_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_E_SCR_01_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G3W_SHIFT)
#define GPIO_E_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_E_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_01_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_E_SCR_01_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G2W_SHIFT)
#define GPIO_E_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_E_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_01_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_E_SCR_01_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G1W_SHIFT)
#define GPIO_E_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_E_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_01_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_E_SCR_01_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G0W_SHIFT)
#define GPIO_E_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_E_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_01_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_E_SCR_01_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G7R_SHIFT)
#define GPIO_E_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_E_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_01_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_E_SCR_01_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G6R_SHIFT)
#define GPIO_E_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_E_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_01_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_E_SCR_01_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G5R_SHIFT)
#define GPIO_E_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_E_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_01_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_E_SCR_01_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G4R_SHIFT)
#define GPIO_E_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_E_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_01_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_E_SCR_01_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G3R_SHIFT)
#define GPIO_E_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_E_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_01_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_E_SCR_01_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G2R_SHIFT)
#define GPIO_E_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_E_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_01_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_E_SCR_01_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G1R_SHIFT)
#define GPIO_E_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_E_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_01_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_E_SCR_01_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G0R_SHIFT)
#define GPIO_E_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_E_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_E_VM_02_0
#define GPIO_E_VM_02_0                  _MK_ADDR_CONST(0x4150)
#define GPIO_E_VM_02_0_SECURE                   0x0
#define GPIO_E_VM_02_0_DUAL                     0x0
#define GPIO_E_VM_02_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_E_VM_02_0_WORD_COUNT                       0x1
#define GPIO_E_VM_02_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_02_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_02_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_02_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_E_VM_02_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_02_0_VM1_SHIFT)
#define GPIO_E_VM_02_0_VM1_RANGE                        1:0
#define GPIO_E_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_E_VM_02_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_02_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_02_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_02_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_E_VM_02_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_02_0_VM2_SHIFT)
#define GPIO_E_VM_02_0_VM2_RANGE                        3:2
#define GPIO_E_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_E_VM_02_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_02_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_02_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_02_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_E_VM_02_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_02_0_VM3_SHIFT)
#define GPIO_E_VM_02_0_VM3_RANGE                        5:4
#define GPIO_E_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_E_VM_02_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_02_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_02_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_02_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_E_VM_02_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_02_0_VM4_SHIFT)
#define GPIO_E_VM_02_0_VM4_RANGE                        7:6
#define GPIO_E_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_E_VM_02_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_02_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_02_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_02_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_E_VM_02_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_02_0_VM5_SHIFT)
#define GPIO_E_VM_02_0_VM5_RANGE                        9:8
#define GPIO_E_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_E_VM_02_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_02_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_02_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_02_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_E_VM_02_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_02_0_VM6_SHIFT)
#define GPIO_E_VM_02_0_VM6_RANGE                        11:10
#define GPIO_E_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_E_VM_02_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_02_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_02_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_02_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_E_VM_02_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_02_0_VM7_SHIFT)
#define GPIO_E_VM_02_0_VM7_RANGE                        13:12
#define GPIO_E_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_E_VM_02_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_02_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_02_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_02_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_E_VM_02_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_02_0_VM8_SHIFT)
#define GPIO_E_VM_02_0_VM8_RANGE                        15:14
#define GPIO_E_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_E_VM_02_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_02_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_02_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_E_SCR_02_0
#define GPIO_E_SCR_02_0                 _MK_ADDR_CONST(0x4154)
#define GPIO_E_SCR_02_0_SECURE                  0x0
#define GPIO_E_SCR_02_0_DUAL                    0x0
#define GPIO_E_SCR_02_0_SCR                     0
#define GPIO_E_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_E_SCR_02_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_02_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_02_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_02_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_E_SCR_02_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_E_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_E_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_E_SCR_02_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_02_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_E_SCR_02_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_E_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_E_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_E_SCR_02_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_02_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_E_SCR_02_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_E_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_E_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_E_SCR_02_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_02_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_E_SCR_02_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_E_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_E_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_E_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_E_SCR_02_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_E_SCR_02_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_02_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_E_SCR_02_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_PR7_SHIFT)
#define GPIO_E_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_E_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_02_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_E_SCR_02_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_PR6_SHIFT)
#define GPIO_E_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_E_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_02_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_E_SCR_02_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_PR5_SHIFT)
#define GPIO_E_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_E_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_02_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_E_SCR_02_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_PR4_SHIFT)
#define GPIO_E_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_E_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_02_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_E_SCR_02_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_PR3_SHIFT)
#define GPIO_E_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_E_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_02_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_E_SCR_02_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_PR2_SHIFT)
#define GPIO_E_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_E_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_02_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_E_SCR_02_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_PR1_SHIFT)
#define GPIO_E_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_E_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_02_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_E_SCR_02_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_PR0_SHIFT)
#define GPIO_E_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_E_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_02_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_E_SCR_02_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G7W_SHIFT)
#define GPIO_E_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_E_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_02_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_E_SCR_02_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G6W_SHIFT)
#define GPIO_E_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_E_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_02_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_E_SCR_02_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G5W_SHIFT)
#define GPIO_E_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_E_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_02_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_E_SCR_02_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G4W_SHIFT)
#define GPIO_E_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_E_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_02_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_E_SCR_02_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G3W_SHIFT)
#define GPIO_E_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_E_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_02_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_E_SCR_02_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G2W_SHIFT)
#define GPIO_E_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_E_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_02_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_E_SCR_02_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G1W_SHIFT)
#define GPIO_E_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_E_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_02_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_E_SCR_02_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G0W_SHIFT)
#define GPIO_E_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_E_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_02_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_E_SCR_02_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G7R_SHIFT)
#define GPIO_E_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_E_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_02_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_E_SCR_02_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G6R_SHIFT)
#define GPIO_E_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_E_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_02_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_E_SCR_02_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G5R_SHIFT)
#define GPIO_E_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_E_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_02_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_E_SCR_02_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G4R_SHIFT)
#define GPIO_E_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_E_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_02_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_E_SCR_02_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G3R_SHIFT)
#define GPIO_E_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_E_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_02_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_E_SCR_02_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G2R_SHIFT)
#define GPIO_E_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_E_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_02_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_E_SCR_02_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G1R_SHIFT)
#define GPIO_E_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_E_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_02_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_E_SCR_02_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G0R_SHIFT)
#define GPIO_E_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_E_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_E_VM_03_0
#define GPIO_E_VM_03_0                  _MK_ADDR_CONST(0x4158)
#define GPIO_E_VM_03_0_SECURE                   0x0
#define GPIO_E_VM_03_0_DUAL                     0x0
#define GPIO_E_VM_03_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_E_VM_03_0_WORD_COUNT                       0x1
#define GPIO_E_VM_03_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_03_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_03_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_03_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_E_VM_03_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_03_0_VM1_SHIFT)
#define GPIO_E_VM_03_0_VM1_RANGE                        1:0
#define GPIO_E_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_E_VM_03_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_03_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_03_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_03_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_E_VM_03_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_03_0_VM2_SHIFT)
#define GPIO_E_VM_03_0_VM2_RANGE                        3:2
#define GPIO_E_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_E_VM_03_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_03_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_03_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_03_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_E_VM_03_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_03_0_VM3_SHIFT)
#define GPIO_E_VM_03_0_VM3_RANGE                        5:4
#define GPIO_E_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_E_VM_03_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_03_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_03_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_03_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_E_VM_03_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_03_0_VM4_SHIFT)
#define GPIO_E_VM_03_0_VM4_RANGE                        7:6
#define GPIO_E_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_E_VM_03_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_03_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_03_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_03_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_E_VM_03_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_03_0_VM5_SHIFT)
#define GPIO_E_VM_03_0_VM5_RANGE                        9:8
#define GPIO_E_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_E_VM_03_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_03_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_03_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_03_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_E_VM_03_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_03_0_VM6_SHIFT)
#define GPIO_E_VM_03_0_VM6_RANGE                        11:10
#define GPIO_E_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_E_VM_03_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_03_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_03_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_03_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_E_VM_03_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_03_0_VM7_SHIFT)
#define GPIO_E_VM_03_0_VM7_RANGE                        13:12
#define GPIO_E_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_E_VM_03_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_03_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_03_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_03_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_E_VM_03_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_03_0_VM8_SHIFT)
#define GPIO_E_VM_03_0_VM8_RANGE                        15:14
#define GPIO_E_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_E_VM_03_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_03_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_03_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_E_SCR_03_0
#define GPIO_E_SCR_03_0                 _MK_ADDR_CONST(0x415c)
#define GPIO_E_SCR_03_0_SECURE                  0x0
#define GPIO_E_SCR_03_0_DUAL                    0x0
#define GPIO_E_SCR_03_0_SCR                     0
#define GPIO_E_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_E_SCR_03_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_03_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_03_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_03_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_E_SCR_03_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_E_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_E_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_E_SCR_03_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_03_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_E_SCR_03_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_E_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_E_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_E_SCR_03_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_03_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_E_SCR_03_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_E_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_E_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_E_SCR_03_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_03_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_E_SCR_03_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_E_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_E_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_E_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_E_SCR_03_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_E_SCR_03_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_03_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_E_SCR_03_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_PR7_SHIFT)
#define GPIO_E_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_E_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_03_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_E_SCR_03_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_PR6_SHIFT)
#define GPIO_E_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_E_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_03_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_E_SCR_03_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_PR5_SHIFT)
#define GPIO_E_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_E_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_03_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_E_SCR_03_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_PR4_SHIFT)
#define GPIO_E_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_E_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_03_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_E_SCR_03_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_PR3_SHIFT)
#define GPIO_E_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_E_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_03_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_E_SCR_03_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_PR2_SHIFT)
#define GPIO_E_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_E_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_03_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_E_SCR_03_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_PR1_SHIFT)
#define GPIO_E_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_E_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_03_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_E_SCR_03_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_PR0_SHIFT)
#define GPIO_E_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_E_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_03_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_E_SCR_03_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G7W_SHIFT)
#define GPIO_E_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_E_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_03_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_E_SCR_03_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G6W_SHIFT)
#define GPIO_E_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_E_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_03_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_E_SCR_03_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G5W_SHIFT)
#define GPIO_E_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_E_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_03_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_E_SCR_03_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G4W_SHIFT)
#define GPIO_E_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_E_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_03_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_E_SCR_03_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G3W_SHIFT)
#define GPIO_E_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_E_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_03_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_E_SCR_03_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G2W_SHIFT)
#define GPIO_E_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_E_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_03_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_E_SCR_03_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G1W_SHIFT)
#define GPIO_E_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_E_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_03_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_E_SCR_03_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G0W_SHIFT)
#define GPIO_E_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_E_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_03_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_E_SCR_03_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G7R_SHIFT)
#define GPIO_E_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_E_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_03_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_E_SCR_03_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G6R_SHIFT)
#define GPIO_E_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_E_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_03_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_E_SCR_03_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G5R_SHIFT)
#define GPIO_E_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_E_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_03_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_E_SCR_03_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G4R_SHIFT)
#define GPIO_E_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_E_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_03_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_E_SCR_03_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G3R_SHIFT)
#define GPIO_E_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_E_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_03_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_E_SCR_03_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G2R_SHIFT)
#define GPIO_E_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_E_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_03_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_E_SCR_03_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G1R_SHIFT)
#define GPIO_E_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_E_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_03_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_E_SCR_03_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G0R_SHIFT)
#define GPIO_E_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_E_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_E_VM_04_0
#define GPIO_E_VM_04_0                  _MK_ADDR_CONST(0x4160)
#define GPIO_E_VM_04_0_SECURE                   0x0
#define GPIO_E_VM_04_0_DUAL                     0x0
#define GPIO_E_VM_04_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_E_VM_04_0_WORD_COUNT                       0x1
#define GPIO_E_VM_04_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_04_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_04_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_04_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_E_VM_04_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_04_0_VM1_SHIFT)
#define GPIO_E_VM_04_0_VM1_RANGE                        1:0
#define GPIO_E_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_E_VM_04_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_04_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_04_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_04_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_E_VM_04_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_04_0_VM2_SHIFT)
#define GPIO_E_VM_04_0_VM2_RANGE                        3:2
#define GPIO_E_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_E_VM_04_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_04_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_04_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_04_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_E_VM_04_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_04_0_VM3_SHIFT)
#define GPIO_E_VM_04_0_VM3_RANGE                        5:4
#define GPIO_E_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_E_VM_04_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_04_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_04_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_04_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_E_VM_04_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_04_0_VM4_SHIFT)
#define GPIO_E_VM_04_0_VM4_RANGE                        7:6
#define GPIO_E_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_E_VM_04_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_04_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_04_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_04_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_E_VM_04_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_04_0_VM5_SHIFT)
#define GPIO_E_VM_04_0_VM5_RANGE                        9:8
#define GPIO_E_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_E_VM_04_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_04_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_04_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_04_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_E_VM_04_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_04_0_VM6_SHIFT)
#define GPIO_E_VM_04_0_VM6_RANGE                        11:10
#define GPIO_E_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_E_VM_04_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_04_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_04_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_04_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_E_VM_04_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_04_0_VM7_SHIFT)
#define GPIO_E_VM_04_0_VM7_RANGE                        13:12
#define GPIO_E_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_E_VM_04_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_04_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_04_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_04_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_E_VM_04_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_04_0_VM8_SHIFT)
#define GPIO_E_VM_04_0_VM8_RANGE                        15:14
#define GPIO_E_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_E_VM_04_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_04_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_04_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_E_SCR_04_0
#define GPIO_E_SCR_04_0                 _MK_ADDR_CONST(0x4164)
#define GPIO_E_SCR_04_0_SECURE                  0x0
#define GPIO_E_SCR_04_0_DUAL                    0x0
#define GPIO_E_SCR_04_0_SCR                     0
#define GPIO_E_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_E_SCR_04_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_04_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_04_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_04_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_E_SCR_04_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_E_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_E_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_E_SCR_04_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_04_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_E_SCR_04_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_E_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_E_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_E_SCR_04_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_04_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_E_SCR_04_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_E_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_E_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_E_SCR_04_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_04_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_E_SCR_04_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_E_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_E_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_E_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_E_SCR_04_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_E_SCR_04_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_04_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_E_SCR_04_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_PR7_SHIFT)
#define GPIO_E_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_E_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_04_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_E_SCR_04_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_PR6_SHIFT)
#define GPIO_E_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_E_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_04_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_E_SCR_04_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_PR5_SHIFT)
#define GPIO_E_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_E_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_04_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_E_SCR_04_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_PR4_SHIFT)
#define GPIO_E_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_E_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_04_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_E_SCR_04_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_PR3_SHIFT)
#define GPIO_E_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_E_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_04_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_E_SCR_04_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_PR2_SHIFT)
#define GPIO_E_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_E_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_04_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_E_SCR_04_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_PR1_SHIFT)
#define GPIO_E_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_E_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_04_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_E_SCR_04_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_PR0_SHIFT)
#define GPIO_E_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_E_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_04_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_E_SCR_04_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G7W_SHIFT)
#define GPIO_E_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_E_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_04_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_E_SCR_04_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G6W_SHIFT)
#define GPIO_E_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_E_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_04_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_E_SCR_04_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G5W_SHIFT)
#define GPIO_E_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_E_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_04_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_E_SCR_04_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G4W_SHIFT)
#define GPIO_E_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_E_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_04_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_E_SCR_04_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G3W_SHIFT)
#define GPIO_E_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_E_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_04_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_E_SCR_04_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G2W_SHIFT)
#define GPIO_E_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_E_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_04_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_E_SCR_04_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G1W_SHIFT)
#define GPIO_E_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_E_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_04_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_E_SCR_04_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G0W_SHIFT)
#define GPIO_E_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_E_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_04_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_E_SCR_04_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G7R_SHIFT)
#define GPIO_E_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_E_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_04_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_E_SCR_04_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G6R_SHIFT)
#define GPIO_E_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_E_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_04_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_E_SCR_04_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G5R_SHIFT)
#define GPIO_E_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_E_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_04_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_E_SCR_04_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G4R_SHIFT)
#define GPIO_E_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_E_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_04_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_E_SCR_04_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G3R_SHIFT)
#define GPIO_E_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_E_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_04_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_E_SCR_04_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G2R_SHIFT)
#define GPIO_E_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_E_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_04_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_E_SCR_04_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G1R_SHIFT)
#define GPIO_E_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_E_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_04_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_E_SCR_04_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G0R_SHIFT)
#define GPIO_E_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_E_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_E_VM_05_0
#define GPIO_E_VM_05_0                  _MK_ADDR_CONST(0x4168)
#define GPIO_E_VM_05_0_SECURE                   0x0
#define GPIO_E_VM_05_0_DUAL                     0x0
#define GPIO_E_VM_05_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_E_VM_05_0_WORD_COUNT                       0x1
#define GPIO_E_VM_05_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_05_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_05_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_05_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_E_VM_05_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_05_0_VM1_SHIFT)
#define GPIO_E_VM_05_0_VM1_RANGE                        1:0
#define GPIO_E_VM_05_0_VM1_WOFFSET                      0x0
#define GPIO_E_VM_05_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_05_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_05_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_05_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_E_VM_05_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_05_0_VM2_SHIFT)
#define GPIO_E_VM_05_0_VM2_RANGE                        3:2
#define GPIO_E_VM_05_0_VM2_WOFFSET                      0x0
#define GPIO_E_VM_05_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_05_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_05_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_05_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_E_VM_05_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_05_0_VM3_SHIFT)
#define GPIO_E_VM_05_0_VM3_RANGE                        5:4
#define GPIO_E_VM_05_0_VM3_WOFFSET                      0x0
#define GPIO_E_VM_05_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_05_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_05_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_05_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_E_VM_05_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_05_0_VM4_SHIFT)
#define GPIO_E_VM_05_0_VM4_RANGE                        7:6
#define GPIO_E_VM_05_0_VM4_WOFFSET                      0x0
#define GPIO_E_VM_05_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_05_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_05_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_05_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_E_VM_05_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_05_0_VM5_SHIFT)
#define GPIO_E_VM_05_0_VM5_RANGE                        9:8
#define GPIO_E_VM_05_0_VM5_WOFFSET                      0x0
#define GPIO_E_VM_05_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_05_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_05_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_05_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_E_VM_05_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_05_0_VM6_SHIFT)
#define GPIO_E_VM_05_0_VM6_RANGE                        11:10
#define GPIO_E_VM_05_0_VM6_WOFFSET                      0x0
#define GPIO_E_VM_05_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_05_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_05_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_05_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_E_VM_05_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_05_0_VM7_SHIFT)
#define GPIO_E_VM_05_0_VM7_RANGE                        13:12
#define GPIO_E_VM_05_0_VM7_WOFFSET                      0x0
#define GPIO_E_VM_05_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_05_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_05_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_05_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_E_VM_05_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_05_0_VM8_SHIFT)
#define GPIO_E_VM_05_0_VM8_RANGE                        15:14
#define GPIO_E_VM_05_0_VM8_WOFFSET                      0x0
#define GPIO_E_VM_05_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_05_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_05_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_E_SCR_05_0
#define GPIO_E_SCR_05_0                 _MK_ADDR_CONST(0x416c)
#define GPIO_E_SCR_05_0_SECURE                  0x0
#define GPIO_E_SCR_05_0_DUAL                    0x0
#define GPIO_E_SCR_05_0_SCR                     0
#define GPIO_E_SCR_05_0_WORD_COUNT                      0x1
#define GPIO_E_SCR_05_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_05_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_05_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_05_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_E_SCR_05_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_E_SCR_05_0_SEC_LCK_RANGE                   29:29
#define GPIO_E_SCR_05_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_E_SCR_05_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_05_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_E_SCR_05_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_E_SCR_05_0_SEC_WEN_RANGE                   28:28
#define GPIO_E_SCR_05_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_E_SCR_05_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_05_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_E_SCR_05_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_E_SCR_05_0_SEC_REN_RANGE                   27:27
#define GPIO_E_SCR_05_0_SEC_REN_WOFFSET                 0x0
#define GPIO_E_SCR_05_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_05_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_E_SCR_05_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_E_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_E_SCR_05_0_SEC_OWNER_RANGE                 26:24
#define GPIO_E_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_E_SCR_05_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_E_SCR_05_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_05_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_E_SCR_05_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_PR7_SHIFT)
#define GPIO_E_SCR_05_0_PR7_RANGE                       23:23
#define GPIO_E_SCR_05_0_PR7_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_05_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_E_SCR_05_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_PR6_SHIFT)
#define GPIO_E_SCR_05_0_PR6_RANGE                       22:22
#define GPIO_E_SCR_05_0_PR6_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_05_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_E_SCR_05_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_PR5_SHIFT)
#define GPIO_E_SCR_05_0_PR5_RANGE                       21:21
#define GPIO_E_SCR_05_0_PR5_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_05_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_E_SCR_05_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_PR4_SHIFT)
#define GPIO_E_SCR_05_0_PR4_RANGE                       20:20
#define GPIO_E_SCR_05_0_PR4_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_05_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_E_SCR_05_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_PR3_SHIFT)
#define GPIO_E_SCR_05_0_PR3_RANGE                       19:19
#define GPIO_E_SCR_05_0_PR3_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_05_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_E_SCR_05_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_PR2_SHIFT)
#define GPIO_E_SCR_05_0_PR2_RANGE                       18:18
#define GPIO_E_SCR_05_0_PR2_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_05_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_E_SCR_05_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_PR1_SHIFT)
#define GPIO_E_SCR_05_0_PR1_RANGE                       17:17
#define GPIO_E_SCR_05_0_PR1_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_05_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_E_SCR_05_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_PR0_SHIFT)
#define GPIO_E_SCR_05_0_PR0_RANGE                       16:16
#define GPIO_E_SCR_05_0_PR0_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_05_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_E_SCR_05_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G7W_SHIFT)
#define GPIO_E_SCR_05_0_G7W_RANGE                       15:15
#define GPIO_E_SCR_05_0_G7W_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_05_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_E_SCR_05_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G6W_SHIFT)
#define GPIO_E_SCR_05_0_G6W_RANGE                       14:14
#define GPIO_E_SCR_05_0_G6W_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_05_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_E_SCR_05_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G5W_SHIFT)
#define GPIO_E_SCR_05_0_G5W_RANGE                       13:13
#define GPIO_E_SCR_05_0_G5W_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_05_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_E_SCR_05_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G4W_SHIFT)
#define GPIO_E_SCR_05_0_G4W_RANGE                       12:12
#define GPIO_E_SCR_05_0_G4W_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_05_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_E_SCR_05_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G3W_SHIFT)
#define GPIO_E_SCR_05_0_G3W_RANGE                       11:11
#define GPIO_E_SCR_05_0_G3W_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_05_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_E_SCR_05_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G2W_SHIFT)
#define GPIO_E_SCR_05_0_G2W_RANGE                       10:10
#define GPIO_E_SCR_05_0_G2W_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_05_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_E_SCR_05_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G1W_SHIFT)
#define GPIO_E_SCR_05_0_G1W_RANGE                       9:9
#define GPIO_E_SCR_05_0_G1W_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_05_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_E_SCR_05_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G0W_SHIFT)
#define GPIO_E_SCR_05_0_G0W_RANGE                       8:8
#define GPIO_E_SCR_05_0_G0W_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_05_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_E_SCR_05_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G7R_SHIFT)
#define GPIO_E_SCR_05_0_G7R_RANGE                       7:7
#define GPIO_E_SCR_05_0_G7R_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_05_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_E_SCR_05_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G6R_SHIFT)
#define GPIO_E_SCR_05_0_G6R_RANGE                       6:6
#define GPIO_E_SCR_05_0_G6R_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_05_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_E_SCR_05_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G5R_SHIFT)
#define GPIO_E_SCR_05_0_G5R_RANGE                       5:5
#define GPIO_E_SCR_05_0_G5R_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_05_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_E_SCR_05_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G4R_SHIFT)
#define GPIO_E_SCR_05_0_G4R_RANGE                       4:4
#define GPIO_E_SCR_05_0_G4R_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_05_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_E_SCR_05_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G3R_SHIFT)
#define GPIO_E_SCR_05_0_G3R_RANGE                       3:3
#define GPIO_E_SCR_05_0_G3R_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_05_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_E_SCR_05_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G2R_SHIFT)
#define GPIO_E_SCR_05_0_G2R_RANGE                       2:2
#define GPIO_E_SCR_05_0_G2R_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_05_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_E_SCR_05_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G1R_SHIFT)
#define GPIO_E_SCR_05_0_G1R_RANGE                       1:1
#define GPIO_E_SCR_05_0_G1R_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_05_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_E_SCR_05_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G0R_SHIFT)
#define GPIO_E_SCR_05_0_G0R_RANGE                       0:0
#define GPIO_E_SCR_05_0_G0R_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_E_VM_06_0
#define GPIO_E_VM_06_0                  _MK_ADDR_CONST(0x4170)
#define GPIO_E_VM_06_0_SECURE                   0x0
#define GPIO_E_VM_06_0_DUAL                     0x0
#define GPIO_E_VM_06_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_E_VM_06_0_WORD_COUNT                       0x1
#define GPIO_E_VM_06_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_06_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_06_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_06_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_06_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_E_VM_06_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_06_0_VM1_SHIFT)
#define GPIO_E_VM_06_0_VM1_RANGE                        1:0
#define GPIO_E_VM_06_0_VM1_WOFFSET                      0x0
#define GPIO_E_VM_06_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_06_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_06_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_06_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_E_VM_06_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_06_0_VM2_SHIFT)
#define GPIO_E_VM_06_0_VM2_RANGE                        3:2
#define GPIO_E_VM_06_0_VM2_WOFFSET                      0x0
#define GPIO_E_VM_06_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_06_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_06_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_06_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_E_VM_06_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_06_0_VM3_SHIFT)
#define GPIO_E_VM_06_0_VM3_RANGE                        5:4
#define GPIO_E_VM_06_0_VM3_WOFFSET                      0x0
#define GPIO_E_VM_06_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_06_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_06_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_06_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_E_VM_06_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_06_0_VM4_SHIFT)
#define GPIO_E_VM_06_0_VM4_RANGE                        7:6
#define GPIO_E_VM_06_0_VM4_WOFFSET                      0x0
#define GPIO_E_VM_06_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_06_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_06_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_06_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_E_VM_06_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_06_0_VM5_SHIFT)
#define GPIO_E_VM_06_0_VM5_RANGE                        9:8
#define GPIO_E_VM_06_0_VM5_WOFFSET                      0x0
#define GPIO_E_VM_06_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_06_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_06_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_06_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_E_VM_06_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_06_0_VM6_SHIFT)
#define GPIO_E_VM_06_0_VM6_RANGE                        11:10
#define GPIO_E_VM_06_0_VM6_WOFFSET                      0x0
#define GPIO_E_VM_06_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_06_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_06_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_06_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_E_VM_06_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_06_0_VM7_SHIFT)
#define GPIO_E_VM_06_0_VM7_RANGE                        13:12
#define GPIO_E_VM_06_0_VM7_WOFFSET                      0x0
#define GPIO_E_VM_06_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_06_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_06_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_06_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_E_VM_06_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_06_0_VM8_SHIFT)
#define GPIO_E_VM_06_0_VM8_RANGE                        15:14
#define GPIO_E_VM_06_0_VM8_WOFFSET                      0x0
#define GPIO_E_VM_06_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_06_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_06_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_E_SCR_06_0
#define GPIO_E_SCR_06_0                 _MK_ADDR_CONST(0x4174)
#define GPIO_E_SCR_06_0_SECURE                  0x0
#define GPIO_E_SCR_06_0_DUAL                    0x0
#define GPIO_E_SCR_06_0_SCR                     0
#define GPIO_E_SCR_06_0_WORD_COUNT                      0x1
#define GPIO_E_SCR_06_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_06_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_06_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_06_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_E_SCR_06_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_SEC_LCK_SHIFT)
#define GPIO_E_SCR_06_0_SEC_LCK_RANGE                   29:29
#define GPIO_E_SCR_06_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_E_SCR_06_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_06_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_E_SCR_06_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_SEC_WEN_SHIFT)
#define GPIO_E_SCR_06_0_SEC_WEN_RANGE                   28:28
#define GPIO_E_SCR_06_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_E_SCR_06_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_06_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_E_SCR_06_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_SEC_REN_SHIFT)
#define GPIO_E_SCR_06_0_SEC_REN_RANGE                   27:27
#define GPIO_E_SCR_06_0_SEC_REN_WOFFSET                 0x0
#define GPIO_E_SCR_06_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_06_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_E_SCR_06_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_E_SCR_06_0_SEC_OWNER_SHIFT)
#define GPIO_E_SCR_06_0_SEC_OWNER_RANGE                 26:24
#define GPIO_E_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_E_SCR_06_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_E_SCR_06_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_06_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_E_SCR_06_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_PR7_SHIFT)
#define GPIO_E_SCR_06_0_PR7_RANGE                       23:23
#define GPIO_E_SCR_06_0_PR7_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_06_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_E_SCR_06_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_PR6_SHIFT)
#define GPIO_E_SCR_06_0_PR6_RANGE                       22:22
#define GPIO_E_SCR_06_0_PR6_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_06_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_E_SCR_06_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_PR5_SHIFT)
#define GPIO_E_SCR_06_0_PR5_RANGE                       21:21
#define GPIO_E_SCR_06_0_PR5_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_06_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_E_SCR_06_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_PR4_SHIFT)
#define GPIO_E_SCR_06_0_PR4_RANGE                       20:20
#define GPIO_E_SCR_06_0_PR4_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_06_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_E_SCR_06_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_PR3_SHIFT)
#define GPIO_E_SCR_06_0_PR3_RANGE                       19:19
#define GPIO_E_SCR_06_0_PR3_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_06_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_E_SCR_06_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_PR2_SHIFT)
#define GPIO_E_SCR_06_0_PR2_RANGE                       18:18
#define GPIO_E_SCR_06_0_PR2_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_06_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_E_SCR_06_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_PR1_SHIFT)
#define GPIO_E_SCR_06_0_PR1_RANGE                       17:17
#define GPIO_E_SCR_06_0_PR1_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_06_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_E_SCR_06_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_PR0_SHIFT)
#define GPIO_E_SCR_06_0_PR0_RANGE                       16:16
#define GPIO_E_SCR_06_0_PR0_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_06_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_E_SCR_06_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G7W_SHIFT)
#define GPIO_E_SCR_06_0_G7W_RANGE                       15:15
#define GPIO_E_SCR_06_0_G7W_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_06_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_E_SCR_06_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G6W_SHIFT)
#define GPIO_E_SCR_06_0_G6W_RANGE                       14:14
#define GPIO_E_SCR_06_0_G6W_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_06_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_E_SCR_06_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G5W_SHIFT)
#define GPIO_E_SCR_06_0_G5W_RANGE                       13:13
#define GPIO_E_SCR_06_0_G5W_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_06_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_E_SCR_06_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G4W_SHIFT)
#define GPIO_E_SCR_06_0_G4W_RANGE                       12:12
#define GPIO_E_SCR_06_0_G4W_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_06_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_E_SCR_06_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G3W_SHIFT)
#define GPIO_E_SCR_06_0_G3W_RANGE                       11:11
#define GPIO_E_SCR_06_0_G3W_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_06_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_E_SCR_06_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G2W_SHIFT)
#define GPIO_E_SCR_06_0_G2W_RANGE                       10:10
#define GPIO_E_SCR_06_0_G2W_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_06_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_E_SCR_06_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G1W_SHIFT)
#define GPIO_E_SCR_06_0_G1W_RANGE                       9:9
#define GPIO_E_SCR_06_0_G1W_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_06_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_E_SCR_06_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G0W_SHIFT)
#define GPIO_E_SCR_06_0_G0W_RANGE                       8:8
#define GPIO_E_SCR_06_0_G0W_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_06_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_E_SCR_06_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G7R_SHIFT)
#define GPIO_E_SCR_06_0_G7R_RANGE                       7:7
#define GPIO_E_SCR_06_0_G7R_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_06_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_E_SCR_06_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G6R_SHIFT)
#define GPIO_E_SCR_06_0_G6R_RANGE                       6:6
#define GPIO_E_SCR_06_0_G6R_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_06_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_E_SCR_06_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G5R_SHIFT)
#define GPIO_E_SCR_06_0_G5R_RANGE                       5:5
#define GPIO_E_SCR_06_0_G5R_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_06_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_E_SCR_06_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G4R_SHIFT)
#define GPIO_E_SCR_06_0_G4R_RANGE                       4:4
#define GPIO_E_SCR_06_0_G4R_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_06_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_E_SCR_06_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G3R_SHIFT)
#define GPIO_E_SCR_06_0_G3R_RANGE                       3:3
#define GPIO_E_SCR_06_0_G3R_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_06_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_E_SCR_06_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G2R_SHIFT)
#define GPIO_E_SCR_06_0_G2R_RANGE                       2:2
#define GPIO_E_SCR_06_0_G2R_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_06_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_E_SCR_06_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G1R_SHIFT)
#define GPIO_E_SCR_06_0_G1R_RANGE                       1:1
#define GPIO_E_SCR_06_0_G1R_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_06_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_E_SCR_06_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G0R_SHIFT)
#define GPIO_E_SCR_06_0_G0R_RANGE                       0:0
#define GPIO_E_SCR_06_0_G0R_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_E_VM_07_0
#define GPIO_E_VM_07_0                  _MK_ADDR_CONST(0x4178)
#define GPIO_E_VM_07_0_SECURE                   0x0
#define GPIO_E_VM_07_0_DUAL                     0x0
#define GPIO_E_VM_07_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_E_VM_07_0_WORD_COUNT                       0x1
#define GPIO_E_VM_07_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_07_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_07_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_07_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_E_VM_07_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_E_VM_07_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_07_0_VM1_SHIFT)
#define GPIO_E_VM_07_0_VM1_RANGE                        1:0
#define GPIO_E_VM_07_0_VM1_WOFFSET                      0x0
#define GPIO_E_VM_07_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_07_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_07_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_07_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_E_VM_07_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_07_0_VM2_SHIFT)
#define GPIO_E_VM_07_0_VM2_RANGE                        3:2
#define GPIO_E_VM_07_0_VM2_WOFFSET                      0x0
#define GPIO_E_VM_07_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_07_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_07_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_07_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_E_VM_07_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_07_0_VM3_SHIFT)
#define GPIO_E_VM_07_0_VM3_RANGE                        5:4
#define GPIO_E_VM_07_0_VM3_WOFFSET                      0x0
#define GPIO_E_VM_07_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_07_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_07_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_07_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_E_VM_07_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_07_0_VM4_SHIFT)
#define GPIO_E_VM_07_0_VM4_RANGE                        7:6
#define GPIO_E_VM_07_0_VM4_WOFFSET                      0x0
#define GPIO_E_VM_07_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_07_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_07_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_07_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_E_VM_07_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_07_0_VM5_SHIFT)
#define GPIO_E_VM_07_0_VM5_RANGE                        9:8
#define GPIO_E_VM_07_0_VM5_WOFFSET                      0x0
#define GPIO_E_VM_07_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_07_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_07_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_07_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_E_VM_07_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_07_0_VM6_SHIFT)
#define GPIO_E_VM_07_0_VM6_RANGE                        11:10
#define GPIO_E_VM_07_0_VM6_WOFFSET                      0x0
#define GPIO_E_VM_07_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_07_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_07_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_07_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_E_VM_07_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_07_0_VM7_SHIFT)
#define GPIO_E_VM_07_0_VM7_RANGE                        13:12
#define GPIO_E_VM_07_0_VM7_WOFFSET                      0x0
#define GPIO_E_VM_07_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_07_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_07_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_E_VM_07_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_E_VM_07_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_E_VM_07_0_VM8_SHIFT)
#define GPIO_E_VM_07_0_VM8_RANGE                        15:14
#define GPIO_E_VM_07_0_VM8_WOFFSET                      0x0
#define GPIO_E_VM_07_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_E_VM_07_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_E_VM_07_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_E_SCR_07_0
#define GPIO_E_SCR_07_0                 _MK_ADDR_CONST(0x417c)
#define GPIO_E_SCR_07_0_SECURE                  0x0
#define GPIO_E_SCR_07_0_DUAL                    0x0
#define GPIO_E_SCR_07_0_SCR                     0
#define GPIO_E_SCR_07_0_WORD_COUNT                      0x1
#define GPIO_E_SCR_07_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_07_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_07_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_07_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_E_SCR_07_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_SEC_LCK_SHIFT)
#define GPIO_E_SCR_07_0_SEC_LCK_RANGE                   29:29
#define GPIO_E_SCR_07_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_E_SCR_07_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_07_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_E_SCR_07_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_SEC_WEN_SHIFT)
#define GPIO_E_SCR_07_0_SEC_WEN_RANGE                   28:28
#define GPIO_E_SCR_07_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_E_SCR_07_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_07_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_E_SCR_07_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_SEC_REN_SHIFT)
#define GPIO_E_SCR_07_0_SEC_REN_RANGE                   27:27
#define GPIO_E_SCR_07_0_SEC_REN_WOFFSET                 0x0
#define GPIO_E_SCR_07_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_07_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_E_SCR_07_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_E_SCR_07_0_SEC_OWNER_SHIFT)
#define GPIO_E_SCR_07_0_SEC_OWNER_RANGE                 26:24
#define GPIO_E_SCR_07_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_E_SCR_07_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_E_SCR_07_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_07_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_E_SCR_07_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_PR7_SHIFT)
#define GPIO_E_SCR_07_0_PR7_RANGE                       23:23
#define GPIO_E_SCR_07_0_PR7_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_07_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_E_SCR_07_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_PR6_SHIFT)
#define GPIO_E_SCR_07_0_PR6_RANGE                       22:22
#define GPIO_E_SCR_07_0_PR6_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_07_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_E_SCR_07_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_PR5_SHIFT)
#define GPIO_E_SCR_07_0_PR5_RANGE                       21:21
#define GPIO_E_SCR_07_0_PR5_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_07_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_E_SCR_07_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_PR4_SHIFT)
#define GPIO_E_SCR_07_0_PR4_RANGE                       20:20
#define GPIO_E_SCR_07_0_PR4_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_07_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_E_SCR_07_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_PR3_SHIFT)
#define GPIO_E_SCR_07_0_PR3_RANGE                       19:19
#define GPIO_E_SCR_07_0_PR3_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_07_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_E_SCR_07_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_PR2_SHIFT)
#define GPIO_E_SCR_07_0_PR2_RANGE                       18:18
#define GPIO_E_SCR_07_0_PR2_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_07_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_E_SCR_07_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_PR1_SHIFT)
#define GPIO_E_SCR_07_0_PR1_RANGE                       17:17
#define GPIO_E_SCR_07_0_PR1_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_07_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_E_SCR_07_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_PR0_SHIFT)
#define GPIO_E_SCR_07_0_PR0_RANGE                       16:16
#define GPIO_E_SCR_07_0_PR0_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_07_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_E_SCR_07_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G7W_SHIFT)
#define GPIO_E_SCR_07_0_G7W_RANGE                       15:15
#define GPIO_E_SCR_07_0_G7W_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_07_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_E_SCR_07_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G6W_SHIFT)
#define GPIO_E_SCR_07_0_G6W_RANGE                       14:14
#define GPIO_E_SCR_07_0_G6W_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_07_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_E_SCR_07_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G5W_SHIFT)
#define GPIO_E_SCR_07_0_G5W_RANGE                       13:13
#define GPIO_E_SCR_07_0_G5W_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_07_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_E_SCR_07_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G4W_SHIFT)
#define GPIO_E_SCR_07_0_G4W_RANGE                       12:12
#define GPIO_E_SCR_07_0_G4W_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_07_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_E_SCR_07_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G3W_SHIFT)
#define GPIO_E_SCR_07_0_G3W_RANGE                       11:11
#define GPIO_E_SCR_07_0_G3W_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_07_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_E_SCR_07_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G2W_SHIFT)
#define GPIO_E_SCR_07_0_G2W_RANGE                       10:10
#define GPIO_E_SCR_07_0_G2W_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_07_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_E_SCR_07_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G1W_SHIFT)
#define GPIO_E_SCR_07_0_G1W_RANGE                       9:9
#define GPIO_E_SCR_07_0_G1W_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_07_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_E_SCR_07_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G0W_SHIFT)
#define GPIO_E_SCR_07_0_G0W_RANGE                       8:8
#define GPIO_E_SCR_07_0_G0W_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_07_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_E_SCR_07_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G7R_SHIFT)
#define GPIO_E_SCR_07_0_G7R_RANGE                       7:7
#define GPIO_E_SCR_07_0_G7R_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_07_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_E_SCR_07_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G6R_SHIFT)
#define GPIO_E_SCR_07_0_G6R_RANGE                       6:6
#define GPIO_E_SCR_07_0_G6R_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_07_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_E_SCR_07_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G5R_SHIFT)
#define GPIO_E_SCR_07_0_G5R_RANGE                       5:5
#define GPIO_E_SCR_07_0_G5R_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_07_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_E_SCR_07_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G4R_SHIFT)
#define GPIO_E_SCR_07_0_G4R_RANGE                       4:4
#define GPIO_E_SCR_07_0_G4R_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_07_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_E_SCR_07_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G3R_SHIFT)
#define GPIO_E_SCR_07_0_G3R_RANGE                       3:3
#define GPIO_E_SCR_07_0_G3R_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_07_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_E_SCR_07_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G2R_SHIFT)
#define GPIO_E_SCR_07_0_G2R_RANGE                       2:2
#define GPIO_E_SCR_07_0_G2R_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_07_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_E_SCR_07_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G1R_SHIFT)
#define GPIO_E_SCR_07_0_G1R_RANGE                       1:1
#define GPIO_E_SCR_07_0_G1R_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_E_SCR_07_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_E_SCR_07_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G0R_SHIFT)
#define GPIO_E_SCR_07_0_G0R_RANGE                       0:0
#define GPIO_E_SCR_07_0_G0R_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_F_VM_00_0
#define GPIO_F_VM_00_0                  _MK_ADDR_CONST(0x4180)
#define GPIO_F_VM_00_0_SECURE                   0x0
#define GPIO_F_VM_00_0_DUAL                     0x0
#define GPIO_F_VM_00_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_F_VM_00_0_WORD_COUNT                       0x1
#define GPIO_F_VM_00_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_F_VM_00_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_F_VM_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_F_VM_00_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_F_VM_00_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_F_VM_00_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_00_0_VM1_SHIFT)
#define GPIO_F_VM_00_0_VM1_RANGE                        1:0
#define GPIO_F_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_F_VM_00_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_00_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_00_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_F_VM_00_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_F_VM_00_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_00_0_VM2_SHIFT)
#define GPIO_F_VM_00_0_VM2_RANGE                        3:2
#define GPIO_F_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_F_VM_00_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_00_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_00_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_F_VM_00_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_F_VM_00_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_00_0_VM3_SHIFT)
#define GPIO_F_VM_00_0_VM3_RANGE                        5:4
#define GPIO_F_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_F_VM_00_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_00_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_00_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_F_VM_00_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_F_VM_00_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_00_0_VM4_SHIFT)
#define GPIO_F_VM_00_0_VM4_RANGE                        7:6
#define GPIO_F_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_F_VM_00_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_00_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_00_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_F_VM_00_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_F_VM_00_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_00_0_VM5_SHIFT)
#define GPIO_F_VM_00_0_VM5_RANGE                        9:8
#define GPIO_F_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_F_VM_00_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_00_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_00_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_F_VM_00_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_F_VM_00_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_00_0_VM6_SHIFT)
#define GPIO_F_VM_00_0_VM6_RANGE                        11:10
#define GPIO_F_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_F_VM_00_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_00_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_00_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_F_VM_00_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_F_VM_00_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_00_0_VM7_SHIFT)
#define GPIO_F_VM_00_0_VM7_RANGE                        13:12
#define GPIO_F_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_F_VM_00_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_00_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_00_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_F_VM_00_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_F_VM_00_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_00_0_VM8_SHIFT)
#define GPIO_F_VM_00_0_VM8_RANGE                        15:14
#define GPIO_F_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_F_VM_00_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_00_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_00_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_F_SCR_00_0
#define GPIO_F_SCR_00_0                 _MK_ADDR_CONST(0x4184)
#define GPIO_F_SCR_00_0_SECURE                  0x0
#define GPIO_F_SCR_00_0_DUAL                    0x0
#define GPIO_F_SCR_00_0_SCR                     0
#define GPIO_F_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_F_SCR_00_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_F_SCR_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_F_SCR_00_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_F_SCR_00_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_F_SCR_00_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_F_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_F_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_F_SCR_00_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_00_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_F_SCR_00_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_F_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_F_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_F_SCR_00_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_00_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_F_SCR_00_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_F_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_F_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_F_SCR_00_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_00_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_F_SCR_00_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_F_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_F_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_F_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_F_SCR_00_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_F_SCR_00_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_00_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_F_SCR_00_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_PR7_SHIFT)
#define GPIO_F_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_F_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_00_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_F_SCR_00_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_PR6_SHIFT)
#define GPIO_F_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_F_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_00_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_F_SCR_00_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_PR5_SHIFT)
#define GPIO_F_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_F_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_00_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_F_SCR_00_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_PR4_SHIFT)
#define GPIO_F_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_F_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_00_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_F_SCR_00_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_PR3_SHIFT)
#define GPIO_F_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_F_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_00_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_F_SCR_00_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_PR2_SHIFT)
#define GPIO_F_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_F_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_00_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_F_SCR_00_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_PR1_SHIFT)
#define GPIO_F_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_F_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_00_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_F_SCR_00_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_PR0_SHIFT)
#define GPIO_F_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_F_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_00_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_F_SCR_00_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G7W_SHIFT)
#define GPIO_F_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_F_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_00_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_F_SCR_00_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G6W_SHIFT)
#define GPIO_F_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_F_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_00_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_F_SCR_00_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G5W_SHIFT)
#define GPIO_F_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_F_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_00_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_F_SCR_00_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G4W_SHIFT)
#define GPIO_F_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_F_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_00_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_F_SCR_00_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G3W_SHIFT)
#define GPIO_F_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_F_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_00_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_F_SCR_00_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G2W_SHIFT)
#define GPIO_F_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_F_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_00_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_F_SCR_00_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G1W_SHIFT)
#define GPIO_F_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_F_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_00_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_F_SCR_00_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G0W_SHIFT)
#define GPIO_F_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_F_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_00_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_F_SCR_00_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G7R_SHIFT)
#define GPIO_F_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_F_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_00_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_F_SCR_00_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G6R_SHIFT)
#define GPIO_F_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_F_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_00_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_F_SCR_00_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G5R_SHIFT)
#define GPIO_F_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_F_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_00_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_F_SCR_00_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G4R_SHIFT)
#define GPIO_F_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_F_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_00_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_F_SCR_00_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G3R_SHIFT)
#define GPIO_F_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_F_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_00_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_F_SCR_00_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G2R_SHIFT)
#define GPIO_F_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_F_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_00_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_F_SCR_00_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G1R_SHIFT)
#define GPIO_F_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_F_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_00_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_F_SCR_00_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G0R_SHIFT)
#define GPIO_F_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_F_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_F_VM_01_0
#define GPIO_F_VM_01_0                  _MK_ADDR_CONST(0x4188)
#define GPIO_F_VM_01_0_SECURE                   0x0
#define GPIO_F_VM_01_0_DUAL                     0x0
#define GPIO_F_VM_01_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_F_VM_01_0_WORD_COUNT                       0x1
#define GPIO_F_VM_01_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_F_VM_01_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_F_VM_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_F_VM_01_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_F_VM_01_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_F_VM_01_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_01_0_VM1_SHIFT)
#define GPIO_F_VM_01_0_VM1_RANGE                        1:0
#define GPIO_F_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_F_VM_01_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_01_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_01_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_F_VM_01_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_F_VM_01_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_01_0_VM2_SHIFT)
#define GPIO_F_VM_01_0_VM2_RANGE                        3:2
#define GPIO_F_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_F_VM_01_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_01_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_01_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_F_VM_01_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_F_VM_01_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_01_0_VM3_SHIFT)
#define GPIO_F_VM_01_0_VM3_RANGE                        5:4
#define GPIO_F_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_F_VM_01_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_01_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_01_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_F_VM_01_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_F_VM_01_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_01_0_VM4_SHIFT)
#define GPIO_F_VM_01_0_VM4_RANGE                        7:6
#define GPIO_F_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_F_VM_01_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_01_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_01_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_F_VM_01_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_F_VM_01_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_01_0_VM5_SHIFT)
#define GPIO_F_VM_01_0_VM5_RANGE                        9:8
#define GPIO_F_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_F_VM_01_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_01_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_01_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_F_VM_01_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_F_VM_01_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_01_0_VM6_SHIFT)
#define GPIO_F_VM_01_0_VM6_RANGE                        11:10
#define GPIO_F_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_F_VM_01_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_01_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_01_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_F_VM_01_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_F_VM_01_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_01_0_VM7_SHIFT)
#define GPIO_F_VM_01_0_VM7_RANGE                        13:12
#define GPIO_F_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_F_VM_01_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_01_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_01_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_F_VM_01_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_F_VM_01_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_01_0_VM8_SHIFT)
#define GPIO_F_VM_01_0_VM8_RANGE                        15:14
#define GPIO_F_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_F_VM_01_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_01_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_01_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_F_SCR_01_0
#define GPIO_F_SCR_01_0                 _MK_ADDR_CONST(0x418c)
#define GPIO_F_SCR_01_0_SECURE                  0x0
#define GPIO_F_SCR_01_0_DUAL                    0x0
#define GPIO_F_SCR_01_0_SCR                     0
#define GPIO_F_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_F_SCR_01_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_F_SCR_01_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_F_SCR_01_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_F_SCR_01_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_F_SCR_01_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_F_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_F_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_F_SCR_01_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_01_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_F_SCR_01_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_F_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_F_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_F_SCR_01_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_01_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_F_SCR_01_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_F_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_F_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_F_SCR_01_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_01_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_F_SCR_01_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_F_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_F_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_F_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_F_SCR_01_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_F_SCR_01_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_01_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_F_SCR_01_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_PR7_SHIFT)
#define GPIO_F_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_F_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_01_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_F_SCR_01_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_PR6_SHIFT)
#define GPIO_F_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_F_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_01_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_F_SCR_01_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_PR5_SHIFT)
#define GPIO_F_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_F_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_01_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_F_SCR_01_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_PR4_SHIFT)
#define GPIO_F_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_F_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_01_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_F_SCR_01_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_PR3_SHIFT)
#define GPIO_F_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_F_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_01_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_F_SCR_01_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_PR2_SHIFT)
#define GPIO_F_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_F_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_01_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_F_SCR_01_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_PR1_SHIFT)
#define GPIO_F_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_F_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_01_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_F_SCR_01_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_PR0_SHIFT)
#define GPIO_F_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_F_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_01_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_F_SCR_01_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G7W_SHIFT)
#define GPIO_F_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_F_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_01_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_F_SCR_01_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G6W_SHIFT)
#define GPIO_F_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_F_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_01_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_F_SCR_01_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G5W_SHIFT)
#define GPIO_F_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_F_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_01_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_F_SCR_01_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G4W_SHIFT)
#define GPIO_F_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_F_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_01_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_F_SCR_01_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G3W_SHIFT)
#define GPIO_F_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_F_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_01_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_F_SCR_01_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G2W_SHIFT)
#define GPIO_F_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_F_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_01_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_F_SCR_01_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G1W_SHIFT)
#define GPIO_F_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_F_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_01_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_F_SCR_01_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G0W_SHIFT)
#define GPIO_F_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_F_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_01_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_F_SCR_01_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G7R_SHIFT)
#define GPIO_F_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_F_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_01_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_F_SCR_01_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G6R_SHIFT)
#define GPIO_F_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_F_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_01_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_F_SCR_01_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G5R_SHIFT)
#define GPIO_F_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_F_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_01_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_F_SCR_01_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G4R_SHIFT)
#define GPIO_F_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_F_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_01_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_F_SCR_01_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G3R_SHIFT)
#define GPIO_F_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_F_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_01_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_F_SCR_01_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G2R_SHIFT)
#define GPIO_F_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_F_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_01_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_F_SCR_01_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G1R_SHIFT)
#define GPIO_F_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_F_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_01_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_F_SCR_01_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G0R_SHIFT)
#define GPIO_F_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_F_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_F_VM_02_0
#define GPIO_F_VM_02_0                  _MK_ADDR_CONST(0x4190)
#define GPIO_F_VM_02_0_SECURE                   0x0
#define GPIO_F_VM_02_0_DUAL                     0x0
#define GPIO_F_VM_02_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_F_VM_02_0_WORD_COUNT                       0x1
#define GPIO_F_VM_02_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_F_VM_02_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_F_VM_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_F_VM_02_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_F_VM_02_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_F_VM_02_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_02_0_VM1_SHIFT)
#define GPIO_F_VM_02_0_VM1_RANGE                        1:0
#define GPIO_F_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_F_VM_02_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_02_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_02_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_F_VM_02_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_F_VM_02_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_02_0_VM2_SHIFT)
#define GPIO_F_VM_02_0_VM2_RANGE                        3:2
#define GPIO_F_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_F_VM_02_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_02_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_02_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_F_VM_02_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_F_VM_02_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_02_0_VM3_SHIFT)
#define GPIO_F_VM_02_0_VM3_RANGE                        5:4
#define GPIO_F_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_F_VM_02_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_02_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_02_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_F_VM_02_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_F_VM_02_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_02_0_VM4_SHIFT)
#define GPIO_F_VM_02_0_VM4_RANGE                        7:6
#define GPIO_F_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_F_VM_02_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_02_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_02_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_F_VM_02_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_F_VM_02_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_02_0_VM5_SHIFT)
#define GPIO_F_VM_02_0_VM5_RANGE                        9:8
#define GPIO_F_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_F_VM_02_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_02_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_02_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_F_VM_02_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_F_VM_02_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_02_0_VM6_SHIFT)
#define GPIO_F_VM_02_0_VM6_RANGE                        11:10
#define GPIO_F_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_F_VM_02_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_02_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_02_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_F_VM_02_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_F_VM_02_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_02_0_VM7_SHIFT)
#define GPIO_F_VM_02_0_VM7_RANGE                        13:12
#define GPIO_F_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_F_VM_02_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_02_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_02_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_F_VM_02_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_F_VM_02_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_02_0_VM8_SHIFT)
#define GPIO_F_VM_02_0_VM8_RANGE                        15:14
#define GPIO_F_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_F_VM_02_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_02_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_02_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_F_SCR_02_0
#define GPIO_F_SCR_02_0                 _MK_ADDR_CONST(0x4194)
#define GPIO_F_SCR_02_0_SECURE                  0x0
#define GPIO_F_SCR_02_0_DUAL                    0x0
#define GPIO_F_SCR_02_0_SCR                     0
#define GPIO_F_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_F_SCR_02_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_F_SCR_02_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_F_SCR_02_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_F_SCR_02_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_F_SCR_02_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_F_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_F_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_F_SCR_02_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_02_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_F_SCR_02_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_F_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_F_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_F_SCR_02_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_02_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_F_SCR_02_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_F_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_F_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_F_SCR_02_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_02_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_F_SCR_02_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_F_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_F_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_F_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_F_SCR_02_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_F_SCR_02_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_02_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_F_SCR_02_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_PR7_SHIFT)
#define GPIO_F_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_F_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_02_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_F_SCR_02_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_PR6_SHIFT)
#define GPIO_F_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_F_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_02_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_F_SCR_02_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_PR5_SHIFT)
#define GPIO_F_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_F_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_02_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_F_SCR_02_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_PR4_SHIFT)
#define GPIO_F_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_F_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_02_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_F_SCR_02_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_PR3_SHIFT)
#define GPIO_F_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_F_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_02_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_F_SCR_02_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_PR2_SHIFT)
#define GPIO_F_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_F_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_02_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_F_SCR_02_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_PR1_SHIFT)
#define GPIO_F_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_F_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_02_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_F_SCR_02_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_PR0_SHIFT)
#define GPIO_F_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_F_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_02_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_F_SCR_02_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G7W_SHIFT)
#define GPIO_F_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_F_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_02_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_F_SCR_02_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G6W_SHIFT)
#define GPIO_F_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_F_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_02_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_F_SCR_02_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G5W_SHIFT)
#define GPIO_F_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_F_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_02_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_F_SCR_02_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G4W_SHIFT)
#define GPIO_F_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_F_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_02_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_F_SCR_02_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G3W_SHIFT)
#define GPIO_F_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_F_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_02_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_F_SCR_02_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G2W_SHIFT)
#define GPIO_F_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_F_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_02_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_F_SCR_02_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G1W_SHIFT)
#define GPIO_F_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_F_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_02_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_F_SCR_02_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G0W_SHIFT)
#define GPIO_F_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_F_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_02_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_F_SCR_02_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G7R_SHIFT)
#define GPIO_F_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_F_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_02_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_F_SCR_02_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G6R_SHIFT)
#define GPIO_F_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_F_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_02_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_F_SCR_02_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G5R_SHIFT)
#define GPIO_F_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_F_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_02_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_F_SCR_02_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G4R_SHIFT)
#define GPIO_F_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_F_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_02_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_F_SCR_02_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G3R_SHIFT)
#define GPIO_F_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_F_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_02_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_F_SCR_02_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G2R_SHIFT)
#define GPIO_F_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_F_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_02_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_F_SCR_02_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G1R_SHIFT)
#define GPIO_F_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_F_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_02_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_F_SCR_02_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G0R_SHIFT)
#define GPIO_F_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_F_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_F_VM_03_0
#define GPIO_F_VM_03_0                  _MK_ADDR_CONST(0x4198)
#define GPIO_F_VM_03_0_SECURE                   0x0
#define GPIO_F_VM_03_0_DUAL                     0x0
#define GPIO_F_VM_03_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_F_VM_03_0_WORD_COUNT                       0x1
#define GPIO_F_VM_03_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_F_VM_03_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_F_VM_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_F_VM_03_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_F_VM_03_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_F_VM_03_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_03_0_VM1_SHIFT)
#define GPIO_F_VM_03_0_VM1_RANGE                        1:0
#define GPIO_F_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_F_VM_03_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_03_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_03_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_F_VM_03_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_F_VM_03_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_03_0_VM2_SHIFT)
#define GPIO_F_VM_03_0_VM2_RANGE                        3:2
#define GPIO_F_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_F_VM_03_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_03_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_03_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_F_VM_03_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_F_VM_03_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_03_0_VM3_SHIFT)
#define GPIO_F_VM_03_0_VM3_RANGE                        5:4
#define GPIO_F_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_F_VM_03_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_03_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_03_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_F_VM_03_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_F_VM_03_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_03_0_VM4_SHIFT)
#define GPIO_F_VM_03_0_VM4_RANGE                        7:6
#define GPIO_F_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_F_VM_03_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_03_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_03_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_F_VM_03_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_F_VM_03_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_03_0_VM5_SHIFT)
#define GPIO_F_VM_03_0_VM5_RANGE                        9:8
#define GPIO_F_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_F_VM_03_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_03_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_03_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_F_VM_03_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_F_VM_03_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_03_0_VM6_SHIFT)
#define GPIO_F_VM_03_0_VM6_RANGE                        11:10
#define GPIO_F_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_F_VM_03_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_03_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_03_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_F_VM_03_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_F_VM_03_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_03_0_VM7_SHIFT)
#define GPIO_F_VM_03_0_VM7_RANGE                        13:12
#define GPIO_F_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_F_VM_03_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_03_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_03_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_F_VM_03_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_F_VM_03_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_03_0_VM8_SHIFT)
#define GPIO_F_VM_03_0_VM8_RANGE                        15:14
#define GPIO_F_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_F_VM_03_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_03_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_03_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_F_SCR_03_0
#define GPIO_F_SCR_03_0                 _MK_ADDR_CONST(0x419c)
#define GPIO_F_SCR_03_0_SECURE                  0x0
#define GPIO_F_SCR_03_0_DUAL                    0x0
#define GPIO_F_SCR_03_0_SCR                     0
#define GPIO_F_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_F_SCR_03_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_F_SCR_03_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_F_SCR_03_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_F_SCR_03_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_F_SCR_03_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_F_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_F_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_F_SCR_03_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_03_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_F_SCR_03_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_F_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_F_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_F_SCR_03_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_03_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_F_SCR_03_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_F_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_F_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_F_SCR_03_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_03_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_F_SCR_03_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_F_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_F_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_F_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_F_SCR_03_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_F_SCR_03_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_03_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_F_SCR_03_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_PR7_SHIFT)
#define GPIO_F_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_F_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_03_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_F_SCR_03_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_PR6_SHIFT)
#define GPIO_F_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_F_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_03_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_F_SCR_03_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_PR5_SHIFT)
#define GPIO_F_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_F_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_03_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_F_SCR_03_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_PR4_SHIFT)
#define GPIO_F_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_F_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_03_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_F_SCR_03_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_PR3_SHIFT)
#define GPIO_F_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_F_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_03_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_F_SCR_03_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_PR2_SHIFT)
#define GPIO_F_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_F_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_03_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_F_SCR_03_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_PR1_SHIFT)
#define GPIO_F_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_F_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_03_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_F_SCR_03_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_PR0_SHIFT)
#define GPIO_F_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_F_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_03_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_F_SCR_03_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G7W_SHIFT)
#define GPIO_F_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_F_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_03_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_F_SCR_03_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G6W_SHIFT)
#define GPIO_F_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_F_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_03_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_F_SCR_03_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G5W_SHIFT)
#define GPIO_F_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_F_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_03_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_F_SCR_03_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G4W_SHIFT)
#define GPIO_F_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_F_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_03_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_F_SCR_03_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G3W_SHIFT)
#define GPIO_F_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_F_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_03_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_F_SCR_03_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G2W_SHIFT)
#define GPIO_F_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_F_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_03_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_F_SCR_03_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G1W_SHIFT)
#define GPIO_F_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_F_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_03_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_F_SCR_03_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G0W_SHIFT)
#define GPIO_F_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_F_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_03_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_F_SCR_03_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G7R_SHIFT)
#define GPIO_F_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_F_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_03_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_F_SCR_03_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G6R_SHIFT)
#define GPIO_F_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_F_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_03_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_F_SCR_03_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G5R_SHIFT)
#define GPIO_F_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_F_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_03_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_F_SCR_03_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G4R_SHIFT)
#define GPIO_F_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_F_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_03_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_F_SCR_03_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G3R_SHIFT)
#define GPIO_F_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_F_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_03_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_F_SCR_03_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G2R_SHIFT)
#define GPIO_F_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_F_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_03_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_F_SCR_03_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G1R_SHIFT)
#define GPIO_F_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_F_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_03_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_F_SCR_03_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G0R_SHIFT)
#define GPIO_F_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_F_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_F_VM_04_0
#define GPIO_F_VM_04_0                  _MK_ADDR_CONST(0x41a0)
#define GPIO_F_VM_04_0_SECURE                   0x0
#define GPIO_F_VM_04_0_DUAL                     0x0
#define GPIO_F_VM_04_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_F_VM_04_0_WORD_COUNT                       0x1
#define GPIO_F_VM_04_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_F_VM_04_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_F_VM_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_F_VM_04_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_F_VM_04_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_F_VM_04_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_04_0_VM1_SHIFT)
#define GPIO_F_VM_04_0_VM1_RANGE                        1:0
#define GPIO_F_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_F_VM_04_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_04_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_04_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_F_VM_04_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_F_VM_04_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_04_0_VM2_SHIFT)
#define GPIO_F_VM_04_0_VM2_RANGE                        3:2
#define GPIO_F_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_F_VM_04_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_04_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_04_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_F_VM_04_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_F_VM_04_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_04_0_VM3_SHIFT)
#define GPIO_F_VM_04_0_VM3_RANGE                        5:4
#define GPIO_F_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_F_VM_04_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_04_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_04_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_F_VM_04_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_F_VM_04_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_04_0_VM4_SHIFT)
#define GPIO_F_VM_04_0_VM4_RANGE                        7:6
#define GPIO_F_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_F_VM_04_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_04_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_04_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_F_VM_04_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_F_VM_04_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_04_0_VM5_SHIFT)
#define GPIO_F_VM_04_0_VM5_RANGE                        9:8
#define GPIO_F_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_F_VM_04_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_04_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_04_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_F_VM_04_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_F_VM_04_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_04_0_VM6_SHIFT)
#define GPIO_F_VM_04_0_VM6_RANGE                        11:10
#define GPIO_F_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_F_VM_04_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_04_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_04_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_F_VM_04_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_F_VM_04_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_04_0_VM7_SHIFT)
#define GPIO_F_VM_04_0_VM7_RANGE                        13:12
#define GPIO_F_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_F_VM_04_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_04_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_04_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_F_VM_04_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_F_VM_04_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_04_0_VM8_SHIFT)
#define GPIO_F_VM_04_0_VM8_RANGE                        15:14
#define GPIO_F_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_F_VM_04_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_04_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_04_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_F_SCR_04_0
#define GPIO_F_SCR_04_0                 _MK_ADDR_CONST(0x41a4)
#define GPIO_F_SCR_04_0_SECURE                  0x0
#define GPIO_F_SCR_04_0_DUAL                    0x0
#define GPIO_F_SCR_04_0_SCR                     0
#define GPIO_F_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_F_SCR_04_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_F_SCR_04_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_F_SCR_04_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_F_SCR_04_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_F_SCR_04_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_F_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_F_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_F_SCR_04_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_04_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_F_SCR_04_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_F_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_F_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_F_SCR_04_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_04_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_F_SCR_04_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_F_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_F_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_F_SCR_04_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_04_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_F_SCR_04_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_F_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_F_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_F_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_F_SCR_04_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_F_SCR_04_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_04_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_F_SCR_04_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_PR7_SHIFT)
#define GPIO_F_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_F_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_04_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_F_SCR_04_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_PR6_SHIFT)
#define GPIO_F_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_F_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_04_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_F_SCR_04_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_PR5_SHIFT)
#define GPIO_F_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_F_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_04_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_F_SCR_04_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_PR4_SHIFT)
#define GPIO_F_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_F_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_04_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_F_SCR_04_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_PR3_SHIFT)
#define GPIO_F_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_F_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_04_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_F_SCR_04_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_PR2_SHIFT)
#define GPIO_F_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_F_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_04_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_F_SCR_04_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_PR1_SHIFT)
#define GPIO_F_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_F_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_04_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_F_SCR_04_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_PR0_SHIFT)
#define GPIO_F_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_F_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_04_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_F_SCR_04_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G7W_SHIFT)
#define GPIO_F_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_F_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_04_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_F_SCR_04_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G6W_SHIFT)
#define GPIO_F_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_F_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_04_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_F_SCR_04_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G5W_SHIFT)
#define GPIO_F_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_F_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_04_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_F_SCR_04_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G4W_SHIFT)
#define GPIO_F_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_F_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_04_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_F_SCR_04_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G3W_SHIFT)
#define GPIO_F_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_F_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_04_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_F_SCR_04_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G2W_SHIFT)
#define GPIO_F_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_F_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_04_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_F_SCR_04_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G1W_SHIFT)
#define GPIO_F_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_F_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_04_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_F_SCR_04_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G0W_SHIFT)
#define GPIO_F_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_F_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_04_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_F_SCR_04_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G7R_SHIFT)
#define GPIO_F_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_F_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_04_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_F_SCR_04_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G6R_SHIFT)
#define GPIO_F_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_F_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_04_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_F_SCR_04_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G5R_SHIFT)
#define GPIO_F_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_F_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_04_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_F_SCR_04_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G4R_SHIFT)
#define GPIO_F_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_F_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_04_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_F_SCR_04_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G3R_SHIFT)
#define GPIO_F_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_F_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_04_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_F_SCR_04_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G2R_SHIFT)
#define GPIO_F_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_F_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_04_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_F_SCR_04_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G1R_SHIFT)
#define GPIO_F_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_F_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_04_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_F_SCR_04_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G0R_SHIFT)
#define GPIO_F_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_F_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_F_VM_05_0
#define GPIO_F_VM_05_0                  _MK_ADDR_CONST(0x41a8)
#define GPIO_F_VM_05_0_SECURE                   0x0
#define GPIO_F_VM_05_0_DUAL                     0x0
#define GPIO_F_VM_05_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_F_VM_05_0_WORD_COUNT                       0x1
#define GPIO_F_VM_05_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_F_VM_05_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_F_VM_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_F_VM_05_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_F_VM_05_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_F_VM_05_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_05_0_VM1_SHIFT)
#define GPIO_F_VM_05_0_VM1_RANGE                        1:0
#define GPIO_F_VM_05_0_VM1_WOFFSET                      0x0
#define GPIO_F_VM_05_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_05_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_05_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_F_VM_05_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_F_VM_05_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_05_0_VM2_SHIFT)
#define GPIO_F_VM_05_0_VM2_RANGE                        3:2
#define GPIO_F_VM_05_0_VM2_WOFFSET                      0x0
#define GPIO_F_VM_05_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_05_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_05_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_F_VM_05_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_F_VM_05_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_05_0_VM3_SHIFT)
#define GPIO_F_VM_05_0_VM3_RANGE                        5:4
#define GPIO_F_VM_05_0_VM3_WOFFSET                      0x0
#define GPIO_F_VM_05_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_05_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_05_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_F_VM_05_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_F_VM_05_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_05_0_VM4_SHIFT)
#define GPIO_F_VM_05_0_VM4_RANGE                        7:6
#define GPIO_F_VM_05_0_VM4_WOFFSET                      0x0
#define GPIO_F_VM_05_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_05_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_05_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_F_VM_05_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_F_VM_05_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_05_0_VM5_SHIFT)
#define GPIO_F_VM_05_0_VM5_RANGE                        9:8
#define GPIO_F_VM_05_0_VM5_WOFFSET                      0x0
#define GPIO_F_VM_05_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_05_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_05_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_F_VM_05_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_F_VM_05_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_05_0_VM6_SHIFT)
#define GPIO_F_VM_05_0_VM6_RANGE                        11:10
#define GPIO_F_VM_05_0_VM6_WOFFSET                      0x0
#define GPIO_F_VM_05_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_05_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_05_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_F_VM_05_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_F_VM_05_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_05_0_VM7_SHIFT)
#define GPIO_F_VM_05_0_VM7_RANGE                        13:12
#define GPIO_F_VM_05_0_VM7_WOFFSET                      0x0
#define GPIO_F_VM_05_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_05_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_05_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_F_VM_05_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_F_VM_05_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_F_VM_05_0_VM8_SHIFT)
#define GPIO_F_VM_05_0_VM8_RANGE                        15:14
#define GPIO_F_VM_05_0_VM8_WOFFSET                      0x0
#define GPIO_F_VM_05_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_F_VM_05_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_F_VM_05_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_F_SCR_05_0
#define GPIO_F_SCR_05_0                 _MK_ADDR_CONST(0x41ac)
#define GPIO_F_SCR_05_0_SECURE                  0x0
#define GPIO_F_SCR_05_0_DUAL                    0x0
#define GPIO_F_SCR_05_0_SCR                     0
#define GPIO_F_SCR_05_0_WORD_COUNT                      0x1
#define GPIO_F_SCR_05_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_F_SCR_05_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_F_SCR_05_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_F_SCR_05_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_F_SCR_05_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_F_SCR_05_0_SEC_LCK_RANGE                   29:29
#define GPIO_F_SCR_05_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_F_SCR_05_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_05_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_F_SCR_05_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_F_SCR_05_0_SEC_WEN_RANGE                   28:28
#define GPIO_F_SCR_05_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_F_SCR_05_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_05_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_F_SCR_05_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_F_SCR_05_0_SEC_REN_RANGE                   27:27
#define GPIO_F_SCR_05_0_SEC_REN_WOFFSET                 0x0
#define GPIO_F_SCR_05_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_05_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_F_SCR_05_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_F_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_F_SCR_05_0_SEC_OWNER_RANGE                 26:24
#define GPIO_F_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_F_SCR_05_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_F_SCR_05_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_05_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_F_SCR_05_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_PR7_SHIFT)
#define GPIO_F_SCR_05_0_PR7_RANGE                       23:23
#define GPIO_F_SCR_05_0_PR7_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_05_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_F_SCR_05_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_PR6_SHIFT)
#define GPIO_F_SCR_05_0_PR6_RANGE                       22:22
#define GPIO_F_SCR_05_0_PR6_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_05_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_F_SCR_05_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_PR5_SHIFT)
#define GPIO_F_SCR_05_0_PR5_RANGE                       21:21
#define GPIO_F_SCR_05_0_PR5_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_05_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_F_SCR_05_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_PR4_SHIFT)
#define GPIO_F_SCR_05_0_PR4_RANGE                       20:20
#define GPIO_F_SCR_05_0_PR4_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_05_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_F_SCR_05_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_PR3_SHIFT)
#define GPIO_F_SCR_05_0_PR3_RANGE                       19:19
#define GPIO_F_SCR_05_0_PR3_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_05_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_F_SCR_05_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_PR2_SHIFT)
#define GPIO_F_SCR_05_0_PR2_RANGE                       18:18
#define GPIO_F_SCR_05_0_PR2_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_05_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_F_SCR_05_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_PR1_SHIFT)
#define GPIO_F_SCR_05_0_PR1_RANGE                       17:17
#define GPIO_F_SCR_05_0_PR1_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_05_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_F_SCR_05_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_PR0_SHIFT)
#define GPIO_F_SCR_05_0_PR0_RANGE                       16:16
#define GPIO_F_SCR_05_0_PR0_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_05_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_F_SCR_05_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G7W_SHIFT)
#define GPIO_F_SCR_05_0_G7W_RANGE                       15:15
#define GPIO_F_SCR_05_0_G7W_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_05_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_F_SCR_05_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G6W_SHIFT)
#define GPIO_F_SCR_05_0_G6W_RANGE                       14:14
#define GPIO_F_SCR_05_0_G6W_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_05_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_F_SCR_05_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G5W_SHIFT)
#define GPIO_F_SCR_05_0_G5W_RANGE                       13:13
#define GPIO_F_SCR_05_0_G5W_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_05_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_F_SCR_05_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G4W_SHIFT)
#define GPIO_F_SCR_05_0_G4W_RANGE                       12:12
#define GPIO_F_SCR_05_0_G4W_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_05_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_F_SCR_05_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G3W_SHIFT)
#define GPIO_F_SCR_05_0_G3W_RANGE                       11:11
#define GPIO_F_SCR_05_0_G3W_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_05_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_F_SCR_05_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G2W_SHIFT)
#define GPIO_F_SCR_05_0_G2W_RANGE                       10:10
#define GPIO_F_SCR_05_0_G2W_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_05_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_F_SCR_05_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G1W_SHIFT)
#define GPIO_F_SCR_05_0_G1W_RANGE                       9:9
#define GPIO_F_SCR_05_0_G1W_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_05_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_F_SCR_05_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G0W_SHIFT)
#define GPIO_F_SCR_05_0_G0W_RANGE                       8:8
#define GPIO_F_SCR_05_0_G0W_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_05_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_F_SCR_05_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G7R_SHIFT)
#define GPIO_F_SCR_05_0_G7R_RANGE                       7:7
#define GPIO_F_SCR_05_0_G7R_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_05_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_F_SCR_05_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G6R_SHIFT)
#define GPIO_F_SCR_05_0_G6R_RANGE                       6:6
#define GPIO_F_SCR_05_0_G6R_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_05_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_F_SCR_05_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G5R_SHIFT)
#define GPIO_F_SCR_05_0_G5R_RANGE                       5:5
#define GPIO_F_SCR_05_0_G5R_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_05_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_F_SCR_05_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G4R_SHIFT)
#define GPIO_F_SCR_05_0_G4R_RANGE                       4:4
#define GPIO_F_SCR_05_0_G4R_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_05_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_F_SCR_05_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G3R_SHIFT)
#define GPIO_F_SCR_05_0_G3R_RANGE                       3:3
#define GPIO_F_SCR_05_0_G3R_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_05_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_F_SCR_05_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G2R_SHIFT)
#define GPIO_F_SCR_05_0_G2R_RANGE                       2:2
#define GPIO_F_SCR_05_0_G2R_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_05_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_F_SCR_05_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G1R_SHIFT)
#define GPIO_F_SCR_05_0_G1R_RANGE                       1:1
#define GPIO_F_SCR_05_0_G1R_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_F_SCR_05_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_F_SCR_05_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G0R_SHIFT)
#define GPIO_F_SCR_05_0_G0R_RANGE                       0:0
#define GPIO_F_SCR_05_0_G0R_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Reserved address 0x41b0

// Reserved address 0x41b4

// Reserved address 0x41b8

// Reserved address 0x41bc

// Register GPIO_B_VM_00_0
#define GPIO_B_VM_00_0                  _MK_ADDR_CONST(0x41c0)
#define GPIO_B_VM_00_0_SECURE                   0x0
#define GPIO_B_VM_00_0_DUAL                     0x0
#define GPIO_B_VM_00_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_B_VM_00_0_WORD_COUNT                       0x1
#define GPIO_B_VM_00_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_B_VM_00_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_B_VM_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_B_VM_00_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_B_VM_00_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_B_VM_00_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_00_0_VM1_SHIFT)
#define GPIO_B_VM_00_0_VM1_RANGE                        1:0
#define GPIO_B_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_B_VM_00_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_00_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_00_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_B_VM_00_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_B_VM_00_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_00_0_VM2_SHIFT)
#define GPIO_B_VM_00_0_VM2_RANGE                        3:2
#define GPIO_B_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_B_VM_00_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_00_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_00_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_B_VM_00_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_B_VM_00_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_00_0_VM3_SHIFT)
#define GPIO_B_VM_00_0_VM3_RANGE                        5:4
#define GPIO_B_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_B_VM_00_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_00_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_00_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_B_VM_00_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_B_VM_00_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_00_0_VM4_SHIFT)
#define GPIO_B_VM_00_0_VM4_RANGE                        7:6
#define GPIO_B_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_B_VM_00_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_00_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_00_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_B_VM_00_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_B_VM_00_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_00_0_VM5_SHIFT)
#define GPIO_B_VM_00_0_VM5_RANGE                        9:8
#define GPIO_B_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_B_VM_00_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_00_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_00_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_B_VM_00_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_B_VM_00_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_00_0_VM6_SHIFT)
#define GPIO_B_VM_00_0_VM6_RANGE                        11:10
#define GPIO_B_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_B_VM_00_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_00_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_00_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_B_VM_00_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_B_VM_00_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_00_0_VM7_SHIFT)
#define GPIO_B_VM_00_0_VM7_RANGE                        13:12
#define GPIO_B_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_B_VM_00_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_00_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_00_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_B_VM_00_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_B_VM_00_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_00_0_VM8_SHIFT)
#define GPIO_B_VM_00_0_VM8_RANGE                        15:14
#define GPIO_B_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_B_VM_00_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_00_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_00_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_B_SCR_00_0
#define GPIO_B_SCR_00_0                 _MK_ADDR_CONST(0x41c4)
#define GPIO_B_SCR_00_0_SECURE                  0x0
#define GPIO_B_SCR_00_0_DUAL                    0x0
#define GPIO_B_SCR_00_0_SCR                     0
#define GPIO_B_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_B_SCR_00_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_B_SCR_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_B_SCR_00_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_B_SCR_00_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_B_SCR_00_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_B_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_B_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_B_SCR_00_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_B_SCR_00_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_B_SCR_00_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_B_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_B_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_B_SCR_00_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_B_SCR_00_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_B_SCR_00_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_B_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_B_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_B_SCR_00_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_B_SCR_00_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_B_SCR_00_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_B_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_B_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_B_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_B_SCR_00_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_B_SCR_00_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_B_SCR_00_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_B_SCR_00_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_PR7_SHIFT)
#define GPIO_B_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_B_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_B_SCR_00_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_B_SCR_00_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_PR6_SHIFT)
#define GPIO_B_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_B_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_B_SCR_00_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_B_SCR_00_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_PR5_SHIFT)
#define GPIO_B_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_B_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_B_SCR_00_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_B_SCR_00_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_PR4_SHIFT)
#define GPIO_B_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_B_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_B_SCR_00_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_B_SCR_00_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_PR3_SHIFT)
#define GPIO_B_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_B_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_B_SCR_00_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_B_SCR_00_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_PR2_SHIFT)
#define GPIO_B_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_B_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_B_SCR_00_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_B_SCR_00_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_PR1_SHIFT)
#define GPIO_B_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_B_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_B_SCR_00_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_B_SCR_00_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_PR0_SHIFT)
#define GPIO_B_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_B_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_B_SCR_00_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_B_SCR_00_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G7W_SHIFT)
#define GPIO_B_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_B_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_B_SCR_00_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_B_SCR_00_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G6W_SHIFT)
#define GPIO_B_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_B_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_B_SCR_00_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_B_SCR_00_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G5W_SHIFT)
#define GPIO_B_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_B_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_B_SCR_00_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_B_SCR_00_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G4W_SHIFT)
#define GPIO_B_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_B_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_B_SCR_00_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_B_SCR_00_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G3W_SHIFT)
#define GPIO_B_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_B_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_B_SCR_00_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_B_SCR_00_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G2W_SHIFT)
#define GPIO_B_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_B_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_B_SCR_00_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_B_SCR_00_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G1W_SHIFT)
#define GPIO_B_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_B_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_B_SCR_00_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_B_SCR_00_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G0W_SHIFT)
#define GPIO_B_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_B_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_B_SCR_00_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_B_SCR_00_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G7R_SHIFT)
#define GPIO_B_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_B_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_B_SCR_00_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_B_SCR_00_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G6R_SHIFT)
#define GPIO_B_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_B_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_B_SCR_00_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_B_SCR_00_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G5R_SHIFT)
#define GPIO_B_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_B_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_B_SCR_00_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_B_SCR_00_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G4R_SHIFT)
#define GPIO_B_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_B_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_B_SCR_00_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_B_SCR_00_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G3R_SHIFT)
#define GPIO_B_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_B_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_B_SCR_00_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_B_SCR_00_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G2R_SHIFT)
#define GPIO_B_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_B_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_B_SCR_00_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_B_SCR_00_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G1R_SHIFT)
#define GPIO_B_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_B_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_B_SCR_00_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_B_SCR_00_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G0R_SHIFT)
#define GPIO_B_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_B_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_B_VM_01_0
#define GPIO_B_VM_01_0                  _MK_ADDR_CONST(0x41c8)
#define GPIO_B_VM_01_0_SECURE                   0x0
#define GPIO_B_VM_01_0_DUAL                     0x0
#define GPIO_B_VM_01_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_B_VM_01_0_WORD_COUNT                       0x1
#define GPIO_B_VM_01_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_B_VM_01_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_B_VM_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_B_VM_01_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_B_VM_01_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_B_VM_01_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_B_VM_01_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_01_0_VM1_SHIFT)
#define GPIO_B_VM_01_0_VM1_RANGE                        1:0
#define GPIO_B_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_B_VM_01_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_01_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_01_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_01_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_B_VM_01_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_B_VM_01_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_B_VM_01_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_B_VM_01_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_01_0_VM2_SHIFT)
#define GPIO_B_VM_01_0_VM2_RANGE                        3:2
#define GPIO_B_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_B_VM_01_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_01_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_01_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_01_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_B_VM_01_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_B_VM_01_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_B_VM_01_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_B_VM_01_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_01_0_VM3_SHIFT)
#define GPIO_B_VM_01_0_VM3_RANGE                        5:4
#define GPIO_B_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_B_VM_01_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_01_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_01_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_01_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_B_VM_01_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_B_VM_01_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_B_VM_01_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_B_VM_01_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_01_0_VM4_SHIFT)
#define GPIO_B_VM_01_0_VM4_RANGE                        7:6
#define GPIO_B_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_B_VM_01_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_01_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_01_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_01_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_B_VM_01_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_B_VM_01_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_B_VM_01_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_B_VM_01_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_01_0_VM5_SHIFT)
#define GPIO_B_VM_01_0_VM5_RANGE                        9:8
#define GPIO_B_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_B_VM_01_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_01_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_01_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_01_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_B_VM_01_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_B_VM_01_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_B_VM_01_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_B_VM_01_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_01_0_VM6_SHIFT)
#define GPIO_B_VM_01_0_VM6_RANGE                        11:10
#define GPIO_B_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_B_VM_01_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_01_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_01_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_01_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_B_VM_01_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_B_VM_01_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_B_VM_01_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_B_VM_01_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_01_0_VM7_SHIFT)
#define GPIO_B_VM_01_0_VM7_RANGE                        13:12
#define GPIO_B_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_B_VM_01_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_01_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_01_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_01_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_B_VM_01_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_B_VM_01_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_B_VM_01_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_B_VM_01_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_VM_01_0_VM8_SHIFT)
#define GPIO_B_VM_01_0_VM8_RANGE                        15:14
#define GPIO_B_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_B_VM_01_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_B_VM_01_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_VM_01_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_VM_01_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_B_VM_01_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_B_VM_01_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_B_SCR_01_0
#define GPIO_B_SCR_01_0                 _MK_ADDR_CONST(0x41cc)
#define GPIO_B_SCR_01_0_SECURE                  0x0
#define GPIO_B_SCR_01_0_DUAL                    0x0
#define GPIO_B_SCR_01_0_SCR                     0
#define GPIO_B_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_B_SCR_01_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_B_SCR_01_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_B_SCR_01_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_B_SCR_01_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_B_SCR_01_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_B_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_B_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_B_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_B_SCR_01_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_01_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_B_SCR_01_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_B_SCR_01_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_B_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_B_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_B_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_B_SCR_01_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_01_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_B_SCR_01_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_B_SCR_01_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_B_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_B_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_B_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_B_SCR_01_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_01_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_B_SCR_01_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_B_SCR_01_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_B_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_B_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_B_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_B_SCR_01_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_B_SCR_01_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_B_SCR_01_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_B_SCR_01_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_01_0_PR7_SHIFT)
#define GPIO_B_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_B_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_B_SCR_01_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_01_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_B_SCR_01_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_B_SCR_01_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_01_0_PR6_SHIFT)
#define GPIO_B_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_B_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_B_SCR_01_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_01_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_B_SCR_01_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_B_SCR_01_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_01_0_PR5_SHIFT)
#define GPIO_B_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_B_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_B_SCR_01_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_01_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_B_SCR_01_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_B_SCR_01_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_01_0_PR4_SHIFT)
#define GPIO_B_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_B_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_B_SCR_01_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_01_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_B_SCR_01_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_B_SCR_01_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_01_0_PR3_SHIFT)
#define GPIO_B_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_B_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_B_SCR_01_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_01_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_B_SCR_01_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_B_SCR_01_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_01_0_PR2_SHIFT)
#define GPIO_B_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_B_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_B_SCR_01_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_01_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_B_SCR_01_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_B_SCR_01_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_01_0_PR1_SHIFT)
#define GPIO_B_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_B_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_B_SCR_01_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_01_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_B_SCR_01_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_B_SCR_01_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_01_0_PR0_SHIFT)
#define GPIO_B_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_B_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_B_SCR_01_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_01_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_B_SCR_01_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_B_SCR_01_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_01_0_G7W_SHIFT)
#define GPIO_B_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_B_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_B_SCR_01_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_01_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_B_SCR_01_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_B_SCR_01_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_01_0_G6W_SHIFT)
#define GPIO_B_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_B_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_B_SCR_01_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_01_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_B_SCR_01_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_B_SCR_01_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_01_0_G5W_SHIFT)
#define GPIO_B_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_B_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_B_SCR_01_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_01_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_B_SCR_01_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_B_SCR_01_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_01_0_G4W_SHIFT)
#define GPIO_B_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_B_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_B_SCR_01_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_01_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_B_SCR_01_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_B_SCR_01_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_01_0_G3W_SHIFT)
#define GPIO_B_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_B_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_B_SCR_01_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_01_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_B_SCR_01_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_B_SCR_01_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_01_0_G2W_SHIFT)
#define GPIO_B_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_B_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_B_SCR_01_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_01_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_B_SCR_01_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_B_SCR_01_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_01_0_G1W_SHIFT)
#define GPIO_B_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_B_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_B_SCR_01_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_01_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_B_SCR_01_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_B_SCR_01_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_01_0_G0W_SHIFT)
#define GPIO_B_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_B_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_B_SCR_01_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_01_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_B_SCR_01_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_B_SCR_01_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_01_0_G7R_SHIFT)
#define GPIO_B_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_B_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_B_SCR_01_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_01_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_B_SCR_01_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_B_SCR_01_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_01_0_G6R_SHIFT)
#define GPIO_B_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_B_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_B_SCR_01_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_01_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_B_SCR_01_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_B_SCR_01_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_01_0_G5R_SHIFT)
#define GPIO_B_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_B_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_B_SCR_01_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_01_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_B_SCR_01_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_B_SCR_01_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_01_0_G4R_SHIFT)
#define GPIO_B_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_B_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_B_SCR_01_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_01_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_B_SCR_01_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_B_SCR_01_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_01_0_G3R_SHIFT)
#define GPIO_B_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_B_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_B_SCR_01_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_01_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_B_SCR_01_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_B_SCR_01_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_01_0_G2R_SHIFT)
#define GPIO_B_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_B_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_B_SCR_01_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_01_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_B_SCR_01_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_B_SCR_01_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_01_0_G1R_SHIFT)
#define GPIO_B_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_B_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_B_SCR_01_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_01_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_B_SCR_01_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_B_SCR_01_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_SCR_01_0_G0R_SHIFT)
#define GPIO_B_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_B_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_B_SCR_01_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_SCR_01_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_B_SCR_01_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Reserved address 0x41d0

// Reserved address 0x41d4

// Reserved address 0x41d8

// Reserved address 0x41dc

// Reserved address 0x41e0

// Reserved address 0x41e4

// Reserved address 0x41e8

// Reserved address 0x41ec

// Reserved address 0x41f0

// Reserved address 0x41f4

// Reserved address 0x41f8

// Reserved address 0x41fc

// Register GPIO_CTL4_VM_SCR_0
#define GPIO_CTL4_VM_SCR_0                      _MK_ADDR_CONST(0x4800)
#define GPIO_CTL4_VM_SCR_0_SECURE                       0x0
#define GPIO_CTL4_VM_SCR_0_DUAL                         0x0
#define GPIO_CTL4_VM_SCR_0_SCR                  0
#define GPIO_CTL4_VM_SCR_0_WORD_COUNT                   0x1
#define GPIO_CTL4_VM_SCR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_RESET_MASK                   _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL4_VM_SCR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_READ_MASK                    _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL4_VM_SCR_0_WRITE_MASK                   _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL4_VM_SCR_0_SEC_LCK_SHIFT                        _MK_SHIFT_CONST(29)
#define GPIO_CTL4_VM_SCR_0_SEC_LCK_FIELD                        _MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_SEC_LCK_SHIFT)
#define GPIO_CTL4_VM_SCR_0_SEC_LCK_RANGE                        29:29
#define GPIO_CTL4_VM_SCR_0_SEC_LCK_WOFFSET                      0x0
#define GPIO_CTL4_VM_SCR_0_SEC_LCK_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_SEC_LCK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_SEC_LCK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_SEC_LCK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_SEC_LCK_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_CTL4_VM_SCR_0_SEC_WEN_SHIFT                        _MK_SHIFT_CONST(28)
#define GPIO_CTL4_VM_SCR_0_SEC_WEN_FIELD                        _MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_SEC_WEN_SHIFT)
#define GPIO_CTL4_VM_SCR_0_SEC_WEN_RANGE                        28:28
#define GPIO_CTL4_VM_SCR_0_SEC_WEN_WOFFSET                      0x0
#define GPIO_CTL4_VM_SCR_0_SEC_WEN_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_SEC_WEN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_SEC_WEN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_SEC_WEN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_SEC_WEN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_CTL4_VM_SCR_0_SEC_REN_SHIFT                        _MK_SHIFT_CONST(27)
#define GPIO_CTL4_VM_SCR_0_SEC_REN_FIELD                        _MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_SEC_REN_SHIFT)
#define GPIO_CTL4_VM_SCR_0_SEC_REN_RANGE                        27:27
#define GPIO_CTL4_VM_SCR_0_SEC_REN_WOFFSET                      0x0
#define GPIO_CTL4_VM_SCR_0_SEC_REN_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_SEC_REN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_SEC_REN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_SEC_REN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_SEC_REN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_SEC_REN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_CTL4_VM_SCR_0_SEC_OWNER_SHIFT                      _MK_SHIFT_CONST(24)
#define GPIO_CTL4_VM_SCR_0_SEC_OWNER_FIELD                      _MK_FIELD_CONST(0x7, GPIO_CTL4_VM_SCR_0_SEC_OWNER_SHIFT)
#define GPIO_CTL4_VM_SCR_0_SEC_OWNER_RANGE                      26:24
#define GPIO_CTL4_VM_SCR_0_SEC_OWNER_WOFFSET                    0x0
#define GPIO_CTL4_VM_SCR_0_SEC_OWNER_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_SEC_OWNER_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
#define GPIO_CTL4_VM_SCR_0_SEC_OWNER_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_SEC_OWNER_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_CTL4_VM_SCR_0_PR7_SHIFT                    _MK_SHIFT_CONST(23)
#define GPIO_CTL4_VM_SCR_0_PR7_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_PR7_SHIFT)
#define GPIO_CTL4_VM_SCR_0_PR7_RANGE                    23:23
#define GPIO_CTL4_VM_SCR_0_PR7_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_PR7_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR7_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_PR7_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR7_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR7_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR7_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL4_VM_SCR_0_PR6_SHIFT                    _MK_SHIFT_CONST(22)
#define GPIO_CTL4_VM_SCR_0_PR6_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_PR6_SHIFT)
#define GPIO_CTL4_VM_SCR_0_PR6_RANGE                    22:22
#define GPIO_CTL4_VM_SCR_0_PR6_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_PR6_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR6_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_PR6_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR6_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR6_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL4_VM_SCR_0_PR5_SHIFT                    _MK_SHIFT_CONST(21)
#define GPIO_CTL4_VM_SCR_0_PR5_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_PR5_SHIFT)
#define GPIO_CTL4_VM_SCR_0_PR5_RANGE                    21:21
#define GPIO_CTL4_VM_SCR_0_PR5_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_PR5_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR5_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_PR5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR5_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR5_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL4_VM_SCR_0_PR4_SHIFT                    _MK_SHIFT_CONST(20)
#define GPIO_CTL4_VM_SCR_0_PR4_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_PR4_SHIFT)
#define GPIO_CTL4_VM_SCR_0_PR4_RANGE                    20:20
#define GPIO_CTL4_VM_SCR_0_PR4_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_PR4_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR4_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_PR4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR4_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR4_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL4_VM_SCR_0_PR3_SHIFT                    _MK_SHIFT_CONST(19)
#define GPIO_CTL4_VM_SCR_0_PR3_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_PR3_SHIFT)
#define GPIO_CTL4_VM_SCR_0_PR3_RANGE                    19:19
#define GPIO_CTL4_VM_SCR_0_PR3_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_PR3_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_PR3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR3_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR3_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL4_VM_SCR_0_PR2_SHIFT                    _MK_SHIFT_CONST(18)
#define GPIO_CTL4_VM_SCR_0_PR2_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_PR2_SHIFT)
#define GPIO_CTL4_VM_SCR_0_PR2_RANGE                    18:18
#define GPIO_CTL4_VM_SCR_0_PR2_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_PR2_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_PR2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR2_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR2_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL4_VM_SCR_0_PR1_SHIFT                    _MK_SHIFT_CONST(17)
#define GPIO_CTL4_VM_SCR_0_PR1_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_PR1_SHIFT)
#define GPIO_CTL4_VM_SCR_0_PR1_RANGE                    17:17
#define GPIO_CTL4_VM_SCR_0_PR1_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_PR1_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_PR1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR1_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR1_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL4_VM_SCR_0_PR0_SHIFT                    _MK_SHIFT_CONST(16)
#define GPIO_CTL4_VM_SCR_0_PR0_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_PR0_SHIFT)
#define GPIO_CTL4_VM_SCR_0_PR0_RANGE                    16:16
#define GPIO_CTL4_VM_SCR_0_PR0_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_PR0_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_PR0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR0_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR0_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL4_VM_SCR_0_G7W_SHIFT                    _MK_SHIFT_CONST(15)
#define GPIO_CTL4_VM_SCR_0_G7W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G7W_SHIFT)
#define GPIO_CTL4_VM_SCR_0_G7W_RANGE                    15:15
#define GPIO_CTL4_VM_SCR_0_G7W_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_G7W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G7W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_G7W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G7W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G7W_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G7W_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL4_VM_SCR_0_G6W_SHIFT                    _MK_SHIFT_CONST(14)
#define GPIO_CTL4_VM_SCR_0_G6W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G6W_SHIFT)
#define GPIO_CTL4_VM_SCR_0_G6W_RANGE                    14:14
#define GPIO_CTL4_VM_SCR_0_G6W_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_G6W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G6W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_G6W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G6W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G6W_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G6W_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL4_VM_SCR_0_G5W_SHIFT                    _MK_SHIFT_CONST(13)
#define GPIO_CTL4_VM_SCR_0_G5W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G5W_SHIFT)
#define GPIO_CTL4_VM_SCR_0_G5W_RANGE                    13:13
#define GPIO_CTL4_VM_SCR_0_G5W_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_G5W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G5W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_G5W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G5W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G5W_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G5W_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL4_VM_SCR_0_G4W_SHIFT                    _MK_SHIFT_CONST(12)
#define GPIO_CTL4_VM_SCR_0_G4W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G4W_SHIFT)
#define GPIO_CTL4_VM_SCR_0_G4W_RANGE                    12:12
#define GPIO_CTL4_VM_SCR_0_G4W_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_G4W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G4W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_G4W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G4W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G4W_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G4W_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL4_VM_SCR_0_G3W_SHIFT                    _MK_SHIFT_CONST(11)
#define GPIO_CTL4_VM_SCR_0_G3W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G3W_SHIFT)
#define GPIO_CTL4_VM_SCR_0_G3W_RANGE                    11:11
#define GPIO_CTL4_VM_SCR_0_G3W_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_G3W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G3W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_G3W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G3W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G3W_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G3W_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL4_VM_SCR_0_G2W_SHIFT                    _MK_SHIFT_CONST(10)
#define GPIO_CTL4_VM_SCR_0_G2W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G2W_SHIFT)
#define GPIO_CTL4_VM_SCR_0_G2W_RANGE                    10:10
#define GPIO_CTL4_VM_SCR_0_G2W_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_G2W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G2W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_G2W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G2W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G2W_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G2W_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL4_VM_SCR_0_G1W_SHIFT                    _MK_SHIFT_CONST(9)
#define GPIO_CTL4_VM_SCR_0_G1W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G1W_SHIFT)
#define GPIO_CTL4_VM_SCR_0_G1W_RANGE                    9:9
#define GPIO_CTL4_VM_SCR_0_G1W_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_G1W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G1W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_G1W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G1W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G1W_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G1W_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL4_VM_SCR_0_G0W_SHIFT                    _MK_SHIFT_CONST(8)
#define GPIO_CTL4_VM_SCR_0_G0W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G0W_SHIFT)
#define GPIO_CTL4_VM_SCR_0_G0W_RANGE                    8:8
#define GPIO_CTL4_VM_SCR_0_G0W_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_G0W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G0W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_G0W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G0W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G0W_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G0W_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL4_VM_SCR_0_G7R_SHIFT                    _MK_SHIFT_CONST(7)
#define GPIO_CTL4_VM_SCR_0_G7R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G7R_SHIFT)
#define GPIO_CTL4_VM_SCR_0_G7R_RANGE                    7:7
#define GPIO_CTL4_VM_SCR_0_G7R_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_G7R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G7R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_G7R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G7R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G7R_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G7R_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL4_VM_SCR_0_G6R_SHIFT                    _MK_SHIFT_CONST(6)
#define GPIO_CTL4_VM_SCR_0_G6R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G6R_SHIFT)
#define GPIO_CTL4_VM_SCR_0_G6R_RANGE                    6:6
#define GPIO_CTL4_VM_SCR_0_G6R_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_G6R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G6R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_G6R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G6R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G6R_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G6R_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL4_VM_SCR_0_G5R_SHIFT                    _MK_SHIFT_CONST(5)
#define GPIO_CTL4_VM_SCR_0_G5R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G5R_SHIFT)
#define GPIO_CTL4_VM_SCR_0_G5R_RANGE                    5:5
#define GPIO_CTL4_VM_SCR_0_G5R_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_G5R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G5R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_G5R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G5R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G5R_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G5R_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL4_VM_SCR_0_G4R_SHIFT                    _MK_SHIFT_CONST(4)
#define GPIO_CTL4_VM_SCR_0_G4R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G4R_SHIFT)
#define GPIO_CTL4_VM_SCR_0_G4R_RANGE                    4:4
#define GPIO_CTL4_VM_SCR_0_G4R_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_G4R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G4R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_G4R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G4R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G4R_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G4R_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL4_VM_SCR_0_G3R_SHIFT                    _MK_SHIFT_CONST(3)
#define GPIO_CTL4_VM_SCR_0_G3R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G3R_SHIFT)
#define GPIO_CTL4_VM_SCR_0_G3R_RANGE                    3:3
#define GPIO_CTL4_VM_SCR_0_G3R_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_G3R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G3R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_G3R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G3R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G3R_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G3R_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL4_VM_SCR_0_G2R_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_CTL4_VM_SCR_0_G2R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G2R_SHIFT)
#define GPIO_CTL4_VM_SCR_0_G2R_RANGE                    2:2
#define GPIO_CTL4_VM_SCR_0_G2R_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_G2R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G2R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_G2R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G2R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G2R_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G2R_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL4_VM_SCR_0_G1R_SHIFT                    _MK_SHIFT_CONST(1)
#define GPIO_CTL4_VM_SCR_0_G1R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G1R_SHIFT)
#define GPIO_CTL4_VM_SCR_0_G1R_RANGE                    1:1
#define GPIO_CTL4_VM_SCR_0_G1R_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_G1R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G1R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_G1R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G1R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G1R_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G1R_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL4_VM_SCR_0_G0R_SHIFT                    _MK_SHIFT_CONST(0)
#define GPIO_CTL4_VM_SCR_0_G0R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G0R_SHIFT)
#define GPIO_CTL4_VM_SCR_0_G0R_RANGE                    0:0
#define GPIO_CTL4_VM_SCR_0_G0R_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_G0R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G0R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_G0R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G0R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G0R_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G0R_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0                     _MK_ADDR_CONST(0x4804)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SECURE                      0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_DUAL                        0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SCR                         0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_WORD_COUNT                  0x1
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_RESET_MASK                  _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_READ_MASK                   _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_WRITE_MASK                  _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SHIFT                       _MK_SHIFT_CONST(29)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_RANGE                       29:29
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_WOFFSET                     0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SHIFT                       _MK_SHIFT_CONST(28)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_RANGE                       28:28
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_WOFFSET                     0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SHIFT                       _MK_SHIFT_CONST(27)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_RANGE                       27:27
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_WOFFSET                     0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SHIFT                     _MK_SHIFT_CONST(24)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_FIELD                     _MK_FIELD_CONST(0x7, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_RANGE                     26:24
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_WOFFSET                   0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR7_SHIFT                   _MK_SHIFT_CONST(23)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR7_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR7_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR7_RANGE                   23:23
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR7_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR7_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR7_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR7_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR7_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR7_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR7_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR6_SHIFT                   _MK_SHIFT_CONST(22)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR6_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR6_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR6_RANGE                   22:22
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR6_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR6_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR6_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR6_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR6_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR6_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR6_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR5_SHIFT                   _MK_SHIFT_CONST(21)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR5_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR5_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR5_RANGE                   21:21
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR5_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR5_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR5_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR5_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR5_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR5_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR5_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR4_SHIFT                   _MK_SHIFT_CONST(20)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR4_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR4_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR4_RANGE                   20:20
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR4_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR4_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR4_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR4_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR4_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR3_SHIFT                   _MK_SHIFT_CONST(19)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR3_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR3_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR3_RANGE                   19:19
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR3_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR3_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR3_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR3_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR2_SHIFT                   _MK_SHIFT_CONST(18)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR2_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR2_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR2_RANGE                   18:18
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR2_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR2_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR2_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR2_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR1_SHIFT                   _MK_SHIFT_CONST(17)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR1_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR1_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR1_RANGE                   17:17
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR1_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR1_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR1_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR1_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR0_SHIFT                   _MK_SHIFT_CONST(16)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR0_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR0_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR0_RANGE                   16:16
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR0_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR0_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR0_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR0_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7W_SHIFT                   _MK_SHIFT_CONST(15)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7W_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7W_RANGE                   15:15
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7W_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6W_SHIFT                   _MK_SHIFT_CONST(14)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6W_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6W_RANGE                   14:14
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6W_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5W_SHIFT                   _MK_SHIFT_CONST(13)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5W_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5W_RANGE                   13:13
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5W_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4W_SHIFT                   _MK_SHIFT_CONST(12)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4W_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4W_RANGE                   12:12
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4W_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3W_SHIFT                   _MK_SHIFT_CONST(11)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3W_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3W_RANGE                   11:11
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3W_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2W_SHIFT                   _MK_SHIFT_CONST(10)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2W_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2W_RANGE                   10:10
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2W_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1W_SHIFT                   _MK_SHIFT_CONST(9)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1W_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1W_RANGE                   9:9
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1W_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0W_SHIFT                   _MK_SHIFT_CONST(8)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0W_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0W_RANGE                   8:8
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0W_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7R_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7R_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7R_RANGE                   7:7
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7R_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6R_SHIFT                   _MK_SHIFT_CONST(6)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6R_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6R_RANGE                   6:6
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6R_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5R_SHIFT                   _MK_SHIFT_CONST(5)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5R_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5R_RANGE                   5:5
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5R_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4R_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4R_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4R_RANGE                   4:4
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4R_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3R_SHIFT                   _MK_SHIFT_CONST(3)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3R_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3R_RANGE                   3:3
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3R_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2R_SHIFT                   _MK_SHIFT_CONST(2)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2R_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2R_RANGE                   2:2
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2R_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1R_SHIFT                   _MK_SHIFT_CONST(1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1R_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1R_RANGE                   1:1
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1R_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0R_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0R_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0R_RANGE                   0:0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0R_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_CTL4_INTERRUPT_STATUS_VM_0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0                 _MK_ADDR_CONST(0x4808)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_SECURE                  0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_DUAL                    0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_SCR                     GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_WORD_COUNT                      0x1
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_RESET_MASK                      _MK_MASK_CONST(0xff)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_READ_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_FIELD                  _MK_FIELD_CONST(0xff, GPIO_CTL4_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_RANGE                  7:0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_WOFFSET                        0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register GPIO_CTL4_SCR_0
#define GPIO_CTL4_SCR_0                 _MK_ADDR_CONST(0x480c)
#define GPIO_CTL4_SCR_0_SECURE                  0x0
#define GPIO_CTL4_SCR_0_DUAL                    0x0
#define GPIO_CTL4_SCR_0_SCR                     0
#define GPIO_CTL4_SCR_0_WORD_COUNT                      0x1
#define GPIO_CTL4_SCR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL4_SCR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL4_SCR_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL4_SCR_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_CTL4_SCR_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_SEC_LCK_SHIFT)
#define GPIO_CTL4_SCR_0_SEC_LCK_RANGE                   29:29
#define GPIO_CTL4_SCR_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_CTL4_SCR_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL4_SCR_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_CTL4_SCR_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_SEC_WEN_SHIFT)
#define GPIO_CTL4_SCR_0_SEC_WEN_RANGE                   28:28
#define GPIO_CTL4_SCR_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_CTL4_SCR_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL4_SCR_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_CTL4_SCR_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_SEC_REN_SHIFT)
#define GPIO_CTL4_SCR_0_SEC_REN_RANGE                   27:27
#define GPIO_CTL4_SCR_0_SEC_REN_WOFFSET                 0x0
#define GPIO_CTL4_SCR_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL4_SCR_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_CTL4_SCR_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_CTL4_SCR_0_SEC_OWNER_SHIFT)
#define GPIO_CTL4_SCR_0_SEC_OWNER_RANGE                 26:24
#define GPIO_CTL4_SCR_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_CTL4_SCR_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_CTL4_SCR_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_CTL4_SCR_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_CTL4_SCR_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_PR7_SHIFT)
#define GPIO_CTL4_SCR_0_PR7_RANGE                       23:23
#define GPIO_CTL4_SCR_0_PR7_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL4_SCR_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_CTL4_SCR_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_PR6_SHIFT)
#define GPIO_CTL4_SCR_0_PR6_RANGE                       22:22
#define GPIO_CTL4_SCR_0_PR6_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL4_SCR_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_CTL4_SCR_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_PR5_SHIFT)
#define GPIO_CTL4_SCR_0_PR5_RANGE                       21:21
#define GPIO_CTL4_SCR_0_PR5_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL4_SCR_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_CTL4_SCR_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_PR4_SHIFT)
#define GPIO_CTL4_SCR_0_PR4_RANGE                       20:20
#define GPIO_CTL4_SCR_0_PR4_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL4_SCR_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_CTL4_SCR_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_PR3_SHIFT)
#define GPIO_CTL4_SCR_0_PR3_RANGE                       19:19
#define GPIO_CTL4_SCR_0_PR3_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL4_SCR_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_CTL4_SCR_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_PR2_SHIFT)
#define GPIO_CTL4_SCR_0_PR2_RANGE                       18:18
#define GPIO_CTL4_SCR_0_PR2_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL4_SCR_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_CTL4_SCR_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_PR1_SHIFT)
#define GPIO_CTL4_SCR_0_PR1_RANGE                       17:17
#define GPIO_CTL4_SCR_0_PR1_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL4_SCR_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_CTL4_SCR_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_PR0_SHIFT)
#define GPIO_CTL4_SCR_0_PR0_RANGE                       16:16
#define GPIO_CTL4_SCR_0_PR0_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL4_SCR_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_CTL4_SCR_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G7W_SHIFT)
#define GPIO_CTL4_SCR_0_G7W_RANGE                       15:15
#define GPIO_CTL4_SCR_0_G7W_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL4_SCR_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_CTL4_SCR_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G6W_SHIFT)
#define GPIO_CTL4_SCR_0_G6W_RANGE                       14:14
#define GPIO_CTL4_SCR_0_G6W_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL4_SCR_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_CTL4_SCR_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G5W_SHIFT)
#define GPIO_CTL4_SCR_0_G5W_RANGE                       13:13
#define GPIO_CTL4_SCR_0_G5W_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL4_SCR_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_CTL4_SCR_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G4W_SHIFT)
#define GPIO_CTL4_SCR_0_G4W_RANGE                       12:12
#define GPIO_CTL4_SCR_0_G4W_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL4_SCR_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_CTL4_SCR_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G3W_SHIFT)
#define GPIO_CTL4_SCR_0_G3W_RANGE                       11:11
#define GPIO_CTL4_SCR_0_G3W_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL4_SCR_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_CTL4_SCR_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G2W_SHIFT)
#define GPIO_CTL4_SCR_0_G2W_RANGE                       10:10
#define GPIO_CTL4_SCR_0_G2W_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL4_SCR_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_CTL4_SCR_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G1W_SHIFT)
#define GPIO_CTL4_SCR_0_G1W_RANGE                       9:9
#define GPIO_CTL4_SCR_0_G1W_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL4_SCR_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_CTL4_SCR_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G0W_SHIFT)
#define GPIO_CTL4_SCR_0_G0W_RANGE                       8:8
#define GPIO_CTL4_SCR_0_G0W_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL4_SCR_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_CTL4_SCR_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G7R_SHIFT)
#define GPIO_CTL4_SCR_0_G7R_RANGE                       7:7
#define GPIO_CTL4_SCR_0_G7R_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL4_SCR_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_CTL4_SCR_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G6R_SHIFT)
#define GPIO_CTL4_SCR_0_G6R_RANGE                       6:6
#define GPIO_CTL4_SCR_0_G6R_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL4_SCR_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_CTL4_SCR_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G5R_SHIFT)
#define GPIO_CTL4_SCR_0_G5R_RANGE                       5:5
#define GPIO_CTL4_SCR_0_G5R_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL4_SCR_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_CTL4_SCR_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G4R_SHIFT)
#define GPIO_CTL4_SCR_0_G4R_RANGE                       4:4
#define GPIO_CTL4_SCR_0_G4R_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL4_SCR_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_CTL4_SCR_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G3R_SHIFT)
#define GPIO_CTL4_SCR_0_G3R_RANGE                       3:3
#define GPIO_CTL4_SCR_0_G3R_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL4_SCR_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_CTL4_SCR_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G2R_SHIFT)
#define GPIO_CTL4_SCR_0_G2R_RANGE                       2:2
#define GPIO_CTL4_SCR_0_G2R_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL4_SCR_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_CTL4_SCR_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G1R_SHIFT)
#define GPIO_CTL4_SCR_0_G1R_RANGE                       1:1
#define GPIO_CTL4_SCR_0_G1R_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL4_SCR_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_CTL4_SCR_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G0R_SHIFT)
#define GPIO_CTL4_SCR_0_G0R_RANGE                       0:0
#define GPIO_CTL4_SCR_0_G0R_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_CTL4_ICG_EN_OVERRIDE_0
#define GPIO_CTL4_ICG_EN_OVERRIDE_0                     _MK_ADDR_CONST(0x4810)
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_SECURE                      0x0
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_DUAL                        0x0
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_WORD_COUNT                  0x1
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_FIELD                  _MK_FIELD_CONST(0x1, GPIO_CTL4_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SHIFT)
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_RANGE                  0:0
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_WOFFSET                        0x0
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register GPIO_G_INT0_ROUTE_MAPPING_0
#define GPIO_G_INT0_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x4814)
#define GPIO_G_INT0_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_G_INT0_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_G_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_G_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_G_INT0_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_G_INT0_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_G_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_G_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_INT0_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_G_INT0_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_G_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_G_INT0_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_G_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_G_INT0_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_G_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_G_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_G_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_G_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_G_INT1_ROUTE_MAPPING_0
#define GPIO_G_INT1_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x4818)
#define GPIO_G_INT1_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_G_INT1_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_G_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_G_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_G_INT1_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_G_INT1_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_G_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_G_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_INT1_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_G_INT1_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_G_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_G_INT1_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_G_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_G_INT1_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_G_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_G_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_G_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_G_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_G_INT2_ROUTE_MAPPING_0
#define GPIO_G_INT2_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x481c)
#define GPIO_G_INT2_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_G_INT2_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_G_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_G_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_G_INT2_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_G_INT2_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_G_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_G_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_INT2_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_G_INT2_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_G_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_G_INT2_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_G_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_G_INT2_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_G_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_G_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_G_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_G_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_G_INT3_ROUTE_MAPPING_0
#define GPIO_G_INT3_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x4820)
#define GPIO_G_INT3_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_G_INT3_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_G_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_G_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_G_INT3_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_G_INT3_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_G_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_G_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_INT3_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_G_INT3_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_G_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_G_INT3_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_G_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_G_INT3_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_G_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_G_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_G_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_G_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_G_INT4_ROUTE_MAPPING_0
#define GPIO_G_INT4_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x4824)
#define GPIO_G_INT4_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_G_INT4_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_G_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_G_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_G_INT4_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_G_INT4_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_G_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_G_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_INT4_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_G_INT4_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_G_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_G_INT4_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_G_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_G_INT4_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_G_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_G_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_G_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_G_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_G_INT5_ROUTE_MAPPING_0
#define GPIO_G_INT5_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x4828)
#define GPIO_G_INT5_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_G_INT5_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_G_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_G_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_G_INT5_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_G_INT5_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_G_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_G_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_INT5_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_G_INT5_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_G_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_G_INT5_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_G_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_G_INT5_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_G_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_G_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_G_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_G_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_G_INT6_ROUTE_MAPPING_0
#define GPIO_G_INT6_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x482c)
#define GPIO_G_INT6_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_G_INT6_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_G_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_G_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_G_INT6_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_G_INT6_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_G_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_G_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_INT6_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_G_INT6_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_G_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_G_INT6_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_G_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_G_INT6_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_G_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_G_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_G_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_G_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_G_INT7_ROUTE_MAPPING_0
#define GPIO_G_INT7_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x4830)
#define GPIO_G_INT7_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_G_INT7_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_G_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_G_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_G_INT7_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_G_INT7_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_G_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_G_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_INT7_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_G_INT7_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_G_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_G_INT7_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_G_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_G_INT7_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_G_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_G_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_G_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_G_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_H_INT0_ROUTE_MAPPING_0
#define GPIO_H_INT0_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x4834)
#define GPIO_H_INT0_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_H_INT0_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_H_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_H_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_H_INT0_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_H_INT0_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_H_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_H_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_INT0_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_H_INT0_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_H_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_H_INT0_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_H_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_H_INT0_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_H_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_H_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_H_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_H_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_H_INT1_ROUTE_MAPPING_0
#define GPIO_H_INT1_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x4838)
#define GPIO_H_INT1_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_H_INT1_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_H_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_H_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_H_INT1_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_H_INT1_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_H_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_H_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_INT1_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_H_INT1_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_H_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_H_INT1_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_H_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_H_INT1_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_H_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_H_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_H_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_H_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_H_INT2_ROUTE_MAPPING_0
#define GPIO_H_INT2_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x483c)
#define GPIO_H_INT2_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_H_INT2_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_H_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_H_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_H_INT2_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_H_INT2_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_H_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_H_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_INT2_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_H_INT2_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_H_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_H_INT2_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_H_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_H_INT2_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_H_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_H_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_H_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_H_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_H_INT3_ROUTE_MAPPING_0
#define GPIO_H_INT3_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x4840)
#define GPIO_H_INT3_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_H_INT3_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_H_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_H_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_H_INT3_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_H_INT3_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_H_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_H_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_INT3_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_H_INT3_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_H_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_H_INT3_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_H_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_H_INT3_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_H_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_H_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_H_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_H_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_H_INT4_ROUTE_MAPPING_0
#define GPIO_H_INT4_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x4844)
#define GPIO_H_INT4_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_H_INT4_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_H_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_H_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_H_INT4_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_H_INT4_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_H_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_H_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_INT4_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_H_INT4_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_H_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_H_INT4_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_H_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_H_INT4_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_H_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_H_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_H_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_H_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_H_INT5_ROUTE_MAPPING_0
#define GPIO_H_INT5_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x4848)
#define GPIO_H_INT5_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_H_INT5_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_H_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_H_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_H_INT5_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_H_INT5_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_H_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_H_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_INT5_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_H_INT5_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_H_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_H_INT5_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_H_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_H_INT5_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_H_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_H_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_H_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_H_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_H_INT6_ROUTE_MAPPING_0
#define GPIO_H_INT6_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x484c)
#define GPIO_H_INT6_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_H_INT6_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_H_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_H_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_H_INT6_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_H_INT6_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_H_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_H_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_INT6_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_H_INT6_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_H_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_H_INT6_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_H_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_H_INT6_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_H_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_H_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_H_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_H_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_H_INT7_ROUTE_MAPPING_0
#define GPIO_H_INT7_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x4850)
#define GPIO_H_INT7_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_H_INT7_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_H_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_H_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_H_INT7_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_H_INT7_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_H_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_H_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_INT7_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_H_INT7_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_H_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_H_INT7_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_H_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_H_INT7_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_H_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_H_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_H_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_H_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_I_INT0_ROUTE_MAPPING_0
#define GPIO_I_INT0_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x4854)
#define GPIO_I_INT0_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_I_INT0_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_I_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_I_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_I_INT0_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_I_INT0_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x1f)
#define GPIO_I_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_I_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_INT0_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x1f)
#define GPIO_I_INT0_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x1f)
#define GPIO_I_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_I_INT0_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x1f, GPIO_I_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_I_INT0_ROUTE_MAPPING_0_VAL_RANGE                   4:0
#define GPIO_I_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_I_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
#define GPIO_I_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_I_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_I_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_I_INT1_ROUTE_MAPPING_0
#define GPIO_I_INT1_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x4858)
#define GPIO_I_INT1_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_I_INT1_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_I_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_I_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_I_INT1_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_I_INT1_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x1f)
#define GPIO_I_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_I_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_INT1_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x1f)
#define GPIO_I_INT1_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x1f)
#define GPIO_I_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_I_INT1_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x1f, GPIO_I_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_I_INT1_ROUTE_MAPPING_0_VAL_RANGE                   4:0
#define GPIO_I_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_I_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
#define GPIO_I_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_I_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_I_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_I_INT2_ROUTE_MAPPING_0
#define GPIO_I_INT2_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x485c)
#define GPIO_I_INT2_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_I_INT2_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_I_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_I_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_I_INT2_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_I_INT2_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x1f)
#define GPIO_I_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_I_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_INT2_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x1f)
#define GPIO_I_INT2_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x1f)
#define GPIO_I_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_I_INT2_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x1f, GPIO_I_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_I_INT2_ROUTE_MAPPING_0_VAL_RANGE                   4:0
#define GPIO_I_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_I_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
#define GPIO_I_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_I_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_I_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_I_INT3_ROUTE_MAPPING_0
#define GPIO_I_INT3_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x4860)
#define GPIO_I_INT3_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_I_INT3_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_I_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_I_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_I_INT3_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_I_INT3_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x1f)
#define GPIO_I_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_I_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_INT3_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x1f)
#define GPIO_I_INT3_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x1f)
#define GPIO_I_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_I_INT3_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x1f, GPIO_I_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_I_INT3_ROUTE_MAPPING_0_VAL_RANGE                   4:0
#define GPIO_I_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_I_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
#define GPIO_I_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_I_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_I_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_I_INT4_ROUTE_MAPPING_0
#define GPIO_I_INT4_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x4864)
#define GPIO_I_INT4_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_I_INT4_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_I_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_I_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_I_INT4_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_I_INT4_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x1f)
#define GPIO_I_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_I_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_INT4_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x1f)
#define GPIO_I_INT4_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x1f)
#define GPIO_I_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_I_INT4_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x1f, GPIO_I_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_I_INT4_ROUTE_MAPPING_0_VAL_RANGE                   4:0
#define GPIO_I_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_I_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
#define GPIO_I_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_I_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_I_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_I_INT5_ROUTE_MAPPING_0
#define GPIO_I_INT5_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x4868)
#define GPIO_I_INT5_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_I_INT5_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_I_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_I_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_I_INT5_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_I_INT5_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x1f)
#define GPIO_I_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_I_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_INT5_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x1f)
#define GPIO_I_INT5_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x1f)
#define GPIO_I_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_I_INT5_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x1f, GPIO_I_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_I_INT5_ROUTE_MAPPING_0_VAL_RANGE                   4:0
#define GPIO_I_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_I_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
#define GPIO_I_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_I_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_I_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_I_INT6_ROUTE_MAPPING_0
#define GPIO_I_INT6_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x486c)
#define GPIO_I_INT6_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_I_INT6_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_I_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_I_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_I_INT6_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_I_INT6_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x1f)
#define GPIO_I_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_I_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_INT6_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x1f)
#define GPIO_I_INT6_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x1f)
#define GPIO_I_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_I_INT6_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x1f, GPIO_I_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_I_INT6_ROUTE_MAPPING_0_VAL_RANGE                   4:0
#define GPIO_I_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_I_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
#define GPIO_I_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_I_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_I_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_I_INT7_ROUTE_MAPPING_0
#define GPIO_I_INT7_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x4870)
#define GPIO_I_INT7_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_I_INT7_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_I_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_I_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_I_INT7_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_I_INT7_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x1f)
#define GPIO_I_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_I_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_INT7_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x1f)
#define GPIO_I_INT7_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x1f)
#define GPIO_I_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_I_INT7_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x1f, GPIO_I_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_I_INT7_ROUTE_MAPPING_0_VAL_RANGE                   4:0
#define GPIO_I_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_I_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
#define GPIO_I_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_I_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_I_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_C_INT0_ROUTE_MAPPING_0
#define GPIO_C_INT0_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x4874)
#define GPIO_C_INT0_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_C_INT0_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_C_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_C_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_C_INT0_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_C_INT0_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_C_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_C_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_INT0_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_C_INT0_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_C_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_C_INT0_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_C_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_C_INT0_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_C_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_C_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_C_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_C_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_C_INT1_ROUTE_MAPPING_0
#define GPIO_C_INT1_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x4878)
#define GPIO_C_INT1_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_C_INT1_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_C_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_C_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_C_INT1_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_C_INT1_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_C_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_C_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_INT1_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_C_INT1_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_C_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_C_INT1_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_C_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_C_INT1_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_C_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_C_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_C_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_C_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_C_INT2_ROUTE_MAPPING_0
#define GPIO_C_INT2_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x487c)
#define GPIO_C_INT2_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_C_INT2_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_C_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_C_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_C_INT2_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_C_INT2_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_C_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_C_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_INT2_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_C_INT2_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_C_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_C_INT2_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_C_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_C_INT2_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_C_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_C_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_C_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_C_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_C_INT3_ROUTE_MAPPING_0
#define GPIO_C_INT3_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x4880)
#define GPIO_C_INT3_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_C_INT3_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_C_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_C_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_C_INT3_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_C_INT3_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_C_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_C_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_INT3_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_C_INT3_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_C_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_C_INT3_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_C_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_C_INT3_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_C_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_C_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_C_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_C_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_C_INT4_ROUTE_MAPPING_0
#define GPIO_C_INT4_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x4884)
#define GPIO_C_INT4_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_C_INT4_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_C_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_C_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_C_INT4_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_C_INT4_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_C_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_C_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_INT4_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_C_INT4_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_C_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_C_INT4_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_C_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_C_INT4_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_C_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_C_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_C_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_C_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_C_INT5_ROUTE_MAPPING_0
#define GPIO_C_INT5_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x4888)
#define GPIO_C_INT5_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_C_INT5_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_C_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_C_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_C_INT5_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_C_INT5_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_C_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_C_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_INT5_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_C_INT5_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_C_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_C_INT5_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_C_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_C_INT5_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_C_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_C_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_C_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_C_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_C_INT6_ROUTE_MAPPING_0
#define GPIO_C_INT6_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x488c)
#define GPIO_C_INT6_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_C_INT6_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_C_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_C_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_C_INT6_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_C_INT6_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_C_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_C_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_INT6_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_C_INT6_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_C_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_C_INT6_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_C_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_C_INT6_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_C_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_C_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_C_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_C_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_C_INT7_ROUTE_MAPPING_0
#define GPIO_C_INT7_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x4890)
#define GPIO_C_INT7_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_C_INT7_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_C_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_C_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_C_INT7_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_C_INT7_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_C_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_C_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_INT7_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_C_INT7_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_C_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_C_INT7_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_C_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_C_INT7_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_C_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_C_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_C_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_C_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_D_INT0_ROUTE_MAPPING_0
#define GPIO_D_INT0_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x4894)
#define GPIO_D_INT0_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_D_INT0_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_D_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_D_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_D_INT0_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_D_INT0_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_D_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_D_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_INT0_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xf)
#define GPIO_D_INT0_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_D_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_D_INT0_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xf, GPIO_D_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_D_INT0_ROUTE_MAPPING_0_VAL_RANGE                   3:0
#define GPIO_D_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_D_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define GPIO_D_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_D_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_D_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_D_INT1_ROUTE_MAPPING_0
#define GPIO_D_INT1_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x4898)
#define GPIO_D_INT1_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_D_INT1_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_D_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_D_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_D_INT1_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_D_INT1_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_D_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_D_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_INT1_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xf)
#define GPIO_D_INT1_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_D_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_D_INT1_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xf, GPIO_D_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_D_INT1_ROUTE_MAPPING_0_VAL_RANGE                   3:0
#define GPIO_D_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_D_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define GPIO_D_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_D_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_D_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_D_INT2_ROUTE_MAPPING_0
#define GPIO_D_INT2_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x489c)
#define GPIO_D_INT2_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_D_INT2_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_D_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_D_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_D_INT2_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_D_INT2_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_D_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_D_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_INT2_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xf)
#define GPIO_D_INT2_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_D_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_D_INT2_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xf, GPIO_D_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_D_INT2_ROUTE_MAPPING_0_VAL_RANGE                   3:0
#define GPIO_D_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_D_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define GPIO_D_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_D_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_D_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_D_INT3_ROUTE_MAPPING_0
#define GPIO_D_INT3_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x48a0)
#define GPIO_D_INT3_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_D_INT3_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_D_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_D_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_D_INT3_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_D_INT3_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_D_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_D_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_INT3_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xf)
#define GPIO_D_INT3_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_D_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_D_INT3_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xf, GPIO_D_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_D_INT3_ROUTE_MAPPING_0_VAL_RANGE                   3:0
#define GPIO_D_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_D_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define GPIO_D_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_D_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_D_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_D_INT4_ROUTE_MAPPING_0
#define GPIO_D_INT4_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x48a4)
#define GPIO_D_INT4_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_D_INT4_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_D_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_D_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_D_INT4_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_D_INT4_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_D_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_D_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_INT4_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xf)
#define GPIO_D_INT4_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_D_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_D_INT4_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xf, GPIO_D_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_D_INT4_ROUTE_MAPPING_0_VAL_RANGE                   3:0
#define GPIO_D_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_D_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define GPIO_D_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_D_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_D_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_D_INT5_ROUTE_MAPPING_0
#define GPIO_D_INT5_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x48a8)
#define GPIO_D_INT5_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_D_INT5_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_D_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_D_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_D_INT5_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_D_INT5_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_D_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_D_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_INT5_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xf)
#define GPIO_D_INT5_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_D_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_D_INT5_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xf, GPIO_D_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_D_INT5_ROUTE_MAPPING_0_VAL_RANGE                   3:0
#define GPIO_D_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_D_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define GPIO_D_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_D_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_D_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_D_INT6_ROUTE_MAPPING_0
#define GPIO_D_INT6_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x48ac)
#define GPIO_D_INT6_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_D_INT6_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_D_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_D_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_D_INT6_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_D_INT6_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_D_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_D_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_INT6_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xf)
#define GPIO_D_INT6_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_D_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_D_INT6_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xf, GPIO_D_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_D_INT6_ROUTE_MAPPING_0_VAL_RANGE                   3:0
#define GPIO_D_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_D_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define GPIO_D_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_D_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_D_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_D_INT7_ROUTE_MAPPING_0
#define GPIO_D_INT7_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x48b0)
#define GPIO_D_INT7_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_D_INT7_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_D_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_D_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_D_INT7_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_D_INT7_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_D_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_D_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_INT7_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xf)
#define GPIO_D_INT7_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_D_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_D_INT7_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xf, GPIO_D_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_D_INT7_ROUTE_MAPPING_0_VAL_RANGE                   3:0
#define GPIO_D_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_D_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define GPIO_D_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_D_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_D_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_E_INT0_ROUTE_MAPPING_0
#define GPIO_E_INT0_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x48b4)
#define GPIO_E_INT0_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_E_INT0_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_E_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_E_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_E_INT0_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_INT0_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_E_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_E_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_INT0_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_E_INT0_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_E_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_E_INT0_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_E_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_E_INT0_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_E_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_E_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_E_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_E_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_E_INT1_ROUTE_MAPPING_0
#define GPIO_E_INT1_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x48b8)
#define GPIO_E_INT1_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_E_INT1_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_E_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_E_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_E_INT1_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_INT1_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_E_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_E_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_INT1_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_E_INT1_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_E_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_E_INT1_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_E_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_E_INT1_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_E_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_E_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_E_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_E_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_E_INT2_ROUTE_MAPPING_0
#define GPIO_E_INT2_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x48bc)
#define GPIO_E_INT2_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_E_INT2_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_E_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_E_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_E_INT2_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_INT2_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_E_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_E_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_INT2_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_E_INT2_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_E_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_E_INT2_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_E_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_E_INT2_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_E_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_E_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_E_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_E_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_E_INT3_ROUTE_MAPPING_0
#define GPIO_E_INT3_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x48c0)
#define GPIO_E_INT3_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_E_INT3_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_E_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_E_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_E_INT3_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_INT3_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_E_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_E_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_INT3_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_E_INT3_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_E_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_E_INT3_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_E_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_E_INT3_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_E_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_E_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_E_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_E_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_E_INT4_ROUTE_MAPPING_0
#define GPIO_E_INT4_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x48c4)
#define GPIO_E_INT4_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_E_INT4_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_E_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_E_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_E_INT4_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_INT4_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_E_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_E_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_INT4_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_E_INT4_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_E_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_E_INT4_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_E_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_E_INT4_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_E_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_E_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_E_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_E_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_E_INT5_ROUTE_MAPPING_0
#define GPIO_E_INT5_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x48c8)
#define GPIO_E_INT5_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_E_INT5_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_E_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_E_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_E_INT5_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_INT5_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_E_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_E_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_INT5_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_E_INT5_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_E_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_E_INT5_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_E_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_E_INT5_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_E_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_E_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_E_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_E_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_E_INT6_ROUTE_MAPPING_0
#define GPIO_E_INT6_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x48cc)
#define GPIO_E_INT6_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_E_INT6_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_E_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_E_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_E_INT6_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_INT6_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_E_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_E_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_INT6_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_E_INT6_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_E_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_E_INT6_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_E_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_E_INT6_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_E_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_E_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_E_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_E_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_E_INT7_ROUTE_MAPPING_0
#define GPIO_E_INT7_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x48d0)
#define GPIO_E_INT7_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_E_INT7_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_E_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_E_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_E_INT7_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_INT7_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_E_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_E_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_INT7_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_E_INT7_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_E_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_E_INT7_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0xff, GPIO_E_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_E_INT7_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_E_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_E_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_E_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_E_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_F_INT0_ROUTE_MAPPING_0
#define GPIO_F_INT0_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x48d4)
#define GPIO_F_INT0_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_F_INT0_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_F_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_F_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_F_INT0_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_F_INT0_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_F_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_F_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_INT0_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x3f)
#define GPIO_F_INT0_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_F_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_F_INT0_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x3f, GPIO_F_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_F_INT0_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_F_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_F_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
#define GPIO_F_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_F_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_F_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_F_INT1_ROUTE_MAPPING_0
#define GPIO_F_INT1_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x48d8)
#define GPIO_F_INT1_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_F_INT1_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_F_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_F_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_F_INT1_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_F_INT1_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_F_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_F_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_INT1_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x3f)
#define GPIO_F_INT1_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_F_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_F_INT1_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x3f, GPIO_F_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_F_INT1_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_F_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_F_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
#define GPIO_F_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_F_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_F_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_F_INT2_ROUTE_MAPPING_0
#define GPIO_F_INT2_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x48dc)
#define GPIO_F_INT2_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_F_INT2_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_F_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_F_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_F_INT2_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_F_INT2_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_F_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_F_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_INT2_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x3f)
#define GPIO_F_INT2_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_F_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_F_INT2_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x3f, GPIO_F_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_F_INT2_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_F_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_F_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
#define GPIO_F_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_F_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_F_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_F_INT3_ROUTE_MAPPING_0
#define GPIO_F_INT3_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x48e0)
#define GPIO_F_INT3_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_F_INT3_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_F_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_F_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_F_INT3_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_F_INT3_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_F_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_F_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_INT3_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x3f)
#define GPIO_F_INT3_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_F_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_F_INT3_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x3f, GPIO_F_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_F_INT3_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_F_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_F_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
#define GPIO_F_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_F_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_F_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_F_INT4_ROUTE_MAPPING_0
#define GPIO_F_INT4_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x48e4)
#define GPIO_F_INT4_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_F_INT4_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_F_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_F_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_F_INT4_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_F_INT4_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_F_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_F_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_INT4_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x3f)
#define GPIO_F_INT4_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_F_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_F_INT4_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x3f, GPIO_F_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_F_INT4_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_F_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_F_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
#define GPIO_F_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_F_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_F_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_F_INT5_ROUTE_MAPPING_0
#define GPIO_F_INT5_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x48e8)
#define GPIO_F_INT5_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_F_INT5_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_F_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_F_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_F_INT5_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_F_INT5_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_F_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_F_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_INT5_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x3f)
#define GPIO_F_INT5_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_F_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_F_INT5_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x3f, GPIO_F_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_F_INT5_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_F_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_F_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
#define GPIO_F_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_F_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_F_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_F_INT6_ROUTE_MAPPING_0
#define GPIO_F_INT6_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x48ec)
#define GPIO_F_INT6_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_F_INT6_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_F_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_F_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_F_INT6_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_F_INT6_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_F_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_F_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_INT6_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x3f)
#define GPIO_F_INT6_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_F_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_F_INT6_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x3f, GPIO_F_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_F_INT6_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_F_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_F_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
#define GPIO_F_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_F_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_F_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_F_INT7_ROUTE_MAPPING_0
#define GPIO_F_INT7_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x48f0)
#define GPIO_F_INT7_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_F_INT7_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_F_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_F_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_F_INT7_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_F_INT7_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_F_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_F_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_INT7_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x3f)
#define GPIO_F_INT7_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_F_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_F_INT7_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x3f, GPIO_F_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_F_INT7_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_F_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_F_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
#define GPIO_F_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_F_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_F_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_B_INT0_ROUTE_MAPPING_0
#define GPIO_B_INT0_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x48f4)
#define GPIO_B_INT0_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_B_INT0_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_B_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_B_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_B_INT0_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_B_INT0_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_B_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_B_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_INT0_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x3)
#define GPIO_B_INT0_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_B_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_B_INT0_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x3, GPIO_B_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_B_INT0_ROUTE_MAPPING_0_VAL_RANGE                   1:0
#define GPIO_B_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_B_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define GPIO_B_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_B_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_B_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_B_INT1_ROUTE_MAPPING_0
#define GPIO_B_INT1_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x48f8)
#define GPIO_B_INT1_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_B_INT1_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_B_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_B_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_B_INT1_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_B_INT1_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_B_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_B_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_INT1_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x3)
#define GPIO_B_INT1_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_B_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_B_INT1_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x3, GPIO_B_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_B_INT1_ROUTE_MAPPING_0_VAL_RANGE                   1:0
#define GPIO_B_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_B_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define GPIO_B_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_B_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_B_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_B_INT2_ROUTE_MAPPING_0
#define GPIO_B_INT2_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x48fc)
#define GPIO_B_INT2_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_B_INT2_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_B_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_B_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_B_INT2_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_B_INT2_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_B_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_B_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_INT2_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x3)
#define GPIO_B_INT2_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_B_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_B_INT2_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x3, GPIO_B_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_B_INT2_ROUTE_MAPPING_0_VAL_RANGE                   1:0
#define GPIO_B_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_B_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define GPIO_B_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_B_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_B_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_B_INT3_ROUTE_MAPPING_0
#define GPIO_B_INT3_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x4900)
#define GPIO_B_INT3_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_B_INT3_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_B_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_B_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_B_INT3_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_B_INT3_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_B_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_B_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_INT3_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x3)
#define GPIO_B_INT3_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_B_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_B_INT3_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x3, GPIO_B_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_B_INT3_ROUTE_MAPPING_0_VAL_RANGE                   1:0
#define GPIO_B_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_B_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define GPIO_B_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_B_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_B_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_B_INT4_ROUTE_MAPPING_0
#define GPIO_B_INT4_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x4904)
#define GPIO_B_INT4_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_B_INT4_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_B_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_B_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_B_INT4_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_B_INT4_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_B_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_B_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_INT4_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x3)
#define GPIO_B_INT4_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_B_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_B_INT4_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x3, GPIO_B_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_B_INT4_ROUTE_MAPPING_0_VAL_RANGE                   1:0
#define GPIO_B_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_B_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define GPIO_B_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_B_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_B_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_B_INT5_ROUTE_MAPPING_0
#define GPIO_B_INT5_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x4908)
#define GPIO_B_INT5_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_B_INT5_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_B_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_B_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_B_INT5_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_B_INT5_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_B_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_B_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_INT5_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x3)
#define GPIO_B_INT5_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_B_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_B_INT5_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x3, GPIO_B_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_B_INT5_ROUTE_MAPPING_0_VAL_RANGE                   1:0
#define GPIO_B_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_B_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define GPIO_B_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_B_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_B_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_B_INT6_ROUTE_MAPPING_0
#define GPIO_B_INT6_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x490c)
#define GPIO_B_INT6_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_B_INT6_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_B_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_B_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_B_INT6_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_B_INT6_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_B_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_B_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_INT6_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x3)
#define GPIO_B_INT6_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_B_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_B_INT6_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x3, GPIO_B_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_B_INT6_ROUTE_MAPPING_0_VAL_RANGE                   1:0
#define GPIO_B_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_B_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define GPIO_B_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_B_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_B_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_B_INT7_ROUTE_MAPPING_0
#define GPIO_B_INT7_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x4910)
#define GPIO_B_INT7_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_B_INT7_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_B_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_B_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_B_INT7_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_B_INT7_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_B_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_B_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_INT7_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x3)
#define GPIO_B_INT7_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_B_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_B_INT7_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x3, GPIO_B_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_B_INT7_ROUTE_MAPPING_0_VAL_RANGE                   1:0
#define GPIO_B_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_B_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define GPIO_B_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_B_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_B_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_CTL4_SPARE_0
#define GPIO_CTL4_SPARE_0                       _MK_ADDR_CONST(0x4914)
#define GPIO_CTL4_SPARE_0_SECURE                        0x0
#define GPIO_CTL4_SPARE_0_DUAL                  0x0
#define GPIO_CTL4_SPARE_0_SCR                   0
#define GPIO_CTL4_SPARE_0_WORD_COUNT                    0x1
#define GPIO_CTL4_SPARE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SPARE_0_RESET_MASK                    _MK_MASK_CONST(0xffff)
#define GPIO_CTL4_SPARE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SPARE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SPARE_0_READ_MASK                     _MK_MASK_CONST(0xffff)
#define GPIO_CTL4_SPARE_0_WRITE_MASK                    _MK_MASK_CONST(0xffff)
#define GPIO_CTL4_SPARE_0_SPARE_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_CTL4_SPARE_0_SPARE_FIELD                   _MK_FIELD_CONST(0xffff, GPIO_CTL4_SPARE_0_SPARE_SHIFT)
#define GPIO_CTL4_SPARE_0_SPARE_RANGE                   15:0
#define GPIO_CTL4_SPARE_0_SPARE_WOFFSET                 0x0
#define GPIO_CTL4_SPARE_0_SPARE_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SPARE_0_SPARE_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define GPIO_CTL4_SPARE_0_SPARE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SPARE_0_SPARE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SPARE_0_SPARE_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL4_SPARE_0_SPARE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_O_VM_00_0
#define GPIO_O_VM_00_0                  _MK_ADDR_CONST(0x5000)
#define GPIO_O_VM_00_0_SECURE                   0x0
#define GPIO_O_VM_00_0_DUAL                     0x0
#define GPIO_O_VM_00_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_O_VM_00_0_WORD_COUNT                       0x1
#define GPIO_O_VM_00_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_O_VM_00_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_O_VM_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_O_VM_00_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_O_VM_00_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_O_VM_00_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_O_VM_00_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_00_0_VM1_SHIFT)
#define GPIO_O_VM_00_0_VM1_RANGE                        1:0
#define GPIO_O_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_O_VM_00_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_00_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_00_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_00_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_VM_00_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_VM_00_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_O_VM_00_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_O_VM_00_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_00_0_VM2_SHIFT)
#define GPIO_O_VM_00_0_VM2_RANGE                        3:2
#define GPIO_O_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_O_VM_00_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_00_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_00_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_00_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_VM_00_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_VM_00_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_O_VM_00_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_O_VM_00_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_00_0_VM3_SHIFT)
#define GPIO_O_VM_00_0_VM3_RANGE                        5:4
#define GPIO_O_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_O_VM_00_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_00_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_00_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_00_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_VM_00_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_VM_00_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_O_VM_00_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_O_VM_00_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_00_0_VM4_SHIFT)
#define GPIO_O_VM_00_0_VM4_RANGE                        7:6
#define GPIO_O_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_O_VM_00_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_00_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_00_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_00_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_VM_00_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_VM_00_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_O_VM_00_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_O_VM_00_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_00_0_VM5_SHIFT)
#define GPIO_O_VM_00_0_VM5_RANGE                        9:8
#define GPIO_O_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_O_VM_00_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_00_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_00_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_00_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_VM_00_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_VM_00_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_O_VM_00_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_O_VM_00_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_00_0_VM6_SHIFT)
#define GPIO_O_VM_00_0_VM6_RANGE                        11:10
#define GPIO_O_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_O_VM_00_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_00_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_00_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_00_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_VM_00_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_VM_00_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_O_VM_00_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_O_VM_00_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_00_0_VM7_SHIFT)
#define GPIO_O_VM_00_0_VM7_RANGE                        13:12
#define GPIO_O_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_O_VM_00_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_00_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_00_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_00_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_VM_00_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_VM_00_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_O_VM_00_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_O_VM_00_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_00_0_VM8_SHIFT)
#define GPIO_O_VM_00_0_VM8_RANGE                        15:14
#define GPIO_O_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_O_VM_00_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_00_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_00_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_00_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_VM_00_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_VM_00_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_O_SCR_00_0
#define GPIO_O_SCR_00_0                 _MK_ADDR_CONST(0x5004)
#define GPIO_O_SCR_00_0_SECURE                  0x0
#define GPIO_O_SCR_00_0_DUAL                    0x0
#define GPIO_O_SCR_00_0_SCR                     0
#define GPIO_O_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_O_SCR_00_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_O_SCR_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_O_SCR_00_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_O_SCR_00_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_O_SCR_00_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_O_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_O_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_O_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_O_SCR_00_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_00_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_00_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_O_SCR_00_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_O_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_O_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_O_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_O_SCR_00_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_00_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_00_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_O_SCR_00_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_O_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_O_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_O_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_O_SCR_00_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_00_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_00_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_O_SCR_00_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_O_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_O_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_O_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_O_SCR_00_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_O_SCR_00_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_00_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_O_SCR_00_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_00_0_PR7_SHIFT)
#define GPIO_O_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_O_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_O_SCR_00_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_00_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_00_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_O_SCR_00_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_00_0_PR6_SHIFT)
#define GPIO_O_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_O_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_O_SCR_00_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_00_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_00_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_O_SCR_00_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_00_0_PR5_SHIFT)
#define GPIO_O_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_O_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_O_SCR_00_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_00_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_00_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_O_SCR_00_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_00_0_PR4_SHIFT)
#define GPIO_O_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_O_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_O_SCR_00_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_00_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_00_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_O_SCR_00_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_00_0_PR3_SHIFT)
#define GPIO_O_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_O_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_O_SCR_00_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_00_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_00_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_O_SCR_00_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_00_0_PR2_SHIFT)
#define GPIO_O_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_O_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_O_SCR_00_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_00_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_00_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_O_SCR_00_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_00_0_PR1_SHIFT)
#define GPIO_O_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_O_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_O_SCR_00_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_00_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_00_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_O_SCR_00_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_00_0_PR0_SHIFT)
#define GPIO_O_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_O_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_O_SCR_00_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_00_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_00_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_O_SCR_00_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_00_0_G7W_SHIFT)
#define GPIO_O_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_O_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_O_SCR_00_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_00_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_00_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_O_SCR_00_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_00_0_G6W_SHIFT)
#define GPIO_O_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_O_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_O_SCR_00_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_00_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_00_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_O_SCR_00_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_00_0_G5W_SHIFT)
#define GPIO_O_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_O_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_O_SCR_00_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_00_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_00_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_O_SCR_00_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_00_0_G4W_SHIFT)
#define GPIO_O_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_O_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_O_SCR_00_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_00_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_00_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_O_SCR_00_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_00_0_G3W_SHIFT)
#define GPIO_O_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_O_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_O_SCR_00_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_00_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_00_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_O_SCR_00_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_00_0_G2W_SHIFT)
#define GPIO_O_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_O_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_O_SCR_00_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_00_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_00_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_O_SCR_00_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_00_0_G1W_SHIFT)
#define GPIO_O_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_O_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_O_SCR_00_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_00_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_00_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_O_SCR_00_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_00_0_G0W_SHIFT)
#define GPIO_O_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_O_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_O_SCR_00_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_00_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_00_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_O_SCR_00_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_00_0_G7R_SHIFT)
#define GPIO_O_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_O_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_O_SCR_00_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_00_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_00_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_O_SCR_00_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_00_0_G6R_SHIFT)
#define GPIO_O_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_O_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_O_SCR_00_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_00_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_00_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_O_SCR_00_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_00_0_G5R_SHIFT)
#define GPIO_O_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_O_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_O_SCR_00_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_00_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_00_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_O_SCR_00_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_00_0_G4R_SHIFT)
#define GPIO_O_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_O_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_O_SCR_00_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_00_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_00_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_O_SCR_00_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_00_0_G3R_SHIFT)
#define GPIO_O_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_O_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_O_SCR_00_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_00_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_00_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_O_SCR_00_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_00_0_G2R_SHIFT)
#define GPIO_O_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_O_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_O_SCR_00_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_00_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_00_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_O_SCR_00_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_00_0_G1R_SHIFT)
#define GPIO_O_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_O_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_O_SCR_00_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_00_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_00_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_O_SCR_00_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_00_0_G0R_SHIFT)
#define GPIO_O_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_O_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_O_SCR_00_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_00_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_00_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_O_VM_01_0
#define GPIO_O_VM_01_0                  _MK_ADDR_CONST(0x5008)
#define GPIO_O_VM_01_0_SECURE                   0x0
#define GPIO_O_VM_01_0_DUAL                     0x0
#define GPIO_O_VM_01_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_O_VM_01_0_WORD_COUNT                       0x1
#define GPIO_O_VM_01_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_O_VM_01_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_O_VM_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_O_VM_01_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_O_VM_01_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_O_VM_01_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_O_VM_01_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_01_0_VM1_SHIFT)
#define GPIO_O_VM_01_0_VM1_RANGE                        1:0
#define GPIO_O_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_O_VM_01_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_01_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_01_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_01_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_VM_01_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_VM_01_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_O_VM_01_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_O_VM_01_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_01_0_VM2_SHIFT)
#define GPIO_O_VM_01_0_VM2_RANGE                        3:2
#define GPIO_O_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_O_VM_01_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_01_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_01_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_01_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_VM_01_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_VM_01_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_O_VM_01_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_O_VM_01_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_01_0_VM3_SHIFT)
#define GPIO_O_VM_01_0_VM3_RANGE                        5:4
#define GPIO_O_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_O_VM_01_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_01_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_01_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_01_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_VM_01_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_VM_01_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_O_VM_01_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_O_VM_01_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_01_0_VM4_SHIFT)
#define GPIO_O_VM_01_0_VM4_RANGE                        7:6
#define GPIO_O_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_O_VM_01_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_01_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_01_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_01_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_VM_01_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_VM_01_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_O_VM_01_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_O_VM_01_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_01_0_VM5_SHIFT)
#define GPIO_O_VM_01_0_VM5_RANGE                        9:8
#define GPIO_O_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_O_VM_01_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_01_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_01_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_01_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_VM_01_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_VM_01_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_O_VM_01_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_O_VM_01_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_01_0_VM6_SHIFT)
#define GPIO_O_VM_01_0_VM6_RANGE                        11:10
#define GPIO_O_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_O_VM_01_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_01_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_01_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_01_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_VM_01_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_VM_01_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_O_VM_01_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_O_VM_01_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_01_0_VM7_SHIFT)
#define GPIO_O_VM_01_0_VM7_RANGE                        13:12
#define GPIO_O_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_O_VM_01_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_01_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_01_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_01_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_VM_01_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_VM_01_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_O_VM_01_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_O_VM_01_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_01_0_VM8_SHIFT)
#define GPIO_O_VM_01_0_VM8_RANGE                        15:14
#define GPIO_O_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_O_VM_01_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_01_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_01_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_01_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_VM_01_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_VM_01_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_O_SCR_01_0
#define GPIO_O_SCR_01_0                 _MK_ADDR_CONST(0x500c)
#define GPIO_O_SCR_01_0_SECURE                  0x0
#define GPIO_O_SCR_01_0_DUAL                    0x0
#define GPIO_O_SCR_01_0_SCR                     0
#define GPIO_O_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_O_SCR_01_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_O_SCR_01_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_O_SCR_01_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_O_SCR_01_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_O_SCR_01_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_O_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_O_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_O_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_O_SCR_01_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_01_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_01_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_O_SCR_01_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_O_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_O_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_O_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_O_SCR_01_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_01_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_01_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_O_SCR_01_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_O_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_O_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_O_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_O_SCR_01_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_01_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_01_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_O_SCR_01_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_O_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_O_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_O_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_O_SCR_01_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_O_SCR_01_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_01_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_O_SCR_01_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_01_0_PR7_SHIFT)
#define GPIO_O_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_O_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_O_SCR_01_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_01_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_01_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_O_SCR_01_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_01_0_PR6_SHIFT)
#define GPIO_O_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_O_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_O_SCR_01_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_01_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_01_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_O_SCR_01_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_01_0_PR5_SHIFT)
#define GPIO_O_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_O_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_O_SCR_01_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_01_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_01_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_O_SCR_01_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_01_0_PR4_SHIFT)
#define GPIO_O_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_O_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_O_SCR_01_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_01_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_01_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_O_SCR_01_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_01_0_PR3_SHIFT)
#define GPIO_O_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_O_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_O_SCR_01_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_01_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_01_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_O_SCR_01_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_01_0_PR2_SHIFT)
#define GPIO_O_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_O_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_O_SCR_01_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_01_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_01_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_O_SCR_01_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_01_0_PR1_SHIFT)
#define GPIO_O_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_O_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_O_SCR_01_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_01_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_01_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_O_SCR_01_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_01_0_PR0_SHIFT)
#define GPIO_O_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_O_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_O_SCR_01_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_01_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_01_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_O_SCR_01_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_01_0_G7W_SHIFT)
#define GPIO_O_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_O_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_O_SCR_01_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_01_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_01_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_O_SCR_01_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_01_0_G6W_SHIFT)
#define GPIO_O_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_O_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_O_SCR_01_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_01_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_01_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_O_SCR_01_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_01_0_G5W_SHIFT)
#define GPIO_O_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_O_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_O_SCR_01_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_01_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_01_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_O_SCR_01_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_01_0_G4W_SHIFT)
#define GPIO_O_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_O_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_O_SCR_01_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_01_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_01_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_O_SCR_01_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_01_0_G3W_SHIFT)
#define GPIO_O_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_O_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_O_SCR_01_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_01_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_01_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_O_SCR_01_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_01_0_G2W_SHIFT)
#define GPIO_O_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_O_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_O_SCR_01_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_01_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_01_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_O_SCR_01_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_01_0_G1W_SHIFT)
#define GPIO_O_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_O_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_O_SCR_01_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_01_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_01_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_O_SCR_01_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_01_0_G0W_SHIFT)
#define GPIO_O_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_O_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_O_SCR_01_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_01_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_01_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_O_SCR_01_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_01_0_G7R_SHIFT)
#define GPIO_O_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_O_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_O_SCR_01_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_01_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_01_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_O_SCR_01_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_01_0_G6R_SHIFT)
#define GPIO_O_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_O_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_O_SCR_01_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_01_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_01_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_O_SCR_01_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_01_0_G5R_SHIFT)
#define GPIO_O_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_O_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_O_SCR_01_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_01_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_01_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_O_SCR_01_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_01_0_G4R_SHIFT)
#define GPIO_O_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_O_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_O_SCR_01_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_01_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_01_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_O_SCR_01_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_01_0_G3R_SHIFT)
#define GPIO_O_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_O_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_O_SCR_01_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_01_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_01_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_O_SCR_01_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_01_0_G2R_SHIFT)
#define GPIO_O_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_O_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_O_SCR_01_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_01_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_01_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_O_SCR_01_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_01_0_G1R_SHIFT)
#define GPIO_O_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_O_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_O_SCR_01_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_01_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_01_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_O_SCR_01_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_01_0_G0R_SHIFT)
#define GPIO_O_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_O_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_O_SCR_01_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_01_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_01_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_O_VM_02_0
#define GPIO_O_VM_02_0                  _MK_ADDR_CONST(0x5010)
#define GPIO_O_VM_02_0_SECURE                   0x0
#define GPIO_O_VM_02_0_DUAL                     0x0
#define GPIO_O_VM_02_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_O_VM_02_0_WORD_COUNT                       0x1
#define GPIO_O_VM_02_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_O_VM_02_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_O_VM_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_O_VM_02_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_O_VM_02_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_O_VM_02_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_O_VM_02_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_02_0_VM1_SHIFT)
#define GPIO_O_VM_02_0_VM1_RANGE                        1:0
#define GPIO_O_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_O_VM_02_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_02_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_02_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_02_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_VM_02_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_VM_02_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_O_VM_02_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_O_VM_02_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_02_0_VM2_SHIFT)
#define GPIO_O_VM_02_0_VM2_RANGE                        3:2
#define GPIO_O_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_O_VM_02_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_02_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_02_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_02_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_VM_02_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_VM_02_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_O_VM_02_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_O_VM_02_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_02_0_VM3_SHIFT)
#define GPIO_O_VM_02_0_VM3_RANGE                        5:4
#define GPIO_O_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_O_VM_02_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_02_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_02_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_02_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_VM_02_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_VM_02_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_O_VM_02_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_O_VM_02_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_02_0_VM4_SHIFT)
#define GPIO_O_VM_02_0_VM4_RANGE                        7:6
#define GPIO_O_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_O_VM_02_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_02_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_02_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_02_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_VM_02_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_VM_02_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_O_VM_02_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_O_VM_02_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_02_0_VM5_SHIFT)
#define GPIO_O_VM_02_0_VM5_RANGE                        9:8
#define GPIO_O_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_O_VM_02_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_02_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_02_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_02_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_VM_02_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_VM_02_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_O_VM_02_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_O_VM_02_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_02_0_VM6_SHIFT)
#define GPIO_O_VM_02_0_VM6_RANGE                        11:10
#define GPIO_O_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_O_VM_02_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_02_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_02_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_02_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_VM_02_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_VM_02_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_O_VM_02_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_O_VM_02_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_02_0_VM7_SHIFT)
#define GPIO_O_VM_02_0_VM7_RANGE                        13:12
#define GPIO_O_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_O_VM_02_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_02_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_02_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_02_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_VM_02_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_VM_02_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_O_VM_02_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_O_VM_02_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_02_0_VM8_SHIFT)
#define GPIO_O_VM_02_0_VM8_RANGE                        15:14
#define GPIO_O_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_O_VM_02_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_02_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_02_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_02_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_VM_02_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_VM_02_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_O_SCR_02_0
#define GPIO_O_SCR_02_0                 _MK_ADDR_CONST(0x5014)
#define GPIO_O_SCR_02_0_SECURE                  0x0
#define GPIO_O_SCR_02_0_DUAL                    0x0
#define GPIO_O_SCR_02_0_SCR                     0
#define GPIO_O_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_O_SCR_02_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_O_SCR_02_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_O_SCR_02_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_O_SCR_02_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_O_SCR_02_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_O_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_O_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_O_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_O_SCR_02_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_02_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_02_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_O_SCR_02_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_O_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_O_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_O_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_O_SCR_02_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_02_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_02_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_O_SCR_02_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_O_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_O_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_O_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_O_SCR_02_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_02_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_02_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_O_SCR_02_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_O_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_O_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_O_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_O_SCR_02_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_O_SCR_02_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_02_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_O_SCR_02_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_02_0_PR7_SHIFT)
#define GPIO_O_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_O_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_O_SCR_02_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_02_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_02_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_O_SCR_02_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_02_0_PR6_SHIFT)
#define GPIO_O_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_O_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_O_SCR_02_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_02_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_02_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_O_SCR_02_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_02_0_PR5_SHIFT)
#define GPIO_O_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_O_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_O_SCR_02_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_02_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_02_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_O_SCR_02_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_02_0_PR4_SHIFT)
#define GPIO_O_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_O_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_O_SCR_02_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_02_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_02_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_O_SCR_02_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_02_0_PR3_SHIFT)
#define GPIO_O_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_O_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_O_SCR_02_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_02_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_02_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_O_SCR_02_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_02_0_PR2_SHIFT)
#define GPIO_O_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_O_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_O_SCR_02_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_02_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_02_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_O_SCR_02_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_02_0_PR1_SHIFT)
#define GPIO_O_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_O_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_O_SCR_02_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_02_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_02_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_O_SCR_02_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_02_0_PR0_SHIFT)
#define GPIO_O_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_O_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_O_SCR_02_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_02_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_02_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_O_SCR_02_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_02_0_G7W_SHIFT)
#define GPIO_O_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_O_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_O_SCR_02_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_02_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_02_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_O_SCR_02_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_02_0_G6W_SHIFT)
#define GPIO_O_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_O_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_O_SCR_02_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_02_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_02_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_O_SCR_02_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_02_0_G5W_SHIFT)
#define GPIO_O_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_O_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_O_SCR_02_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_02_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_02_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_O_SCR_02_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_02_0_G4W_SHIFT)
#define GPIO_O_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_O_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_O_SCR_02_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_02_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_02_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_O_SCR_02_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_02_0_G3W_SHIFT)
#define GPIO_O_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_O_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_O_SCR_02_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_02_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_02_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_O_SCR_02_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_02_0_G2W_SHIFT)
#define GPIO_O_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_O_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_O_SCR_02_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_02_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_02_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_O_SCR_02_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_02_0_G1W_SHIFT)
#define GPIO_O_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_O_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_O_SCR_02_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_02_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_02_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_O_SCR_02_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_02_0_G0W_SHIFT)
#define GPIO_O_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_O_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_O_SCR_02_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_02_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_02_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_O_SCR_02_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_02_0_G7R_SHIFT)
#define GPIO_O_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_O_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_O_SCR_02_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_02_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_02_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_O_SCR_02_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_02_0_G6R_SHIFT)
#define GPIO_O_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_O_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_O_SCR_02_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_02_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_02_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_O_SCR_02_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_02_0_G5R_SHIFT)
#define GPIO_O_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_O_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_O_SCR_02_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_02_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_02_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_O_SCR_02_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_02_0_G4R_SHIFT)
#define GPIO_O_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_O_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_O_SCR_02_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_02_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_02_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_O_SCR_02_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_02_0_G3R_SHIFT)
#define GPIO_O_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_O_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_O_SCR_02_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_02_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_02_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_O_SCR_02_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_02_0_G2R_SHIFT)
#define GPIO_O_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_O_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_O_SCR_02_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_02_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_02_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_O_SCR_02_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_02_0_G1R_SHIFT)
#define GPIO_O_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_O_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_O_SCR_02_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_02_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_02_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_O_SCR_02_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_02_0_G0R_SHIFT)
#define GPIO_O_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_O_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_O_SCR_02_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_02_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_02_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_O_VM_03_0
#define GPIO_O_VM_03_0                  _MK_ADDR_CONST(0x5018)
#define GPIO_O_VM_03_0_SECURE                   0x0
#define GPIO_O_VM_03_0_DUAL                     0x0
#define GPIO_O_VM_03_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_O_VM_03_0_WORD_COUNT                       0x1
#define GPIO_O_VM_03_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_O_VM_03_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_O_VM_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_O_VM_03_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_O_VM_03_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_O_VM_03_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_O_VM_03_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_03_0_VM1_SHIFT)
#define GPIO_O_VM_03_0_VM1_RANGE                        1:0
#define GPIO_O_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_O_VM_03_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_03_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_03_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_03_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_VM_03_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_VM_03_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_O_VM_03_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_O_VM_03_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_03_0_VM2_SHIFT)
#define GPIO_O_VM_03_0_VM2_RANGE                        3:2
#define GPIO_O_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_O_VM_03_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_03_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_03_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_03_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_VM_03_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_VM_03_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_O_VM_03_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_O_VM_03_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_03_0_VM3_SHIFT)
#define GPIO_O_VM_03_0_VM3_RANGE                        5:4
#define GPIO_O_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_O_VM_03_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_03_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_03_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_03_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_VM_03_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_VM_03_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_O_VM_03_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_O_VM_03_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_03_0_VM4_SHIFT)
#define GPIO_O_VM_03_0_VM4_RANGE                        7:6
#define GPIO_O_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_O_VM_03_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_03_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_03_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_03_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_VM_03_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_VM_03_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_O_VM_03_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_O_VM_03_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_03_0_VM5_SHIFT)
#define GPIO_O_VM_03_0_VM5_RANGE                        9:8
#define GPIO_O_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_O_VM_03_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_03_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_03_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_03_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_VM_03_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_VM_03_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_O_VM_03_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_O_VM_03_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_03_0_VM6_SHIFT)
#define GPIO_O_VM_03_0_VM6_RANGE                        11:10
#define GPIO_O_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_O_VM_03_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_03_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_03_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_03_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_VM_03_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_VM_03_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_O_VM_03_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_O_VM_03_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_03_0_VM7_SHIFT)
#define GPIO_O_VM_03_0_VM7_RANGE                        13:12
#define GPIO_O_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_O_VM_03_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_03_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_03_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_03_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_VM_03_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_VM_03_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_O_VM_03_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_O_VM_03_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_03_0_VM8_SHIFT)
#define GPIO_O_VM_03_0_VM8_RANGE                        15:14
#define GPIO_O_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_O_VM_03_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_03_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_03_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_03_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_VM_03_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_VM_03_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_O_SCR_03_0
#define GPIO_O_SCR_03_0                 _MK_ADDR_CONST(0x501c)
#define GPIO_O_SCR_03_0_SECURE                  0x0
#define GPIO_O_SCR_03_0_DUAL                    0x0
#define GPIO_O_SCR_03_0_SCR                     0
#define GPIO_O_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_O_SCR_03_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_O_SCR_03_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_O_SCR_03_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_O_SCR_03_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_O_SCR_03_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_O_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_O_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_O_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_O_SCR_03_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_03_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_03_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_O_SCR_03_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_O_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_O_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_O_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_O_SCR_03_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_03_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_03_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_O_SCR_03_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_O_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_O_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_O_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_O_SCR_03_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_03_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_03_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_O_SCR_03_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_O_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_O_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_O_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_O_SCR_03_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_O_SCR_03_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_03_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_O_SCR_03_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_03_0_PR7_SHIFT)
#define GPIO_O_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_O_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_O_SCR_03_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_03_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_03_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_O_SCR_03_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_03_0_PR6_SHIFT)
#define GPIO_O_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_O_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_O_SCR_03_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_03_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_03_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_O_SCR_03_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_03_0_PR5_SHIFT)
#define GPIO_O_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_O_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_O_SCR_03_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_03_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_03_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_O_SCR_03_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_03_0_PR4_SHIFT)
#define GPIO_O_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_O_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_O_SCR_03_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_03_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_03_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_O_SCR_03_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_03_0_PR3_SHIFT)
#define GPIO_O_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_O_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_O_SCR_03_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_03_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_03_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_O_SCR_03_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_03_0_PR2_SHIFT)
#define GPIO_O_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_O_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_O_SCR_03_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_03_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_03_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_O_SCR_03_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_03_0_PR1_SHIFT)
#define GPIO_O_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_O_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_O_SCR_03_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_03_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_03_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_O_SCR_03_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_03_0_PR0_SHIFT)
#define GPIO_O_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_O_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_O_SCR_03_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_03_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_03_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_O_SCR_03_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_03_0_G7W_SHIFT)
#define GPIO_O_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_O_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_O_SCR_03_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_03_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_03_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_O_SCR_03_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_03_0_G6W_SHIFT)
#define GPIO_O_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_O_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_O_SCR_03_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_03_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_03_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_O_SCR_03_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_03_0_G5W_SHIFT)
#define GPIO_O_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_O_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_O_SCR_03_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_03_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_03_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_O_SCR_03_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_03_0_G4W_SHIFT)
#define GPIO_O_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_O_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_O_SCR_03_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_03_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_03_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_O_SCR_03_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_03_0_G3W_SHIFT)
#define GPIO_O_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_O_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_O_SCR_03_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_03_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_03_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_O_SCR_03_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_03_0_G2W_SHIFT)
#define GPIO_O_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_O_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_O_SCR_03_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_03_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_03_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_O_SCR_03_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_03_0_G1W_SHIFT)
#define GPIO_O_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_O_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_O_SCR_03_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_03_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_03_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_O_SCR_03_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_03_0_G0W_SHIFT)
#define GPIO_O_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_O_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_O_SCR_03_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_03_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_03_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_O_SCR_03_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_03_0_G7R_SHIFT)
#define GPIO_O_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_O_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_O_SCR_03_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_03_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_03_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_O_SCR_03_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_03_0_G6R_SHIFT)
#define GPIO_O_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_O_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_O_SCR_03_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_03_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_03_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_O_SCR_03_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_03_0_G5R_SHIFT)
#define GPIO_O_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_O_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_O_SCR_03_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_03_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_03_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_O_SCR_03_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_03_0_G4R_SHIFT)
#define GPIO_O_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_O_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_O_SCR_03_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_03_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_03_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_O_SCR_03_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_03_0_G3R_SHIFT)
#define GPIO_O_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_O_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_O_SCR_03_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_03_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_03_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_O_SCR_03_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_03_0_G2R_SHIFT)
#define GPIO_O_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_O_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_O_SCR_03_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_03_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_03_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_O_SCR_03_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_03_0_G1R_SHIFT)
#define GPIO_O_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_O_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_O_SCR_03_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_03_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_03_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_O_SCR_03_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_03_0_G0R_SHIFT)
#define GPIO_O_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_O_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_O_SCR_03_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_03_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_03_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_O_VM_04_0
#define GPIO_O_VM_04_0                  _MK_ADDR_CONST(0x5020)
#define GPIO_O_VM_04_0_SECURE                   0x0
#define GPIO_O_VM_04_0_DUAL                     0x0
#define GPIO_O_VM_04_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_O_VM_04_0_WORD_COUNT                       0x1
#define GPIO_O_VM_04_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_O_VM_04_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_O_VM_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_O_VM_04_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_O_VM_04_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_O_VM_04_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_O_VM_04_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_04_0_VM1_SHIFT)
#define GPIO_O_VM_04_0_VM1_RANGE                        1:0
#define GPIO_O_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_O_VM_04_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_04_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_04_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_04_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_VM_04_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_VM_04_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_O_VM_04_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_O_VM_04_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_04_0_VM2_SHIFT)
#define GPIO_O_VM_04_0_VM2_RANGE                        3:2
#define GPIO_O_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_O_VM_04_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_04_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_04_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_04_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_VM_04_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_VM_04_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_O_VM_04_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_O_VM_04_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_04_0_VM3_SHIFT)
#define GPIO_O_VM_04_0_VM3_RANGE                        5:4
#define GPIO_O_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_O_VM_04_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_04_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_04_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_04_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_VM_04_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_VM_04_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_O_VM_04_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_O_VM_04_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_04_0_VM4_SHIFT)
#define GPIO_O_VM_04_0_VM4_RANGE                        7:6
#define GPIO_O_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_O_VM_04_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_04_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_04_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_04_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_VM_04_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_VM_04_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_O_VM_04_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_O_VM_04_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_04_0_VM5_SHIFT)
#define GPIO_O_VM_04_0_VM5_RANGE                        9:8
#define GPIO_O_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_O_VM_04_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_04_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_04_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_04_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_VM_04_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_VM_04_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_O_VM_04_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_O_VM_04_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_04_0_VM6_SHIFT)
#define GPIO_O_VM_04_0_VM6_RANGE                        11:10
#define GPIO_O_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_O_VM_04_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_04_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_04_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_04_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_VM_04_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_VM_04_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_O_VM_04_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_O_VM_04_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_04_0_VM7_SHIFT)
#define GPIO_O_VM_04_0_VM7_RANGE                        13:12
#define GPIO_O_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_O_VM_04_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_04_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_04_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_04_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_VM_04_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_VM_04_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_O_VM_04_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_O_VM_04_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_04_0_VM8_SHIFT)
#define GPIO_O_VM_04_0_VM8_RANGE                        15:14
#define GPIO_O_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_O_VM_04_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_04_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_04_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_04_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_VM_04_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_VM_04_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_O_SCR_04_0
#define GPIO_O_SCR_04_0                 _MK_ADDR_CONST(0x5024)
#define GPIO_O_SCR_04_0_SECURE                  0x0
#define GPIO_O_SCR_04_0_DUAL                    0x0
#define GPIO_O_SCR_04_0_SCR                     0
#define GPIO_O_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_O_SCR_04_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_O_SCR_04_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_O_SCR_04_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_O_SCR_04_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_O_SCR_04_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_O_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_O_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_O_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_O_SCR_04_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_04_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_04_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_O_SCR_04_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_O_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_O_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_O_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_O_SCR_04_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_04_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_04_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_O_SCR_04_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_O_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_O_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_O_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_O_SCR_04_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_04_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_04_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_O_SCR_04_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_O_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_O_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_O_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_O_SCR_04_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_O_SCR_04_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_04_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_O_SCR_04_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_04_0_PR7_SHIFT)
#define GPIO_O_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_O_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_O_SCR_04_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_04_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_04_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_O_SCR_04_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_04_0_PR6_SHIFT)
#define GPIO_O_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_O_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_O_SCR_04_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_04_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_04_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_O_SCR_04_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_04_0_PR5_SHIFT)
#define GPIO_O_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_O_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_O_SCR_04_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_04_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_04_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_O_SCR_04_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_04_0_PR4_SHIFT)
#define GPIO_O_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_O_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_O_SCR_04_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_04_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_04_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_O_SCR_04_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_04_0_PR3_SHIFT)
#define GPIO_O_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_O_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_O_SCR_04_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_04_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_04_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_O_SCR_04_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_04_0_PR2_SHIFT)
#define GPIO_O_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_O_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_O_SCR_04_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_04_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_04_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_O_SCR_04_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_04_0_PR1_SHIFT)
#define GPIO_O_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_O_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_O_SCR_04_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_04_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_04_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_O_SCR_04_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_04_0_PR0_SHIFT)
#define GPIO_O_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_O_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_O_SCR_04_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_04_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_04_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_O_SCR_04_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_04_0_G7W_SHIFT)
#define GPIO_O_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_O_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_O_SCR_04_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_04_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_04_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_O_SCR_04_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_04_0_G6W_SHIFT)
#define GPIO_O_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_O_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_O_SCR_04_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_04_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_04_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_O_SCR_04_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_04_0_G5W_SHIFT)
#define GPIO_O_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_O_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_O_SCR_04_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_04_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_04_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_O_SCR_04_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_04_0_G4W_SHIFT)
#define GPIO_O_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_O_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_O_SCR_04_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_04_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_04_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_O_SCR_04_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_04_0_G3W_SHIFT)
#define GPIO_O_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_O_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_O_SCR_04_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_04_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_04_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_O_SCR_04_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_04_0_G2W_SHIFT)
#define GPIO_O_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_O_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_O_SCR_04_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_04_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_04_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_O_SCR_04_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_04_0_G1W_SHIFT)
#define GPIO_O_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_O_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_O_SCR_04_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_04_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_04_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_O_SCR_04_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_04_0_G0W_SHIFT)
#define GPIO_O_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_O_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_O_SCR_04_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_04_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_04_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_O_SCR_04_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_04_0_G7R_SHIFT)
#define GPIO_O_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_O_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_O_SCR_04_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_04_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_04_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_O_SCR_04_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_04_0_G6R_SHIFT)
#define GPIO_O_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_O_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_O_SCR_04_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_04_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_04_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_O_SCR_04_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_04_0_G5R_SHIFT)
#define GPIO_O_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_O_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_O_SCR_04_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_04_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_04_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_O_SCR_04_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_04_0_G4R_SHIFT)
#define GPIO_O_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_O_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_O_SCR_04_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_04_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_04_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_O_SCR_04_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_04_0_G3R_SHIFT)
#define GPIO_O_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_O_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_O_SCR_04_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_04_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_04_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_O_SCR_04_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_04_0_G2R_SHIFT)
#define GPIO_O_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_O_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_O_SCR_04_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_04_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_04_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_O_SCR_04_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_04_0_G1R_SHIFT)
#define GPIO_O_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_O_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_O_SCR_04_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_04_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_04_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_O_SCR_04_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_04_0_G0R_SHIFT)
#define GPIO_O_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_O_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_O_SCR_04_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_04_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_04_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_O_VM_05_0
#define GPIO_O_VM_05_0                  _MK_ADDR_CONST(0x5028)
#define GPIO_O_VM_05_0_SECURE                   0x0
#define GPIO_O_VM_05_0_DUAL                     0x0
#define GPIO_O_VM_05_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_O_VM_05_0_WORD_COUNT                       0x1
#define GPIO_O_VM_05_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_O_VM_05_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_O_VM_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_O_VM_05_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_O_VM_05_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_O_VM_05_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_O_VM_05_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_05_0_VM1_SHIFT)
#define GPIO_O_VM_05_0_VM1_RANGE                        1:0
#define GPIO_O_VM_05_0_VM1_WOFFSET                      0x0
#define GPIO_O_VM_05_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_05_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_05_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_05_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_VM_05_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_VM_05_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_O_VM_05_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_O_VM_05_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_05_0_VM2_SHIFT)
#define GPIO_O_VM_05_0_VM2_RANGE                        3:2
#define GPIO_O_VM_05_0_VM2_WOFFSET                      0x0
#define GPIO_O_VM_05_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_05_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_05_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_05_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_VM_05_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_VM_05_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_O_VM_05_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_O_VM_05_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_05_0_VM3_SHIFT)
#define GPIO_O_VM_05_0_VM3_RANGE                        5:4
#define GPIO_O_VM_05_0_VM3_WOFFSET                      0x0
#define GPIO_O_VM_05_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_05_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_05_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_05_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_VM_05_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_VM_05_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_O_VM_05_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_O_VM_05_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_05_0_VM4_SHIFT)
#define GPIO_O_VM_05_0_VM4_RANGE                        7:6
#define GPIO_O_VM_05_0_VM4_WOFFSET                      0x0
#define GPIO_O_VM_05_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_05_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_05_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_05_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_VM_05_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_VM_05_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_O_VM_05_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_O_VM_05_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_05_0_VM5_SHIFT)
#define GPIO_O_VM_05_0_VM5_RANGE                        9:8
#define GPIO_O_VM_05_0_VM5_WOFFSET                      0x0
#define GPIO_O_VM_05_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_05_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_05_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_05_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_VM_05_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_VM_05_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_O_VM_05_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_O_VM_05_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_05_0_VM6_SHIFT)
#define GPIO_O_VM_05_0_VM6_RANGE                        11:10
#define GPIO_O_VM_05_0_VM6_WOFFSET                      0x0
#define GPIO_O_VM_05_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_05_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_05_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_05_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_VM_05_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_VM_05_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_O_VM_05_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_O_VM_05_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_05_0_VM7_SHIFT)
#define GPIO_O_VM_05_0_VM7_RANGE                        13:12
#define GPIO_O_VM_05_0_VM7_WOFFSET                      0x0
#define GPIO_O_VM_05_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_05_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_05_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_05_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_VM_05_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_VM_05_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_O_VM_05_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_O_VM_05_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_O_VM_05_0_VM8_SHIFT)
#define GPIO_O_VM_05_0_VM8_RANGE                        15:14
#define GPIO_O_VM_05_0_VM8_WOFFSET                      0x0
#define GPIO_O_VM_05_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_O_VM_05_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_O_VM_05_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_VM_05_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_VM_05_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_VM_05_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_O_SCR_05_0
#define GPIO_O_SCR_05_0                 _MK_ADDR_CONST(0x502c)
#define GPIO_O_SCR_05_0_SECURE                  0x0
#define GPIO_O_SCR_05_0_DUAL                    0x0
#define GPIO_O_SCR_05_0_SCR                     0
#define GPIO_O_SCR_05_0_WORD_COUNT                      0x1
#define GPIO_O_SCR_05_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_O_SCR_05_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_O_SCR_05_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_O_SCR_05_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_O_SCR_05_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_O_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_O_SCR_05_0_SEC_LCK_RANGE                   29:29
#define GPIO_O_SCR_05_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_O_SCR_05_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_05_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_05_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_O_SCR_05_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_O_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_O_SCR_05_0_SEC_WEN_RANGE                   28:28
#define GPIO_O_SCR_05_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_O_SCR_05_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_05_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_05_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_O_SCR_05_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_O_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_O_SCR_05_0_SEC_REN_RANGE                   27:27
#define GPIO_O_SCR_05_0_SEC_REN_WOFFSET                 0x0
#define GPIO_O_SCR_05_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_05_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_05_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_O_SCR_05_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_O_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_O_SCR_05_0_SEC_OWNER_RANGE                 26:24
#define GPIO_O_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_O_SCR_05_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_O_SCR_05_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_05_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_O_SCR_05_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_05_0_PR7_SHIFT)
#define GPIO_O_SCR_05_0_PR7_RANGE                       23:23
#define GPIO_O_SCR_05_0_PR7_WOFFSET                     0x0
#define GPIO_O_SCR_05_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_05_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_05_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_O_SCR_05_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_05_0_PR6_SHIFT)
#define GPIO_O_SCR_05_0_PR6_RANGE                       22:22
#define GPIO_O_SCR_05_0_PR6_WOFFSET                     0x0
#define GPIO_O_SCR_05_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_05_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_05_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_O_SCR_05_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_05_0_PR5_SHIFT)
#define GPIO_O_SCR_05_0_PR5_RANGE                       21:21
#define GPIO_O_SCR_05_0_PR5_WOFFSET                     0x0
#define GPIO_O_SCR_05_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_05_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_05_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_O_SCR_05_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_05_0_PR4_SHIFT)
#define GPIO_O_SCR_05_0_PR4_RANGE                       20:20
#define GPIO_O_SCR_05_0_PR4_WOFFSET                     0x0
#define GPIO_O_SCR_05_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_05_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_05_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_O_SCR_05_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_05_0_PR3_SHIFT)
#define GPIO_O_SCR_05_0_PR3_RANGE                       19:19
#define GPIO_O_SCR_05_0_PR3_WOFFSET                     0x0
#define GPIO_O_SCR_05_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_05_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_05_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_O_SCR_05_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_05_0_PR2_SHIFT)
#define GPIO_O_SCR_05_0_PR2_RANGE                       18:18
#define GPIO_O_SCR_05_0_PR2_WOFFSET                     0x0
#define GPIO_O_SCR_05_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_05_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_05_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_O_SCR_05_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_05_0_PR1_SHIFT)
#define GPIO_O_SCR_05_0_PR1_RANGE                       17:17
#define GPIO_O_SCR_05_0_PR1_WOFFSET                     0x0
#define GPIO_O_SCR_05_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_05_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_05_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_O_SCR_05_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_05_0_PR0_SHIFT)
#define GPIO_O_SCR_05_0_PR0_RANGE                       16:16
#define GPIO_O_SCR_05_0_PR0_WOFFSET                     0x0
#define GPIO_O_SCR_05_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_05_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_05_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_O_SCR_05_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_05_0_G7W_SHIFT)
#define GPIO_O_SCR_05_0_G7W_RANGE                       15:15
#define GPIO_O_SCR_05_0_G7W_WOFFSET                     0x0
#define GPIO_O_SCR_05_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_05_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_05_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_O_SCR_05_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_05_0_G6W_SHIFT)
#define GPIO_O_SCR_05_0_G6W_RANGE                       14:14
#define GPIO_O_SCR_05_0_G6W_WOFFSET                     0x0
#define GPIO_O_SCR_05_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_05_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_05_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_O_SCR_05_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_05_0_G5W_SHIFT)
#define GPIO_O_SCR_05_0_G5W_RANGE                       13:13
#define GPIO_O_SCR_05_0_G5W_WOFFSET                     0x0
#define GPIO_O_SCR_05_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_05_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_05_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_O_SCR_05_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_05_0_G4W_SHIFT)
#define GPIO_O_SCR_05_0_G4W_RANGE                       12:12
#define GPIO_O_SCR_05_0_G4W_WOFFSET                     0x0
#define GPIO_O_SCR_05_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_05_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_05_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_O_SCR_05_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_05_0_G3W_SHIFT)
#define GPIO_O_SCR_05_0_G3W_RANGE                       11:11
#define GPIO_O_SCR_05_0_G3W_WOFFSET                     0x0
#define GPIO_O_SCR_05_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_05_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_05_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_O_SCR_05_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_05_0_G2W_SHIFT)
#define GPIO_O_SCR_05_0_G2W_RANGE                       10:10
#define GPIO_O_SCR_05_0_G2W_WOFFSET                     0x0
#define GPIO_O_SCR_05_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_05_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_05_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_O_SCR_05_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_05_0_G1W_SHIFT)
#define GPIO_O_SCR_05_0_G1W_RANGE                       9:9
#define GPIO_O_SCR_05_0_G1W_WOFFSET                     0x0
#define GPIO_O_SCR_05_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_05_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_05_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_O_SCR_05_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_05_0_G0W_SHIFT)
#define GPIO_O_SCR_05_0_G0W_RANGE                       8:8
#define GPIO_O_SCR_05_0_G0W_WOFFSET                     0x0
#define GPIO_O_SCR_05_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_05_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_05_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_O_SCR_05_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_05_0_G7R_SHIFT)
#define GPIO_O_SCR_05_0_G7R_RANGE                       7:7
#define GPIO_O_SCR_05_0_G7R_WOFFSET                     0x0
#define GPIO_O_SCR_05_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_05_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_05_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_O_SCR_05_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_05_0_G6R_SHIFT)
#define GPIO_O_SCR_05_0_G6R_RANGE                       6:6
#define GPIO_O_SCR_05_0_G6R_WOFFSET                     0x0
#define GPIO_O_SCR_05_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_05_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_05_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_O_SCR_05_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_05_0_G5R_SHIFT)
#define GPIO_O_SCR_05_0_G5R_RANGE                       5:5
#define GPIO_O_SCR_05_0_G5R_WOFFSET                     0x0
#define GPIO_O_SCR_05_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_05_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_05_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_O_SCR_05_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_05_0_G4R_SHIFT)
#define GPIO_O_SCR_05_0_G4R_RANGE                       4:4
#define GPIO_O_SCR_05_0_G4R_WOFFSET                     0x0
#define GPIO_O_SCR_05_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_05_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_05_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_O_SCR_05_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_05_0_G3R_SHIFT)
#define GPIO_O_SCR_05_0_G3R_RANGE                       3:3
#define GPIO_O_SCR_05_0_G3R_WOFFSET                     0x0
#define GPIO_O_SCR_05_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_05_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_05_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_O_SCR_05_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_05_0_G2R_SHIFT)
#define GPIO_O_SCR_05_0_G2R_RANGE                       2:2
#define GPIO_O_SCR_05_0_G2R_WOFFSET                     0x0
#define GPIO_O_SCR_05_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_05_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_05_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_O_SCR_05_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_05_0_G1R_SHIFT)
#define GPIO_O_SCR_05_0_G1R_RANGE                       1:1
#define GPIO_O_SCR_05_0_G1R_WOFFSET                     0x0
#define GPIO_O_SCR_05_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_05_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_O_SCR_05_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_O_SCR_05_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_SCR_05_0_G0R_SHIFT)
#define GPIO_O_SCR_05_0_G0R_RANGE                       0:0
#define GPIO_O_SCR_05_0_G0R_WOFFSET                     0x0
#define GPIO_O_SCR_05_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_SCR_05_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_SCR_05_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Reserved address 0x5030

// Reserved address 0x5034

// Reserved address 0x5038

// Reserved address 0x503c

// Register GPIO_J_VM_00_0
#define GPIO_J_VM_00_0                  _MK_ADDR_CONST(0x5040)
#define GPIO_J_VM_00_0_SECURE                   0x0
#define GPIO_J_VM_00_0_DUAL                     0x0
#define GPIO_J_VM_00_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_J_VM_00_0_WORD_COUNT                       0x1
#define GPIO_J_VM_00_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_00_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_00_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_00_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_J_VM_00_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_00_0_VM1_SHIFT)
#define GPIO_J_VM_00_0_VM1_RANGE                        1:0
#define GPIO_J_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_J_VM_00_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_00_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_00_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_J_VM_00_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_J_VM_00_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_00_0_VM2_SHIFT)
#define GPIO_J_VM_00_0_VM2_RANGE                        3:2
#define GPIO_J_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_J_VM_00_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_00_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_00_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_J_VM_00_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_J_VM_00_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_00_0_VM3_SHIFT)
#define GPIO_J_VM_00_0_VM3_RANGE                        5:4
#define GPIO_J_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_J_VM_00_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_00_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_00_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_J_VM_00_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_J_VM_00_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_00_0_VM4_SHIFT)
#define GPIO_J_VM_00_0_VM4_RANGE                        7:6
#define GPIO_J_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_J_VM_00_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_00_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_00_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_J_VM_00_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_J_VM_00_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_00_0_VM5_SHIFT)
#define GPIO_J_VM_00_0_VM5_RANGE                        9:8
#define GPIO_J_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_J_VM_00_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_00_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_00_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_J_VM_00_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_J_VM_00_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_00_0_VM6_SHIFT)
#define GPIO_J_VM_00_0_VM6_RANGE                        11:10
#define GPIO_J_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_J_VM_00_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_00_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_00_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_J_VM_00_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_J_VM_00_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_00_0_VM7_SHIFT)
#define GPIO_J_VM_00_0_VM7_RANGE                        13:12
#define GPIO_J_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_J_VM_00_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_00_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_00_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_J_VM_00_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_J_VM_00_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_00_0_VM8_SHIFT)
#define GPIO_J_VM_00_0_VM8_RANGE                        15:14
#define GPIO_J_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_J_VM_00_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_00_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_00_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_J_SCR_00_0
#define GPIO_J_SCR_00_0                 _MK_ADDR_CONST(0x5044)
#define GPIO_J_SCR_00_0_SECURE                  0x0
#define GPIO_J_SCR_00_0_DUAL                    0x0
#define GPIO_J_SCR_00_0_SCR                     0
#define GPIO_J_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_J_SCR_00_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_00_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_00_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_J_SCR_00_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_J_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_J_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_J_SCR_00_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_00_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_J_SCR_00_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_J_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_J_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_J_SCR_00_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_00_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_J_SCR_00_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_J_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_J_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_J_SCR_00_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_00_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_J_SCR_00_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_J_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_J_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_J_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_J_SCR_00_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_J_SCR_00_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_00_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_J_SCR_00_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_PR7_SHIFT)
#define GPIO_J_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_J_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_00_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_J_SCR_00_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_PR6_SHIFT)
#define GPIO_J_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_J_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_00_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_J_SCR_00_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_PR5_SHIFT)
#define GPIO_J_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_J_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_00_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_J_SCR_00_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_PR4_SHIFT)
#define GPIO_J_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_J_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_00_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_J_SCR_00_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_PR3_SHIFT)
#define GPIO_J_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_J_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_00_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_J_SCR_00_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_PR2_SHIFT)
#define GPIO_J_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_J_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_00_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_J_SCR_00_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_PR1_SHIFT)
#define GPIO_J_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_J_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_00_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_J_SCR_00_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_PR0_SHIFT)
#define GPIO_J_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_J_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_00_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_J_SCR_00_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G7W_SHIFT)
#define GPIO_J_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_J_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_00_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_J_SCR_00_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G6W_SHIFT)
#define GPIO_J_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_J_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_00_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_J_SCR_00_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G5W_SHIFT)
#define GPIO_J_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_J_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_00_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_J_SCR_00_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G4W_SHIFT)
#define GPIO_J_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_J_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_00_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_J_SCR_00_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G3W_SHIFT)
#define GPIO_J_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_J_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_00_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_J_SCR_00_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G2W_SHIFT)
#define GPIO_J_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_J_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_00_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_J_SCR_00_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G1W_SHIFT)
#define GPIO_J_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_J_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_00_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_J_SCR_00_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G0W_SHIFT)
#define GPIO_J_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_J_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_00_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_J_SCR_00_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G7R_SHIFT)
#define GPIO_J_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_J_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_00_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_J_SCR_00_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G6R_SHIFT)
#define GPIO_J_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_J_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_00_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_J_SCR_00_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G5R_SHIFT)
#define GPIO_J_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_J_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_00_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_J_SCR_00_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G4R_SHIFT)
#define GPIO_J_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_J_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_00_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_J_SCR_00_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G3R_SHIFT)
#define GPIO_J_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_J_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_00_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_J_SCR_00_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G2R_SHIFT)
#define GPIO_J_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_J_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_00_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_J_SCR_00_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G1R_SHIFT)
#define GPIO_J_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_J_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_00_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_J_SCR_00_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G0R_SHIFT)
#define GPIO_J_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_J_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_J_VM_01_0
#define GPIO_J_VM_01_0                  _MK_ADDR_CONST(0x5048)
#define GPIO_J_VM_01_0_SECURE                   0x0
#define GPIO_J_VM_01_0_DUAL                     0x0
#define GPIO_J_VM_01_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_J_VM_01_0_WORD_COUNT                       0x1
#define GPIO_J_VM_01_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_01_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_01_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_01_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_J_VM_01_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_01_0_VM1_SHIFT)
#define GPIO_J_VM_01_0_VM1_RANGE                        1:0
#define GPIO_J_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_J_VM_01_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_01_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_01_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_J_VM_01_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_J_VM_01_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_01_0_VM2_SHIFT)
#define GPIO_J_VM_01_0_VM2_RANGE                        3:2
#define GPIO_J_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_J_VM_01_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_01_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_01_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_J_VM_01_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_J_VM_01_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_01_0_VM3_SHIFT)
#define GPIO_J_VM_01_0_VM3_RANGE                        5:4
#define GPIO_J_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_J_VM_01_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_01_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_01_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_J_VM_01_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_J_VM_01_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_01_0_VM4_SHIFT)
#define GPIO_J_VM_01_0_VM4_RANGE                        7:6
#define GPIO_J_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_J_VM_01_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_01_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_01_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_J_VM_01_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_J_VM_01_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_01_0_VM5_SHIFT)
#define GPIO_J_VM_01_0_VM5_RANGE                        9:8
#define GPIO_J_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_J_VM_01_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_01_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_01_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_J_VM_01_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_J_VM_01_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_01_0_VM6_SHIFT)
#define GPIO_J_VM_01_0_VM6_RANGE                        11:10
#define GPIO_J_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_J_VM_01_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_01_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_01_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_J_VM_01_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_J_VM_01_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_01_0_VM7_SHIFT)
#define GPIO_J_VM_01_0_VM7_RANGE                        13:12
#define GPIO_J_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_J_VM_01_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_01_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_01_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_J_VM_01_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_J_VM_01_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_01_0_VM8_SHIFT)
#define GPIO_J_VM_01_0_VM8_RANGE                        15:14
#define GPIO_J_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_J_VM_01_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_01_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_01_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_J_SCR_01_0
#define GPIO_J_SCR_01_0                 _MK_ADDR_CONST(0x504c)
#define GPIO_J_SCR_01_0_SECURE                  0x0
#define GPIO_J_SCR_01_0_DUAL                    0x0
#define GPIO_J_SCR_01_0_SCR                     0
#define GPIO_J_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_J_SCR_01_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_01_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_01_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_01_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_J_SCR_01_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_J_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_J_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_J_SCR_01_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_01_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_J_SCR_01_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_J_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_J_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_J_SCR_01_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_01_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_J_SCR_01_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_J_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_J_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_J_SCR_01_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_01_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_J_SCR_01_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_J_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_J_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_J_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_J_SCR_01_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_J_SCR_01_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_01_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_J_SCR_01_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_PR7_SHIFT)
#define GPIO_J_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_J_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_01_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_J_SCR_01_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_PR6_SHIFT)
#define GPIO_J_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_J_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_01_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_J_SCR_01_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_PR5_SHIFT)
#define GPIO_J_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_J_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_01_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_J_SCR_01_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_PR4_SHIFT)
#define GPIO_J_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_J_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_01_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_J_SCR_01_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_PR3_SHIFT)
#define GPIO_J_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_J_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_01_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_J_SCR_01_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_PR2_SHIFT)
#define GPIO_J_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_J_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_01_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_J_SCR_01_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_PR1_SHIFT)
#define GPIO_J_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_J_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_01_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_J_SCR_01_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_PR0_SHIFT)
#define GPIO_J_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_J_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_01_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_J_SCR_01_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G7W_SHIFT)
#define GPIO_J_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_J_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_01_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_J_SCR_01_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G6W_SHIFT)
#define GPIO_J_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_J_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_01_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_J_SCR_01_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G5W_SHIFT)
#define GPIO_J_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_J_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_01_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_J_SCR_01_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G4W_SHIFT)
#define GPIO_J_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_J_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_01_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_J_SCR_01_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G3W_SHIFT)
#define GPIO_J_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_J_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_01_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_J_SCR_01_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G2W_SHIFT)
#define GPIO_J_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_J_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_01_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_J_SCR_01_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G1W_SHIFT)
#define GPIO_J_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_J_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_01_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_J_SCR_01_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G0W_SHIFT)
#define GPIO_J_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_J_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_01_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_J_SCR_01_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G7R_SHIFT)
#define GPIO_J_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_J_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_01_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_J_SCR_01_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G6R_SHIFT)
#define GPIO_J_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_J_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_01_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_J_SCR_01_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G5R_SHIFT)
#define GPIO_J_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_J_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_01_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_J_SCR_01_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G4R_SHIFT)
#define GPIO_J_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_J_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_01_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_J_SCR_01_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G3R_SHIFT)
#define GPIO_J_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_J_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_01_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_J_SCR_01_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G2R_SHIFT)
#define GPIO_J_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_J_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_01_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_J_SCR_01_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G1R_SHIFT)
#define GPIO_J_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_J_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_01_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_J_SCR_01_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G0R_SHIFT)
#define GPIO_J_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_J_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_J_VM_02_0
#define GPIO_J_VM_02_0                  _MK_ADDR_CONST(0x5050)
#define GPIO_J_VM_02_0_SECURE                   0x0
#define GPIO_J_VM_02_0_DUAL                     0x0
#define GPIO_J_VM_02_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_J_VM_02_0_WORD_COUNT                       0x1
#define GPIO_J_VM_02_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_02_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_02_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_02_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_J_VM_02_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_02_0_VM1_SHIFT)
#define GPIO_J_VM_02_0_VM1_RANGE                        1:0
#define GPIO_J_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_J_VM_02_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_02_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_02_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_J_VM_02_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_J_VM_02_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_02_0_VM2_SHIFT)
#define GPIO_J_VM_02_0_VM2_RANGE                        3:2
#define GPIO_J_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_J_VM_02_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_02_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_02_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_J_VM_02_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_J_VM_02_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_02_0_VM3_SHIFT)
#define GPIO_J_VM_02_0_VM3_RANGE                        5:4
#define GPIO_J_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_J_VM_02_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_02_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_02_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_J_VM_02_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_J_VM_02_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_02_0_VM4_SHIFT)
#define GPIO_J_VM_02_0_VM4_RANGE                        7:6
#define GPIO_J_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_J_VM_02_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_02_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_02_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_J_VM_02_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_J_VM_02_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_02_0_VM5_SHIFT)
#define GPIO_J_VM_02_0_VM5_RANGE                        9:8
#define GPIO_J_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_J_VM_02_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_02_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_02_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_J_VM_02_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_J_VM_02_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_02_0_VM6_SHIFT)
#define GPIO_J_VM_02_0_VM6_RANGE                        11:10
#define GPIO_J_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_J_VM_02_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_02_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_02_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_J_VM_02_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_J_VM_02_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_02_0_VM7_SHIFT)
#define GPIO_J_VM_02_0_VM7_RANGE                        13:12
#define GPIO_J_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_J_VM_02_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_02_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_02_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_J_VM_02_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_J_VM_02_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_02_0_VM8_SHIFT)
#define GPIO_J_VM_02_0_VM8_RANGE                        15:14
#define GPIO_J_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_J_VM_02_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_02_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_02_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_J_SCR_02_0
#define GPIO_J_SCR_02_0                 _MK_ADDR_CONST(0x5054)
#define GPIO_J_SCR_02_0_SECURE                  0x0
#define GPIO_J_SCR_02_0_DUAL                    0x0
#define GPIO_J_SCR_02_0_SCR                     0
#define GPIO_J_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_J_SCR_02_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_02_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_02_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_02_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_J_SCR_02_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_J_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_J_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_J_SCR_02_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_02_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_J_SCR_02_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_J_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_J_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_J_SCR_02_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_02_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_J_SCR_02_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_J_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_J_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_J_SCR_02_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_02_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_J_SCR_02_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_J_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_J_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_J_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_J_SCR_02_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_J_SCR_02_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_02_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_J_SCR_02_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_PR7_SHIFT)
#define GPIO_J_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_J_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_02_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_J_SCR_02_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_PR6_SHIFT)
#define GPIO_J_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_J_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_02_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_J_SCR_02_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_PR5_SHIFT)
#define GPIO_J_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_J_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_02_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_J_SCR_02_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_PR4_SHIFT)
#define GPIO_J_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_J_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_02_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_J_SCR_02_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_PR3_SHIFT)
#define GPIO_J_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_J_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_02_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_J_SCR_02_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_PR2_SHIFT)
#define GPIO_J_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_J_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_02_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_J_SCR_02_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_PR1_SHIFT)
#define GPIO_J_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_J_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_02_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_J_SCR_02_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_PR0_SHIFT)
#define GPIO_J_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_J_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_02_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_J_SCR_02_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G7W_SHIFT)
#define GPIO_J_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_J_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_02_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_J_SCR_02_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G6W_SHIFT)
#define GPIO_J_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_J_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_02_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_J_SCR_02_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G5W_SHIFT)
#define GPIO_J_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_J_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_02_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_J_SCR_02_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G4W_SHIFT)
#define GPIO_J_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_J_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_02_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_J_SCR_02_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G3W_SHIFT)
#define GPIO_J_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_J_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_02_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_J_SCR_02_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G2W_SHIFT)
#define GPIO_J_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_J_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_02_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_J_SCR_02_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G1W_SHIFT)
#define GPIO_J_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_J_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_02_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_J_SCR_02_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G0W_SHIFT)
#define GPIO_J_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_J_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_02_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_J_SCR_02_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G7R_SHIFT)
#define GPIO_J_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_J_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_02_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_J_SCR_02_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G6R_SHIFT)
#define GPIO_J_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_J_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_02_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_J_SCR_02_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G5R_SHIFT)
#define GPIO_J_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_J_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_02_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_J_SCR_02_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G4R_SHIFT)
#define GPIO_J_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_J_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_02_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_J_SCR_02_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G3R_SHIFT)
#define GPIO_J_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_J_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_02_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_J_SCR_02_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G2R_SHIFT)
#define GPIO_J_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_J_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_02_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_J_SCR_02_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G1R_SHIFT)
#define GPIO_J_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_J_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_02_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_J_SCR_02_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G0R_SHIFT)
#define GPIO_J_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_J_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_J_VM_03_0
#define GPIO_J_VM_03_0                  _MK_ADDR_CONST(0x5058)
#define GPIO_J_VM_03_0_SECURE                   0x0
#define GPIO_J_VM_03_0_DUAL                     0x0
#define GPIO_J_VM_03_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_J_VM_03_0_WORD_COUNT                       0x1
#define GPIO_J_VM_03_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_03_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_03_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_03_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_J_VM_03_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_03_0_VM1_SHIFT)
#define GPIO_J_VM_03_0_VM1_RANGE                        1:0
#define GPIO_J_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_J_VM_03_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_03_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_03_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_J_VM_03_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_J_VM_03_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_03_0_VM2_SHIFT)
#define GPIO_J_VM_03_0_VM2_RANGE                        3:2
#define GPIO_J_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_J_VM_03_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_03_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_03_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_J_VM_03_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_J_VM_03_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_03_0_VM3_SHIFT)
#define GPIO_J_VM_03_0_VM3_RANGE                        5:4
#define GPIO_J_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_J_VM_03_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_03_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_03_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_J_VM_03_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_J_VM_03_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_03_0_VM4_SHIFT)
#define GPIO_J_VM_03_0_VM4_RANGE                        7:6
#define GPIO_J_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_J_VM_03_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_03_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_03_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_J_VM_03_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_J_VM_03_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_03_0_VM5_SHIFT)
#define GPIO_J_VM_03_0_VM5_RANGE                        9:8
#define GPIO_J_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_J_VM_03_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_03_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_03_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_J_VM_03_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_J_VM_03_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_03_0_VM6_SHIFT)
#define GPIO_J_VM_03_0_VM6_RANGE                        11:10
#define GPIO_J_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_J_VM_03_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_03_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_03_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_J_VM_03_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_J_VM_03_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_03_0_VM7_SHIFT)
#define GPIO_J_VM_03_0_VM7_RANGE                        13:12
#define GPIO_J_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_J_VM_03_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_03_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_03_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_J_VM_03_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_J_VM_03_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_03_0_VM8_SHIFT)
#define GPIO_J_VM_03_0_VM8_RANGE                        15:14
#define GPIO_J_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_J_VM_03_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_03_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_03_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_J_SCR_03_0
#define GPIO_J_SCR_03_0                 _MK_ADDR_CONST(0x505c)
#define GPIO_J_SCR_03_0_SECURE                  0x0
#define GPIO_J_SCR_03_0_DUAL                    0x0
#define GPIO_J_SCR_03_0_SCR                     0
#define GPIO_J_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_J_SCR_03_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_03_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_03_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_03_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_J_SCR_03_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_J_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_J_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_J_SCR_03_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_03_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_J_SCR_03_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_J_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_J_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_J_SCR_03_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_03_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_J_SCR_03_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_J_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_J_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_J_SCR_03_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_03_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_J_SCR_03_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_J_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_J_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_J_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_J_SCR_03_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_J_SCR_03_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_03_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_J_SCR_03_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_PR7_SHIFT)
#define GPIO_J_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_J_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_03_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_J_SCR_03_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_PR6_SHIFT)
#define GPIO_J_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_J_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_03_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_J_SCR_03_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_PR5_SHIFT)
#define GPIO_J_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_J_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_03_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_J_SCR_03_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_PR4_SHIFT)
#define GPIO_J_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_J_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_03_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_J_SCR_03_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_PR3_SHIFT)
#define GPIO_J_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_J_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_03_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_J_SCR_03_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_PR2_SHIFT)
#define GPIO_J_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_J_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_03_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_J_SCR_03_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_PR1_SHIFT)
#define GPIO_J_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_J_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_03_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_J_SCR_03_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_PR0_SHIFT)
#define GPIO_J_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_J_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_03_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_J_SCR_03_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G7W_SHIFT)
#define GPIO_J_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_J_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_03_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_J_SCR_03_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G6W_SHIFT)
#define GPIO_J_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_J_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_03_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_J_SCR_03_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G5W_SHIFT)
#define GPIO_J_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_J_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_03_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_J_SCR_03_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G4W_SHIFT)
#define GPIO_J_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_J_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_03_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_J_SCR_03_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G3W_SHIFT)
#define GPIO_J_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_J_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_03_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_J_SCR_03_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G2W_SHIFT)
#define GPIO_J_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_J_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_03_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_J_SCR_03_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G1W_SHIFT)
#define GPIO_J_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_J_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_03_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_J_SCR_03_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G0W_SHIFT)
#define GPIO_J_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_J_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_03_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_J_SCR_03_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G7R_SHIFT)
#define GPIO_J_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_J_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_03_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_J_SCR_03_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G6R_SHIFT)
#define GPIO_J_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_J_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_03_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_J_SCR_03_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G5R_SHIFT)
#define GPIO_J_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_J_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_03_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_J_SCR_03_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G4R_SHIFT)
#define GPIO_J_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_J_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_03_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_J_SCR_03_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G3R_SHIFT)
#define GPIO_J_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_J_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_03_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_J_SCR_03_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G2R_SHIFT)
#define GPIO_J_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_J_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_03_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_J_SCR_03_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G1R_SHIFT)
#define GPIO_J_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_J_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_03_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_J_SCR_03_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G0R_SHIFT)
#define GPIO_J_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_J_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_J_VM_04_0
#define GPIO_J_VM_04_0                  _MK_ADDR_CONST(0x5060)
#define GPIO_J_VM_04_0_SECURE                   0x0
#define GPIO_J_VM_04_0_DUAL                     0x0
#define GPIO_J_VM_04_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_J_VM_04_0_WORD_COUNT                       0x1
#define GPIO_J_VM_04_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_04_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_04_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_04_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_J_VM_04_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_04_0_VM1_SHIFT)
#define GPIO_J_VM_04_0_VM1_RANGE                        1:0
#define GPIO_J_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_J_VM_04_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_04_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_04_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_J_VM_04_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_J_VM_04_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_04_0_VM2_SHIFT)
#define GPIO_J_VM_04_0_VM2_RANGE                        3:2
#define GPIO_J_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_J_VM_04_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_04_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_04_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_J_VM_04_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_J_VM_04_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_04_0_VM3_SHIFT)
#define GPIO_J_VM_04_0_VM3_RANGE                        5:4
#define GPIO_J_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_J_VM_04_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_04_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_04_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_J_VM_04_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_J_VM_04_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_04_0_VM4_SHIFT)
#define GPIO_J_VM_04_0_VM4_RANGE                        7:6
#define GPIO_J_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_J_VM_04_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_04_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_04_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_J_VM_04_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_J_VM_04_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_04_0_VM5_SHIFT)
#define GPIO_J_VM_04_0_VM5_RANGE                        9:8
#define GPIO_J_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_J_VM_04_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_04_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_04_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_J_VM_04_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_J_VM_04_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_04_0_VM6_SHIFT)
#define GPIO_J_VM_04_0_VM6_RANGE                        11:10
#define GPIO_J_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_J_VM_04_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_04_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_04_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_J_VM_04_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_J_VM_04_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_04_0_VM7_SHIFT)
#define GPIO_J_VM_04_0_VM7_RANGE                        13:12
#define GPIO_J_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_J_VM_04_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_04_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_04_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_J_VM_04_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_J_VM_04_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_04_0_VM8_SHIFT)
#define GPIO_J_VM_04_0_VM8_RANGE                        15:14
#define GPIO_J_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_J_VM_04_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_04_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_04_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_J_SCR_04_0
#define GPIO_J_SCR_04_0                 _MK_ADDR_CONST(0x5064)
#define GPIO_J_SCR_04_0_SECURE                  0x0
#define GPIO_J_SCR_04_0_DUAL                    0x0
#define GPIO_J_SCR_04_0_SCR                     0
#define GPIO_J_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_J_SCR_04_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_04_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_04_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_04_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_J_SCR_04_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_J_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_J_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_J_SCR_04_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_04_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_J_SCR_04_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_J_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_J_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_J_SCR_04_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_04_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_J_SCR_04_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_J_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_J_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_J_SCR_04_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_04_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_J_SCR_04_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_J_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_J_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_J_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_J_SCR_04_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_J_SCR_04_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_04_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_J_SCR_04_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_PR7_SHIFT)
#define GPIO_J_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_J_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_04_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_J_SCR_04_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_PR6_SHIFT)
#define GPIO_J_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_J_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_04_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_J_SCR_04_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_PR5_SHIFT)
#define GPIO_J_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_J_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_04_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_J_SCR_04_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_PR4_SHIFT)
#define GPIO_J_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_J_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_04_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_J_SCR_04_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_PR3_SHIFT)
#define GPIO_J_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_J_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_04_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_J_SCR_04_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_PR2_SHIFT)
#define GPIO_J_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_J_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_04_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_J_SCR_04_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_PR1_SHIFT)
#define GPIO_J_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_J_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_04_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_J_SCR_04_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_PR0_SHIFT)
#define GPIO_J_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_J_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_04_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_J_SCR_04_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G7W_SHIFT)
#define GPIO_J_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_J_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_04_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_J_SCR_04_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G6W_SHIFT)
#define GPIO_J_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_J_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_04_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_J_SCR_04_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G5W_SHIFT)
#define GPIO_J_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_J_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_04_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_J_SCR_04_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G4W_SHIFT)
#define GPIO_J_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_J_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_04_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_J_SCR_04_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G3W_SHIFT)
#define GPIO_J_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_J_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_04_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_J_SCR_04_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G2W_SHIFT)
#define GPIO_J_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_J_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_04_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_J_SCR_04_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G1W_SHIFT)
#define GPIO_J_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_J_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_04_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_J_SCR_04_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G0W_SHIFT)
#define GPIO_J_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_J_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_04_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_J_SCR_04_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G7R_SHIFT)
#define GPIO_J_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_J_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_04_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_J_SCR_04_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G6R_SHIFT)
#define GPIO_J_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_J_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_04_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_J_SCR_04_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G5R_SHIFT)
#define GPIO_J_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_J_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_04_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_J_SCR_04_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G4R_SHIFT)
#define GPIO_J_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_J_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_04_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_J_SCR_04_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G3R_SHIFT)
#define GPIO_J_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_J_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_04_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_J_SCR_04_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G2R_SHIFT)
#define GPIO_J_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_J_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_04_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_J_SCR_04_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G1R_SHIFT)
#define GPIO_J_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_J_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_04_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_J_SCR_04_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G0R_SHIFT)
#define GPIO_J_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_J_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_J_VM_05_0
#define GPIO_J_VM_05_0                  _MK_ADDR_CONST(0x5068)
#define GPIO_J_VM_05_0_SECURE                   0x0
#define GPIO_J_VM_05_0_DUAL                     0x0
#define GPIO_J_VM_05_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_J_VM_05_0_WORD_COUNT                       0x1
#define GPIO_J_VM_05_0_RESET_VAL                        _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_05_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_05_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define GPIO_J_VM_05_0_VM1_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_J_VM_05_0_VM1_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_05_0_VM1_SHIFT)
#define GPIO_J_VM_05_0_VM1_RANGE                        1:0
#define GPIO_J_VM_05_0_VM1_WOFFSET                      0x0
#define GPIO_J_VM_05_0_VM1_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_05_0_VM1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_05_0_VM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_J_VM_05_0_VM2_SHIFT                        _MK_SHIFT_CONST(2)
#define GPIO_J_VM_05_0_VM2_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_05_0_VM2_SHIFT)
#define GPIO_J_VM_05_0_VM2_RANGE                        3:2
#define GPIO_J_VM_05_0_VM2_WOFFSET                      0x0
#define GPIO_J_VM_05_0_VM2_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_05_0_VM2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_05_0_VM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_J_VM_05_0_VM3_SHIFT                        _MK_SHIFT_CONST(4)
#define GPIO_J_VM_05_0_VM3_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_05_0_VM3_SHIFT)
#define GPIO_J_VM_05_0_VM3_RANGE                        5:4
#define GPIO_J_VM_05_0_VM3_WOFFSET                      0x0
#define GPIO_J_VM_05_0_VM3_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_05_0_VM3_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_05_0_VM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_J_VM_05_0_VM4_SHIFT                        _MK_SHIFT_CONST(6)
#define GPIO_J_VM_05_0_VM4_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_05_0_VM4_SHIFT)
#define GPIO_J_VM_05_0_VM4_RANGE                        7:6
#define GPIO_J_VM_05_0_VM4_WOFFSET                      0x0
#define GPIO_J_VM_05_0_VM4_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_05_0_VM4_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_05_0_VM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_J_VM_05_0_VM5_SHIFT                        _MK_SHIFT_CONST(8)
#define GPIO_J_VM_05_0_VM5_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_05_0_VM5_SHIFT)
#define GPIO_J_VM_05_0_VM5_RANGE                        9:8
#define GPIO_J_VM_05_0_VM5_WOFFSET                      0x0
#define GPIO_J_VM_05_0_VM5_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_05_0_VM5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_05_0_VM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_J_VM_05_0_VM6_SHIFT                        _MK_SHIFT_CONST(10)
#define GPIO_J_VM_05_0_VM6_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_05_0_VM6_SHIFT)
#define GPIO_J_VM_05_0_VM6_RANGE                        11:10
#define GPIO_J_VM_05_0_VM6_WOFFSET                      0x0
#define GPIO_J_VM_05_0_VM6_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_05_0_VM6_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_05_0_VM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_J_VM_05_0_VM7_SHIFT                        _MK_SHIFT_CONST(12)
#define GPIO_J_VM_05_0_VM7_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_05_0_VM7_SHIFT)
#define GPIO_J_VM_05_0_VM7_RANGE                        13:12
#define GPIO_J_VM_05_0_VM7_WOFFSET                      0x0
#define GPIO_J_VM_05_0_VM7_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_05_0_VM7_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_05_0_VM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_J_VM_05_0_VM8_SHIFT                        _MK_SHIFT_CONST(14)
#define GPIO_J_VM_05_0_VM8_FIELD                        _MK_FIELD_CONST(0x3, GPIO_J_VM_05_0_VM8_SHIFT)
#define GPIO_J_VM_05_0_VM8_RANGE                        15:14
#define GPIO_J_VM_05_0_VM8_WOFFSET                      0x0
#define GPIO_J_VM_05_0_VM8_DEFAULT                      _MK_MASK_CONST(0x3)
#define GPIO_J_VM_05_0_VM8_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_J_VM_05_0_VM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_J_SCR_05_0
#define GPIO_J_SCR_05_0                 _MK_ADDR_CONST(0x506c)
#define GPIO_J_SCR_05_0_SECURE                  0x0
#define GPIO_J_SCR_05_0_DUAL                    0x0
#define GPIO_J_SCR_05_0_SCR                     0
#define GPIO_J_SCR_05_0_WORD_COUNT                      0x1
#define GPIO_J_SCR_05_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_05_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_05_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_05_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_J_SCR_05_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_J_SCR_05_0_SEC_LCK_RANGE                   29:29
#define GPIO_J_SCR_05_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_J_SCR_05_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_05_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_J_SCR_05_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_J_SCR_05_0_SEC_WEN_RANGE                   28:28
#define GPIO_J_SCR_05_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_J_SCR_05_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_05_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_J_SCR_05_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_J_SCR_05_0_SEC_REN_RANGE                   27:27
#define GPIO_J_SCR_05_0_SEC_REN_WOFFSET                 0x0
#define GPIO_J_SCR_05_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_05_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_J_SCR_05_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_J_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_J_SCR_05_0_SEC_OWNER_RANGE                 26:24
#define GPIO_J_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_J_SCR_05_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_J_SCR_05_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_05_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_J_SCR_05_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_PR7_SHIFT)
#define GPIO_J_SCR_05_0_PR7_RANGE                       23:23
#define GPIO_J_SCR_05_0_PR7_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_05_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_J_SCR_05_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_PR6_SHIFT)
#define GPIO_J_SCR_05_0_PR6_RANGE                       22:22
#define GPIO_J_SCR_05_0_PR6_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_05_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_J_SCR_05_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_PR5_SHIFT)
#define GPIO_J_SCR_05_0_PR5_RANGE                       21:21
#define GPIO_J_SCR_05_0_PR5_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_05_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_J_SCR_05_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_PR4_SHIFT)
#define GPIO_J_SCR_05_0_PR4_RANGE                       20:20
#define GPIO_J_SCR_05_0_PR4_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_05_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_J_SCR_05_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_PR3_SHIFT)
#define GPIO_J_SCR_05_0_PR3_RANGE                       19:19
#define GPIO_J_SCR_05_0_PR3_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_05_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_J_SCR_05_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_PR2_SHIFT)
#define GPIO_J_SCR_05_0_PR2_RANGE                       18:18
#define GPIO_J_SCR_05_0_PR2_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_05_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_J_SCR_05_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_PR1_SHIFT)
#define GPIO_J_SCR_05_0_PR1_RANGE                       17:17
#define GPIO_J_SCR_05_0_PR1_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_05_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_J_SCR_05_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_PR0_SHIFT)
#define GPIO_J_SCR_05_0_PR0_RANGE                       16:16
#define GPIO_J_SCR_05_0_PR0_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_05_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_J_SCR_05_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G7W_SHIFT)
#define GPIO_J_SCR_05_0_G7W_RANGE                       15:15
#define GPIO_J_SCR_05_0_G7W_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_05_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_J_SCR_05_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G6W_SHIFT)
#define GPIO_J_SCR_05_0_G6W_RANGE                       14:14
#define GPIO_J_SCR_05_0_G6W_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_05_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_J_SCR_05_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G5W_SHIFT)
#define GPIO_J_SCR_05_0_G5W_RANGE                       13:13
#define GPIO_J_SCR_05_0_G5W_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_05_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_J_SCR_05_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G4W_SHIFT)
#define GPIO_J_SCR_05_0_G4W_RANGE                       12:12
#define GPIO_J_SCR_05_0_G4W_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_05_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_J_SCR_05_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G3W_SHIFT)
#define GPIO_J_SCR_05_0_G3W_RANGE                       11:11
#define GPIO_J_SCR_05_0_G3W_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_05_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_J_SCR_05_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G2W_SHIFT)
#define GPIO_J_SCR_05_0_G2W_RANGE                       10:10
#define GPIO_J_SCR_05_0_G2W_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_05_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_J_SCR_05_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G1W_SHIFT)
#define GPIO_J_SCR_05_0_G1W_RANGE                       9:9
#define GPIO_J_SCR_05_0_G1W_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_05_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_J_SCR_05_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G0W_SHIFT)
#define GPIO_J_SCR_05_0_G0W_RANGE                       8:8
#define GPIO_J_SCR_05_0_G0W_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_05_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_J_SCR_05_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G7R_SHIFT)
#define GPIO_J_SCR_05_0_G7R_RANGE                       7:7
#define GPIO_J_SCR_05_0_G7R_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_05_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_J_SCR_05_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G6R_SHIFT)
#define GPIO_J_SCR_05_0_G6R_RANGE                       6:6
#define GPIO_J_SCR_05_0_G6R_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_05_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_J_SCR_05_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G5R_SHIFT)
#define GPIO_J_SCR_05_0_G5R_RANGE                       5:5
#define GPIO_J_SCR_05_0_G5R_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_05_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_J_SCR_05_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G4R_SHIFT)
#define GPIO_J_SCR_05_0_G4R_RANGE                       4:4
#define GPIO_J_SCR_05_0_G4R_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_05_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_J_SCR_05_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G3R_SHIFT)
#define GPIO_J_SCR_05_0_G3R_RANGE                       3:3
#define GPIO_J_SCR_05_0_G3R_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_05_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_J_SCR_05_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G2R_SHIFT)
#define GPIO_J_SCR_05_0_G2R_RANGE                       2:2
#define GPIO_J_SCR_05_0_G2R_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_05_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_J_SCR_05_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G1R_SHIFT)
#define GPIO_J_SCR_05_0_G1R_RANGE                       1:1
#define GPIO_J_SCR_05_0_G1R_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_J_SCR_05_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_J_SCR_05_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G0R_SHIFT)
#define GPIO_J_SCR_05_0_G0R_RANGE                       0:0
#define GPIO_J_SCR_05_0_G0R_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Reserved address 0x5070

// Reserved address 0x5074

// Reserved address 0x5078

// Reserved address 0x507c

// Register GPIO_CTL5_VM_SCR_0
#define GPIO_CTL5_VM_SCR_0                      _MK_ADDR_CONST(0x5800)
#define GPIO_CTL5_VM_SCR_0_SECURE                       0x0
#define GPIO_CTL5_VM_SCR_0_DUAL                         0x0
#define GPIO_CTL5_VM_SCR_0_SCR                  0
#define GPIO_CTL5_VM_SCR_0_WORD_COUNT                   0x1
#define GPIO_CTL5_VM_SCR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_RESET_MASK                   _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL5_VM_SCR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_READ_MASK                    _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL5_VM_SCR_0_WRITE_MASK                   _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL5_VM_SCR_0_SEC_LCK_SHIFT                        _MK_SHIFT_CONST(29)
#define GPIO_CTL5_VM_SCR_0_SEC_LCK_FIELD                        _MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_SEC_LCK_SHIFT)
#define GPIO_CTL5_VM_SCR_0_SEC_LCK_RANGE                        29:29
#define GPIO_CTL5_VM_SCR_0_SEC_LCK_WOFFSET                      0x0
#define GPIO_CTL5_VM_SCR_0_SEC_LCK_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_SEC_LCK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_SEC_LCK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_SEC_LCK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_SEC_LCK_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_CTL5_VM_SCR_0_SEC_WEN_SHIFT                        _MK_SHIFT_CONST(28)
#define GPIO_CTL5_VM_SCR_0_SEC_WEN_FIELD                        _MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_SEC_WEN_SHIFT)
#define GPIO_CTL5_VM_SCR_0_SEC_WEN_RANGE                        28:28
#define GPIO_CTL5_VM_SCR_0_SEC_WEN_WOFFSET                      0x0
#define GPIO_CTL5_VM_SCR_0_SEC_WEN_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_SEC_WEN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_SEC_WEN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_SEC_WEN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_SEC_WEN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_CTL5_VM_SCR_0_SEC_REN_SHIFT                        _MK_SHIFT_CONST(27)
#define GPIO_CTL5_VM_SCR_0_SEC_REN_FIELD                        _MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_SEC_REN_SHIFT)
#define GPIO_CTL5_VM_SCR_0_SEC_REN_RANGE                        27:27
#define GPIO_CTL5_VM_SCR_0_SEC_REN_WOFFSET                      0x0
#define GPIO_CTL5_VM_SCR_0_SEC_REN_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_SEC_REN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_SEC_REN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_SEC_REN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_SEC_REN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_SEC_REN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define GPIO_CTL5_VM_SCR_0_SEC_OWNER_SHIFT                      _MK_SHIFT_CONST(24)
#define GPIO_CTL5_VM_SCR_0_SEC_OWNER_FIELD                      _MK_FIELD_CONST(0x7, GPIO_CTL5_VM_SCR_0_SEC_OWNER_SHIFT)
#define GPIO_CTL5_VM_SCR_0_SEC_OWNER_RANGE                      26:24
#define GPIO_CTL5_VM_SCR_0_SEC_OWNER_WOFFSET                    0x0
#define GPIO_CTL5_VM_SCR_0_SEC_OWNER_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_SEC_OWNER_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
#define GPIO_CTL5_VM_SCR_0_SEC_OWNER_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_SEC_OWNER_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define GPIO_CTL5_VM_SCR_0_PR7_SHIFT                    _MK_SHIFT_CONST(23)
#define GPIO_CTL5_VM_SCR_0_PR7_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_PR7_SHIFT)
#define GPIO_CTL5_VM_SCR_0_PR7_RANGE                    23:23
#define GPIO_CTL5_VM_SCR_0_PR7_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_PR7_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR7_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_PR7_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR7_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR7_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR7_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL5_VM_SCR_0_PR6_SHIFT                    _MK_SHIFT_CONST(22)
#define GPIO_CTL5_VM_SCR_0_PR6_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_PR6_SHIFT)
#define GPIO_CTL5_VM_SCR_0_PR6_RANGE                    22:22
#define GPIO_CTL5_VM_SCR_0_PR6_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_PR6_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR6_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_PR6_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR6_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR6_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL5_VM_SCR_0_PR5_SHIFT                    _MK_SHIFT_CONST(21)
#define GPIO_CTL5_VM_SCR_0_PR5_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_PR5_SHIFT)
#define GPIO_CTL5_VM_SCR_0_PR5_RANGE                    21:21
#define GPIO_CTL5_VM_SCR_0_PR5_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_PR5_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR5_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_PR5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR5_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR5_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL5_VM_SCR_0_PR4_SHIFT                    _MK_SHIFT_CONST(20)
#define GPIO_CTL5_VM_SCR_0_PR4_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_PR4_SHIFT)
#define GPIO_CTL5_VM_SCR_0_PR4_RANGE                    20:20
#define GPIO_CTL5_VM_SCR_0_PR4_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_PR4_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR4_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_PR4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR4_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR4_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL5_VM_SCR_0_PR3_SHIFT                    _MK_SHIFT_CONST(19)
#define GPIO_CTL5_VM_SCR_0_PR3_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_PR3_SHIFT)
#define GPIO_CTL5_VM_SCR_0_PR3_RANGE                    19:19
#define GPIO_CTL5_VM_SCR_0_PR3_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_PR3_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_PR3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR3_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR3_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL5_VM_SCR_0_PR2_SHIFT                    _MK_SHIFT_CONST(18)
#define GPIO_CTL5_VM_SCR_0_PR2_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_PR2_SHIFT)
#define GPIO_CTL5_VM_SCR_0_PR2_RANGE                    18:18
#define GPIO_CTL5_VM_SCR_0_PR2_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_PR2_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_PR2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR2_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR2_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL5_VM_SCR_0_PR1_SHIFT                    _MK_SHIFT_CONST(17)
#define GPIO_CTL5_VM_SCR_0_PR1_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_PR1_SHIFT)
#define GPIO_CTL5_VM_SCR_0_PR1_RANGE                    17:17
#define GPIO_CTL5_VM_SCR_0_PR1_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_PR1_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_PR1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR1_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR1_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL5_VM_SCR_0_PR0_SHIFT                    _MK_SHIFT_CONST(16)
#define GPIO_CTL5_VM_SCR_0_PR0_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_PR0_SHIFT)
#define GPIO_CTL5_VM_SCR_0_PR0_RANGE                    16:16
#define GPIO_CTL5_VM_SCR_0_PR0_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_PR0_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_PR0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR0_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR0_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL5_VM_SCR_0_G7W_SHIFT                    _MK_SHIFT_CONST(15)
#define GPIO_CTL5_VM_SCR_0_G7W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G7W_SHIFT)
#define GPIO_CTL5_VM_SCR_0_G7W_RANGE                    15:15
#define GPIO_CTL5_VM_SCR_0_G7W_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_G7W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G7W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_G7W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G7W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G7W_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G7W_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL5_VM_SCR_0_G6W_SHIFT                    _MK_SHIFT_CONST(14)
#define GPIO_CTL5_VM_SCR_0_G6W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G6W_SHIFT)
#define GPIO_CTL5_VM_SCR_0_G6W_RANGE                    14:14
#define GPIO_CTL5_VM_SCR_0_G6W_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_G6W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G6W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_G6W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G6W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G6W_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G6W_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL5_VM_SCR_0_G5W_SHIFT                    _MK_SHIFT_CONST(13)
#define GPIO_CTL5_VM_SCR_0_G5W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G5W_SHIFT)
#define GPIO_CTL5_VM_SCR_0_G5W_RANGE                    13:13
#define GPIO_CTL5_VM_SCR_0_G5W_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_G5W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G5W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_G5W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G5W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G5W_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G5W_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL5_VM_SCR_0_G4W_SHIFT                    _MK_SHIFT_CONST(12)
#define GPIO_CTL5_VM_SCR_0_G4W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G4W_SHIFT)
#define GPIO_CTL5_VM_SCR_0_G4W_RANGE                    12:12
#define GPIO_CTL5_VM_SCR_0_G4W_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_G4W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G4W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_G4W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G4W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G4W_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G4W_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL5_VM_SCR_0_G3W_SHIFT                    _MK_SHIFT_CONST(11)
#define GPIO_CTL5_VM_SCR_0_G3W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G3W_SHIFT)
#define GPIO_CTL5_VM_SCR_0_G3W_RANGE                    11:11
#define GPIO_CTL5_VM_SCR_0_G3W_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_G3W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G3W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_G3W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G3W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G3W_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G3W_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL5_VM_SCR_0_G2W_SHIFT                    _MK_SHIFT_CONST(10)
#define GPIO_CTL5_VM_SCR_0_G2W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G2W_SHIFT)
#define GPIO_CTL5_VM_SCR_0_G2W_RANGE                    10:10
#define GPIO_CTL5_VM_SCR_0_G2W_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_G2W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G2W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_G2W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G2W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G2W_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G2W_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL5_VM_SCR_0_G1W_SHIFT                    _MK_SHIFT_CONST(9)
#define GPIO_CTL5_VM_SCR_0_G1W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G1W_SHIFT)
#define GPIO_CTL5_VM_SCR_0_G1W_RANGE                    9:9
#define GPIO_CTL5_VM_SCR_0_G1W_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_G1W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G1W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_G1W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G1W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G1W_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G1W_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL5_VM_SCR_0_G0W_SHIFT                    _MK_SHIFT_CONST(8)
#define GPIO_CTL5_VM_SCR_0_G0W_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G0W_SHIFT)
#define GPIO_CTL5_VM_SCR_0_G0W_RANGE                    8:8
#define GPIO_CTL5_VM_SCR_0_G0W_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_G0W_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G0W_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_G0W_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G0W_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G0W_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G0W_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL5_VM_SCR_0_G7R_SHIFT                    _MK_SHIFT_CONST(7)
#define GPIO_CTL5_VM_SCR_0_G7R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G7R_SHIFT)
#define GPIO_CTL5_VM_SCR_0_G7R_RANGE                    7:7
#define GPIO_CTL5_VM_SCR_0_G7R_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_G7R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G7R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_G7R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G7R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G7R_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G7R_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL5_VM_SCR_0_G6R_SHIFT                    _MK_SHIFT_CONST(6)
#define GPIO_CTL5_VM_SCR_0_G6R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G6R_SHIFT)
#define GPIO_CTL5_VM_SCR_0_G6R_RANGE                    6:6
#define GPIO_CTL5_VM_SCR_0_G6R_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_G6R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G6R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_G6R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G6R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G6R_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G6R_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL5_VM_SCR_0_G5R_SHIFT                    _MK_SHIFT_CONST(5)
#define GPIO_CTL5_VM_SCR_0_G5R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G5R_SHIFT)
#define GPIO_CTL5_VM_SCR_0_G5R_RANGE                    5:5
#define GPIO_CTL5_VM_SCR_0_G5R_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_G5R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G5R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_G5R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G5R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G5R_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G5R_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL5_VM_SCR_0_G4R_SHIFT                    _MK_SHIFT_CONST(4)
#define GPIO_CTL5_VM_SCR_0_G4R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G4R_SHIFT)
#define GPIO_CTL5_VM_SCR_0_G4R_RANGE                    4:4
#define GPIO_CTL5_VM_SCR_0_G4R_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_G4R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G4R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_G4R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G4R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G4R_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G4R_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL5_VM_SCR_0_G3R_SHIFT                    _MK_SHIFT_CONST(3)
#define GPIO_CTL5_VM_SCR_0_G3R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G3R_SHIFT)
#define GPIO_CTL5_VM_SCR_0_G3R_RANGE                    3:3
#define GPIO_CTL5_VM_SCR_0_G3R_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_G3R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G3R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_G3R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G3R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G3R_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G3R_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL5_VM_SCR_0_G2R_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_CTL5_VM_SCR_0_G2R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G2R_SHIFT)
#define GPIO_CTL5_VM_SCR_0_G2R_RANGE                    2:2
#define GPIO_CTL5_VM_SCR_0_G2R_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_G2R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G2R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_G2R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G2R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G2R_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G2R_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL5_VM_SCR_0_G1R_SHIFT                    _MK_SHIFT_CONST(1)
#define GPIO_CTL5_VM_SCR_0_G1R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G1R_SHIFT)
#define GPIO_CTL5_VM_SCR_0_G1R_RANGE                    1:1
#define GPIO_CTL5_VM_SCR_0_G1R_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_G1R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G1R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_G1R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G1R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G1R_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G1R_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define GPIO_CTL5_VM_SCR_0_G0R_SHIFT                    _MK_SHIFT_CONST(0)
#define GPIO_CTL5_VM_SCR_0_G0R_FIELD                    _MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G0R_SHIFT)
#define GPIO_CTL5_VM_SCR_0_G0R_RANGE                    0:0
#define GPIO_CTL5_VM_SCR_0_G0R_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_G0R_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G0R_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_G0R_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G0R_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G0R_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G0R_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0                     _MK_ADDR_CONST(0x5804)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SECURE                      0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_DUAL                        0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SCR                         0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_WORD_COUNT                  0x1
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_RESET_MASK                  _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_READ_MASK                   _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_WRITE_MASK                  _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SHIFT                       _MK_SHIFT_CONST(29)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_RANGE                       29:29
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_WOFFSET                     0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SHIFT                       _MK_SHIFT_CONST(28)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_RANGE                       28:28
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_WOFFSET                     0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SHIFT                       _MK_SHIFT_CONST(27)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_RANGE                       27:27
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_WOFFSET                     0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SHIFT                     _MK_SHIFT_CONST(24)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_FIELD                     _MK_FIELD_CONST(0x7, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_RANGE                     26:24
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_WOFFSET                   0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR7_SHIFT                   _MK_SHIFT_CONST(23)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR7_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR7_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR7_RANGE                   23:23
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR7_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR7_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR7_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR7_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR7_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR7_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR7_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR6_SHIFT                   _MK_SHIFT_CONST(22)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR6_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR6_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR6_RANGE                   22:22
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR6_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR6_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR6_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR6_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR6_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR6_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR6_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR5_SHIFT                   _MK_SHIFT_CONST(21)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR5_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR5_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR5_RANGE                   21:21
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR5_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR5_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR5_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR5_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR5_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR5_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR5_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR4_SHIFT                   _MK_SHIFT_CONST(20)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR4_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR4_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR4_RANGE                   20:20
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR4_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR4_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR4_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR4_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR4_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR3_SHIFT                   _MK_SHIFT_CONST(19)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR3_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR3_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR3_RANGE                   19:19
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR3_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR3_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR3_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR3_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR2_SHIFT                   _MK_SHIFT_CONST(18)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR2_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR2_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR2_RANGE                   18:18
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR2_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR2_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR2_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR2_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR1_SHIFT                   _MK_SHIFT_CONST(17)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR1_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR1_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR1_RANGE                   17:17
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR1_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR1_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR1_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR1_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR0_SHIFT                   _MK_SHIFT_CONST(16)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR0_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR0_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR0_RANGE                   16:16
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR0_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR0_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR0_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR0_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7W_SHIFT                   _MK_SHIFT_CONST(15)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7W_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7W_RANGE                   15:15
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7W_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6W_SHIFT                   _MK_SHIFT_CONST(14)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6W_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6W_RANGE                   14:14
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6W_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5W_SHIFT                   _MK_SHIFT_CONST(13)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5W_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5W_RANGE                   13:13
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5W_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4W_SHIFT                   _MK_SHIFT_CONST(12)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4W_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4W_RANGE                   12:12
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4W_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3W_SHIFT                   _MK_SHIFT_CONST(11)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3W_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3W_RANGE                   11:11
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3W_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2W_SHIFT                   _MK_SHIFT_CONST(10)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2W_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2W_RANGE                   10:10
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2W_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1W_SHIFT                   _MK_SHIFT_CONST(9)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1W_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1W_RANGE                   9:9
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1W_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0W_SHIFT                   _MK_SHIFT_CONST(8)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0W_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0W_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0W_RANGE                   8:8
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0W_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0W_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0W_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0W_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0W_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0W_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0W_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7R_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7R_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7R_RANGE                   7:7
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7R_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6R_SHIFT                   _MK_SHIFT_CONST(6)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6R_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6R_RANGE                   6:6
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6R_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5R_SHIFT                   _MK_SHIFT_CONST(5)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5R_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5R_RANGE                   5:5
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5R_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4R_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4R_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4R_RANGE                   4:4
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4R_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3R_SHIFT                   _MK_SHIFT_CONST(3)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3R_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3R_RANGE                   3:3
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3R_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2R_SHIFT                   _MK_SHIFT_CONST(2)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2R_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2R_RANGE                   2:2
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2R_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1R_SHIFT                   _MK_SHIFT_CONST(1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1R_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1R_RANGE                   1:1
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1R_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0R_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0R_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0R_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0R_RANGE                   0:0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0R_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0R_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0R_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0R_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0R_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0R_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0R_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_CTL5_INTERRUPT_STATUS_VM_0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0                 _MK_ADDR_CONST(0x5808)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_SECURE                  0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_DUAL                    0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_SCR                     GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_WORD_COUNT                      0x1
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_RESET_MASK                      _MK_MASK_CONST(0xff)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_READ_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_FIELD                  _MK_FIELD_CONST(0xff, GPIO_CTL5_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_RANGE                  7:0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_WOFFSET                        0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register GPIO_CTL5_SCR_0
#define GPIO_CTL5_SCR_0                 _MK_ADDR_CONST(0x580c)
#define GPIO_CTL5_SCR_0_SECURE                  0x0
#define GPIO_CTL5_SCR_0_DUAL                    0x0
#define GPIO_CTL5_SCR_0_SCR                     0
#define GPIO_CTL5_SCR_0_WORD_COUNT                      0x1
#define GPIO_CTL5_SCR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_RESET_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL5_SCR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_READ_MASK                       _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL5_SCR_0_WRITE_MASK                      _MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL5_SCR_0_SEC_LCK_SHIFT                   _MK_SHIFT_CONST(29)
#define GPIO_CTL5_SCR_0_SEC_LCK_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_SEC_LCK_SHIFT)
#define GPIO_CTL5_SCR_0_SEC_LCK_RANGE                   29:29
#define GPIO_CTL5_SCR_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_CTL5_SCR_0_SEC_LCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_SEC_LCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_SEC_LCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_SEC_LCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL5_SCR_0_SEC_WEN_SHIFT                   _MK_SHIFT_CONST(28)
#define GPIO_CTL5_SCR_0_SEC_WEN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_SEC_WEN_SHIFT)
#define GPIO_CTL5_SCR_0_SEC_WEN_RANGE                   28:28
#define GPIO_CTL5_SCR_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_CTL5_SCR_0_SEC_WEN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_SEC_WEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_SEC_WEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_SEC_WEN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL5_SCR_0_SEC_REN_SHIFT                   _MK_SHIFT_CONST(27)
#define GPIO_CTL5_SCR_0_SEC_REN_FIELD                   _MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_SEC_REN_SHIFT)
#define GPIO_CTL5_SCR_0_SEC_REN_RANGE                   27:27
#define GPIO_CTL5_SCR_0_SEC_REN_WOFFSET                 0x0
#define GPIO_CTL5_SCR_0_SEC_REN_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_SEC_REN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_SEC_REN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_SEC_REN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_SEC_REN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_SEC_REN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define GPIO_CTL5_SCR_0_SEC_OWNER_SHIFT                 _MK_SHIFT_CONST(24)
#define GPIO_CTL5_SCR_0_SEC_OWNER_FIELD                 _MK_FIELD_CONST(0x7, GPIO_CTL5_SCR_0_SEC_OWNER_SHIFT)
#define GPIO_CTL5_SCR_0_SEC_OWNER_RANGE                 26:24
#define GPIO_CTL5_SCR_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_CTL5_SCR_0_SEC_OWNER_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_SEC_OWNER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_CTL5_SCR_0_SEC_OWNER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_SEC_OWNER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define GPIO_CTL5_SCR_0_PR7_SHIFT                       _MK_SHIFT_CONST(23)
#define GPIO_CTL5_SCR_0_PR7_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_PR7_SHIFT)
#define GPIO_CTL5_SCR_0_PR7_RANGE                       23:23
#define GPIO_CTL5_SCR_0_PR7_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_PR7_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_PR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR7_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR7_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL5_SCR_0_PR6_SHIFT                       _MK_SHIFT_CONST(22)
#define GPIO_CTL5_SCR_0_PR6_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_PR6_SHIFT)
#define GPIO_CTL5_SCR_0_PR6_RANGE                       22:22
#define GPIO_CTL5_SCR_0_PR6_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_PR6_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_PR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR6_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR6_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL5_SCR_0_PR5_SHIFT                       _MK_SHIFT_CONST(21)
#define GPIO_CTL5_SCR_0_PR5_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_PR5_SHIFT)
#define GPIO_CTL5_SCR_0_PR5_RANGE                       21:21
#define GPIO_CTL5_SCR_0_PR5_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_PR5_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_PR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR5_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR5_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL5_SCR_0_PR4_SHIFT                       _MK_SHIFT_CONST(20)
#define GPIO_CTL5_SCR_0_PR4_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_PR4_SHIFT)
#define GPIO_CTL5_SCR_0_PR4_RANGE                       20:20
#define GPIO_CTL5_SCR_0_PR4_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_PR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_PR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR4_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL5_SCR_0_PR3_SHIFT                       _MK_SHIFT_CONST(19)
#define GPIO_CTL5_SCR_0_PR3_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_PR3_SHIFT)
#define GPIO_CTL5_SCR_0_PR3_RANGE                       19:19
#define GPIO_CTL5_SCR_0_PR3_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_PR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_PR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR3_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL5_SCR_0_PR2_SHIFT                       _MK_SHIFT_CONST(18)
#define GPIO_CTL5_SCR_0_PR2_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_PR2_SHIFT)
#define GPIO_CTL5_SCR_0_PR2_RANGE                       18:18
#define GPIO_CTL5_SCR_0_PR2_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_PR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_PR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL5_SCR_0_PR1_SHIFT                       _MK_SHIFT_CONST(17)
#define GPIO_CTL5_SCR_0_PR1_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_PR1_SHIFT)
#define GPIO_CTL5_SCR_0_PR1_RANGE                       17:17
#define GPIO_CTL5_SCR_0_PR1_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_PR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_PR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL5_SCR_0_PR0_SHIFT                       _MK_SHIFT_CONST(16)
#define GPIO_CTL5_SCR_0_PR0_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_PR0_SHIFT)
#define GPIO_CTL5_SCR_0_PR0_RANGE                       16:16
#define GPIO_CTL5_SCR_0_PR0_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_PR0_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_PR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL5_SCR_0_G7W_SHIFT                       _MK_SHIFT_CONST(15)
#define GPIO_CTL5_SCR_0_G7W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G7W_SHIFT)
#define GPIO_CTL5_SCR_0_G7W_RANGE                       15:15
#define GPIO_CTL5_SCR_0_G7W_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_G7W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G7W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_G7W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G7W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G7W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G7W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL5_SCR_0_G6W_SHIFT                       _MK_SHIFT_CONST(14)
#define GPIO_CTL5_SCR_0_G6W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G6W_SHIFT)
#define GPIO_CTL5_SCR_0_G6W_RANGE                       14:14
#define GPIO_CTL5_SCR_0_G6W_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_G6W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G6W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_G6W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G6W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G6W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G6W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL5_SCR_0_G5W_SHIFT                       _MK_SHIFT_CONST(13)
#define GPIO_CTL5_SCR_0_G5W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G5W_SHIFT)
#define GPIO_CTL5_SCR_0_G5W_RANGE                       13:13
#define GPIO_CTL5_SCR_0_G5W_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_G5W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G5W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_G5W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G5W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G5W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G5W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL5_SCR_0_G4W_SHIFT                       _MK_SHIFT_CONST(12)
#define GPIO_CTL5_SCR_0_G4W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G4W_SHIFT)
#define GPIO_CTL5_SCR_0_G4W_RANGE                       12:12
#define GPIO_CTL5_SCR_0_G4W_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_G4W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G4W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_G4W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G4W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G4W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G4W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL5_SCR_0_G3W_SHIFT                       _MK_SHIFT_CONST(11)
#define GPIO_CTL5_SCR_0_G3W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G3W_SHIFT)
#define GPIO_CTL5_SCR_0_G3W_RANGE                       11:11
#define GPIO_CTL5_SCR_0_G3W_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_G3W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G3W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_G3W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G3W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G3W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G3W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL5_SCR_0_G2W_SHIFT                       _MK_SHIFT_CONST(10)
#define GPIO_CTL5_SCR_0_G2W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G2W_SHIFT)
#define GPIO_CTL5_SCR_0_G2W_RANGE                       10:10
#define GPIO_CTL5_SCR_0_G2W_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_G2W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G2W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_G2W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G2W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G2W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G2W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL5_SCR_0_G1W_SHIFT                       _MK_SHIFT_CONST(9)
#define GPIO_CTL5_SCR_0_G1W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G1W_SHIFT)
#define GPIO_CTL5_SCR_0_G1W_RANGE                       9:9
#define GPIO_CTL5_SCR_0_G1W_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_G1W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G1W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_G1W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G1W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G1W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G1W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL5_SCR_0_G0W_SHIFT                       _MK_SHIFT_CONST(8)
#define GPIO_CTL5_SCR_0_G0W_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G0W_SHIFT)
#define GPIO_CTL5_SCR_0_G0W_RANGE                       8:8
#define GPIO_CTL5_SCR_0_G0W_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_G0W_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G0W_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_G0W_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G0W_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G0W_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G0W_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL5_SCR_0_G7R_SHIFT                       _MK_SHIFT_CONST(7)
#define GPIO_CTL5_SCR_0_G7R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G7R_SHIFT)
#define GPIO_CTL5_SCR_0_G7R_RANGE                       7:7
#define GPIO_CTL5_SCR_0_G7R_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_G7R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G7R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_G7R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G7R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G7R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G7R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL5_SCR_0_G6R_SHIFT                       _MK_SHIFT_CONST(6)
#define GPIO_CTL5_SCR_0_G6R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G6R_SHIFT)
#define GPIO_CTL5_SCR_0_G6R_RANGE                       6:6
#define GPIO_CTL5_SCR_0_G6R_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_G6R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G6R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_G6R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G6R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G6R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G6R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL5_SCR_0_G5R_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_CTL5_SCR_0_G5R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G5R_SHIFT)
#define GPIO_CTL5_SCR_0_G5R_RANGE                       5:5
#define GPIO_CTL5_SCR_0_G5R_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_G5R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G5R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_G5R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G5R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G5R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G5R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL5_SCR_0_G4R_SHIFT                       _MK_SHIFT_CONST(4)
#define GPIO_CTL5_SCR_0_G4R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G4R_SHIFT)
#define GPIO_CTL5_SCR_0_G4R_RANGE                       4:4
#define GPIO_CTL5_SCR_0_G4R_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_G4R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G4R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_G4R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G4R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G4R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G4R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL5_SCR_0_G3R_SHIFT                       _MK_SHIFT_CONST(3)
#define GPIO_CTL5_SCR_0_G3R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G3R_SHIFT)
#define GPIO_CTL5_SCR_0_G3R_RANGE                       3:3
#define GPIO_CTL5_SCR_0_G3R_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_G3R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G3R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_G3R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G3R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G3R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G3R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL5_SCR_0_G2R_SHIFT                       _MK_SHIFT_CONST(2)
#define GPIO_CTL5_SCR_0_G2R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G2R_SHIFT)
#define GPIO_CTL5_SCR_0_G2R_RANGE                       2:2
#define GPIO_CTL5_SCR_0_G2R_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_G2R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G2R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_G2R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G2R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G2R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G2R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL5_SCR_0_G1R_SHIFT                       _MK_SHIFT_CONST(1)
#define GPIO_CTL5_SCR_0_G1R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G1R_SHIFT)
#define GPIO_CTL5_SCR_0_G1R_RANGE                       1:1
#define GPIO_CTL5_SCR_0_G1R_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_G1R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G1R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_G1R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G1R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G1R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G1R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define GPIO_CTL5_SCR_0_G0R_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_CTL5_SCR_0_G0R_FIELD                       _MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G0R_SHIFT)
#define GPIO_CTL5_SCR_0_G0R_RANGE                       0:0
#define GPIO_CTL5_SCR_0_G0R_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_G0R_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G0R_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_G0R_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G0R_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G0R_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G0R_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_CTL5_ICG_EN_OVERRIDE_0
#define GPIO_CTL5_ICG_EN_OVERRIDE_0                     _MK_ADDR_CONST(0x5810)
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_SECURE                      0x0
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_DUAL                        0x0
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_WORD_COUNT                  0x1
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_FIELD                  _MK_FIELD_CONST(0x1, GPIO_CTL5_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SHIFT)
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_RANGE                  0:0
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_WOFFSET                        0x0
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register GPIO_O_INT0_ROUTE_MAPPING_0
#define GPIO_O_INT0_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x5814)
#define GPIO_O_INT0_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_O_INT0_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_O_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_O_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_O_INT0_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_O_INT0_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_O_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_O_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_INT0_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x3f)
#define GPIO_O_INT0_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_O_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_O_INT0_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x3f, GPIO_O_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_O_INT0_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_O_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_O_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
#define GPIO_O_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_O_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_O_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_O_INT1_ROUTE_MAPPING_0
#define GPIO_O_INT1_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x5818)
#define GPIO_O_INT1_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_O_INT1_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_O_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_O_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_O_INT1_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_O_INT1_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_O_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_O_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_INT1_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x3f)
#define GPIO_O_INT1_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_O_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_O_INT1_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x3f, GPIO_O_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_O_INT1_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_O_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_O_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
#define GPIO_O_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_O_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_O_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_O_INT2_ROUTE_MAPPING_0
#define GPIO_O_INT2_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x581c)
#define GPIO_O_INT2_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_O_INT2_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_O_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_O_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_O_INT2_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_O_INT2_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_O_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_O_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_INT2_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x3f)
#define GPIO_O_INT2_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_O_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_O_INT2_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x3f, GPIO_O_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_O_INT2_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_O_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_O_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
#define GPIO_O_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_O_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_O_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_O_INT3_ROUTE_MAPPING_0
#define GPIO_O_INT3_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x5820)
#define GPIO_O_INT3_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_O_INT3_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_O_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_O_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_O_INT3_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_O_INT3_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_O_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_O_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_INT3_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x3f)
#define GPIO_O_INT3_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_O_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_O_INT3_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x3f, GPIO_O_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_O_INT3_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_O_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_O_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
#define GPIO_O_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_O_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_O_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_O_INT4_ROUTE_MAPPING_0
#define GPIO_O_INT4_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x5824)
#define GPIO_O_INT4_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_O_INT4_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_O_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_O_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_O_INT4_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_O_INT4_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_O_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_O_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_INT4_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x3f)
#define GPIO_O_INT4_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_O_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_O_INT4_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x3f, GPIO_O_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_O_INT4_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_O_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_O_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
#define GPIO_O_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_O_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_O_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_O_INT5_ROUTE_MAPPING_0
#define GPIO_O_INT5_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x5828)
#define GPIO_O_INT5_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_O_INT5_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_O_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_O_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_O_INT5_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_O_INT5_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_O_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_O_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_INT5_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x3f)
#define GPIO_O_INT5_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_O_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_O_INT5_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x3f, GPIO_O_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_O_INT5_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_O_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_O_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
#define GPIO_O_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_O_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_O_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_O_INT6_ROUTE_MAPPING_0
#define GPIO_O_INT6_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x582c)
#define GPIO_O_INT6_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_O_INT6_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_O_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_O_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_O_INT6_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_O_INT6_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_O_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_O_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_INT6_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x3f)
#define GPIO_O_INT6_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_O_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_O_INT6_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x3f, GPIO_O_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_O_INT6_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_O_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_O_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
#define GPIO_O_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_O_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_O_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_O_INT7_ROUTE_MAPPING_0
#define GPIO_O_INT7_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x5830)
#define GPIO_O_INT7_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_O_INT7_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_O_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_O_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_O_INT7_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_O_INT7_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_O_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_O_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_INT7_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x3f)
#define GPIO_O_INT7_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_O_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_O_INT7_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x3f, GPIO_O_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_O_INT7_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_O_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_O_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
#define GPIO_O_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_O_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_O_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_J_INT0_ROUTE_MAPPING_0
#define GPIO_J_INT0_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x5834)
#define GPIO_J_INT0_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_J_INT0_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_J_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_J_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_J_INT0_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_J_INT0_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_J_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_J_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_INT0_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x3f)
#define GPIO_J_INT0_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_J_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_J_INT0_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x3f, GPIO_J_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_J_INT0_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_J_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_J_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
#define GPIO_J_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_J_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_J_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_J_INT1_ROUTE_MAPPING_0
#define GPIO_J_INT1_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x5838)
#define GPIO_J_INT1_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_J_INT1_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_J_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_J_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_J_INT1_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_J_INT1_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_J_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_J_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_INT1_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x3f)
#define GPIO_J_INT1_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_J_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_J_INT1_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x3f, GPIO_J_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_J_INT1_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_J_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_J_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
#define GPIO_J_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_J_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_J_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_J_INT2_ROUTE_MAPPING_0
#define GPIO_J_INT2_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x583c)
#define GPIO_J_INT2_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_J_INT2_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_J_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_J_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_J_INT2_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_J_INT2_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_J_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_J_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_INT2_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x3f)
#define GPIO_J_INT2_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_J_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_J_INT2_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x3f, GPIO_J_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_J_INT2_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_J_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_J_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
#define GPIO_J_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_J_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_J_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_J_INT3_ROUTE_MAPPING_0
#define GPIO_J_INT3_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x5840)
#define GPIO_J_INT3_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_J_INT3_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_J_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_J_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_J_INT3_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_J_INT3_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_J_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_J_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_INT3_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x3f)
#define GPIO_J_INT3_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_J_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_J_INT3_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x3f, GPIO_J_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_J_INT3_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_J_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_J_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
#define GPIO_J_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_J_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_J_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_J_INT4_ROUTE_MAPPING_0
#define GPIO_J_INT4_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x5844)
#define GPIO_J_INT4_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_J_INT4_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_J_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_J_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_J_INT4_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_J_INT4_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_J_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_J_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_INT4_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x3f)
#define GPIO_J_INT4_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_J_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_J_INT4_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x3f, GPIO_J_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_J_INT4_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_J_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_J_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
#define GPIO_J_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_J_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_J_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_J_INT5_ROUTE_MAPPING_0
#define GPIO_J_INT5_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x5848)
#define GPIO_J_INT5_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_J_INT5_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_J_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_J_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_J_INT5_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_J_INT5_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_J_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_J_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_INT5_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x3f)
#define GPIO_J_INT5_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_J_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_J_INT5_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x3f, GPIO_J_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_J_INT5_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_J_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_J_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
#define GPIO_J_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_J_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_J_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_J_INT6_ROUTE_MAPPING_0
#define GPIO_J_INT6_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x584c)
#define GPIO_J_INT6_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_J_INT6_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_J_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_J_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_J_INT6_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_J_INT6_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_J_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_J_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_INT6_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x3f)
#define GPIO_J_INT6_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_J_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_J_INT6_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x3f, GPIO_J_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_J_INT6_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_J_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_J_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
#define GPIO_J_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_J_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_J_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_J_INT7_ROUTE_MAPPING_0
#define GPIO_J_INT7_ROUTE_MAPPING_0                     _MK_ADDR_CONST(0x5850)
#define GPIO_J_INT7_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_J_INT7_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_J_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_J_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_J_INT7_ROUTE_MAPPING_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_J_INT7_ROUTE_MAPPING_0_RESET_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_J_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_J_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_INT7_ROUTE_MAPPING_0_READ_MASK                   _MK_MASK_CONST(0x3f)
#define GPIO_J_INT7_ROUTE_MAPPING_0_WRITE_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_J_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_J_INT7_ROUTE_MAPPING_0_VAL_FIELD                   _MK_FIELD_CONST(0x3f, GPIO_J_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_J_INT7_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_J_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_J_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
#define GPIO_J_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_J_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_J_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_CTL5_SPARE_0
#define GPIO_CTL5_SPARE_0                       _MK_ADDR_CONST(0x5854)
#define GPIO_CTL5_SPARE_0_SECURE                        0x0
#define GPIO_CTL5_SPARE_0_DUAL                  0x0
#define GPIO_CTL5_SPARE_0_SCR                   0
#define GPIO_CTL5_SPARE_0_WORD_COUNT                    0x1
#define GPIO_CTL5_SPARE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SPARE_0_RESET_MASK                    _MK_MASK_CONST(0xffff)
#define GPIO_CTL5_SPARE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SPARE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SPARE_0_READ_MASK                     _MK_MASK_CONST(0xffff)
#define GPIO_CTL5_SPARE_0_WRITE_MASK                    _MK_MASK_CONST(0xffff)
#define GPIO_CTL5_SPARE_0_SPARE_SHIFT                   _MK_SHIFT_CONST(0)
#define GPIO_CTL5_SPARE_0_SPARE_FIELD                   _MK_FIELD_CONST(0xffff, GPIO_CTL5_SPARE_0_SPARE_SHIFT)
#define GPIO_CTL5_SPARE_0_SPARE_RANGE                   15:0
#define GPIO_CTL5_SPARE_0_SPARE_WOFFSET                 0x0
#define GPIO_CTL5_SPARE_0_SPARE_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SPARE_0_SPARE_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define GPIO_CTL5_SPARE_0_SPARE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SPARE_0_SPARE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SPARE_0_SPARE_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_CTL5_SPARE_0_SPARE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register GPIO_GG_ENABLE_CONFIG_00_0
#define GPIO_GG_ENABLE_CONFIG_00_0                      _MK_ADDR_CONST(0x10000)
#define GPIO_GG_ENABLE_CONFIG_00_0_SECURE                       0x0
#define GPIO_GG_ENABLE_CONFIG_00_0_DUAL                         0x0
#define GPIO_GG_ENABLE_CONFIG_00_0_SCR                  GPIO_GG_SCR_00_0
#define GPIO_GG_ENABLE_CONFIG_00_0_WORD_COUNT                   0x1
#define GPIO_GG_ENABLE_CONFIG_00_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_RESET_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_GG_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_READ_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_GG_ENABLE_CONFIG_00_0_WRITE_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_GG_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                    _MK_SHIFT_CONST(0)
#define GPIO_GG_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                    _MK_FIELD_CONST(0x1, GPIO_GG_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_GG_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_GG_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_GG_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_GG_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_GG_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                  _MK_ENUM_CONST(0)
#define GPIO_GG_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                   _MK_ENUM_CONST(1)

#define GPIO_GG_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                 _MK_SHIFT_CONST(1)
#define GPIO_GG_ENABLE_CONFIG_00_0_IN_OUT_FIELD                 _MK_FIELD_CONST(0x1, GPIO_GG_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_GG_ENABLE_CONFIG_00_0_IN_OUT_RANGE                 1:1
#define GPIO_GG_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                       0x0
#define GPIO_GG_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_GG_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define GPIO_GG_ENABLE_CONFIG_00_0_IN_OUT_IN                    _MK_ENUM_CONST(0)
#define GPIO_GG_ENABLE_CONFIG_00_0_IN_OUT_OUT                   _MK_ENUM_CONST(1)

#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                   _MK_SHIFT_CONST(2)
#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                   _MK_FIELD_CONST(0x3, GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                      _MK_ENUM_CONST(0)
#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                   _MK_ENUM_CONST(1)
#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                     _MK_ENUM_CONST(2)
#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                     _MK_ENUM_CONST(3)

#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                  _MK_SHIFT_CONST(4)
#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                  _MK_FIELD_CONST(0x1, GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        _MK_ENUM_CONST(0)
#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        _MK_ENUM_CONST(1)

#define GPIO_GG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                      _MK_SHIFT_CONST(5)
#define GPIO_GG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_GG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_GG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_GG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_GG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_GG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_GG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_GG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_GG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                     _MK_SHIFT_CONST(6)
#define GPIO_GG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                     _MK_FIELD_CONST(0x1, GPIO_GG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_GG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_GG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_GG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_GG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_GG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_GG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_GG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                  _MK_SHIFT_CONST(7)
#define GPIO_GG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                  _MK_FIELD_CONST(0x1, GPIO_GG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_GG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_GG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_GG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_GG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_GG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                        _MK_ENUM_CONST(0)
#define GPIO_GG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                 _MK_ENUM_CONST(1)


// Register GPIO_GG_DEBOUNCE_THRESHOLD_00_0
#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0                 _MK_ADDR_CONST(0x10004)
#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_SECURE                  0x0
#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_DUAL                    0x0
#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_SCR                     GPIO_GG_SCR_00_0
#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                      0x1
#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                      _MK_MASK_CONST(0xff)
#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_READ_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                      _MK_MASK_CONST(0xff)
#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                        _MK_FIELD_CONST(0xff, GPIO_GG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_GG_INPUT_00_0
#define GPIO_GG_INPUT_00_0                      _MK_ADDR_CONST(0x10008)
#define GPIO_GG_INPUT_00_0_SECURE                       0x0
#define GPIO_GG_INPUT_00_0_DUAL                         0x0
#define GPIO_GG_INPUT_00_0_SCR                  GPIO_GG_SCR_00_0
#define GPIO_GG_INPUT_00_0_WORD_COUNT                   0x1
#define GPIO_GG_INPUT_00_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_GG_INPUT_00_0_RESET_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_GG_INPUT_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_GG_INPUT_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_GG_INPUT_00_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_GG_INPUT_00_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_GG_INPUT_00_0_GPIO_IN_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_GG_INPUT_00_0_GPIO_IN_FIELD                        _MK_FIELD_CONST(0x1, GPIO_GG_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_GG_INPUT_00_0_GPIO_IN_RANGE                        0:0
#define GPIO_GG_INPUT_00_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_GG_INPUT_00_0_GPIO_IN_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_GG_INPUT_00_0_GPIO_IN_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_GG_INPUT_00_0_GPIO_IN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_GG_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_GG_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_GG_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_GG_OUTPUT_CONTROL_00_0
#define GPIO_GG_OUTPUT_CONTROL_00_0                     _MK_ADDR_CONST(0x1000c)
#define GPIO_GG_OUTPUT_CONTROL_00_0_SECURE                      0x0
#define GPIO_GG_OUTPUT_CONTROL_00_0_DUAL                        0x0
#define GPIO_GG_OUTPUT_CONTROL_00_0_SCR                         GPIO_GG_SCR_00_0
#define GPIO_GG_OUTPUT_CONTROL_00_0_WORD_COUNT                  0x1
#define GPIO_GG_OUTPUT_CONTROL_00_0_RESET_VAL                   _MK_MASK_CONST(0x1)
#define GPIO_GG_OUTPUT_CONTROL_00_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_GG_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_GG_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_GG_OUTPUT_CONTROL_00_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_GG_OUTPUT_CONTROL_00_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_GG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                      _MK_SHIFT_CONST(0)
#define GPIO_GG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                      _MK_FIELD_CONST(0x1, GPIO_GG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_GG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_GG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_GG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                    _MK_MASK_CONST(0x1)
#define GPIO_GG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_GG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_GG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_GG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_GG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                     _MK_ENUM_CONST(0)
#define GPIO_GG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                    _MK_ENUM_CONST(1)


// Register GPIO_GG_OUTPUT_VALUE_00_0
#define GPIO_GG_OUTPUT_VALUE_00_0                       _MK_ADDR_CONST(0x10010)
#define GPIO_GG_OUTPUT_VALUE_00_0_SECURE                        0x0
#define GPIO_GG_OUTPUT_VALUE_00_0_DUAL                  0x0
#define GPIO_GG_OUTPUT_VALUE_00_0_SCR                   GPIO_GG_SCR_00_0
#define GPIO_GG_OUTPUT_VALUE_00_0_WORD_COUNT                    0x1
#define GPIO_GG_OUTPUT_VALUE_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_GG_OUTPUT_VALUE_00_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_GG_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_GG_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_GG_OUTPUT_VALUE_00_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_GG_OUTPUT_VALUE_00_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_GG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                    _MK_SHIFT_CONST(0)
#define GPIO_GG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                    _MK_FIELD_CONST(0x1, GPIO_GG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_GG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_GG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_GG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_GG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_GG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_GG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_GG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_GG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register GPIO_GG_INTERRUPT_CLEAR_00_0
#define GPIO_GG_INTERRUPT_CLEAR_00_0                    _MK_ADDR_CONST(0x10014)
#define GPIO_GG_INTERRUPT_CLEAR_00_0_SECURE                     0x0
#define GPIO_GG_INTERRUPT_CLEAR_00_0_DUAL                       0x0
#define GPIO_GG_INTERRUPT_CLEAR_00_0_SCR                        GPIO_GG_SCR_00_0
#define GPIO_GG_INTERRUPT_CLEAR_00_0_WORD_COUNT                         0x1
#define GPIO_GG_INTERRUPT_CLEAR_00_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_CLEAR_00_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define GPIO_GG_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_CLEAR_00_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_GG_INTERRUPT_CLEAR_00_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define GPIO_GG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_GG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                 _MK_FIELD_CONST(0x1, GPIO_GG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_GG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_GG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_GG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_GG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define GPIO_GG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     _MK_ENUM_CONST(0)
#define GPIO_GG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                 _MK_ENUM_CONST(1)


// Reserved address 0x10018

// Reserved address 0x1001c

// Register GPIO_GG_ENABLE_CONFIG_01_0
#define GPIO_GG_ENABLE_CONFIG_01_0                      _MK_ADDR_CONST(0x10020)
#define GPIO_GG_ENABLE_CONFIG_01_0_SECURE                       0x0
#define GPIO_GG_ENABLE_CONFIG_01_0_DUAL                         0x0
#define GPIO_GG_ENABLE_CONFIG_01_0_SCR                  GPIO_GG_SCR_01_0
#define GPIO_GG_ENABLE_CONFIG_01_0_WORD_COUNT                   0x1
#define GPIO_GG_ENABLE_CONFIG_01_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_01_0_RESET_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_GG_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_01_0_READ_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_GG_ENABLE_CONFIG_01_0_WRITE_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_GG_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                    _MK_SHIFT_CONST(0)
#define GPIO_GG_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                    _MK_FIELD_CONST(0x1, GPIO_GG_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_GG_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_GG_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_GG_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_GG_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_GG_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                  _MK_ENUM_CONST(0)
#define GPIO_GG_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                   _MK_ENUM_CONST(1)

#define GPIO_GG_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                 _MK_SHIFT_CONST(1)
#define GPIO_GG_ENABLE_CONFIG_01_0_IN_OUT_FIELD                 _MK_FIELD_CONST(0x1, GPIO_GG_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_GG_ENABLE_CONFIG_01_0_IN_OUT_RANGE                 1:1
#define GPIO_GG_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                       0x0
#define GPIO_GG_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_GG_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define GPIO_GG_ENABLE_CONFIG_01_0_IN_OUT_IN                    _MK_ENUM_CONST(0)
#define GPIO_GG_ENABLE_CONFIG_01_0_IN_OUT_OUT                   _MK_ENUM_CONST(1)

#define GPIO_GG_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                   _MK_SHIFT_CONST(2)
#define GPIO_GG_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                   _MK_FIELD_CONST(0x3, GPIO_GG_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_GG_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_GG_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_GG_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define GPIO_GG_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_GG_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                      _MK_ENUM_CONST(0)
#define GPIO_GG_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                   _MK_ENUM_CONST(1)
#define GPIO_GG_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                     _MK_ENUM_CONST(2)
#define GPIO_GG_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                     _MK_ENUM_CONST(3)

#define GPIO_GG_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                  _MK_SHIFT_CONST(4)
#define GPIO_GG_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                  _MK_FIELD_CONST(0x1, GPIO_GG_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_GG_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_GG_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_GG_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_GG_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_GG_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        _MK_ENUM_CONST(0)
#define GPIO_GG_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        _MK_ENUM_CONST(1)

#define GPIO_GG_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                      _MK_SHIFT_CONST(5)
#define GPIO_GG_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_GG_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_GG_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_GG_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_GG_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_GG_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_GG_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_GG_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_GG_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                     _MK_SHIFT_CONST(6)
#define GPIO_GG_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                     _MK_FIELD_CONST(0x1, GPIO_GG_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_GG_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_GG_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_GG_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_GG_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_GG_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_GG_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_GG_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                  _MK_SHIFT_CONST(7)
#define GPIO_GG_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                  _MK_FIELD_CONST(0x1, GPIO_GG_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_GG_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_GG_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_GG_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_GG_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_GG_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_GG_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                        _MK_ENUM_CONST(0)
#define GPIO_GG_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                 _MK_ENUM_CONST(1)


// Register GPIO_GG_DEBOUNCE_THRESHOLD_01_0
#define GPIO_GG_DEBOUNCE_THRESHOLD_01_0                 _MK_ADDR_CONST(0x10024)
#define GPIO_GG_DEBOUNCE_THRESHOLD_01_0_SECURE                  0x0
#define GPIO_GG_DEBOUNCE_THRESHOLD_01_0_DUAL                    0x0
#define GPIO_GG_DEBOUNCE_THRESHOLD_01_0_SCR                     GPIO_GG_SCR_01_0
#define GPIO_GG_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                      0x1
#define GPIO_GG_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_GG_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                      _MK_MASK_CONST(0xff)
#define GPIO_GG_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_GG_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_GG_DEBOUNCE_THRESHOLD_01_0_READ_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_GG_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                      _MK_MASK_CONST(0xff)
#define GPIO_GG_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_GG_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                        _MK_FIELD_CONST(0xff, GPIO_GG_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_GG_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_GG_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_GG_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_GG_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_GG_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_GG_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_GG_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_GG_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_GG_INPUT_01_0
#define GPIO_GG_INPUT_01_0                      _MK_ADDR_CONST(0x10028)
#define GPIO_GG_INPUT_01_0_SECURE                       0x0
#define GPIO_GG_INPUT_01_0_DUAL                         0x0
#define GPIO_GG_INPUT_01_0_SCR                  GPIO_GG_SCR_01_0
#define GPIO_GG_INPUT_01_0_WORD_COUNT                   0x1
#define GPIO_GG_INPUT_01_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_GG_INPUT_01_0_RESET_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_GG_INPUT_01_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_GG_INPUT_01_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_GG_INPUT_01_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_GG_INPUT_01_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_GG_INPUT_01_0_GPIO_IN_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_GG_INPUT_01_0_GPIO_IN_FIELD                        _MK_FIELD_CONST(0x1, GPIO_GG_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_GG_INPUT_01_0_GPIO_IN_RANGE                        0:0
#define GPIO_GG_INPUT_01_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_GG_INPUT_01_0_GPIO_IN_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_GG_INPUT_01_0_GPIO_IN_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_GG_INPUT_01_0_GPIO_IN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_GG_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_GG_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_GG_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_GG_OUTPUT_CONTROL_01_0
#define GPIO_GG_OUTPUT_CONTROL_01_0                     _MK_ADDR_CONST(0x1002c)
#define GPIO_GG_OUTPUT_CONTROL_01_0_SECURE                      0x0
#define GPIO_GG_OUTPUT_CONTROL_01_0_DUAL                        0x0
#define GPIO_GG_OUTPUT_CONTROL_01_0_SCR                         GPIO_GG_SCR_01_0
#define GPIO_GG_OUTPUT_CONTROL_01_0_WORD_COUNT                  0x1
#define GPIO_GG_OUTPUT_CONTROL_01_0_RESET_VAL                   _MK_MASK_CONST(0x1)
#define GPIO_GG_OUTPUT_CONTROL_01_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_GG_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_GG_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_GG_OUTPUT_CONTROL_01_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_GG_OUTPUT_CONTROL_01_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_GG_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                      _MK_SHIFT_CONST(0)
#define GPIO_GG_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                      _MK_FIELD_CONST(0x1, GPIO_GG_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_GG_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_GG_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_GG_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                    _MK_MASK_CONST(0x1)
#define GPIO_GG_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_GG_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_GG_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_GG_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_GG_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                     _MK_ENUM_CONST(0)
#define GPIO_GG_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                    _MK_ENUM_CONST(1)


// Register GPIO_GG_OUTPUT_VALUE_01_0
#define GPIO_GG_OUTPUT_VALUE_01_0                       _MK_ADDR_CONST(0x10030)
#define GPIO_GG_OUTPUT_VALUE_01_0_SECURE                        0x0
#define GPIO_GG_OUTPUT_VALUE_01_0_DUAL                  0x0
#define GPIO_GG_OUTPUT_VALUE_01_0_SCR                   GPIO_GG_SCR_01_0
#define GPIO_GG_OUTPUT_VALUE_01_0_WORD_COUNT                    0x1
#define GPIO_GG_OUTPUT_VALUE_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_GG_OUTPUT_VALUE_01_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_GG_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_GG_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_GG_OUTPUT_VALUE_01_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_GG_OUTPUT_VALUE_01_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_GG_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                    _MK_SHIFT_CONST(0)
#define GPIO_GG_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                    _MK_FIELD_CONST(0x1, GPIO_GG_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_GG_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_GG_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_GG_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_GG_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_GG_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_GG_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_GG_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_GG_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register GPIO_GG_INTERRUPT_CLEAR_01_0
#define GPIO_GG_INTERRUPT_CLEAR_01_0                    _MK_ADDR_CONST(0x10034)
#define GPIO_GG_INTERRUPT_CLEAR_01_0_SECURE                     0x0
#define GPIO_GG_INTERRUPT_CLEAR_01_0_DUAL                       0x0
#define GPIO_GG_INTERRUPT_CLEAR_01_0_SCR                        GPIO_GG_SCR_01_0
#define GPIO_GG_INTERRUPT_CLEAR_01_0_WORD_COUNT                         0x1
#define GPIO_GG_INTERRUPT_CLEAR_01_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_CLEAR_01_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define GPIO_GG_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_CLEAR_01_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_GG_INTERRUPT_CLEAR_01_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define GPIO_GG_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_GG_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                 _MK_FIELD_CONST(0x1, GPIO_GG_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_GG_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_GG_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_GG_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_GG_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define GPIO_GG_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     _MK_ENUM_CONST(0)
#define GPIO_GG_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                 _MK_ENUM_CONST(1)


// Reserved address 0x10038

// Reserved address 0x1003c

// Reserved address 0x10040

// Reserved address 0x10044

// Reserved address 0x10048

// Reserved address 0x1004c

// Reserved address 0x10050

// Reserved address 0x10054

// Reserved address 0x10058

// Reserved address 0x1005c

// Reserved address 0x10060

// Reserved address 0x10064

// Reserved address 0x10068

// Reserved address 0x1006c

// Reserved address 0x10070

// Reserved address 0x10074

// Reserved address 0x10078

// Reserved address 0x1007c

// Reserved address 0x10080

// Reserved address 0x10084

// Reserved address 0x10088

// Reserved address 0x1008c

// Reserved address 0x10090

// Reserved address 0x10094

// Reserved address 0x10098

// Reserved address 0x1009c

// Reserved address 0x100a0

// Reserved address 0x100a4

// Reserved address 0x100a8

// Reserved address 0x100ac

// Reserved address 0x100b0

// Reserved address 0x100b4

// Reserved address 0x100b8

// Reserved address 0x100bc

// Reserved address 0x100c0

// Reserved address 0x100c4

// Reserved address 0x100c8

// Reserved address 0x100cc

// Reserved address 0x100d0

// Reserved address 0x100d4

// Reserved address 0x100d8

// Reserved address 0x100dc

// Reserved address 0x100e0

// Reserved address 0x100e4

// Reserved address 0x100e8

// Reserved address 0x100ec

// Reserved address 0x100f0

// Reserved address 0x100f4

// Reserved address 0x100f8

// Reserved address 0x100fc

// Register GPIO_GG_INTERRUPT_STATUS_G0_0
#define GPIO_GG_INTERRUPT_STATUS_G0_0                   _MK_ADDR_CONST(0x10100)
#define GPIO_GG_INTERRUPT_STATUS_G0_0_SECURE                    0x0
#define GPIO_GG_INTERRUPT_STATUS_G0_0_DUAL                      0x0
#define GPIO_GG_INTERRUPT_STATUS_G0_0_SCR                       0
#define GPIO_GG_INTERRUPT_STATUS_G0_0_WORD_COUNT                        0x1
#define GPIO_GG_INTERRUPT_STATUS_G0_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G0_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_GG_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G0_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_GG_INTERRUPT_STATUS_G0_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_GG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                       _MK_FIELD_CONST(0x3, GPIO_GG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_GG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                       1:0
#define GPIO_GG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_GG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_GG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_GG_INTERRUPT_STATUS_G1_0
#define GPIO_GG_INTERRUPT_STATUS_G1_0                   _MK_ADDR_CONST(0x10104)
#define GPIO_GG_INTERRUPT_STATUS_G1_0_SECURE                    0x0
#define GPIO_GG_INTERRUPT_STATUS_G1_0_DUAL                      0x0
#define GPIO_GG_INTERRUPT_STATUS_G1_0_SCR                       0
#define GPIO_GG_INTERRUPT_STATUS_G1_0_WORD_COUNT                        0x1
#define GPIO_GG_INTERRUPT_STATUS_G1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G1_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_GG_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G1_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_GG_INTERRUPT_STATUS_G1_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_GG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                       _MK_FIELD_CONST(0x3, GPIO_GG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_GG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                       1:0
#define GPIO_GG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_GG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_GG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_GG_INTERRUPT_STATUS_G2_0
#define GPIO_GG_INTERRUPT_STATUS_G2_0                   _MK_ADDR_CONST(0x10108)
#define GPIO_GG_INTERRUPT_STATUS_G2_0_SECURE                    0x0
#define GPIO_GG_INTERRUPT_STATUS_G2_0_DUAL                      0x0
#define GPIO_GG_INTERRUPT_STATUS_G2_0_SCR                       0
#define GPIO_GG_INTERRUPT_STATUS_G2_0_WORD_COUNT                        0x1
#define GPIO_GG_INTERRUPT_STATUS_G2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G2_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_GG_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G2_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_GG_INTERRUPT_STATUS_G2_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_GG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                       _MK_FIELD_CONST(0x3, GPIO_GG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_GG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                       1:0
#define GPIO_GG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_GG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_GG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_GG_INTERRUPT_STATUS_G3_0
#define GPIO_GG_INTERRUPT_STATUS_G3_0                   _MK_ADDR_CONST(0x1010c)
#define GPIO_GG_INTERRUPT_STATUS_G3_0_SECURE                    0x0
#define GPIO_GG_INTERRUPT_STATUS_G3_0_DUAL                      0x0
#define GPIO_GG_INTERRUPT_STATUS_G3_0_SCR                       0
#define GPIO_GG_INTERRUPT_STATUS_G3_0_WORD_COUNT                        0x1
#define GPIO_GG_INTERRUPT_STATUS_G3_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G3_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_GG_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G3_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_GG_INTERRUPT_STATUS_G3_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_GG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                       _MK_FIELD_CONST(0x3, GPIO_GG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_GG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                       1:0
#define GPIO_GG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_GG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_GG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_GG_INTERRUPT_STATUS_G4_0
#define GPIO_GG_INTERRUPT_STATUS_G4_0                   _MK_ADDR_CONST(0x10110)
#define GPIO_GG_INTERRUPT_STATUS_G4_0_SECURE                    0x0
#define GPIO_GG_INTERRUPT_STATUS_G4_0_DUAL                      0x0
#define GPIO_GG_INTERRUPT_STATUS_G4_0_SCR                       0
#define GPIO_GG_INTERRUPT_STATUS_G4_0_WORD_COUNT                        0x1
#define GPIO_GG_INTERRUPT_STATUS_G4_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G4_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_GG_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G4_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_GG_INTERRUPT_STATUS_G4_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_GG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                       _MK_FIELD_CONST(0x3, GPIO_GG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_GG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                       1:0
#define GPIO_GG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_GG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_GG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_GG_INTERRUPT_STATUS_G5_0
#define GPIO_GG_INTERRUPT_STATUS_G5_0                   _MK_ADDR_CONST(0x10114)
#define GPIO_GG_INTERRUPT_STATUS_G5_0_SECURE                    0x0
#define GPIO_GG_INTERRUPT_STATUS_G5_0_DUAL                      0x0
#define GPIO_GG_INTERRUPT_STATUS_G5_0_SCR                       0
#define GPIO_GG_INTERRUPT_STATUS_G5_0_WORD_COUNT                        0x1
#define GPIO_GG_INTERRUPT_STATUS_G5_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G5_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_GG_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G5_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_GG_INTERRUPT_STATUS_G5_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_GG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                       _MK_FIELD_CONST(0x3, GPIO_GG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_GG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                       1:0
#define GPIO_GG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_GG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_GG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_GG_INTERRUPT_STATUS_G6_0
#define GPIO_GG_INTERRUPT_STATUS_G6_0                   _MK_ADDR_CONST(0x10118)
#define GPIO_GG_INTERRUPT_STATUS_G6_0_SECURE                    0x0
#define GPIO_GG_INTERRUPT_STATUS_G6_0_DUAL                      0x0
#define GPIO_GG_INTERRUPT_STATUS_G6_0_SCR                       0
#define GPIO_GG_INTERRUPT_STATUS_G6_0_WORD_COUNT                        0x1
#define GPIO_GG_INTERRUPT_STATUS_G6_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G6_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_GG_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G6_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_GG_INTERRUPT_STATUS_G6_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_GG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                       _MK_FIELD_CONST(0x3, GPIO_GG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_GG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                       1:0
#define GPIO_GG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_GG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_GG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_GG_INTERRUPT_STATUS_G7_0
#define GPIO_GG_INTERRUPT_STATUS_G7_0                   _MK_ADDR_CONST(0x1011c)
#define GPIO_GG_INTERRUPT_STATUS_G7_0_SECURE                    0x0
#define GPIO_GG_INTERRUPT_STATUS_G7_0_DUAL                      0x0
#define GPIO_GG_INTERRUPT_STATUS_G7_0_SCR                       0
#define GPIO_GG_INTERRUPT_STATUS_G7_0_WORD_COUNT                        0x1
#define GPIO_GG_INTERRUPT_STATUS_G7_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G7_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_GG_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G7_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_GG_INTERRUPT_STATUS_G7_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_GG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                       _MK_FIELD_CONST(0x3, GPIO_GG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_GG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                       1:0
#define GPIO_GG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_GG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_GG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_GG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Reserved address 0x10120

// Reserved address 0x10124

// Reserved address 0x10128

// Reserved address 0x1012c

// Reserved address 0x10130

// Reserved address 0x10134

// Reserved address 0x10138

// Reserved address 0x1013c

// Reserved address 0x10140

// Reserved address 0x10144

// Reserved address 0x10148

// Reserved address 0x1014c

// Reserved address 0x10150

// Reserved address 0x10154

// Reserved address 0x10158

// Reserved address 0x1015c

// Reserved address 0x10160

// Reserved address 0x10164

// Reserved address 0x10168

// Reserved address 0x1016c

// Reserved address 0x10170

// Reserved address 0x10174

// Reserved address 0x10178

// Reserved address 0x1017c

// Reserved address 0x10180

// Reserved address 0x10184

// Reserved address 0x10188

// Reserved address 0x1018c

// Reserved address 0x10190

// Reserved address 0x10194

// Reserved address 0x10198

// Reserved address 0x1019c

// Reserved address 0x101a0

// Reserved address 0x101a4

// Reserved address 0x101a8

// Reserved address 0x101ac

// Reserved address 0x101b0

// Reserved address 0x101b4

// Reserved address 0x101b8

// Reserved address 0x101bc

// Reserved address 0x101c0

// Reserved address 0x101c4

// Reserved address 0x101c8

// Reserved address 0x101cc

// Reserved address 0x101d0

// Reserved address 0x101d4

// Reserved address 0x101d8

// Reserved address 0x101dc

// Reserved address 0x101e0

// Reserved address 0x101e4

// Reserved address 0x101e8

// Reserved address 0x101ec

// Reserved address 0x101f0

// Reserved address 0x101f4

// Reserved address 0x101f8

// Reserved address 0x101fc

// Register GPIO_V_ENABLE_CONFIG_00_0
#define GPIO_V_ENABLE_CONFIG_00_0                       _MK_ADDR_CONST(0x11000)
#define GPIO_V_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_V_ENABLE_CONFIG_00_0_DUAL                  0x0
#define GPIO_V_ENABLE_CONFIG_00_0_SCR                   GPIO_V_SCR_00_0
#define GPIO_V_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_V_ENABLE_CONFIG_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_00_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_V_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_00_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_V_ENABLE_CONFIG_00_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_V_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_V_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_V_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_V_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_V_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_V_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_V_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_V_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_V_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_V_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_V_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_V_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_00_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_00_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_V_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_V_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_V_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_V_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_V_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_V_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_V_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_V_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_V_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_V_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_V_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_V_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_V_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_V_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_V_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_V_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_V_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_V_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_V_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_V_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_V_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_V_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_V_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_V_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_V_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_V_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_V_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_V_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_V_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_V_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_V_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_V_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_V_DEBOUNCE_THRESHOLD_00_0
#define GPIO_V_DEBOUNCE_THRESHOLD_00_0                  _MK_ADDR_CONST(0x11004)
#define GPIO_V_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_V_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
#define GPIO_V_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_V_SCR_00_0
#define GPIO_V_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_V_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_V_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_V_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_V_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_V_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_V_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_V_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_V_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_V_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_V_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_V_INPUT_00_0
#define GPIO_V_INPUT_00_0                       _MK_ADDR_CONST(0x11008)
#define GPIO_V_INPUT_00_0_SECURE                        0x0
#define GPIO_V_INPUT_00_0_DUAL                  0x0
#define GPIO_V_INPUT_00_0_SCR                   GPIO_V_SCR_00_0
#define GPIO_V_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_V_INPUT_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_00_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_00_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_V_INPUT_00_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_00_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_V_INPUT_00_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_V_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_V_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_V_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_V_INPUT_00_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_00_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_V_OUTPUT_CONTROL_00_0
#define GPIO_V_OUTPUT_CONTROL_00_0                      _MK_ADDR_CONST(0x1100c)
#define GPIO_V_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_V_OUTPUT_CONTROL_00_0_DUAL                         0x0
#define GPIO_V_OUTPUT_CONTROL_00_0_SCR                  GPIO_V_SCR_00_0
#define GPIO_V_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_V_OUTPUT_CONTROL_00_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_00_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_CONTROL_00_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_00_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_V_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_V_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_V_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_V_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_V_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_V_OUTPUT_VALUE_00_0
#define GPIO_V_OUTPUT_VALUE_00_0                        _MK_ADDR_CONST(0x11010)
#define GPIO_V_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_V_OUTPUT_VALUE_00_0_DUAL                   0x0
#define GPIO_V_OUTPUT_VALUE_00_0_SCR                    GPIO_V_SCR_00_0
#define GPIO_V_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_V_OUTPUT_VALUE_00_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_00_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_00_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_VALUE_00_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_V_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_V_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_V_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_V_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_V_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_V_INTERRUPT_CLEAR_00_0
#define GPIO_V_INTERRUPT_CLEAR_00_0                     _MK_ADDR_CONST(0x11014)
#define GPIO_V_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_V_INTERRUPT_CLEAR_00_0_DUAL                        0x0
#define GPIO_V_INTERRUPT_CLEAR_00_0_SCR                         GPIO_V_SCR_00_0
#define GPIO_V_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_V_INTERRUPT_CLEAR_00_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_00_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_V_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_00_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_V_INTERRUPT_CLEAR_00_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_V_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_V_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_V_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_V_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_V_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_V_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_V_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_V_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_V_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x11018

// Reserved address 0x1101c

// Register GPIO_V_ENABLE_CONFIG_01_0
#define GPIO_V_ENABLE_CONFIG_01_0                       _MK_ADDR_CONST(0x11020)
#define GPIO_V_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_V_ENABLE_CONFIG_01_0_DUAL                  0x0
#define GPIO_V_ENABLE_CONFIG_01_0_SCR                   GPIO_V_SCR_01_0
#define GPIO_V_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_V_ENABLE_CONFIG_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_01_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_V_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_01_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_V_ENABLE_CONFIG_01_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_V_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_V_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_V_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_V_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_V_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_V_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_V_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_V_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_V_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_V_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_V_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_V_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_01_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_01_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_V_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_V_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_V_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_V_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_V_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_V_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_V_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_V_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_V_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_V_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_V_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_V_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_V_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_V_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_V_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_V_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_V_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_V_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_V_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_V_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_V_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_V_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_V_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_V_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_V_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_V_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_V_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_V_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_V_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_V_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_V_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_V_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_V_DEBOUNCE_THRESHOLD_01_0
#define GPIO_V_DEBOUNCE_THRESHOLD_01_0                  _MK_ADDR_CONST(0x11024)
#define GPIO_V_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_V_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
#define GPIO_V_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_V_SCR_01_0
#define GPIO_V_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_V_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_V_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_V_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_V_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_V_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_V_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_V_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_V_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_V_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_V_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_V_INPUT_01_0
#define GPIO_V_INPUT_01_0                       _MK_ADDR_CONST(0x11028)
#define GPIO_V_INPUT_01_0_SECURE                        0x0
#define GPIO_V_INPUT_01_0_DUAL                  0x0
#define GPIO_V_INPUT_01_0_SCR                   GPIO_V_SCR_01_0
#define GPIO_V_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_V_INPUT_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_01_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_01_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_V_INPUT_01_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_01_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_V_INPUT_01_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_V_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_V_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_V_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_V_INPUT_01_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_01_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_V_OUTPUT_CONTROL_01_0
#define GPIO_V_OUTPUT_CONTROL_01_0                      _MK_ADDR_CONST(0x1102c)
#define GPIO_V_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_V_OUTPUT_CONTROL_01_0_DUAL                         0x0
#define GPIO_V_OUTPUT_CONTROL_01_0_SCR                  GPIO_V_SCR_01_0
#define GPIO_V_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_V_OUTPUT_CONTROL_01_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_01_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_CONTROL_01_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_01_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_V_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_V_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_V_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_V_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_V_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_V_OUTPUT_VALUE_01_0
#define GPIO_V_OUTPUT_VALUE_01_0                        _MK_ADDR_CONST(0x11030)
#define GPIO_V_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_V_OUTPUT_VALUE_01_0_DUAL                   0x0
#define GPIO_V_OUTPUT_VALUE_01_0_SCR                    GPIO_V_SCR_01_0
#define GPIO_V_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_V_OUTPUT_VALUE_01_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_01_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_01_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_VALUE_01_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_V_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_V_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_V_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_V_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_V_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_V_INTERRUPT_CLEAR_01_0
#define GPIO_V_INTERRUPT_CLEAR_01_0                     _MK_ADDR_CONST(0x11034)
#define GPIO_V_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_V_INTERRUPT_CLEAR_01_0_DUAL                        0x0
#define GPIO_V_INTERRUPT_CLEAR_01_0_SCR                         GPIO_V_SCR_01_0
#define GPIO_V_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_V_INTERRUPT_CLEAR_01_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_01_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_V_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_01_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_V_INTERRUPT_CLEAR_01_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_V_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_V_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_V_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_V_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_V_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_V_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_V_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_V_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_V_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x11038

// Reserved address 0x1103c

// Register GPIO_V_ENABLE_CONFIG_02_0
#define GPIO_V_ENABLE_CONFIG_02_0                       _MK_ADDR_CONST(0x11040)
#define GPIO_V_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_V_ENABLE_CONFIG_02_0_DUAL                  0x0
#define GPIO_V_ENABLE_CONFIG_02_0_SCR                   GPIO_V_SCR_02_0
#define GPIO_V_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_V_ENABLE_CONFIG_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_02_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_V_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_02_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_V_ENABLE_CONFIG_02_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_V_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_V_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_V_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_V_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_V_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_V_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_V_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_V_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_V_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_V_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_V_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_V_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_02_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_02_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_V_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_V_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_V_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_V_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_V_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_V_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_V_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_V_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_V_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_V_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_V_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_V_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_V_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_V_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_V_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_V_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_V_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_V_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_V_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_V_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_V_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_V_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_V_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_V_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_V_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_V_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_V_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_V_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_V_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_V_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_V_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_V_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_V_DEBOUNCE_THRESHOLD_02_0
#define GPIO_V_DEBOUNCE_THRESHOLD_02_0                  _MK_ADDR_CONST(0x11044)
#define GPIO_V_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_V_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
#define GPIO_V_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_V_SCR_02_0
#define GPIO_V_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_V_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_V_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_V_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_V_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_V_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_V_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_V_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_V_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_V_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_V_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_V_INPUT_02_0
#define GPIO_V_INPUT_02_0                       _MK_ADDR_CONST(0x11048)
#define GPIO_V_INPUT_02_0_SECURE                        0x0
#define GPIO_V_INPUT_02_0_DUAL                  0x0
#define GPIO_V_INPUT_02_0_SCR                   GPIO_V_SCR_02_0
#define GPIO_V_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_V_INPUT_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_02_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_02_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_V_INPUT_02_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_02_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_V_INPUT_02_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_V_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_V_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_V_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_V_INPUT_02_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_02_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_V_OUTPUT_CONTROL_02_0
#define GPIO_V_OUTPUT_CONTROL_02_0                      _MK_ADDR_CONST(0x1104c)
#define GPIO_V_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_V_OUTPUT_CONTROL_02_0_DUAL                         0x0
#define GPIO_V_OUTPUT_CONTROL_02_0_SCR                  GPIO_V_SCR_02_0
#define GPIO_V_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_V_OUTPUT_CONTROL_02_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_02_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_CONTROL_02_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_02_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_V_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_V_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_V_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_V_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_V_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_V_OUTPUT_VALUE_02_0
#define GPIO_V_OUTPUT_VALUE_02_0                        _MK_ADDR_CONST(0x11050)
#define GPIO_V_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_V_OUTPUT_VALUE_02_0_DUAL                   0x0
#define GPIO_V_OUTPUT_VALUE_02_0_SCR                    GPIO_V_SCR_02_0
#define GPIO_V_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_V_OUTPUT_VALUE_02_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_02_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_02_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_VALUE_02_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_V_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_V_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_V_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_V_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_V_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_V_INTERRUPT_CLEAR_02_0
#define GPIO_V_INTERRUPT_CLEAR_02_0                     _MK_ADDR_CONST(0x11054)
#define GPIO_V_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_V_INTERRUPT_CLEAR_02_0_DUAL                        0x0
#define GPIO_V_INTERRUPT_CLEAR_02_0_SCR                         GPIO_V_SCR_02_0
#define GPIO_V_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_V_INTERRUPT_CLEAR_02_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_02_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_V_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_02_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_V_INTERRUPT_CLEAR_02_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_V_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_V_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_V_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_V_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_V_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_V_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_V_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_V_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_V_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x11058

// Reserved address 0x1105c

// Register GPIO_V_ENABLE_CONFIG_03_0
#define GPIO_V_ENABLE_CONFIG_03_0                       _MK_ADDR_CONST(0x11060)
#define GPIO_V_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_V_ENABLE_CONFIG_03_0_DUAL                  0x0
#define GPIO_V_ENABLE_CONFIG_03_0_SCR                   GPIO_V_SCR_03_0
#define GPIO_V_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_V_ENABLE_CONFIG_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_03_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_V_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_03_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_V_ENABLE_CONFIG_03_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_V_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_V_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_V_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_V_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_V_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_V_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_V_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_V_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_V_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_V_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_V_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_V_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_03_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_03_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_V_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_V_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_V_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_V_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_V_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_V_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_V_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_V_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_V_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_V_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_V_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_V_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_V_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_V_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_V_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_V_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_V_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_V_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_V_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_V_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_V_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_V_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_V_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_V_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_V_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_V_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_V_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_V_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_V_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_V_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_V_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_V_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_V_DEBOUNCE_THRESHOLD_03_0
#define GPIO_V_DEBOUNCE_THRESHOLD_03_0                  _MK_ADDR_CONST(0x11064)
#define GPIO_V_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_V_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
#define GPIO_V_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_V_SCR_03_0
#define GPIO_V_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_V_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_V_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_V_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_V_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_V_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_V_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_V_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_V_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_V_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_V_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_V_INPUT_03_0
#define GPIO_V_INPUT_03_0                       _MK_ADDR_CONST(0x11068)
#define GPIO_V_INPUT_03_0_SECURE                        0x0
#define GPIO_V_INPUT_03_0_DUAL                  0x0
#define GPIO_V_INPUT_03_0_SCR                   GPIO_V_SCR_03_0
#define GPIO_V_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_V_INPUT_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_03_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_03_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_V_INPUT_03_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_03_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_V_INPUT_03_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_V_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_V_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_V_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_V_INPUT_03_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_03_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_V_OUTPUT_CONTROL_03_0
#define GPIO_V_OUTPUT_CONTROL_03_0                      _MK_ADDR_CONST(0x1106c)
#define GPIO_V_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_V_OUTPUT_CONTROL_03_0_DUAL                         0x0
#define GPIO_V_OUTPUT_CONTROL_03_0_SCR                  GPIO_V_SCR_03_0
#define GPIO_V_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_V_OUTPUT_CONTROL_03_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_03_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_CONTROL_03_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_03_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_V_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_V_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_V_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_V_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_V_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_V_OUTPUT_VALUE_03_0
#define GPIO_V_OUTPUT_VALUE_03_0                        _MK_ADDR_CONST(0x11070)
#define GPIO_V_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_V_OUTPUT_VALUE_03_0_DUAL                   0x0
#define GPIO_V_OUTPUT_VALUE_03_0_SCR                    GPIO_V_SCR_03_0
#define GPIO_V_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_V_OUTPUT_VALUE_03_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_03_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_03_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_VALUE_03_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_V_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_V_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_V_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_V_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_V_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_V_INTERRUPT_CLEAR_03_0
#define GPIO_V_INTERRUPT_CLEAR_03_0                     _MK_ADDR_CONST(0x11074)
#define GPIO_V_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_V_INTERRUPT_CLEAR_03_0_DUAL                        0x0
#define GPIO_V_INTERRUPT_CLEAR_03_0_SCR                         GPIO_V_SCR_03_0
#define GPIO_V_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_V_INTERRUPT_CLEAR_03_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_03_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_V_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_03_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_V_INTERRUPT_CLEAR_03_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_V_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_V_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_V_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_V_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_V_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_V_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_V_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_V_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_V_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x11078

// Reserved address 0x1107c

// Register GPIO_V_ENABLE_CONFIG_04_0
#define GPIO_V_ENABLE_CONFIG_04_0                       _MK_ADDR_CONST(0x11080)
#define GPIO_V_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_V_ENABLE_CONFIG_04_0_DUAL                  0x0
#define GPIO_V_ENABLE_CONFIG_04_0_SCR                   GPIO_V_SCR_04_0
#define GPIO_V_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_V_ENABLE_CONFIG_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_04_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_V_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_04_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_V_ENABLE_CONFIG_04_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_V_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_V_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_V_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_V_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_V_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_V_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_V_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_V_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_V_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_V_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_V_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_V_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_04_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_04_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_V_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_V_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_V_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_V_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_V_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_V_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_V_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_V_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_V_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_V_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_V_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_V_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_V_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_V_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_V_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_V_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_V_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_V_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_V_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_V_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_V_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_V_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_V_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_V_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_V_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_V_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_V_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_V_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_V_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_V_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_V_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_V_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_V_DEBOUNCE_THRESHOLD_04_0
#define GPIO_V_DEBOUNCE_THRESHOLD_04_0                  _MK_ADDR_CONST(0x11084)
#define GPIO_V_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_V_DEBOUNCE_THRESHOLD_04_0_DUAL                     0x0
#define GPIO_V_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_V_SCR_04_0
#define GPIO_V_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_V_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_V_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_V_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_V_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_V_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_V_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_V_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_V_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_V_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_V_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_V_INPUT_04_0
#define GPIO_V_INPUT_04_0                       _MK_ADDR_CONST(0x11088)
#define GPIO_V_INPUT_04_0_SECURE                        0x0
#define GPIO_V_INPUT_04_0_DUAL                  0x0
#define GPIO_V_INPUT_04_0_SCR                   GPIO_V_SCR_04_0
#define GPIO_V_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_V_INPUT_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_04_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_04_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_V_INPUT_04_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_04_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_V_INPUT_04_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_V_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_V_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_V_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_V_INPUT_04_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_04_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_V_OUTPUT_CONTROL_04_0
#define GPIO_V_OUTPUT_CONTROL_04_0                      _MK_ADDR_CONST(0x1108c)
#define GPIO_V_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_V_OUTPUT_CONTROL_04_0_DUAL                         0x0
#define GPIO_V_OUTPUT_CONTROL_04_0_SCR                  GPIO_V_SCR_04_0
#define GPIO_V_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_V_OUTPUT_CONTROL_04_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_04_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_CONTROL_04_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_04_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_V_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_V_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_V_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_V_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_V_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_V_OUTPUT_VALUE_04_0
#define GPIO_V_OUTPUT_VALUE_04_0                        _MK_ADDR_CONST(0x11090)
#define GPIO_V_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_V_OUTPUT_VALUE_04_0_DUAL                   0x0
#define GPIO_V_OUTPUT_VALUE_04_0_SCR                    GPIO_V_SCR_04_0
#define GPIO_V_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_V_OUTPUT_VALUE_04_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_04_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_04_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_VALUE_04_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_V_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_V_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_V_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_V_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_V_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_V_INTERRUPT_CLEAR_04_0
#define GPIO_V_INTERRUPT_CLEAR_04_0                     _MK_ADDR_CONST(0x11094)
#define GPIO_V_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_V_INTERRUPT_CLEAR_04_0_DUAL                        0x0
#define GPIO_V_INTERRUPT_CLEAR_04_0_SCR                         GPIO_V_SCR_04_0
#define GPIO_V_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_V_INTERRUPT_CLEAR_04_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_04_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_V_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_04_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_V_INTERRUPT_CLEAR_04_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_V_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_V_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_V_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_V_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_V_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_V_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_V_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_V_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_V_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x11098

// Reserved address 0x1109c

// Register GPIO_V_ENABLE_CONFIG_05_0
#define GPIO_V_ENABLE_CONFIG_05_0                       _MK_ADDR_CONST(0x110a0)
#define GPIO_V_ENABLE_CONFIG_05_0_SECURE                        0x0
#define GPIO_V_ENABLE_CONFIG_05_0_DUAL                  0x0
#define GPIO_V_ENABLE_CONFIG_05_0_SCR                   GPIO_V_SCR_05_0
#define GPIO_V_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
#define GPIO_V_ENABLE_CONFIG_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_05_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_V_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_05_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_V_ENABLE_CONFIG_05_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_V_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_V_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_V_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_V_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_V_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_V_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_V_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_V_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_V_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_V_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
#define GPIO_V_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
#define GPIO_V_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_05_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_05_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_V_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_V_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_V_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_V_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_V_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_V_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_V_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_V_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_V_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_V_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_V_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_V_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_V_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_V_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_V_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_V_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_V_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_V_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_V_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_V_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_V_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_V_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_V_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_V_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_V_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_V_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_V_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_V_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_V_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_V_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_V_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_V_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_V_DEBOUNCE_THRESHOLD_05_0
#define GPIO_V_DEBOUNCE_THRESHOLD_05_0                  _MK_ADDR_CONST(0x110a4)
#define GPIO_V_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
#define GPIO_V_DEBOUNCE_THRESHOLD_05_0_DUAL                     0x0
#define GPIO_V_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_V_SCR_05_0
#define GPIO_V_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
#define GPIO_V_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_V_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_V_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_V_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_V_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_V_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_V_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_V_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_V_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_V_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_V_INPUT_05_0
#define GPIO_V_INPUT_05_0                       _MK_ADDR_CONST(0x110a8)
#define GPIO_V_INPUT_05_0_SECURE                        0x0
#define GPIO_V_INPUT_05_0_DUAL                  0x0
#define GPIO_V_INPUT_05_0_SCR                   GPIO_V_SCR_05_0
#define GPIO_V_INPUT_05_0_WORD_COUNT                    0x1
#define GPIO_V_INPUT_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_05_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_05_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_V_INPUT_05_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_05_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_V_INPUT_05_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_V_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_V_INPUT_05_0_GPIO_IN_RANGE                 0:0
#define GPIO_V_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_V_INPUT_05_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_05_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_V_OUTPUT_CONTROL_05_0
#define GPIO_V_OUTPUT_CONTROL_05_0                      _MK_ADDR_CONST(0x110ac)
#define GPIO_V_OUTPUT_CONTROL_05_0_SECURE                       0x0
#define GPIO_V_OUTPUT_CONTROL_05_0_DUAL                         0x0
#define GPIO_V_OUTPUT_CONTROL_05_0_SCR                  GPIO_V_SCR_05_0
#define GPIO_V_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
#define GPIO_V_OUTPUT_CONTROL_05_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_05_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_CONTROL_05_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_05_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_V_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_V_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_V_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_V_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_V_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_V_OUTPUT_VALUE_05_0
#define GPIO_V_OUTPUT_VALUE_05_0                        _MK_ADDR_CONST(0x110b0)
#define GPIO_V_OUTPUT_VALUE_05_0_SECURE                         0x0
#define GPIO_V_OUTPUT_VALUE_05_0_DUAL                   0x0
#define GPIO_V_OUTPUT_VALUE_05_0_SCR                    GPIO_V_SCR_05_0
#define GPIO_V_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
#define GPIO_V_OUTPUT_VALUE_05_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_05_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_05_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_VALUE_05_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_V_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_V_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_V_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_V_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_V_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_V_INTERRUPT_CLEAR_05_0
#define GPIO_V_INTERRUPT_CLEAR_05_0                     _MK_ADDR_CONST(0x110b4)
#define GPIO_V_INTERRUPT_CLEAR_05_0_SECURE                      0x0
#define GPIO_V_INTERRUPT_CLEAR_05_0_DUAL                        0x0
#define GPIO_V_INTERRUPT_CLEAR_05_0_SCR                         GPIO_V_SCR_05_0
#define GPIO_V_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
#define GPIO_V_INTERRUPT_CLEAR_05_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_05_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_V_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_05_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_V_INTERRUPT_CLEAR_05_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_V_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_V_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_V_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_V_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_V_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_V_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_V_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_V_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_V_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x110b8

// Reserved address 0x110bc

// Register GPIO_V_ENABLE_CONFIG_06_0
#define GPIO_V_ENABLE_CONFIG_06_0                       _MK_ADDR_CONST(0x110c0)
#define GPIO_V_ENABLE_CONFIG_06_0_SECURE                        0x0
#define GPIO_V_ENABLE_CONFIG_06_0_DUAL                  0x0
#define GPIO_V_ENABLE_CONFIG_06_0_SCR                   GPIO_V_SCR_06_0
#define GPIO_V_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
#define GPIO_V_ENABLE_CONFIG_06_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_06_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_V_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_06_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_V_ENABLE_CONFIG_06_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_V_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_V_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_V_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
#define GPIO_V_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_V_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_V_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_06_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_06_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_V_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_V_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_V_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
#define GPIO_V_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
#define GPIO_V_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
#define GPIO_V_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_06_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_06_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_06_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_06_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_V_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_V_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_V_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
#define GPIO_V_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_V_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_V_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_V_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_V_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_V_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_V_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_V_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_V_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_V_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_V_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_V_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_V_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_V_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_V_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_V_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_V_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_V_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_V_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_V_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_V_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_V_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_V_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_V_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_V_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_V_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_V_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_V_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_V_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_V_DEBOUNCE_THRESHOLD_06_0
#define GPIO_V_DEBOUNCE_THRESHOLD_06_0                  _MK_ADDR_CONST(0x110c4)
#define GPIO_V_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
#define GPIO_V_DEBOUNCE_THRESHOLD_06_0_DUAL                     0x0
#define GPIO_V_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_V_SCR_06_0
#define GPIO_V_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
#define GPIO_V_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_V_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_V_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_V_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_V_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_V_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_V_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_V_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_V_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_V_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_V_INPUT_06_0
#define GPIO_V_INPUT_06_0                       _MK_ADDR_CONST(0x110c8)
#define GPIO_V_INPUT_06_0_SECURE                        0x0
#define GPIO_V_INPUT_06_0_DUAL                  0x0
#define GPIO_V_INPUT_06_0_SCR                   GPIO_V_SCR_06_0
#define GPIO_V_INPUT_06_0_WORD_COUNT                    0x1
#define GPIO_V_INPUT_06_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_06_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_06_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_06_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_06_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_V_INPUT_06_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_06_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_V_INPUT_06_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_V_INPUT_06_0_GPIO_IN_SHIFT)
#define GPIO_V_INPUT_06_0_GPIO_IN_RANGE                 0:0
#define GPIO_V_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_V_INPUT_06_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_06_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_06_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_06_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_V_OUTPUT_CONTROL_06_0
#define GPIO_V_OUTPUT_CONTROL_06_0                      _MK_ADDR_CONST(0x110cc)
#define GPIO_V_OUTPUT_CONTROL_06_0_SECURE                       0x0
#define GPIO_V_OUTPUT_CONTROL_06_0_DUAL                         0x0
#define GPIO_V_OUTPUT_CONTROL_06_0_SCR                  GPIO_V_SCR_06_0
#define GPIO_V_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
#define GPIO_V_OUTPUT_CONTROL_06_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_06_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_CONTROL_06_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_06_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_V_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_V_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_V_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_V_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_V_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_V_OUTPUT_VALUE_06_0
#define GPIO_V_OUTPUT_VALUE_06_0                        _MK_ADDR_CONST(0x110d0)
#define GPIO_V_OUTPUT_VALUE_06_0_SECURE                         0x0
#define GPIO_V_OUTPUT_VALUE_06_0_DUAL                   0x0
#define GPIO_V_OUTPUT_VALUE_06_0_SCR                    GPIO_V_SCR_06_0
#define GPIO_V_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
#define GPIO_V_OUTPUT_VALUE_06_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_06_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_06_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_VALUE_06_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_V_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_V_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_V_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_V_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_V_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_V_INTERRUPT_CLEAR_06_0
#define GPIO_V_INTERRUPT_CLEAR_06_0                     _MK_ADDR_CONST(0x110d4)
#define GPIO_V_INTERRUPT_CLEAR_06_0_SECURE                      0x0
#define GPIO_V_INTERRUPT_CLEAR_06_0_DUAL                        0x0
#define GPIO_V_INTERRUPT_CLEAR_06_0_SCR                         GPIO_V_SCR_06_0
#define GPIO_V_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
#define GPIO_V_INTERRUPT_CLEAR_06_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_06_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_V_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_06_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_V_INTERRUPT_CLEAR_06_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_V_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_V_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_V_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_V_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_V_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_V_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_V_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_V_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_V_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x110d8

// Reserved address 0x110dc

// Register GPIO_V_ENABLE_CONFIG_07_0
#define GPIO_V_ENABLE_CONFIG_07_0                       _MK_ADDR_CONST(0x110e0)
#define GPIO_V_ENABLE_CONFIG_07_0_SECURE                        0x0
#define GPIO_V_ENABLE_CONFIG_07_0_DUAL                  0x0
#define GPIO_V_ENABLE_CONFIG_07_0_SCR                   GPIO_V_SCR_07_0
#define GPIO_V_ENABLE_CONFIG_07_0_WORD_COUNT                    0x1
#define GPIO_V_ENABLE_CONFIG_07_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_07_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_V_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_07_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_V_ENABLE_CONFIG_07_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_V_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_V_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_V_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
#define GPIO_V_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_V_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_V_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_07_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_07_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_V_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_V_ENABLE_CONFIG_07_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_V_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
#define GPIO_V_ENABLE_CONFIG_07_0_IN_OUT_RANGE                  1:1
#define GPIO_V_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                        0x0
#define GPIO_V_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_07_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_07_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_07_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_07_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_V_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_V_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_V_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
#define GPIO_V_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_V_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_V_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_V_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_V_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_V_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_V_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_V_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_V_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_V_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_V_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_V_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_V_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_V_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_V_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_V_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_V_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_V_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_V_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_V_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_V_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_V_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_V_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_V_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_V_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_V_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_V_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_V_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_V_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_V_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_V_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_V_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_V_DEBOUNCE_THRESHOLD_07_0
#define GPIO_V_DEBOUNCE_THRESHOLD_07_0                  _MK_ADDR_CONST(0x110e4)
#define GPIO_V_DEBOUNCE_THRESHOLD_07_0_SECURE                   0x0
#define GPIO_V_DEBOUNCE_THRESHOLD_07_0_DUAL                     0x0
#define GPIO_V_DEBOUNCE_THRESHOLD_07_0_SCR                      GPIO_V_SCR_07_0
#define GPIO_V_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                       0x1
#define GPIO_V_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_V_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_07_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_V_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_V_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_V_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_V_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_V_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_V_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_V_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_V_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_V_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_V_INPUT_07_0
#define GPIO_V_INPUT_07_0                       _MK_ADDR_CONST(0x110e8)
#define GPIO_V_INPUT_07_0_SECURE                        0x0
#define GPIO_V_INPUT_07_0_DUAL                  0x0
#define GPIO_V_INPUT_07_0_SCR                   GPIO_V_SCR_07_0
#define GPIO_V_INPUT_07_0_WORD_COUNT                    0x1
#define GPIO_V_INPUT_07_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_07_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_07_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_07_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_07_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_V_INPUT_07_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_07_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_V_INPUT_07_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_V_INPUT_07_0_GPIO_IN_SHIFT)
#define GPIO_V_INPUT_07_0_GPIO_IN_RANGE                 0:0
#define GPIO_V_INPUT_07_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_V_INPUT_07_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_07_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_07_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_07_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_V_INPUT_07_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_V_OUTPUT_CONTROL_07_0
#define GPIO_V_OUTPUT_CONTROL_07_0                      _MK_ADDR_CONST(0x110ec)
#define GPIO_V_OUTPUT_CONTROL_07_0_SECURE                       0x0
#define GPIO_V_OUTPUT_CONTROL_07_0_DUAL                         0x0
#define GPIO_V_OUTPUT_CONTROL_07_0_SCR                  GPIO_V_SCR_07_0
#define GPIO_V_OUTPUT_CONTROL_07_0_WORD_COUNT                   0x1
#define GPIO_V_OUTPUT_CONTROL_07_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_07_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_CONTROL_07_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_07_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_V_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_V_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_V_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_V_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_V_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_V_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_V_OUTPUT_VALUE_07_0
#define GPIO_V_OUTPUT_VALUE_07_0                        _MK_ADDR_CONST(0x110f0)
#define GPIO_V_OUTPUT_VALUE_07_0_SECURE                         0x0
#define GPIO_V_OUTPUT_VALUE_07_0_DUAL                   0x0
#define GPIO_V_OUTPUT_VALUE_07_0_SCR                    GPIO_V_SCR_07_0
#define GPIO_V_OUTPUT_VALUE_07_0_WORD_COUNT                     0x1
#define GPIO_V_OUTPUT_VALUE_07_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_07_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_07_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_VALUE_07_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_V_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_V_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_V_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_V_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_V_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_V_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_V_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_V_INTERRUPT_CLEAR_07_0
#define GPIO_V_INTERRUPT_CLEAR_07_0                     _MK_ADDR_CONST(0x110f4)
#define GPIO_V_INTERRUPT_CLEAR_07_0_SECURE                      0x0
#define GPIO_V_INTERRUPT_CLEAR_07_0_DUAL                        0x0
#define GPIO_V_INTERRUPT_CLEAR_07_0_SCR                         GPIO_V_SCR_07_0
#define GPIO_V_INTERRUPT_CLEAR_07_0_WORD_COUNT                  0x1
#define GPIO_V_INTERRUPT_CLEAR_07_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_07_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_V_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_07_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_V_INTERRUPT_CLEAR_07_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_V_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_V_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_V_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_V_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_V_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_V_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_V_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_V_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_V_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x110f8

// Reserved address 0x110fc

// Register GPIO_V_INTERRUPT_STATUS_G0_0
#define GPIO_V_INTERRUPT_STATUS_G0_0                    _MK_ADDR_CONST(0x11100)
#define GPIO_V_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_V_INTERRUPT_STATUS_G0_0_DUAL                       0x0
#define GPIO_V_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_V_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_V_INTERRUPT_STATUS_G0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G0_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_V_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G0_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_V_INTERRUPT_STATUS_G0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_V_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_V_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_V_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_V_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_V_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_V_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_V_INTERRUPT_STATUS_G1_0
#define GPIO_V_INTERRUPT_STATUS_G1_0                    _MK_ADDR_CONST(0x11104)
#define GPIO_V_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_V_INTERRUPT_STATUS_G1_0_DUAL                       0x0
#define GPIO_V_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_V_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_V_INTERRUPT_STATUS_G1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G1_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_V_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G1_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_V_INTERRUPT_STATUS_G1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_V_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_V_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_V_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_V_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_V_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_V_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_V_INTERRUPT_STATUS_G2_0
#define GPIO_V_INTERRUPT_STATUS_G2_0                    _MK_ADDR_CONST(0x11108)
#define GPIO_V_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_V_INTERRUPT_STATUS_G2_0_DUAL                       0x0
#define GPIO_V_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_V_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_V_INTERRUPT_STATUS_G2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G2_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_V_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G2_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_V_INTERRUPT_STATUS_G2_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_V_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_V_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_V_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_V_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_V_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_V_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_V_INTERRUPT_STATUS_G3_0
#define GPIO_V_INTERRUPT_STATUS_G3_0                    _MK_ADDR_CONST(0x1110c)
#define GPIO_V_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_V_INTERRUPT_STATUS_G3_0_DUAL                       0x0
#define GPIO_V_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_V_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_V_INTERRUPT_STATUS_G3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G3_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_V_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G3_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_V_INTERRUPT_STATUS_G3_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_V_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_V_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_V_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_V_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_V_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_V_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_V_INTERRUPT_STATUS_G4_0
#define GPIO_V_INTERRUPT_STATUS_G4_0                    _MK_ADDR_CONST(0x11110)
#define GPIO_V_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_V_INTERRUPT_STATUS_G4_0_DUAL                       0x0
#define GPIO_V_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_V_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_V_INTERRUPT_STATUS_G4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G4_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_V_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G4_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_V_INTERRUPT_STATUS_G4_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_V_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_V_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_V_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_V_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_V_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_V_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_V_INTERRUPT_STATUS_G5_0
#define GPIO_V_INTERRUPT_STATUS_G5_0                    _MK_ADDR_CONST(0x11114)
#define GPIO_V_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_V_INTERRUPT_STATUS_G5_0_DUAL                       0x0
#define GPIO_V_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_V_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_V_INTERRUPT_STATUS_G5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G5_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_V_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G5_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_V_INTERRUPT_STATUS_G5_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_V_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_V_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_V_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_V_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_V_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_V_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_V_INTERRUPT_STATUS_G6_0
#define GPIO_V_INTERRUPT_STATUS_G6_0                    _MK_ADDR_CONST(0x11118)
#define GPIO_V_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_V_INTERRUPT_STATUS_G6_0_DUAL                       0x0
#define GPIO_V_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_V_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_V_INTERRUPT_STATUS_G6_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G6_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_V_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G6_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_V_INTERRUPT_STATUS_G6_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_V_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_V_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_V_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_V_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_V_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_V_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_V_INTERRUPT_STATUS_G7_0
#define GPIO_V_INTERRUPT_STATUS_G7_0                    _MK_ADDR_CONST(0x1111c)
#define GPIO_V_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_V_INTERRUPT_STATUS_G7_0_DUAL                       0x0
#define GPIO_V_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_V_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_V_INTERRUPT_STATUS_G7_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G7_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_V_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G7_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_V_INTERRUPT_STATUS_G7_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_V_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_V_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_V_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_V_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_V_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_V_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_V_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Reserved address 0x11120

// Reserved address 0x11124

// Reserved address 0x11128

// Reserved address 0x1112c

// Reserved address 0x11130

// Reserved address 0x11134

// Reserved address 0x11138

// Reserved address 0x1113c

// Reserved address 0x11140

// Reserved address 0x11144

// Reserved address 0x11148

// Reserved address 0x1114c

// Reserved address 0x11150

// Reserved address 0x11154

// Reserved address 0x11158

// Reserved address 0x1115c

// Reserved address 0x11160

// Reserved address 0x11164

// Reserved address 0x11168

// Reserved address 0x1116c

// Reserved address 0x11170

// Reserved address 0x11174

// Reserved address 0x11178

// Reserved address 0x1117c

// Reserved address 0x11180

// Reserved address 0x11184

// Reserved address 0x11188

// Reserved address 0x1118c

// Reserved address 0x11190

// Reserved address 0x11194

// Reserved address 0x11198

// Reserved address 0x1119c

// Reserved address 0x111a0

// Reserved address 0x111a4

// Reserved address 0x111a8

// Reserved address 0x111ac

// Reserved address 0x111b0

// Reserved address 0x111b4

// Reserved address 0x111b8

// Reserved address 0x111bc

// Reserved address 0x111c0

// Reserved address 0x111c4

// Reserved address 0x111c8

// Reserved address 0x111cc

// Reserved address 0x111d0

// Reserved address 0x111d4

// Reserved address 0x111d8

// Reserved address 0x111dc

// Reserved address 0x111e0

// Reserved address 0x111e4

// Reserved address 0x111e8

// Reserved address 0x111ec

// Reserved address 0x111f0

// Reserved address 0x111f4

// Reserved address 0x111f8

// Reserved address 0x111fc

// Register GPIO_W_ENABLE_CONFIG_00_0
#define GPIO_W_ENABLE_CONFIG_00_0                       _MK_ADDR_CONST(0x11200)
#define GPIO_W_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_W_ENABLE_CONFIG_00_0_DUAL                  0x0
#define GPIO_W_ENABLE_CONFIG_00_0_SCR                   GPIO_W_SCR_00_0
#define GPIO_W_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_W_ENABLE_CONFIG_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_00_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_W_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_00_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_W_ENABLE_CONFIG_00_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_W_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_W_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_W_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_W_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_W_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_W_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_W_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_W_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_W_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_W_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_W_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_W_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_W_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_W_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_W_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_W_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_W_ENABLE_CONFIG_00_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_W_ENABLE_CONFIG_00_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_W_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_W_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_W_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_W_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_W_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_W_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_W_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_W_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_W_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_W_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_W_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_W_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_W_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_W_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_W_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_W_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_W_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_W_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_W_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_W_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_W_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_W_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_W_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_W_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_W_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_W_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_W_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_W_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_W_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_W_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_W_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_W_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_W_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_W_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_W_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_W_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_W_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_W_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_W_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_W_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_W_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_W_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_W_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_W_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_W_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_W_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_W_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_W_DEBOUNCE_THRESHOLD_00_0
#define GPIO_W_DEBOUNCE_THRESHOLD_00_0                  _MK_ADDR_CONST(0x11204)
#define GPIO_W_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_W_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
#define GPIO_W_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_W_SCR_00_0
#define GPIO_W_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_W_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_W_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_W_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_W_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_W_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_W_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_W_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_W_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_W_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_W_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_W_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_W_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_W_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_W_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_W_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_W_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_W_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_W_INPUT_00_0
#define GPIO_W_INPUT_00_0                       _MK_ADDR_CONST(0x11208)
#define GPIO_W_INPUT_00_0_SECURE                        0x0
#define GPIO_W_INPUT_00_0_DUAL                  0x0
#define GPIO_W_INPUT_00_0_SCR                   GPIO_W_SCR_00_0
#define GPIO_W_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_W_INPUT_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_W_INPUT_00_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_W_INPUT_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_W_INPUT_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_W_INPUT_00_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_W_INPUT_00_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_W_INPUT_00_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_W_INPUT_00_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_W_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_W_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_W_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_W_INPUT_00_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_W_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_W_INPUT_00_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_W_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_W_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_W_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_W_OUTPUT_CONTROL_00_0
#define GPIO_W_OUTPUT_CONTROL_00_0                      _MK_ADDR_CONST(0x1120c)
#define GPIO_W_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_W_OUTPUT_CONTROL_00_0_DUAL                         0x0
#define GPIO_W_OUTPUT_CONTROL_00_0_SCR                  GPIO_W_SCR_00_0
#define GPIO_W_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_W_OUTPUT_CONTROL_00_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_W_OUTPUT_CONTROL_00_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_W_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_W_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_W_OUTPUT_CONTROL_00_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_W_OUTPUT_CONTROL_00_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_W_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_W_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_W_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_W_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_W_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_W_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_W_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_W_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_W_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_W_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_W_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_W_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_W_OUTPUT_VALUE_00_0
#define GPIO_W_OUTPUT_VALUE_00_0                        _MK_ADDR_CONST(0x11210)
#define GPIO_W_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_W_OUTPUT_VALUE_00_0_DUAL                   0x0
#define GPIO_W_OUTPUT_VALUE_00_0_SCR                    GPIO_W_SCR_00_0
#define GPIO_W_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_W_OUTPUT_VALUE_00_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_W_OUTPUT_VALUE_00_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_W_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_W_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_W_OUTPUT_VALUE_00_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_W_OUTPUT_VALUE_00_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_W_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_W_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_W_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_W_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_W_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_W_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_W_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_W_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_W_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_W_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_W_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_W_INTERRUPT_CLEAR_00_0
#define GPIO_W_INTERRUPT_CLEAR_00_0                     _MK_ADDR_CONST(0x11214)
#define GPIO_W_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_W_INTERRUPT_CLEAR_00_0_DUAL                        0x0
#define GPIO_W_INTERRUPT_CLEAR_00_0_SCR                         GPIO_W_SCR_00_0
#define GPIO_W_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_W_INTERRUPT_CLEAR_00_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_CLEAR_00_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_W_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_CLEAR_00_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_W_INTERRUPT_CLEAR_00_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_W_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_W_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_W_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_W_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_W_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_W_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_W_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_W_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_W_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x11218

// Reserved address 0x1121c

// Register GPIO_W_ENABLE_CONFIG_01_0
#define GPIO_W_ENABLE_CONFIG_01_0                       _MK_ADDR_CONST(0x11220)
#define GPIO_W_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_W_ENABLE_CONFIG_01_0_DUAL                  0x0
#define GPIO_W_ENABLE_CONFIG_01_0_SCR                   GPIO_W_SCR_01_0
#define GPIO_W_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_W_ENABLE_CONFIG_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_01_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_W_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_01_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_W_ENABLE_CONFIG_01_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_W_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_W_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_W_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_W_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_W_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_W_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_W_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_W_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_W_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_W_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_W_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_W_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_W_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_W_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_W_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_W_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_W_ENABLE_CONFIG_01_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_W_ENABLE_CONFIG_01_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_W_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_W_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_W_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_W_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_W_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_W_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_W_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_W_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_W_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_W_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_W_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_W_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_W_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_W_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_W_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_W_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_W_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_W_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_W_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_W_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_W_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_W_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_W_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_W_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_W_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_W_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_W_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_W_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_W_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_W_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_W_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_W_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_W_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_W_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_W_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_W_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_W_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_W_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_W_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_W_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_W_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_W_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_W_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_W_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_W_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_W_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_W_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_W_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_W_DEBOUNCE_THRESHOLD_01_0
#define GPIO_W_DEBOUNCE_THRESHOLD_01_0                  _MK_ADDR_CONST(0x11224)
#define GPIO_W_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_W_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
#define GPIO_W_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_W_SCR_01_0
#define GPIO_W_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_W_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_W_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_W_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_W_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_W_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_W_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_W_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_W_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_W_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_W_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_W_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_W_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_W_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_W_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_W_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_W_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_W_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_W_INPUT_01_0
#define GPIO_W_INPUT_01_0                       _MK_ADDR_CONST(0x11228)
#define GPIO_W_INPUT_01_0_SECURE                        0x0
#define GPIO_W_INPUT_01_0_DUAL                  0x0
#define GPIO_W_INPUT_01_0_SCR                   GPIO_W_SCR_01_0
#define GPIO_W_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_W_INPUT_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_W_INPUT_01_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_W_INPUT_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_W_INPUT_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_W_INPUT_01_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_W_INPUT_01_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_W_INPUT_01_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_W_INPUT_01_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_W_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_W_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_W_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_W_INPUT_01_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_W_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_W_INPUT_01_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_W_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_W_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_W_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_W_OUTPUT_CONTROL_01_0
#define GPIO_W_OUTPUT_CONTROL_01_0                      _MK_ADDR_CONST(0x1122c)
#define GPIO_W_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_W_OUTPUT_CONTROL_01_0_DUAL                         0x0
#define GPIO_W_OUTPUT_CONTROL_01_0_SCR                  GPIO_W_SCR_01_0
#define GPIO_W_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_W_OUTPUT_CONTROL_01_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_W_OUTPUT_CONTROL_01_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_W_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_W_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_W_OUTPUT_CONTROL_01_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_W_OUTPUT_CONTROL_01_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_W_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_W_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_W_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_W_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_W_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_W_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_W_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_W_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_W_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_W_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_W_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_W_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_W_OUTPUT_VALUE_01_0
#define GPIO_W_OUTPUT_VALUE_01_0                        _MK_ADDR_CONST(0x11230)
#define GPIO_W_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_W_OUTPUT_VALUE_01_0_DUAL                   0x0
#define GPIO_W_OUTPUT_VALUE_01_0_SCR                    GPIO_W_SCR_01_0
#define GPIO_W_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_W_OUTPUT_VALUE_01_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_W_OUTPUT_VALUE_01_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_W_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_W_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_W_OUTPUT_VALUE_01_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_W_OUTPUT_VALUE_01_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_W_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_W_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_W_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_W_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_W_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_W_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_W_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_W_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_W_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_W_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_W_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_W_INTERRUPT_CLEAR_01_0
#define GPIO_W_INTERRUPT_CLEAR_01_0                     _MK_ADDR_CONST(0x11234)
#define GPIO_W_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_W_INTERRUPT_CLEAR_01_0_DUAL                        0x0
#define GPIO_W_INTERRUPT_CLEAR_01_0_SCR                         GPIO_W_SCR_01_0
#define GPIO_W_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_W_INTERRUPT_CLEAR_01_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_CLEAR_01_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_W_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_CLEAR_01_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_W_INTERRUPT_CLEAR_01_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_W_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_W_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_W_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_W_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_W_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_W_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_W_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_W_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_W_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x11238

// Reserved address 0x1123c

// Reserved address 0x11240

// Reserved address 0x11244

// Reserved address 0x11248

// Reserved address 0x1124c

// Reserved address 0x11250

// Reserved address 0x11254

// Reserved address 0x11258

// Reserved address 0x1125c

// Reserved address 0x11260

// Reserved address 0x11264

// Reserved address 0x11268

// Reserved address 0x1126c

// Reserved address 0x11270

// Reserved address 0x11274

// Reserved address 0x11278

// Reserved address 0x1127c

// Reserved address 0x11280

// Reserved address 0x11284

// Reserved address 0x11288

// Reserved address 0x1128c

// Reserved address 0x11290

// Reserved address 0x11294

// Reserved address 0x11298

// Reserved address 0x1129c

// Reserved address 0x112a0

// Reserved address 0x112a4

// Reserved address 0x112a8

// Reserved address 0x112ac

// Reserved address 0x112b0

// Reserved address 0x112b4

// Reserved address 0x112b8

// Reserved address 0x112bc

// Reserved address 0x112c0

// Reserved address 0x112c4

// Reserved address 0x112c8

// Reserved address 0x112cc

// Reserved address 0x112d0

// Reserved address 0x112d4

// Reserved address 0x112d8

// Reserved address 0x112dc

// Reserved address 0x112e0

// Reserved address 0x112e4

// Reserved address 0x112e8

// Reserved address 0x112ec

// Reserved address 0x112f0

// Reserved address 0x112f4

// Reserved address 0x112f8

// Reserved address 0x112fc

// Register GPIO_W_INTERRUPT_STATUS_G0_0
#define GPIO_W_INTERRUPT_STATUS_G0_0                    _MK_ADDR_CONST(0x11300)
#define GPIO_W_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_W_INTERRUPT_STATUS_G0_0_DUAL                       0x0
#define GPIO_W_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_W_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_W_INTERRUPT_STATUS_G0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G0_0_RESET_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_W_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G0_0_READ_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_W_INTERRUPT_STATUS_G0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_W_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3, GPIO_W_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_W_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        1:0
#define GPIO_W_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_W_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_W_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_W_INTERRUPT_STATUS_G1_0
#define GPIO_W_INTERRUPT_STATUS_G1_0                    _MK_ADDR_CONST(0x11304)
#define GPIO_W_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_W_INTERRUPT_STATUS_G1_0_DUAL                       0x0
#define GPIO_W_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_W_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_W_INTERRUPT_STATUS_G1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G1_0_RESET_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_W_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G1_0_READ_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_W_INTERRUPT_STATUS_G1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_W_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3, GPIO_W_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_W_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        1:0
#define GPIO_W_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_W_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_W_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_W_INTERRUPT_STATUS_G2_0
#define GPIO_W_INTERRUPT_STATUS_G2_0                    _MK_ADDR_CONST(0x11308)
#define GPIO_W_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_W_INTERRUPT_STATUS_G2_0_DUAL                       0x0
#define GPIO_W_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_W_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_W_INTERRUPT_STATUS_G2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G2_0_RESET_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_W_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G2_0_READ_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_W_INTERRUPT_STATUS_G2_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_W_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3, GPIO_W_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_W_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        1:0
#define GPIO_W_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_W_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_W_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_W_INTERRUPT_STATUS_G3_0
#define GPIO_W_INTERRUPT_STATUS_G3_0                    _MK_ADDR_CONST(0x1130c)
#define GPIO_W_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_W_INTERRUPT_STATUS_G3_0_DUAL                       0x0
#define GPIO_W_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_W_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_W_INTERRUPT_STATUS_G3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G3_0_RESET_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_W_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G3_0_READ_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_W_INTERRUPT_STATUS_G3_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_W_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3, GPIO_W_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_W_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        1:0
#define GPIO_W_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_W_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_W_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_W_INTERRUPT_STATUS_G4_0
#define GPIO_W_INTERRUPT_STATUS_G4_0                    _MK_ADDR_CONST(0x11310)
#define GPIO_W_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_W_INTERRUPT_STATUS_G4_0_DUAL                       0x0
#define GPIO_W_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_W_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_W_INTERRUPT_STATUS_G4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G4_0_RESET_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_W_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G4_0_READ_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_W_INTERRUPT_STATUS_G4_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_W_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3, GPIO_W_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_W_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        1:0
#define GPIO_W_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_W_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_W_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_W_INTERRUPT_STATUS_G5_0
#define GPIO_W_INTERRUPT_STATUS_G5_0                    _MK_ADDR_CONST(0x11314)
#define GPIO_W_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_W_INTERRUPT_STATUS_G5_0_DUAL                       0x0
#define GPIO_W_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_W_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_W_INTERRUPT_STATUS_G5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G5_0_RESET_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_W_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G5_0_READ_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_W_INTERRUPT_STATUS_G5_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_W_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3, GPIO_W_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_W_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        1:0
#define GPIO_W_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_W_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_W_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_W_INTERRUPT_STATUS_G6_0
#define GPIO_W_INTERRUPT_STATUS_G6_0                    _MK_ADDR_CONST(0x11318)
#define GPIO_W_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_W_INTERRUPT_STATUS_G6_0_DUAL                       0x0
#define GPIO_W_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_W_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_W_INTERRUPT_STATUS_G6_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G6_0_RESET_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_W_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G6_0_READ_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_W_INTERRUPT_STATUS_G6_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_W_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3, GPIO_W_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_W_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        1:0
#define GPIO_W_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_W_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_W_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_W_INTERRUPT_STATUS_G7_0
#define GPIO_W_INTERRUPT_STATUS_G7_0                    _MK_ADDR_CONST(0x1131c)
#define GPIO_W_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_W_INTERRUPT_STATUS_G7_0_DUAL                       0x0
#define GPIO_W_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_W_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_W_INTERRUPT_STATUS_G7_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G7_0_RESET_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_W_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G7_0_READ_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_W_INTERRUPT_STATUS_G7_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_W_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3, GPIO_W_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_W_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        1:0
#define GPIO_W_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_W_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_W_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_W_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Reserved address 0x11320

// Reserved address 0x11324

// Reserved address 0x11328

// Reserved address 0x1132c

// Reserved address 0x11330

// Reserved address 0x11334

// Reserved address 0x11338

// Reserved address 0x1133c

// Reserved address 0x11340

// Reserved address 0x11344

// Reserved address 0x11348

// Reserved address 0x1134c

// Reserved address 0x11350

// Reserved address 0x11354

// Reserved address 0x11358

// Reserved address 0x1135c

// Reserved address 0x11360

// Reserved address 0x11364

// Reserved address 0x11368

// Reserved address 0x1136c

// Reserved address 0x11370

// Reserved address 0x11374

// Reserved address 0x11378

// Reserved address 0x1137c

// Reserved address 0x11380

// Reserved address 0x11384

// Reserved address 0x11388

// Reserved address 0x1138c

// Reserved address 0x11390

// Reserved address 0x11394

// Reserved address 0x11398

// Reserved address 0x1139c

// Reserved address 0x113a0

// Reserved address 0x113a4

// Reserved address 0x113a8

// Reserved address 0x113ac

// Reserved address 0x113b0

// Reserved address 0x113b4

// Reserved address 0x113b8

// Reserved address 0x113bc

// Reserved address 0x113c0

// Reserved address 0x113c4

// Reserved address 0x113c8

// Reserved address 0x113cc

// Reserved address 0x113d0

// Reserved address 0x113d4

// Reserved address 0x113d8

// Reserved address 0x113dc

// Reserved address 0x113e0

// Reserved address 0x113e4

// Reserved address 0x113e8

// Reserved address 0x113ec

// Reserved address 0x113f0

// Reserved address 0x113f4

// Reserved address 0x113f8

// Reserved address 0x113fc

// Register GPIO_A_ENABLE_CONFIG_00_0
#define GPIO_A_ENABLE_CONFIG_00_0                       _MK_ADDR_CONST(0x11400)
#define GPIO_A_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_A_ENABLE_CONFIG_00_0_DUAL                  0x0
#define GPIO_A_ENABLE_CONFIG_00_0_SCR                   GPIO_A_SCR_00_0
#define GPIO_A_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_A_ENABLE_CONFIG_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_00_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_A_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_A_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_A_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_A_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_A_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_A_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_A_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_A_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_00_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_00_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_A_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_A_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_A_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_A_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_A_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_A_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_A_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_A_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_A_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_A_DEBOUNCE_THRESHOLD_00_0
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0                  _MK_ADDR_CONST(0x11404)
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_A_SCR_00_0
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_A_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_A_INPUT_00_0
#define GPIO_A_INPUT_00_0                       _MK_ADDR_CONST(0x11408)
#define GPIO_A_INPUT_00_0_SECURE                        0x0
#define GPIO_A_INPUT_00_0_DUAL                  0x0
#define GPIO_A_INPUT_00_0_SCR                   GPIO_A_SCR_00_0
#define GPIO_A_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_A_INPUT_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_00_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_00_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_A_INPUT_00_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_00_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_A_INPUT_00_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_A_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_A_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_A_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_A_INPUT_00_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_00_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_A_OUTPUT_CONTROL_00_0
#define GPIO_A_OUTPUT_CONTROL_00_0                      _MK_ADDR_CONST(0x1140c)
#define GPIO_A_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_A_OUTPUT_CONTROL_00_0_DUAL                         0x0
#define GPIO_A_OUTPUT_CONTROL_00_0_SCR                  GPIO_A_SCR_00_0
#define GPIO_A_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_A_OUTPUT_CONTROL_00_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_00_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_00_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_00_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_A_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_A_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_A_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_A_OUTPUT_VALUE_00_0
#define GPIO_A_OUTPUT_VALUE_00_0                        _MK_ADDR_CONST(0x11410)
#define GPIO_A_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_A_OUTPUT_VALUE_00_0_DUAL                   0x0
#define GPIO_A_OUTPUT_VALUE_00_0_SCR                    GPIO_A_SCR_00_0
#define GPIO_A_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_A_OUTPUT_VALUE_00_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_00_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_00_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_00_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_A_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_A_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_A_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_A_INTERRUPT_CLEAR_00_0
#define GPIO_A_INTERRUPT_CLEAR_00_0                     _MK_ADDR_CONST(0x11414)
#define GPIO_A_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_A_INTERRUPT_CLEAR_00_0_DUAL                        0x0
#define GPIO_A_INTERRUPT_CLEAR_00_0_SCR                         GPIO_A_SCR_00_0
#define GPIO_A_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_A_INTERRUPT_CLEAR_00_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_00_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_00_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_00_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_A_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_A_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_A_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_A_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x11418

// Reserved address 0x1141c

// Register GPIO_A_ENABLE_CONFIG_01_0
#define GPIO_A_ENABLE_CONFIG_01_0                       _MK_ADDR_CONST(0x11420)
#define GPIO_A_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_A_ENABLE_CONFIG_01_0_DUAL                  0x0
#define GPIO_A_ENABLE_CONFIG_01_0_SCR                   GPIO_A_SCR_01_0
#define GPIO_A_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_A_ENABLE_CONFIG_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_01_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_A_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_A_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_A_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_A_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_A_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_A_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_A_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_A_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_01_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_01_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_A_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_A_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_A_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_A_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_A_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_A_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_A_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_A_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_A_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_A_DEBOUNCE_THRESHOLD_01_0
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0                  _MK_ADDR_CONST(0x11424)
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_A_SCR_01_0
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_A_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_A_INPUT_01_0
#define GPIO_A_INPUT_01_0                       _MK_ADDR_CONST(0x11428)
#define GPIO_A_INPUT_01_0_SECURE                        0x0
#define GPIO_A_INPUT_01_0_DUAL                  0x0
#define GPIO_A_INPUT_01_0_SCR                   GPIO_A_SCR_01_0
#define GPIO_A_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_A_INPUT_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_01_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_01_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_A_INPUT_01_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_01_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_A_INPUT_01_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_A_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_A_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_A_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_A_INPUT_01_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_01_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_A_OUTPUT_CONTROL_01_0
#define GPIO_A_OUTPUT_CONTROL_01_0                      _MK_ADDR_CONST(0x1142c)
#define GPIO_A_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_A_OUTPUT_CONTROL_01_0_DUAL                         0x0
#define GPIO_A_OUTPUT_CONTROL_01_0_SCR                  GPIO_A_SCR_01_0
#define GPIO_A_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_A_OUTPUT_CONTROL_01_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_01_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_01_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_01_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_A_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_A_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_A_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_A_OUTPUT_VALUE_01_0
#define GPIO_A_OUTPUT_VALUE_01_0                        _MK_ADDR_CONST(0x11430)
#define GPIO_A_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_A_OUTPUT_VALUE_01_0_DUAL                   0x0
#define GPIO_A_OUTPUT_VALUE_01_0_SCR                    GPIO_A_SCR_01_0
#define GPIO_A_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_A_OUTPUT_VALUE_01_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_01_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_01_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_01_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_A_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_A_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_A_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_A_INTERRUPT_CLEAR_01_0
#define GPIO_A_INTERRUPT_CLEAR_01_0                     _MK_ADDR_CONST(0x11434)
#define GPIO_A_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_A_INTERRUPT_CLEAR_01_0_DUAL                        0x0
#define GPIO_A_INTERRUPT_CLEAR_01_0_SCR                         GPIO_A_SCR_01_0
#define GPIO_A_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_A_INTERRUPT_CLEAR_01_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_01_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_01_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_01_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_A_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_A_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_A_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_A_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x11438

// Reserved address 0x1143c

// Register GPIO_A_ENABLE_CONFIG_02_0
#define GPIO_A_ENABLE_CONFIG_02_0                       _MK_ADDR_CONST(0x11440)
#define GPIO_A_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_A_ENABLE_CONFIG_02_0_DUAL                  0x0
#define GPIO_A_ENABLE_CONFIG_02_0_SCR                   GPIO_A_SCR_02_0
#define GPIO_A_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_A_ENABLE_CONFIG_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_02_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_A_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_A_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_A_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_A_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_A_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_A_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_A_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_A_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_02_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_02_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_A_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_A_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_A_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_A_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_A_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_A_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_A_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_A_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_A_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_A_DEBOUNCE_THRESHOLD_02_0
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0                  _MK_ADDR_CONST(0x11444)
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_A_SCR_02_0
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_A_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_A_INPUT_02_0
#define GPIO_A_INPUT_02_0                       _MK_ADDR_CONST(0x11448)
#define GPIO_A_INPUT_02_0_SECURE                        0x0
#define GPIO_A_INPUT_02_0_DUAL                  0x0
#define GPIO_A_INPUT_02_0_SCR                   GPIO_A_SCR_02_0
#define GPIO_A_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_A_INPUT_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_02_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_02_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_A_INPUT_02_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_02_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_A_INPUT_02_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_A_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_A_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_A_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_A_INPUT_02_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_02_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_A_OUTPUT_CONTROL_02_0
#define GPIO_A_OUTPUT_CONTROL_02_0                      _MK_ADDR_CONST(0x1144c)
#define GPIO_A_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_A_OUTPUT_CONTROL_02_0_DUAL                         0x0
#define GPIO_A_OUTPUT_CONTROL_02_0_SCR                  GPIO_A_SCR_02_0
#define GPIO_A_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_A_OUTPUT_CONTROL_02_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_02_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_02_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_02_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_A_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_A_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_A_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_A_OUTPUT_VALUE_02_0
#define GPIO_A_OUTPUT_VALUE_02_0                        _MK_ADDR_CONST(0x11450)
#define GPIO_A_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_A_OUTPUT_VALUE_02_0_DUAL                   0x0
#define GPIO_A_OUTPUT_VALUE_02_0_SCR                    GPIO_A_SCR_02_0
#define GPIO_A_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_A_OUTPUT_VALUE_02_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_02_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_02_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_02_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_A_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_A_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_A_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_A_INTERRUPT_CLEAR_02_0
#define GPIO_A_INTERRUPT_CLEAR_02_0                     _MK_ADDR_CONST(0x11454)
#define GPIO_A_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_A_INTERRUPT_CLEAR_02_0_DUAL                        0x0
#define GPIO_A_INTERRUPT_CLEAR_02_0_SCR                         GPIO_A_SCR_02_0
#define GPIO_A_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_A_INTERRUPT_CLEAR_02_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_02_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_02_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_02_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_A_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_A_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_A_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_A_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x11458

// Reserved address 0x1145c

// Register GPIO_A_ENABLE_CONFIG_03_0
#define GPIO_A_ENABLE_CONFIG_03_0                       _MK_ADDR_CONST(0x11460)
#define GPIO_A_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_A_ENABLE_CONFIG_03_0_DUAL                  0x0
#define GPIO_A_ENABLE_CONFIG_03_0_SCR                   GPIO_A_SCR_03_0
#define GPIO_A_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_A_ENABLE_CONFIG_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_03_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_A_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_A_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_A_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_A_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_A_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_A_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_A_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_A_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_03_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_03_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_A_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_A_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_A_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_A_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_A_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_A_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_A_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_A_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_A_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_A_DEBOUNCE_THRESHOLD_03_0
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0                  _MK_ADDR_CONST(0x11464)
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_A_SCR_03_0
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_A_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_A_INPUT_03_0
#define GPIO_A_INPUT_03_0                       _MK_ADDR_CONST(0x11468)
#define GPIO_A_INPUT_03_0_SECURE                        0x0
#define GPIO_A_INPUT_03_0_DUAL                  0x0
#define GPIO_A_INPUT_03_0_SCR                   GPIO_A_SCR_03_0
#define GPIO_A_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_A_INPUT_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_03_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_03_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_A_INPUT_03_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_03_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_A_INPUT_03_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_A_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_A_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_A_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_A_INPUT_03_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_03_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_A_OUTPUT_CONTROL_03_0
#define GPIO_A_OUTPUT_CONTROL_03_0                      _MK_ADDR_CONST(0x1146c)
#define GPIO_A_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_A_OUTPUT_CONTROL_03_0_DUAL                         0x0
#define GPIO_A_OUTPUT_CONTROL_03_0_SCR                  GPIO_A_SCR_03_0
#define GPIO_A_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_A_OUTPUT_CONTROL_03_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_03_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_03_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_03_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_A_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_A_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_A_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_A_OUTPUT_VALUE_03_0
#define GPIO_A_OUTPUT_VALUE_03_0                        _MK_ADDR_CONST(0x11470)
#define GPIO_A_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_A_OUTPUT_VALUE_03_0_DUAL                   0x0
#define GPIO_A_OUTPUT_VALUE_03_0_SCR                    GPIO_A_SCR_03_0
#define GPIO_A_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_A_OUTPUT_VALUE_03_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_03_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_03_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_03_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_A_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_A_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_A_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_A_INTERRUPT_CLEAR_03_0
#define GPIO_A_INTERRUPT_CLEAR_03_0                     _MK_ADDR_CONST(0x11474)
#define GPIO_A_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_A_INTERRUPT_CLEAR_03_0_DUAL                        0x0
#define GPIO_A_INTERRUPT_CLEAR_03_0_SCR                         GPIO_A_SCR_03_0
#define GPIO_A_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_A_INTERRUPT_CLEAR_03_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_03_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_03_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_03_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_A_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_A_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_A_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_A_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x11478

// Reserved address 0x1147c

// Register GPIO_A_ENABLE_CONFIG_04_0
#define GPIO_A_ENABLE_CONFIG_04_0                       _MK_ADDR_CONST(0x11480)
#define GPIO_A_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_A_ENABLE_CONFIG_04_0_DUAL                  0x0
#define GPIO_A_ENABLE_CONFIG_04_0_SCR                   GPIO_A_SCR_04_0
#define GPIO_A_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_A_ENABLE_CONFIG_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_04_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_A_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_A_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_A_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_A_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_A_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_A_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_A_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_A_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_04_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_04_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_A_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_A_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_A_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_A_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_A_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_A_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_A_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_A_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_A_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_A_DEBOUNCE_THRESHOLD_04_0
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0                  _MK_ADDR_CONST(0x11484)
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_DUAL                     0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_A_SCR_04_0
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_A_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_A_INPUT_04_0
#define GPIO_A_INPUT_04_0                       _MK_ADDR_CONST(0x11488)
#define GPIO_A_INPUT_04_0_SECURE                        0x0
#define GPIO_A_INPUT_04_0_DUAL                  0x0
#define GPIO_A_INPUT_04_0_SCR                   GPIO_A_SCR_04_0
#define GPIO_A_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_A_INPUT_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_04_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_04_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_A_INPUT_04_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_04_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_A_INPUT_04_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_A_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_A_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_A_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_A_INPUT_04_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_04_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_A_OUTPUT_CONTROL_04_0
#define GPIO_A_OUTPUT_CONTROL_04_0                      _MK_ADDR_CONST(0x1148c)
#define GPIO_A_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_A_OUTPUT_CONTROL_04_0_DUAL                         0x0
#define GPIO_A_OUTPUT_CONTROL_04_0_SCR                  GPIO_A_SCR_04_0
#define GPIO_A_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_A_OUTPUT_CONTROL_04_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_04_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_04_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_04_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_A_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_A_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_A_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_A_OUTPUT_VALUE_04_0
#define GPIO_A_OUTPUT_VALUE_04_0                        _MK_ADDR_CONST(0x11490)
#define GPIO_A_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_A_OUTPUT_VALUE_04_0_DUAL                   0x0
#define GPIO_A_OUTPUT_VALUE_04_0_SCR                    GPIO_A_SCR_04_0
#define GPIO_A_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_A_OUTPUT_VALUE_04_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_04_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_04_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_04_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_A_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_A_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_A_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_A_INTERRUPT_CLEAR_04_0
#define GPIO_A_INTERRUPT_CLEAR_04_0                     _MK_ADDR_CONST(0x11494)
#define GPIO_A_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_A_INTERRUPT_CLEAR_04_0_DUAL                        0x0
#define GPIO_A_INTERRUPT_CLEAR_04_0_SCR                         GPIO_A_SCR_04_0
#define GPIO_A_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_A_INTERRUPT_CLEAR_04_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_04_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_04_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_04_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_A_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_A_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_A_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_A_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x11498

// Reserved address 0x1149c

// Register GPIO_A_ENABLE_CONFIG_05_0
#define GPIO_A_ENABLE_CONFIG_05_0                       _MK_ADDR_CONST(0x114a0)
#define GPIO_A_ENABLE_CONFIG_05_0_SECURE                        0x0
#define GPIO_A_ENABLE_CONFIG_05_0_DUAL                  0x0
#define GPIO_A_ENABLE_CONFIG_05_0_SCR                   GPIO_A_SCR_05_0
#define GPIO_A_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
#define GPIO_A_ENABLE_CONFIG_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_05_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_A_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_A_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_A_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_A_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_A_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_A_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
#define GPIO_A_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
#define GPIO_A_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_05_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_05_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_A_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_A_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_A_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_A_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_A_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_A_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_A_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_A_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_A_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_A_DEBOUNCE_THRESHOLD_05_0
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0                  _MK_ADDR_CONST(0x114a4)
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_DUAL                     0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_A_SCR_05_0
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_A_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_A_INPUT_05_0
#define GPIO_A_INPUT_05_0                       _MK_ADDR_CONST(0x114a8)
#define GPIO_A_INPUT_05_0_SECURE                        0x0
#define GPIO_A_INPUT_05_0_DUAL                  0x0
#define GPIO_A_INPUT_05_0_SCR                   GPIO_A_SCR_05_0
#define GPIO_A_INPUT_05_0_WORD_COUNT                    0x1
#define GPIO_A_INPUT_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_05_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_05_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_A_INPUT_05_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_05_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_A_INPUT_05_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_A_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_A_INPUT_05_0_GPIO_IN_RANGE                 0:0
#define GPIO_A_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_A_INPUT_05_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_05_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_A_OUTPUT_CONTROL_05_0
#define GPIO_A_OUTPUT_CONTROL_05_0                      _MK_ADDR_CONST(0x114ac)
#define GPIO_A_OUTPUT_CONTROL_05_0_SECURE                       0x0
#define GPIO_A_OUTPUT_CONTROL_05_0_DUAL                         0x0
#define GPIO_A_OUTPUT_CONTROL_05_0_SCR                  GPIO_A_SCR_05_0
#define GPIO_A_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
#define GPIO_A_OUTPUT_CONTROL_05_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_05_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_05_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_05_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_A_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_A_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_A_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_A_OUTPUT_VALUE_05_0
#define GPIO_A_OUTPUT_VALUE_05_0                        _MK_ADDR_CONST(0x114b0)
#define GPIO_A_OUTPUT_VALUE_05_0_SECURE                         0x0
#define GPIO_A_OUTPUT_VALUE_05_0_DUAL                   0x0
#define GPIO_A_OUTPUT_VALUE_05_0_SCR                    GPIO_A_SCR_05_0
#define GPIO_A_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
#define GPIO_A_OUTPUT_VALUE_05_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_05_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_05_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_05_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_A_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_A_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_A_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_A_INTERRUPT_CLEAR_05_0
#define GPIO_A_INTERRUPT_CLEAR_05_0                     _MK_ADDR_CONST(0x114b4)
#define GPIO_A_INTERRUPT_CLEAR_05_0_SECURE                      0x0
#define GPIO_A_INTERRUPT_CLEAR_05_0_DUAL                        0x0
#define GPIO_A_INTERRUPT_CLEAR_05_0_SCR                         GPIO_A_SCR_05_0
#define GPIO_A_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
#define GPIO_A_INTERRUPT_CLEAR_05_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_05_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_05_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_05_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_A_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_A_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_A_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_A_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x114b8

// Reserved address 0x114bc

// Register GPIO_A_ENABLE_CONFIG_06_0
#define GPIO_A_ENABLE_CONFIG_06_0                       _MK_ADDR_CONST(0x114c0)
#define GPIO_A_ENABLE_CONFIG_06_0_SECURE                        0x0
#define GPIO_A_ENABLE_CONFIG_06_0_DUAL                  0x0
#define GPIO_A_ENABLE_CONFIG_06_0_SCR                   GPIO_A_SCR_06_0
#define GPIO_A_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
#define GPIO_A_ENABLE_CONFIG_06_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_06_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_A_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
#define GPIO_A_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_A_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_A_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_A_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
#define GPIO_A_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
#define GPIO_A_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
#define GPIO_A_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_06_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_06_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_A_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_A_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_A_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_A_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_A_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_A_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_A_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_A_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_A_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_A_DEBOUNCE_THRESHOLD_06_0
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0                  _MK_ADDR_CONST(0x114c4)
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_DUAL                     0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_A_SCR_06_0
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_A_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_A_INPUT_06_0
#define GPIO_A_INPUT_06_0                       _MK_ADDR_CONST(0x114c8)
#define GPIO_A_INPUT_06_0_SECURE                        0x0
#define GPIO_A_INPUT_06_0_DUAL                  0x0
#define GPIO_A_INPUT_06_0_SCR                   GPIO_A_SCR_06_0
#define GPIO_A_INPUT_06_0_WORD_COUNT                    0x1
#define GPIO_A_INPUT_06_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_06_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_06_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_06_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_06_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_A_INPUT_06_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_06_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_A_INPUT_06_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_A_INPUT_06_0_GPIO_IN_SHIFT)
#define GPIO_A_INPUT_06_0_GPIO_IN_RANGE                 0:0
#define GPIO_A_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_A_INPUT_06_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_06_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_06_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_06_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_A_OUTPUT_CONTROL_06_0
#define GPIO_A_OUTPUT_CONTROL_06_0                      _MK_ADDR_CONST(0x114cc)
#define GPIO_A_OUTPUT_CONTROL_06_0_SECURE                       0x0
#define GPIO_A_OUTPUT_CONTROL_06_0_DUAL                         0x0
#define GPIO_A_OUTPUT_CONTROL_06_0_SCR                  GPIO_A_SCR_06_0
#define GPIO_A_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
#define GPIO_A_OUTPUT_CONTROL_06_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_06_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_06_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_06_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_A_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_A_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_A_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_A_OUTPUT_VALUE_06_0
#define GPIO_A_OUTPUT_VALUE_06_0                        _MK_ADDR_CONST(0x114d0)
#define GPIO_A_OUTPUT_VALUE_06_0_SECURE                         0x0
#define GPIO_A_OUTPUT_VALUE_06_0_DUAL                   0x0
#define GPIO_A_OUTPUT_VALUE_06_0_SCR                    GPIO_A_SCR_06_0
#define GPIO_A_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
#define GPIO_A_OUTPUT_VALUE_06_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_06_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_06_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_06_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_A_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_A_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_A_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_A_INTERRUPT_CLEAR_06_0
#define GPIO_A_INTERRUPT_CLEAR_06_0                     _MK_ADDR_CONST(0x114d4)
#define GPIO_A_INTERRUPT_CLEAR_06_0_SECURE                      0x0
#define GPIO_A_INTERRUPT_CLEAR_06_0_DUAL                        0x0
#define GPIO_A_INTERRUPT_CLEAR_06_0_SCR                         GPIO_A_SCR_06_0
#define GPIO_A_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
#define GPIO_A_INTERRUPT_CLEAR_06_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_06_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_06_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_06_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_A_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_A_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_A_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_A_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x114d8

// Reserved address 0x114dc

// Register GPIO_A_ENABLE_CONFIG_07_0
#define GPIO_A_ENABLE_CONFIG_07_0                       _MK_ADDR_CONST(0x114e0)
#define GPIO_A_ENABLE_CONFIG_07_0_SECURE                        0x0
#define GPIO_A_ENABLE_CONFIG_07_0_DUAL                  0x0
#define GPIO_A_ENABLE_CONFIG_07_0_SCR                   GPIO_A_SCR_07_0
#define GPIO_A_ENABLE_CONFIG_07_0_WORD_COUNT                    0x1
#define GPIO_A_ENABLE_CONFIG_07_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_07_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_A_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
#define GPIO_A_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_A_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_A_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_A_ENABLE_CONFIG_07_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
#define GPIO_A_ENABLE_CONFIG_07_0_IN_OUT_RANGE                  1:1
#define GPIO_A_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                        0x0
#define GPIO_A_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_07_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_07_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_A_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_A_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_A_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_A_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_A_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_A_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_A_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_A_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_A_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_A_DEBOUNCE_THRESHOLD_07_0
#define GPIO_A_DEBOUNCE_THRESHOLD_07_0                  _MK_ADDR_CONST(0x114e4)
#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_SECURE                   0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_DUAL                     0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_SCR                      GPIO_A_SCR_07_0
#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                       0x1
#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_A_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_A_INPUT_07_0
#define GPIO_A_INPUT_07_0                       _MK_ADDR_CONST(0x114e8)
#define GPIO_A_INPUT_07_0_SECURE                        0x0
#define GPIO_A_INPUT_07_0_DUAL                  0x0
#define GPIO_A_INPUT_07_0_SCR                   GPIO_A_SCR_07_0
#define GPIO_A_INPUT_07_0_WORD_COUNT                    0x1
#define GPIO_A_INPUT_07_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_07_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_07_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_07_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_07_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_A_INPUT_07_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_07_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_A_INPUT_07_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_A_INPUT_07_0_GPIO_IN_SHIFT)
#define GPIO_A_INPUT_07_0_GPIO_IN_RANGE                 0:0
#define GPIO_A_INPUT_07_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_A_INPUT_07_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_07_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_07_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_07_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_07_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_A_OUTPUT_CONTROL_07_0
#define GPIO_A_OUTPUT_CONTROL_07_0                      _MK_ADDR_CONST(0x114ec)
#define GPIO_A_OUTPUT_CONTROL_07_0_SECURE                       0x0
#define GPIO_A_OUTPUT_CONTROL_07_0_DUAL                         0x0
#define GPIO_A_OUTPUT_CONTROL_07_0_SCR                  GPIO_A_SCR_07_0
#define GPIO_A_OUTPUT_CONTROL_07_0_WORD_COUNT                   0x1
#define GPIO_A_OUTPUT_CONTROL_07_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_07_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_07_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_07_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_A_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_A_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_A_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_A_OUTPUT_VALUE_07_0
#define GPIO_A_OUTPUT_VALUE_07_0                        _MK_ADDR_CONST(0x114f0)
#define GPIO_A_OUTPUT_VALUE_07_0_SECURE                         0x0
#define GPIO_A_OUTPUT_VALUE_07_0_DUAL                   0x0
#define GPIO_A_OUTPUT_VALUE_07_0_SCR                    GPIO_A_SCR_07_0
#define GPIO_A_OUTPUT_VALUE_07_0_WORD_COUNT                     0x1
#define GPIO_A_OUTPUT_VALUE_07_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_07_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_07_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_07_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_A_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_A_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_A_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_A_INTERRUPT_CLEAR_07_0
#define GPIO_A_INTERRUPT_CLEAR_07_0                     _MK_ADDR_CONST(0x114f4)
#define GPIO_A_INTERRUPT_CLEAR_07_0_SECURE                      0x0
#define GPIO_A_INTERRUPT_CLEAR_07_0_DUAL                        0x0
#define GPIO_A_INTERRUPT_CLEAR_07_0_SCR                         GPIO_A_SCR_07_0
#define GPIO_A_INTERRUPT_CLEAR_07_0_WORD_COUNT                  0x1
#define GPIO_A_INTERRUPT_CLEAR_07_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_07_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_07_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_07_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_A_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_A_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_A_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_A_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x114f8

// Reserved address 0x114fc

// Register GPIO_A_INTERRUPT_STATUS_G0_0
#define GPIO_A_INTERRUPT_STATUS_G0_0                    _MK_ADDR_CONST(0x11500)
#define GPIO_A_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_A_INTERRUPT_STATUS_G0_0_DUAL                       0x0
#define GPIO_A_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_A_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_A_INTERRUPT_STATUS_G0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G0_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_A_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G0_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_A_INTERRUPT_STATUS_G0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_A_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_A_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_A_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_A_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_A_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_A_INTERRUPT_STATUS_G1_0
#define GPIO_A_INTERRUPT_STATUS_G1_0                    _MK_ADDR_CONST(0x11504)
#define GPIO_A_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_A_INTERRUPT_STATUS_G1_0_DUAL                       0x0
#define GPIO_A_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_A_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_A_INTERRUPT_STATUS_G1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G1_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_A_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G1_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_A_INTERRUPT_STATUS_G1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_A_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_A_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_A_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_A_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_A_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_A_INTERRUPT_STATUS_G2_0
#define GPIO_A_INTERRUPT_STATUS_G2_0                    _MK_ADDR_CONST(0x11508)
#define GPIO_A_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_A_INTERRUPT_STATUS_G2_0_DUAL                       0x0
#define GPIO_A_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_A_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_A_INTERRUPT_STATUS_G2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G2_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_A_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G2_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_A_INTERRUPT_STATUS_G2_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_A_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_A_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_A_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_A_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_A_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_A_INTERRUPT_STATUS_G3_0
#define GPIO_A_INTERRUPT_STATUS_G3_0                    _MK_ADDR_CONST(0x1150c)
#define GPIO_A_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_A_INTERRUPT_STATUS_G3_0_DUAL                       0x0
#define GPIO_A_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_A_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_A_INTERRUPT_STATUS_G3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G3_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_A_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G3_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_A_INTERRUPT_STATUS_G3_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_A_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_A_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_A_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_A_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_A_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_A_INTERRUPT_STATUS_G4_0
#define GPIO_A_INTERRUPT_STATUS_G4_0                    _MK_ADDR_CONST(0x11510)
#define GPIO_A_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_A_INTERRUPT_STATUS_G4_0_DUAL                       0x0
#define GPIO_A_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_A_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_A_INTERRUPT_STATUS_G4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G4_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_A_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G4_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_A_INTERRUPT_STATUS_G4_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_A_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_A_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_A_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_A_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_A_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_A_INTERRUPT_STATUS_G5_0
#define GPIO_A_INTERRUPT_STATUS_G5_0                    _MK_ADDR_CONST(0x11514)
#define GPIO_A_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_A_INTERRUPT_STATUS_G5_0_DUAL                       0x0
#define GPIO_A_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_A_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_A_INTERRUPT_STATUS_G5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G5_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_A_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G5_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_A_INTERRUPT_STATUS_G5_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_A_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_A_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_A_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_A_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_A_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_A_INTERRUPT_STATUS_G6_0
#define GPIO_A_INTERRUPT_STATUS_G6_0                    _MK_ADDR_CONST(0x11518)
#define GPIO_A_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_A_INTERRUPT_STATUS_G6_0_DUAL                       0x0
#define GPIO_A_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_A_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_A_INTERRUPT_STATUS_G6_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G6_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_A_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G6_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_A_INTERRUPT_STATUS_G6_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_A_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_A_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_A_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_A_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_A_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_A_INTERRUPT_STATUS_G7_0
#define GPIO_A_INTERRUPT_STATUS_G7_0                    _MK_ADDR_CONST(0x1151c)
#define GPIO_A_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_A_INTERRUPT_STATUS_G7_0_DUAL                       0x0
#define GPIO_A_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_A_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_A_INTERRUPT_STATUS_G7_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G7_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_A_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G7_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_A_INTERRUPT_STATUS_G7_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_A_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_A_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_A_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_A_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_A_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Reserved address 0x11520

// Reserved address 0x11524

// Reserved address 0x11528

// Reserved address 0x1152c

// Reserved address 0x11530

// Reserved address 0x11534

// Reserved address 0x11538

// Reserved address 0x1153c

// Reserved address 0x11540

// Reserved address 0x11544

// Reserved address 0x11548

// Reserved address 0x1154c

// Reserved address 0x11550

// Reserved address 0x11554

// Reserved address 0x11558

// Reserved address 0x1155c

// Reserved address 0x11560

// Reserved address 0x11564

// Reserved address 0x11568

// Reserved address 0x1156c

// Reserved address 0x11570

// Reserved address 0x11574

// Reserved address 0x11578

// Reserved address 0x1157c

// Reserved address 0x11580

// Reserved address 0x11584

// Reserved address 0x11588

// Reserved address 0x1158c

// Reserved address 0x11590

// Reserved address 0x11594

// Reserved address 0x11598

// Reserved address 0x1159c

// Reserved address 0x115a0

// Reserved address 0x115a4

// Reserved address 0x115a8

// Reserved address 0x115ac

// Reserved address 0x115b0

// Reserved address 0x115b4

// Reserved address 0x115b8

// Reserved address 0x115bc

// Reserved address 0x115c0

// Reserved address 0x115c4

// Reserved address 0x115c8

// Reserved address 0x115cc

// Reserved address 0x115d0

// Reserved address 0x115d4

// Reserved address 0x115d8

// Reserved address 0x115dc

// Reserved address 0x115e0

// Reserved address 0x115e4

// Reserved address 0x115e8

// Reserved address 0x115ec

// Reserved address 0x115f0

// Reserved address 0x115f4

// Reserved address 0x115f8

// Reserved address 0x115fc

// Register GPIO_X_ENABLE_CONFIG_00_0
#define GPIO_X_ENABLE_CONFIG_00_0                       _MK_ADDR_CONST(0x12000)
#define GPIO_X_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_X_ENABLE_CONFIG_00_0_DUAL                  0x0
#define GPIO_X_ENABLE_CONFIG_00_0_SCR                   GPIO_X_SCR_00_0
#define GPIO_X_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_X_ENABLE_CONFIG_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_00_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_X_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_X_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_X_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_X_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_X_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_X_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_X_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_X_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_00_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_00_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_X_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_X_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_X_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_X_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_X_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_X_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_X_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_X_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_X_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_X_DEBOUNCE_THRESHOLD_00_0
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0                  _MK_ADDR_CONST(0x12004)
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_X_SCR_00_0
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_X_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_X_INPUT_00_0
#define GPIO_X_INPUT_00_0                       _MK_ADDR_CONST(0x12008)
#define GPIO_X_INPUT_00_0_SECURE                        0x0
#define GPIO_X_INPUT_00_0_DUAL                  0x0
#define GPIO_X_INPUT_00_0_SCR                   GPIO_X_SCR_00_0
#define GPIO_X_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_X_INPUT_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_00_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_00_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_X_INPUT_00_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_00_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_X_INPUT_00_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_X_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_X_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_X_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_X_INPUT_00_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_00_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_X_OUTPUT_CONTROL_00_0
#define GPIO_X_OUTPUT_CONTROL_00_0                      _MK_ADDR_CONST(0x1200c)
#define GPIO_X_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_X_OUTPUT_CONTROL_00_0_DUAL                         0x0
#define GPIO_X_OUTPUT_CONTROL_00_0_SCR                  GPIO_X_SCR_00_0
#define GPIO_X_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_X_OUTPUT_CONTROL_00_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_00_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_00_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_00_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_X_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_X_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_X_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_X_OUTPUT_VALUE_00_0
#define GPIO_X_OUTPUT_VALUE_00_0                        _MK_ADDR_CONST(0x12010)
#define GPIO_X_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_X_OUTPUT_VALUE_00_0_DUAL                   0x0
#define GPIO_X_OUTPUT_VALUE_00_0_SCR                    GPIO_X_SCR_00_0
#define GPIO_X_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_X_OUTPUT_VALUE_00_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_00_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_00_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_00_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_X_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_X_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_X_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_X_INTERRUPT_CLEAR_00_0
#define GPIO_X_INTERRUPT_CLEAR_00_0                     _MK_ADDR_CONST(0x12014)
#define GPIO_X_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_X_INTERRUPT_CLEAR_00_0_DUAL                        0x0
#define GPIO_X_INTERRUPT_CLEAR_00_0_SCR                         GPIO_X_SCR_00_0
#define GPIO_X_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_X_INTERRUPT_CLEAR_00_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_00_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_00_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_00_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_X_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_X_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_X_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_X_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x12018

// Reserved address 0x1201c

// Register GPIO_X_ENABLE_CONFIG_01_0
#define GPIO_X_ENABLE_CONFIG_01_0                       _MK_ADDR_CONST(0x12020)
#define GPIO_X_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_X_ENABLE_CONFIG_01_0_DUAL                  0x0
#define GPIO_X_ENABLE_CONFIG_01_0_SCR                   GPIO_X_SCR_01_0
#define GPIO_X_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_X_ENABLE_CONFIG_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_01_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_X_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_X_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_X_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_X_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_X_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_X_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_X_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_X_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_01_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_01_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_X_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_X_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_X_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_X_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_X_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_X_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_X_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_X_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_X_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_X_DEBOUNCE_THRESHOLD_01_0
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0                  _MK_ADDR_CONST(0x12024)
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_X_SCR_01_0
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_X_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_X_INPUT_01_0
#define GPIO_X_INPUT_01_0                       _MK_ADDR_CONST(0x12028)
#define GPIO_X_INPUT_01_0_SECURE                        0x0
#define GPIO_X_INPUT_01_0_DUAL                  0x0
#define GPIO_X_INPUT_01_0_SCR                   GPIO_X_SCR_01_0
#define GPIO_X_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_X_INPUT_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_01_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_01_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_X_INPUT_01_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_01_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_X_INPUT_01_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_X_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_X_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_X_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_X_INPUT_01_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_01_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_X_OUTPUT_CONTROL_01_0
#define GPIO_X_OUTPUT_CONTROL_01_0                      _MK_ADDR_CONST(0x1202c)
#define GPIO_X_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_X_OUTPUT_CONTROL_01_0_DUAL                         0x0
#define GPIO_X_OUTPUT_CONTROL_01_0_SCR                  GPIO_X_SCR_01_0
#define GPIO_X_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_X_OUTPUT_CONTROL_01_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_01_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_01_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_01_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_X_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_X_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_X_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_X_OUTPUT_VALUE_01_0
#define GPIO_X_OUTPUT_VALUE_01_0                        _MK_ADDR_CONST(0x12030)
#define GPIO_X_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_X_OUTPUT_VALUE_01_0_DUAL                   0x0
#define GPIO_X_OUTPUT_VALUE_01_0_SCR                    GPIO_X_SCR_01_0
#define GPIO_X_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_X_OUTPUT_VALUE_01_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_01_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_01_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_01_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_X_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_X_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_X_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_X_INTERRUPT_CLEAR_01_0
#define GPIO_X_INTERRUPT_CLEAR_01_0                     _MK_ADDR_CONST(0x12034)
#define GPIO_X_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_X_INTERRUPT_CLEAR_01_0_DUAL                        0x0
#define GPIO_X_INTERRUPT_CLEAR_01_0_SCR                         GPIO_X_SCR_01_0
#define GPIO_X_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_X_INTERRUPT_CLEAR_01_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_01_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_01_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_01_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_X_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_X_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_X_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_X_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x12038

// Reserved address 0x1203c

// Register GPIO_X_ENABLE_CONFIG_02_0
#define GPIO_X_ENABLE_CONFIG_02_0                       _MK_ADDR_CONST(0x12040)
#define GPIO_X_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_X_ENABLE_CONFIG_02_0_DUAL                  0x0
#define GPIO_X_ENABLE_CONFIG_02_0_SCR                   GPIO_X_SCR_02_0
#define GPIO_X_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_X_ENABLE_CONFIG_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_02_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_X_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_X_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_X_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_X_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_X_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_X_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_X_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_X_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_02_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_02_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_X_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_X_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_X_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_X_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_X_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_X_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_X_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_X_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_X_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_X_DEBOUNCE_THRESHOLD_02_0
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0                  _MK_ADDR_CONST(0x12044)
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_X_SCR_02_0
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_X_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_X_INPUT_02_0
#define GPIO_X_INPUT_02_0                       _MK_ADDR_CONST(0x12048)
#define GPIO_X_INPUT_02_0_SECURE                        0x0
#define GPIO_X_INPUT_02_0_DUAL                  0x0
#define GPIO_X_INPUT_02_0_SCR                   GPIO_X_SCR_02_0
#define GPIO_X_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_X_INPUT_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_02_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_02_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_X_INPUT_02_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_02_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_X_INPUT_02_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_X_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_X_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_X_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_X_INPUT_02_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_02_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_X_OUTPUT_CONTROL_02_0
#define GPIO_X_OUTPUT_CONTROL_02_0                      _MK_ADDR_CONST(0x1204c)
#define GPIO_X_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_X_OUTPUT_CONTROL_02_0_DUAL                         0x0
#define GPIO_X_OUTPUT_CONTROL_02_0_SCR                  GPIO_X_SCR_02_0
#define GPIO_X_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_X_OUTPUT_CONTROL_02_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_02_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_02_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_02_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_X_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_X_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_X_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_X_OUTPUT_VALUE_02_0
#define GPIO_X_OUTPUT_VALUE_02_0                        _MK_ADDR_CONST(0x12050)
#define GPIO_X_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_X_OUTPUT_VALUE_02_0_DUAL                   0x0
#define GPIO_X_OUTPUT_VALUE_02_0_SCR                    GPIO_X_SCR_02_0
#define GPIO_X_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_X_OUTPUT_VALUE_02_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_02_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_02_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_02_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_X_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_X_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_X_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_X_INTERRUPT_CLEAR_02_0
#define GPIO_X_INTERRUPT_CLEAR_02_0                     _MK_ADDR_CONST(0x12054)
#define GPIO_X_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_X_INTERRUPT_CLEAR_02_0_DUAL                        0x0
#define GPIO_X_INTERRUPT_CLEAR_02_0_SCR                         GPIO_X_SCR_02_0
#define GPIO_X_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_X_INTERRUPT_CLEAR_02_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_02_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_02_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_02_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_X_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_X_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_X_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_X_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x12058

// Reserved address 0x1205c

// Register GPIO_X_ENABLE_CONFIG_03_0
#define GPIO_X_ENABLE_CONFIG_03_0                       _MK_ADDR_CONST(0x12060)
#define GPIO_X_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_X_ENABLE_CONFIG_03_0_DUAL                  0x0
#define GPIO_X_ENABLE_CONFIG_03_0_SCR                   GPIO_X_SCR_03_0
#define GPIO_X_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_X_ENABLE_CONFIG_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_03_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_X_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_X_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_X_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_X_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_X_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_X_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_X_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_X_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_03_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_03_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_X_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_X_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_X_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_X_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_X_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_X_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_X_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_X_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_X_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_X_DEBOUNCE_THRESHOLD_03_0
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0                  _MK_ADDR_CONST(0x12064)
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_X_SCR_03_0
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_X_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_X_INPUT_03_0
#define GPIO_X_INPUT_03_0                       _MK_ADDR_CONST(0x12068)
#define GPIO_X_INPUT_03_0_SECURE                        0x0
#define GPIO_X_INPUT_03_0_DUAL                  0x0
#define GPIO_X_INPUT_03_0_SCR                   GPIO_X_SCR_03_0
#define GPIO_X_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_X_INPUT_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_03_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_03_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_X_INPUT_03_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_03_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_X_INPUT_03_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_X_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_X_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_X_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_X_INPUT_03_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_03_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_X_OUTPUT_CONTROL_03_0
#define GPIO_X_OUTPUT_CONTROL_03_0                      _MK_ADDR_CONST(0x1206c)
#define GPIO_X_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_X_OUTPUT_CONTROL_03_0_DUAL                         0x0
#define GPIO_X_OUTPUT_CONTROL_03_0_SCR                  GPIO_X_SCR_03_0
#define GPIO_X_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_X_OUTPUT_CONTROL_03_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_03_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_03_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_03_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_X_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_X_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_X_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_X_OUTPUT_VALUE_03_0
#define GPIO_X_OUTPUT_VALUE_03_0                        _MK_ADDR_CONST(0x12070)
#define GPIO_X_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_X_OUTPUT_VALUE_03_0_DUAL                   0x0
#define GPIO_X_OUTPUT_VALUE_03_0_SCR                    GPIO_X_SCR_03_0
#define GPIO_X_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_X_OUTPUT_VALUE_03_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_03_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_03_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_03_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_X_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_X_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_X_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_X_INTERRUPT_CLEAR_03_0
#define GPIO_X_INTERRUPT_CLEAR_03_0                     _MK_ADDR_CONST(0x12074)
#define GPIO_X_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_X_INTERRUPT_CLEAR_03_0_DUAL                        0x0
#define GPIO_X_INTERRUPT_CLEAR_03_0_SCR                         GPIO_X_SCR_03_0
#define GPIO_X_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_X_INTERRUPT_CLEAR_03_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_03_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_03_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_03_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_X_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_X_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_X_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_X_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x12078

// Reserved address 0x1207c

// Register GPIO_X_ENABLE_CONFIG_04_0
#define GPIO_X_ENABLE_CONFIG_04_0                       _MK_ADDR_CONST(0x12080)
#define GPIO_X_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_X_ENABLE_CONFIG_04_0_DUAL                  0x0
#define GPIO_X_ENABLE_CONFIG_04_0_SCR                   GPIO_X_SCR_04_0
#define GPIO_X_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_X_ENABLE_CONFIG_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_04_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_X_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_X_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_X_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_X_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_X_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_X_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_X_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_X_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_04_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_04_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_X_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_X_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_X_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_X_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_X_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_X_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_X_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_X_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_X_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_X_DEBOUNCE_THRESHOLD_04_0
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0                  _MK_ADDR_CONST(0x12084)
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_DUAL                     0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_X_SCR_04_0
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_X_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_X_INPUT_04_0
#define GPIO_X_INPUT_04_0                       _MK_ADDR_CONST(0x12088)
#define GPIO_X_INPUT_04_0_SECURE                        0x0
#define GPIO_X_INPUT_04_0_DUAL                  0x0
#define GPIO_X_INPUT_04_0_SCR                   GPIO_X_SCR_04_0
#define GPIO_X_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_X_INPUT_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_04_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_04_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_X_INPUT_04_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_04_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_X_INPUT_04_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_X_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_X_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_X_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_X_INPUT_04_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_04_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_X_OUTPUT_CONTROL_04_0
#define GPIO_X_OUTPUT_CONTROL_04_0                      _MK_ADDR_CONST(0x1208c)
#define GPIO_X_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_X_OUTPUT_CONTROL_04_0_DUAL                         0x0
#define GPIO_X_OUTPUT_CONTROL_04_0_SCR                  GPIO_X_SCR_04_0
#define GPIO_X_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_X_OUTPUT_CONTROL_04_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_04_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_04_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_04_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_X_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_X_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_X_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_X_OUTPUT_VALUE_04_0
#define GPIO_X_OUTPUT_VALUE_04_0                        _MK_ADDR_CONST(0x12090)
#define GPIO_X_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_X_OUTPUT_VALUE_04_0_DUAL                   0x0
#define GPIO_X_OUTPUT_VALUE_04_0_SCR                    GPIO_X_SCR_04_0
#define GPIO_X_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_X_OUTPUT_VALUE_04_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_04_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_04_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_04_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_X_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_X_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_X_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_X_INTERRUPT_CLEAR_04_0
#define GPIO_X_INTERRUPT_CLEAR_04_0                     _MK_ADDR_CONST(0x12094)
#define GPIO_X_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_X_INTERRUPT_CLEAR_04_0_DUAL                        0x0
#define GPIO_X_INTERRUPT_CLEAR_04_0_SCR                         GPIO_X_SCR_04_0
#define GPIO_X_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_X_INTERRUPT_CLEAR_04_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_04_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_04_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_04_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_X_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_X_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_X_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_X_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x12098

// Reserved address 0x1209c

// Register GPIO_X_ENABLE_CONFIG_05_0
#define GPIO_X_ENABLE_CONFIG_05_0                       _MK_ADDR_CONST(0x120a0)
#define GPIO_X_ENABLE_CONFIG_05_0_SECURE                        0x0
#define GPIO_X_ENABLE_CONFIG_05_0_DUAL                  0x0
#define GPIO_X_ENABLE_CONFIG_05_0_SCR                   GPIO_X_SCR_05_0
#define GPIO_X_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
#define GPIO_X_ENABLE_CONFIG_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_05_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_X_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_X_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_X_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_X_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_X_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_X_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
#define GPIO_X_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
#define GPIO_X_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_05_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_05_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_X_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_X_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_X_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_X_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_X_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_X_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_X_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_X_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_X_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_X_DEBOUNCE_THRESHOLD_05_0
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0                  _MK_ADDR_CONST(0x120a4)
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_DUAL                     0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_X_SCR_05_0
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_X_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_X_INPUT_05_0
#define GPIO_X_INPUT_05_0                       _MK_ADDR_CONST(0x120a8)
#define GPIO_X_INPUT_05_0_SECURE                        0x0
#define GPIO_X_INPUT_05_0_DUAL                  0x0
#define GPIO_X_INPUT_05_0_SCR                   GPIO_X_SCR_05_0
#define GPIO_X_INPUT_05_0_WORD_COUNT                    0x1
#define GPIO_X_INPUT_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_05_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_05_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_X_INPUT_05_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_05_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_X_INPUT_05_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_X_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_X_INPUT_05_0_GPIO_IN_RANGE                 0:0
#define GPIO_X_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_X_INPUT_05_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_05_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_X_OUTPUT_CONTROL_05_0
#define GPIO_X_OUTPUT_CONTROL_05_0                      _MK_ADDR_CONST(0x120ac)
#define GPIO_X_OUTPUT_CONTROL_05_0_SECURE                       0x0
#define GPIO_X_OUTPUT_CONTROL_05_0_DUAL                         0x0
#define GPIO_X_OUTPUT_CONTROL_05_0_SCR                  GPIO_X_SCR_05_0
#define GPIO_X_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
#define GPIO_X_OUTPUT_CONTROL_05_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_05_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_05_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_05_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_X_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_X_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_X_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_X_OUTPUT_VALUE_05_0
#define GPIO_X_OUTPUT_VALUE_05_0                        _MK_ADDR_CONST(0x120b0)
#define GPIO_X_OUTPUT_VALUE_05_0_SECURE                         0x0
#define GPIO_X_OUTPUT_VALUE_05_0_DUAL                   0x0
#define GPIO_X_OUTPUT_VALUE_05_0_SCR                    GPIO_X_SCR_05_0
#define GPIO_X_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
#define GPIO_X_OUTPUT_VALUE_05_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_05_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_05_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_05_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_X_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_X_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_X_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_X_INTERRUPT_CLEAR_05_0
#define GPIO_X_INTERRUPT_CLEAR_05_0                     _MK_ADDR_CONST(0x120b4)
#define GPIO_X_INTERRUPT_CLEAR_05_0_SECURE                      0x0
#define GPIO_X_INTERRUPT_CLEAR_05_0_DUAL                        0x0
#define GPIO_X_INTERRUPT_CLEAR_05_0_SCR                         GPIO_X_SCR_05_0
#define GPIO_X_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
#define GPIO_X_INTERRUPT_CLEAR_05_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_05_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_05_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_05_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_X_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_X_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_X_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_X_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x120b8

// Reserved address 0x120bc

// Register GPIO_X_ENABLE_CONFIG_06_0
#define GPIO_X_ENABLE_CONFIG_06_0                       _MK_ADDR_CONST(0x120c0)
#define GPIO_X_ENABLE_CONFIG_06_0_SECURE                        0x0
#define GPIO_X_ENABLE_CONFIG_06_0_DUAL                  0x0
#define GPIO_X_ENABLE_CONFIG_06_0_SCR                   GPIO_X_SCR_06_0
#define GPIO_X_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
#define GPIO_X_ENABLE_CONFIG_06_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_06_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_X_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
#define GPIO_X_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_X_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_X_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_X_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
#define GPIO_X_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
#define GPIO_X_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
#define GPIO_X_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_06_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_06_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_X_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_X_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_X_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_X_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_X_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_X_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_X_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_X_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_X_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_X_DEBOUNCE_THRESHOLD_06_0
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0                  _MK_ADDR_CONST(0x120c4)
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_DUAL                     0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_X_SCR_06_0
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_X_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_X_INPUT_06_0
#define GPIO_X_INPUT_06_0                       _MK_ADDR_CONST(0x120c8)
#define GPIO_X_INPUT_06_0_SECURE                        0x0
#define GPIO_X_INPUT_06_0_DUAL                  0x0
#define GPIO_X_INPUT_06_0_SCR                   GPIO_X_SCR_06_0
#define GPIO_X_INPUT_06_0_WORD_COUNT                    0x1
#define GPIO_X_INPUT_06_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_06_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_06_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_06_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_06_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_X_INPUT_06_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_06_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_X_INPUT_06_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_X_INPUT_06_0_GPIO_IN_SHIFT)
#define GPIO_X_INPUT_06_0_GPIO_IN_RANGE                 0:0
#define GPIO_X_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_X_INPUT_06_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_06_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_06_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_06_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_X_OUTPUT_CONTROL_06_0
#define GPIO_X_OUTPUT_CONTROL_06_0                      _MK_ADDR_CONST(0x120cc)
#define GPIO_X_OUTPUT_CONTROL_06_0_SECURE                       0x0
#define GPIO_X_OUTPUT_CONTROL_06_0_DUAL                         0x0
#define GPIO_X_OUTPUT_CONTROL_06_0_SCR                  GPIO_X_SCR_06_0
#define GPIO_X_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
#define GPIO_X_OUTPUT_CONTROL_06_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_06_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_06_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_06_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_X_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_X_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_X_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_X_OUTPUT_VALUE_06_0
#define GPIO_X_OUTPUT_VALUE_06_0                        _MK_ADDR_CONST(0x120d0)
#define GPIO_X_OUTPUT_VALUE_06_0_SECURE                         0x0
#define GPIO_X_OUTPUT_VALUE_06_0_DUAL                   0x0
#define GPIO_X_OUTPUT_VALUE_06_0_SCR                    GPIO_X_SCR_06_0
#define GPIO_X_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
#define GPIO_X_OUTPUT_VALUE_06_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_06_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_06_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_06_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_X_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_X_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_X_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_X_INTERRUPT_CLEAR_06_0
#define GPIO_X_INTERRUPT_CLEAR_06_0                     _MK_ADDR_CONST(0x120d4)
#define GPIO_X_INTERRUPT_CLEAR_06_0_SECURE                      0x0
#define GPIO_X_INTERRUPT_CLEAR_06_0_DUAL                        0x0
#define GPIO_X_INTERRUPT_CLEAR_06_0_SCR                         GPIO_X_SCR_06_0
#define GPIO_X_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
#define GPIO_X_INTERRUPT_CLEAR_06_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_06_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_06_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_06_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_X_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_X_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_X_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_X_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x120d8

// Reserved address 0x120dc

// Register GPIO_X_ENABLE_CONFIG_07_0
#define GPIO_X_ENABLE_CONFIG_07_0                       _MK_ADDR_CONST(0x120e0)
#define GPIO_X_ENABLE_CONFIG_07_0_SECURE                        0x0
#define GPIO_X_ENABLE_CONFIG_07_0_DUAL                  0x0
#define GPIO_X_ENABLE_CONFIG_07_0_SCR                   GPIO_X_SCR_07_0
#define GPIO_X_ENABLE_CONFIG_07_0_WORD_COUNT                    0x1
#define GPIO_X_ENABLE_CONFIG_07_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_07_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_X_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
#define GPIO_X_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_X_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_X_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_X_ENABLE_CONFIG_07_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
#define GPIO_X_ENABLE_CONFIG_07_0_IN_OUT_RANGE                  1:1
#define GPIO_X_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                        0x0
#define GPIO_X_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_07_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_07_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_X_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_X_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_X_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_X_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_X_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_X_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_X_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_X_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_X_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_X_DEBOUNCE_THRESHOLD_07_0
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0                  _MK_ADDR_CONST(0x120e4)
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_SECURE                   0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_DUAL                     0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_SCR                      GPIO_X_SCR_07_0
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                       0x1
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_X_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_X_INPUT_07_0
#define GPIO_X_INPUT_07_0                       _MK_ADDR_CONST(0x120e8)
#define GPIO_X_INPUT_07_0_SECURE                        0x0
#define GPIO_X_INPUT_07_0_DUAL                  0x0
#define GPIO_X_INPUT_07_0_SCR                   GPIO_X_SCR_07_0
#define GPIO_X_INPUT_07_0_WORD_COUNT                    0x1
#define GPIO_X_INPUT_07_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_07_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_07_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_07_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_07_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_X_INPUT_07_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_07_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_X_INPUT_07_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_X_INPUT_07_0_GPIO_IN_SHIFT)
#define GPIO_X_INPUT_07_0_GPIO_IN_RANGE                 0:0
#define GPIO_X_INPUT_07_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_X_INPUT_07_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_07_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_07_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_07_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_07_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_X_OUTPUT_CONTROL_07_0
#define GPIO_X_OUTPUT_CONTROL_07_0                      _MK_ADDR_CONST(0x120ec)
#define GPIO_X_OUTPUT_CONTROL_07_0_SECURE                       0x0
#define GPIO_X_OUTPUT_CONTROL_07_0_DUAL                         0x0
#define GPIO_X_OUTPUT_CONTROL_07_0_SCR                  GPIO_X_SCR_07_0
#define GPIO_X_OUTPUT_CONTROL_07_0_WORD_COUNT                   0x1
#define GPIO_X_OUTPUT_CONTROL_07_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_07_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_07_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_07_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_X_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_X_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_X_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_X_OUTPUT_VALUE_07_0
#define GPIO_X_OUTPUT_VALUE_07_0                        _MK_ADDR_CONST(0x120f0)
#define GPIO_X_OUTPUT_VALUE_07_0_SECURE                         0x0
#define GPIO_X_OUTPUT_VALUE_07_0_DUAL                   0x0
#define GPIO_X_OUTPUT_VALUE_07_0_SCR                    GPIO_X_SCR_07_0
#define GPIO_X_OUTPUT_VALUE_07_0_WORD_COUNT                     0x1
#define GPIO_X_OUTPUT_VALUE_07_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_07_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_07_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_07_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_X_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_X_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_X_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_X_INTERRUPT_CLEAR_07_0
#define GPIO_X_INTERRUPT_CLEAR_07_0                     _MK_ADDR_CONST(0x120f4)
#define GPIO_X_INTERRUPT_CLEAR_07_0_SECURE                      0x0
#define GPIO_X_INTERRUPT_CLEAR_07_0_DUAL                        0x0
#define GPIO_X_INTERRUPT_CLEAR_07_0_SCR                         GPIO_X_SCR_07_0
#define GPIO_X_INTERRUPT_CLEAR_07_0_WORD_COUNT                  0x1
#define GPIO_X_INTERRUPT_CLEAR_07_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_07_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_07_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_07_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_X_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_X_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_X_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_X_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x120f8

// Reserved address 0x120fc

// Register GPIO_X_INTERRUPT_STATUS_G0_0
#define GPIO_X_INTERRUPT_STATUS_G0_0                    _MK_ADDR_CONST(0x12100)
#define GPIO_X_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_X_INTERRUPT_STATUS_G0_0_DUAL                       0x0
#define GPIO_X_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_X_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_X_INTERRUPT_STATUS_G0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G0_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G0_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_X_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_X_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_X_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_X_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_X_INTERRUPT_STATUS_G1_0
#define GPIO_X_INTERRUPT_STATUS_G1_0                    _MK_ADDR_CONST(0x12104)
#define GPIO_X_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_X_INTERRUPT_STATUS_G1_0_DUAL                       0x0
#define GPIO_X_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_X_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_X_INTERRUPT_STATUS_G1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G1_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G1_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_X_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_X_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_X_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_X_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_X_INTERRUPT_STATUS_G2_0
#define GPIO_X_INTERRUPT_STATUS_G2_0                    _MK_ADDR_CONST(0x12108)
#define GPIO_X_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_X_INTERRUPT_STATUS_G2_0_DUAL                       0x0
#define GPIO_X_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_X_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_X_INTERRUPT_STATUS_G2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G2_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G2_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G2_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_X_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_X_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_X_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_X_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_X_INTERRUPT_STATUS_G3_0
#define GPIO_X_INTERRUPT_STATUS_G3_0                    _MK_ADDR_CONST(0x1210c)
#define GPIO_X_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_X_INTERRUPT_STATUS_G3_0_DUAL                       0x0
#define GPIO_X_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_X_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_X_INTERRUPT_STATUS_G3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G3_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G3_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G3_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_X_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_X_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_X_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_X_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_X_INTERRUPT_STATUS_G4_0
#define GPIO_X_INTERRUPT_STATUS_G4_0                    _MK_ADDR_CONST(0x12110)
#define GPIO_X_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_X_INTERRUPT_STATUS_G4_0_DUAL                       0x0
#define GPIO_X_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_X_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_X_INTERRUPT_STATUS_G4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G4_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G4_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G4_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_X_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_X_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_X_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_X_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_X_INTERRUPT_STATUS_G5_0
#define GPIO_X_INTERRUPT_STATUS_G5_0                    _MK_ADDR_CONST(0x12114)
#define GPIO_X_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_X_INTERRUPT_STATUS_G5_0_DUAL                       0x0
#define GPIO_X_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_X_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_X_INTERRUPT_STATUS_G5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G5_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G5_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G5_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_X_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_X_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_X_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_X_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_X_INTERRUPT_STATUS_G6_0
#define GPIO_X_INTERRUPT_STATUS_G6_0                    _MK_ADDR_CONST(0x12118)
#define GPIO_X_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_X_INTERRUPT_STATUS_G6_0_DUAL                       0x0
#define GPIO_X_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_X_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_X_INTERRUPT_STATUS_G6_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G6_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G6_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G6_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_X_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_X_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_X_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_X_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_X_INTERRUPT_STATUS_G7_0
#define GPIO_X_INTERRUPT_STATUS_G7_0                    _MK_ADDR_CONST(0x1211c)
#define GPIO_X_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_X_INTERRUPT_STATUS_G7_0_DUAL                       0x0
#define GPIO_X_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_X_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_X_INTERRUPT_STATUS_G7_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G7_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G7_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G7_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_X_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_X_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_X_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_X_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Reserved address 0x12120

// Reserved address 0x12124

// Reserved address 0x12128

// Reserved address 0x1212c

// Reserved address 0x12130

// Reserved address 0x12134

// Reserved address 0x12138

// Reserved address 0x1213c

// Reserved address 0x12140

// Reserved address 0x12144

// Reserved address 0x12148

// Reserved address 0x1214c

// Reserved address 0x12150

// Reserved address 0x12154

// Reserved address 0x12158

// Reserved address 0x1215c

// Reserved address 0x12160

// Reserved address 0x12164

// Reserved address 0x12168

// Reserved address 0x1216c

// Reserved address 0x12170

// Reserved address 0x12174

// Reserved address 0x12178

// Reserved address 0x1217c

// Reserved address 0x12180

// Reserved address 0x12184

// Reserved address 0x12188

// Reserved address 0x1218c

// Reserved address 0x12190

// Reserved address 0x12194

// Reserved address 0x12198

// Reserved address 0x1219c

// Reserved address 0x121a0

// Reserved address 0x121a4

// Reserved address 0x121a8

// Reserved address 0x121ac

// Reserved address 0x121b0

// Reserved address 0x121b4

// Reserved address 0x121b8

// Reserved address 0x121bc

// Reserved address 0x121c0

// Reserved address 0x121c4

// Reserved address 0x121c8

// Reserved address 0x121cc

// Reserved address 0x121d0

// Reserved address 0x121d4

// Reserved address 0x121d8

// Reserved address 0x121dc

// Reserved address 0x121e0

// Reserved address 0x121e4

// Reserved address 0x121e8

// Reserved address 0x121ec

// Reserved address 0x121f0

// Reserved address 0x121f4

// Reserved address 0x121f8

// Reserved address 0x121fc

// Register GPIO_Y_ENABLE_CONFIG_00_0
#define GPIO_Y_ENABLE_CONFIG_00_0                       _MK_ADDR_CONST(0x12200)
#define GPIO_Y_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_Y_ENABLE_CONFIG_00_0_DUAL                  0x0
#define GPIO_Y_ENABLE_CONFIG_00_0_SCR                   GPIO_Y_SCR_00_0
#define GPIO_Y_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_Y_ENABLE_CONFIG_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_00_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Y_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Y_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_Y_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Y_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_00_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_00_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Y_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Y_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Y_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_Y_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Y_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Y_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_Y_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Y_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Y_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_Y_DEBOUNCE_THRESHOLD_00_0
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0                  _MK_ADDR_CONST(0x12204)
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_Y_SCR_00_0
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_Y_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_Y_INPUT_00_0
#define GPIO_Y_INPUT_00_0                       _MK_ADDR_CONST(0x12208)
#define GPIO_Y_INPUT_00_0_SECURE                        0x0
#define GPIO_Y_INPUT_00_0_DUAL                  0x0
#define GPIO_Y_INPUT_00_0_SCR                   GPIO_Y_SCR_00_0
#define GPIO_Y_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_Y_INPUT_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_00_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_00_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Y_INPUT_00_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_00_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Y_INPUT_00_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_Y_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_Y_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_Y_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Y_INPUT_00_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_00_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_Y_OUTPUT_CONTROL_00_0
#define GPIO_Y_OUTPUT_CONTROL_00_0                      _MK_ADDR_CONST(0x1220c)
#define GPIO_Y_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_Y_OUTPUT_CONTROL_00_0_DUAL                         0x0
#define GPIO_Y_OUTPUT_CONTROL_00_0_SCR                  GPIO_Y_SCR_00_0
#define GPIO_Y_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_Y_OUTPUT_CONTROL_00_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_00_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_00_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_00_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Y_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Y_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Y_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_Y_OUTPUT_VALUE_00_0
#define GPIO_Y_OUTPUT_VALUE_00_0                        _MK_ADDR_CONST(0x12210)
#define GPIO_Y_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_Y_OUTPUT_VALUE_00_0_DUAL                   0x0
#define GPIO_Y_OUTPUT_VALUE_00_0_SCR                    GPIO_Y_SCR_00_0
#define GPIO_Y_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_Y_OUTPUT_VALUE_00_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_00_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_00_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_00_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Y_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Y_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Y_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_Y_INTERRUPT_CLEAR_00_0
#define GPIO_Y_INTERRUPT_CLEAR_00_0                     _MK_ADDR_CONST(0x12214)
#define GPIO_Y_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_Y_INTERRUPT_CLEAR_00_0_DUAL                        0x0
#define GPIO_Y_INTERRUPT_CLEAR_00_0_SCR                         GPIO_Y_SCR_00_0
#define GPIO_Y_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_Y_INTERRUPT_CLEAR_00_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_00_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_00_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_00_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Y_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Y_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Y_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Y_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x12218

// Reserved address 0x1221c

// Register GPIO_Y_ENABLE_CONFIG_01_0
#define GPIO_Y_ENABLE_CONFIG_01_0                       _MK_ADDR_CONST(0x12220)
#define GPIO_Y_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_Y_ENABLE_CONFIG_01_0_DUAL                  0x0
#define GPIO_Y_ENABLE_CONFIG_01_0_SCR                   GPIO_Y_SCR_01_0
#define GPIO_Y_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_Y_ENABLE_CONFIG_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_01_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Y_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Y_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_Y_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Y_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_01_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_01_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Y_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Y_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Y_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_Y_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Y_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Y_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_Y_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Y_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Y_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_Y_DEBOUNCE_THRESHOLD_01_0
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0                  _MK_ADDR_CONST(0x12224)
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_Y_SCR_01_0
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_Y_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_Y_INPUT_01_0
#define GPIO_Y_INPUT_01_0                       _MK_ADDR_CONST(0x12228)
#define GPIO_Y_INPUT_01_0_SECURE                        0x0
#define GPIO_Y_INPUT_01_0_DUAL                  0x0
#define GPIO_Y_INPUT_01_0_SCR                   GPIO_Y_SCR_01_0
#define GPIO_Y_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_Y_INPUT_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_01_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_01_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Y_INPUT_01_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_01_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Y_INPUT_01_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_Y_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_Y_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_Y_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Y_INPUT_01_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_01_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_Y_OUTPUT_CONTROL_01_0
#define GPIO_Y_OUTPUT_CONTROL_01_0                      _MK_ADDR_CONST(0x1222c)
#define GPIO_Y_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_Y_OUTPUT_CONTROL_01_0_DUAL                         0x0
#define GPIO_Y_OUTPUT_CONTROL_01_0_SCR                  GPIO_Y_SCR_01_0
#define GPIO_Y_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_Y_OUTPUT_CONTROL_01_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_01_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_01_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_01_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Y_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Y_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Y_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_Y_OUTPUT_VALUE_01_0
#define GPIO_Y_OUTPUT_VALUE_01_0                        _MK_ADDR_CONST(0x12230)
#define GPIO_Y_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_Y_OUTPUT_VALUE_01_0_DUAL                   0x0
#define GPIO_Y_OUTPUT_VALUE_01_0_SCR                    GPIO_Y_SCR_01_0
#define GPIO_Y_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_Y_OUTPUT_VALUE_01_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_01_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_01_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_01_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Y_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Y_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Y_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_Y_INTERRUPT_CLEAR_01_0
#define GPIO_Y_INTERRUPT_CLEAR_01_0                     _MK_ADDR_CONST(0x12234)
#define GPIO_Y_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_Y_INTERRUPT_CLEAR_01_0_DUAL                        0x0
#define GPIO_Y_INTERRUPT_CLEAR_01_0_SCR                         GPIO_Y_SCR_01_0
#define GPIO_Y_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_Y_INTERRUPT_CLEAR_01_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_01_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_01_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_01_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Y_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Y_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Y_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Y_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x12238

// Reserved address 0x1223c

// Register GPIO_Y_ENABLE_CONFIG_02_0
#define GPIO_Y_ENABLE_CONFIG_02_0                       _MK_ADDR_CONST(0x12240)
#define GPIO_Y_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_Y_ENABLE_CONFIG_02_0_DUAL                  0x0
#define GPIO_Y_ENABLE_CONFIG_02_0_SCR                   GPIO_Y_SCR_02_0
#define GPIO_Y_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_Y_ENABLE_CONFIG_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_02_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Y_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Y_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_Y_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Y_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_02_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_02_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Y_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Y_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Y_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_Y_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Y_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Y_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_Y_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Y_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Y_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_Y_DEBOUNCE_THRESHOLD_02_0
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0                  _MK_ADDR_CONST(0x12244)
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_Y_SCR_02_0
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_Y_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_Y_INPUT_02_0
#define GPIO_Y_INPUT_02_0                       _MK_ADDR_CONST(0x12248)
#define GPIO_Y_INPUT_02_0_SECURE                        0x0
#define GPIO_Y_INPUT_02_0_DUAL                  0x0
#define GPIO_Y_INPUT_02_0_SCR                   GPIO_Y_SCR_02_0
#define GPIO_Y_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_Y_INPUT_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_02_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_02_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Y_INPUT_02_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_02_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Y_INPUT_02_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_Y_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_Y_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_Y_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Y_INPUT_02_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_02_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_Y_OUTPUT_CONTROL_02_0
#define GPIO_Y_OUTPUT_CONTROL_02_0                      _MK_ADDR_CONST(0x1224c)
#define GPIO_Y_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_Y_OUTPUT_CONTROL_02_0_DUAL                         0x0
#define GPIO_Y_OUTPUT_CONTROL_02_0_SCR                  GPIO_Y_SCR_02_0
#define GPIO_Y_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_Y_OUTPUT_CONTROL_02_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_02_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_02_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_02_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Y_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Y_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Y_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_Y_OUTPUT_VALUE_02_0
#define GPIO_Y_OUTPUT_VALUE_02_0                        _MK_ADDR_CONST(0x12250)
#define GPIO_Y_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_Y_OUTPUT_VALUE_02_0_DUAL                   0x0
#define GPIO_Y_OUTPUT_VALUE_02_0_SCR                    GPIO_Y_SCR_02_0
#define GPIO_Y_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_Y_OUTPUT_VALUE_02_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_02_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_02_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_02_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Y_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Y_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Y_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_Y_INTERRUPT_CLEAR_02_0
#define GPIO_Y_INTERRUPT_CLEAR_02_0                     _MK_ADDR_CONST(0x12254)
#define GPIO_Y_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_Y_INTERRUPT_CLEAR_02_0_DUAL                        0x0
#define GPIO_Y_INTERRUPT_CLEAR_02_0_SCR                         GPIO_Y_SCR_02_0
#define GPIO_Y_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_Y_INTERRUPT_CLEAR_02_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_02_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_02_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_02_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Y_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Y_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Y_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Y_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x12258

// Reserved address 0x1225c

// Register GPIO_Y_ENABLE_CONFIG_03_0
#define GPIO_Y_ENABLE_CONFIG_03_0                       _MK_ADDR_CONST(0x12260)
#define GPIO_Y_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_Y_ENABLE_CONFIG_03_0_DUAL                  0x0
#define GPIO_Y_ENABLE_CONFIG_03_0_SCR                   GPIO_Y_SCR_03_0
#define GPIO_Y_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_Y_ENABLE_CONFIG_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_03_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Y_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Y_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_Y_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Y_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_03_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_03_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Y_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Y_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Y_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_Y_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Y_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Y_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_Y_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Y_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Y_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_Y_DEBOUNCE_THRESHOLD_03_0
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0                  _MK_ADDR_CONST(0x12264)
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_Y_SCR_03_0
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_Y_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_Y_INPUT_03_0
#define GPIO_Y_INPUT_03_0                       _MK_ADDR_CONST(0x12268)
#define GPIO_Y_INPUT_03_0_SECURE                        0x0
#define GPIO_Y_INPUT_03_0_DUAL                  0x0
#define GPIO_Y_INPUT_03_0_SCR                   GPIO_Y_SCR_03_0
#define GPIO_Y_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_Y_INPUT_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_03_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_03_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Y_INPUT_03_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_03_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Y_INPUT_03_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_Y_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_Y_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_Y_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Y_INPUT_03_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_03_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_Y_OUTPUT_CONTROL_03_0
#define GPIO_Y_OUTPUT_CONTROL_03_0                      _MK_ADDR_CONST(0x1226c)
#define GPIO_Y_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_Y_OUTPUT_CONTROL_03_0_DUAL                         0x0
#define GPIO_Y_OUTPUT_CONTROL_03_0_SCR                  GPIO_Y_SCR_03_0
#define GPIO_Y_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_Y_OUTPUT_CONTROL_03_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_03_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_03_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_03_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Y_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Y_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Y_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_Y_OUTPUT_VALUE_03_0
#define GPIO_Y_OUTPUT_VALUE_03_0                        _MK_ADDR_CONST(0x12270)
#define GPIO_Y_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_Y_OUTPUT_VALUE_03_0_DUAL                   0x0
#define GPIO_Y_OUTPUT_VALUE_03_0_SCR                    GPIO_Y_SCR_03_0
#define GPIO_Y_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_Y_OUTPUT_VALUE_03_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_03_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_03_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_03_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Y_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Y_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Y_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_Y_INTERRUPT_CLEAR_03_0
#define GPIO_Y_INTERRUPT_CLEAR_03_0                     _MK_ADDR_CONST(0x12274)
#define GPIO_Y_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_Y_INTERRUPT_CLEAR_03_0_DUAL                        0x0
#define GPIO_Y_INTERRUPT_CLEAR_03_0_SCR                         GPIO_Y_SCR_03_0
#define GPIO_Y_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_Y_INTERRUPT_CLEAR_03_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_03_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_03_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_03_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Y_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Y_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Y_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Y_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x12278

// Reserved address 0x1227c

// Register GPIO_Y_ENABLE_CONFIG_04_0
#define GPIO_Y_ENABLE_CONFIG_04_0                       _MK_ADDR_CONST(0x12280)
#define GPIO_Y_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_Y_ENABLE_CONFIG_04_0_DUAL                  0x0
#define GPIO_Y_ENABLE_CONFIG_04_0_SCR                   GPIO_Y_SCR_04_0
#define GPIO_Y_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_Y_ENABLE_CONFIG_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_04_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Y_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Y_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_Y_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Y_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_04_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_04_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Y_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Y_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Y_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_Y_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Y_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Y_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_Y_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Y_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Y_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_Y_DEBOUNCE_THRESHOLD_04_0
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0                  _MK_ADDR_CONST(0x12284)
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_DUAL                     0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_Y_SCR_04_0
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_Y_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_Y_INPUT_04_0
#define GPIO_Y_INPUT_04_0                       _MK_ADDR_CONST(0x12288)
#define GPIO_Y_INPUT_04_0_SECURE                        0x0
#define GPIO_Y_INPUT_04_0_DUAL                  0x0
#define GPIO_Y_INPUT_04_0_SCR                   GPIO_Y_SCR_04_0
#define GPIO_Y_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_Y_INPUT_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_04_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_04_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Y_INPUT_04_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_04_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Y_INPUT_04_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_Y_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_Y_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_Y_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Y_INPUT_04_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_04_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_Y_OUTPUT_CONTROL_04_0
#define GPIO_Y_OUTPUT_CONTROL_04_0                      _MK_ADDR_CONST(0x1228c)
#define GPIO_Y_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_Y_OUTPUT_CONTROL_04_0_DUAL                         0x0
#define GPIO_Y_OUTPUT_CONTROL_04_0_SCR                  GPIO_Y_SCR_04_0
#define GPIO_Y_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_Y_OUTPUT_CONTROL_04_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_04_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_04_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_04_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Y_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Y_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Y_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_Y_OUTPUT_VALUE_04_0
#define GPIO_Y_OUTPUT_VALUE_04_0                        _MK_ADDR_CONST(0x12290)
#define GPIO_Y_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_Y_OUTPUT_VALUE_04_0_DUAL                   0x0
#define GPIO_Y_OUTPUT_VALUE_04_0_SCR                    GPIO_Y_SCR_04_0
#define GPIO_Y_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_Y_OUTPUT_VALUE_04_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_04_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_04_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_04_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Y_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Y_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Y_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_Y_INTERRUPT_CLEAR_04_0
#define GPIO_Y_INTERRUPT_CLEAR_04_0                     _MK_ADDR_CONST(0x12294)
#define GPIO_Y_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_Y_INTERRUPT_CLEAR_04_0_DUAL                        0x0
#define GPIO_Y_INTERRUPT_CLEAR_04_0_SCR                         GPIO_Y_SCR_04_0
#define GPIO_Y_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_Y_INTERRUPT_CLEAR_04_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_04_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_04_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_04_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Y_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Y_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Y_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Y_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x12298

// Reserved address 0x1229c

// Register GPIO_Y_ENABLE_CONFIG_05_0
#define GPIO_Y_ENABLE_CONFIG_05_0                       _MK_ADDR_CONST(0x122a0)
#define GPIO_Y_ENABLE_CONFIG_05_0_SECURE                        0x0
#define GPIO_Y_ENABLE_CONFIG_05_0_DUAL                  0x0
#define GPIO_Y_ENABLE_CONFIG_05_0_SCR                   GPIO_Y_SCR_05_0
#define GPIO_Y_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
#define GPIO_Y_ENABLE_CONFIG_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_05_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Y_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Y_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
#define GPIO_Y_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Y_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_05_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_05_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Y_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Y_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Y_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_Y_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Y_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Y_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_Y_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Y_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Y_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_Y_DEBOUNCE_THRESHOLD_05_0
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0                  _MK_ADDR_CONST(0x122a4)
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_DUAL                     0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_Y_SCR_05_0
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_Y_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_Y_INPUT_05_0
#define GPIO_Y_INPUT_05_0                       _MK_ADDR_CONST(0x122a8)
#define GPIO_Y_INPUT_05_0_SECURE                        0x0
#define GPIO_Y_INPUT_05_0_DUAL                  0x0
#define GPIO_Y_INPUT_05_0_SCR                   GPIO_Y_SCR_05_0
#define GPIO_Y_INPUT_05_0_WORD_COUNT                    0x1
#define GPIO_Y_INPUT_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_05_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_05_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Y_INPUT_05_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_05_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Y_INPUT_05_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_Y_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_Y_INPUT_05_0_GPIO_IN_RANGE                 0:0
#define GPIO_Y_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Y_INPUT_05_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_05_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_Y_OUTPUT_CONTROL_05_0
#define GPIO_Y_OUTPUT_CONTROL_05_0                      _MK_ADDR_CONST(0x122ac)
#define GPIO_Y_OUTPUT_CONTROL_05_0_SECURE                       0x0
#define GPIO_Y_OUTPUT_CONTROL_05_0_DUAL                         0x0
#define GPIO_Y_OUTPUT_CONTROL_05_0_SCR                  GPIO_Y_SCR_05_0
#define GPIO_Y_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
#define GPIO_Y_OUTPUT_CONTROL_05_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_05_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_05_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_05_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Y_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Y_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Y_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_Y_OUTPUT_VALUE_05_0
#define GPIO_Y_OUTPUT_VALUE_05_0                        _MK_ADDR_CONST(0x122b0)
#define GPIO_Y_OUTPUT_VALUE_05_0_SECURE                         0x0
#define GPIO_Y_OUTPUT_VALUE_05_0_DUAL                   0x0
#define GPIO_Y_OUTPUT_VALUE_05_0_SCR                    GPIO_Y_SCR_05_0
#define GPIO_Y_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
#define GPIO_Y_OUTPUT_VALUE_05_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_05_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_05_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_05_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Y_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Y_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Y_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_Y_INTERRUPT_CLEAR_05_0
#define GPIO_Y_INTERRUPT_CLEAR_05_0                     _MK_ADDR_CONST(0x122b4)
#define GPIO_Y_INTERRUPT_CLEAR_05_0_SECURE                      0x0
#define GPIO_Y_INTERRUPT_CLEAR_05_0_DUAL                        0x0
#define GPIO_Y_INTERRUPT_CLEAR_05_0_SCR                         GPIO_Y_SCR_05_0
#define GPIO_Y_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
#define GPIO_Y_INTERRUPT_CLEAR_05_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_05_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_05_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_05_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Y_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Y_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Y_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Y_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x122b8

// Reserved address 0x122bc

// Register GPIO_Y_ENABLE_CONFIG_06_0
#define GPIO_Y_ENABLE_CONFIG_06_0                       _MK_ADDR_CONST(0x122c0)
#define GPIO_Y_ENABLE_CONFIG_06_0_SECURE                        0x0
#define GPIO_Y_ENABLE_CONFIG_06_0_DUAL                  0x0
#define GPIO_Y_ENABLE_CONFIG_06_0_SCR                   GPIO_Y_SCR_06_0
#define GPIO_Y_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
#define GPIO_Y_ENABLE_CONFIG_06_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_06_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Y_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Y_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
#define GPIO_Y_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Y_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_06_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_06_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Y_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Y_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Y_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_Y_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Y_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Y_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_Y_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Y_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Y_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_Y_DEBOUNCE_THRESHOLD_06_0
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0                  _MK_ADDR_CONST(0x122c4)
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_DUAL                     0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_Y_SCR_06_0
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_Y_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_Y_INPUT_06_0
#define GPIO_Y_INPUT_06_0                       _MK_ADDR_CONST(0x122c8)
#define GPIO_Y_INPUT_06_0_SECURE                        0x0
#define GPIO_Y_INPUT_06_0_DUAL                  0x0
#define GPIO_Y_INPUT_06_0_SCR                   GPIO_Y_SCR_06_0
#define GPIO_Y_INPUT_06_0_WORD_COUNT                    0x1
#define GPIO_Y_INPUT_06_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_06_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_06_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_06_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_06_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Y_INPUT_06_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_06_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Y_INPUT_06_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_Y_INPUT_06_0_GPIO_IN_SHIFT)
#define GPIO_Y_INPUT_06_0_GPIO_IN_RANGE                 0:0
#define GPIO_Y_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Y_INPUT_06_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_06_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_06_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_06_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_Y_OUTPUT_CONTROL_06_0
#define GPIO_Y_OUTPUT_CONTROL_06_0                      _MK_ADDR_CONST(0x122cc)
#define GPIO_Y_OUTPUT_CONTROL_06_0_SECURE                       0x0
#define GPIO_Y_OUTPUT_CONTROL_06_0_DUAL                         0x0
#define GPIO_Y_OUTPUT_CONTROL_06_0_SCR                  GPIO_Y_SCR_06_0
#define GPIO_Y_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
#define GPIO_Y_OUTPUT_CONTROL_06_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_06_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_06_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_06_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Y_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Y_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Y_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_Y_OUTPUT_VALUE_06_0
#define GPIO_Y_OUTPUT_VALUE_06_0                        _MK_ADDR_CONST(0x122d0)
#define GPIO_Y_OUTPUT_VALUE_06_0_SECURE                         0x0
#define GPIO_Y_OUTPUT_VALUE_06_0_DUAL                   0x0
#define GPIO_Y_OUTPUT_VALUE_06_0_SCR                    GPIO_Y_SCR_06_0
#define GPIO_Y_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
#define GPIO_Y_OUTPUT_VALUE_06_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_06_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_06_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_06_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Y_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Y_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Y_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_Y_INTERRUPT_CLEAR_06_0
#define GPIO_Y_INTERRUPT_CLEAR_06_0                     _MK_ADDR_CONST(0x122d4)
#define GPIO_Y_INTERRUPT_CLEAR_06_0_SECURE                      0x0
#define GPIO_Y_INTERRUPT_CLEAR_06_0_DUAL                        0x0
#define GPIO_Y_INTERRUPT_CLEAR_06_0_SCR                         GPIO_Y_SCR_06_0
#define GPIO_Y_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
#define GPIO_Y_INTERRUPT_CLEAR_06_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_06_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_06_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_06_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Y_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Y_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Y_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Y_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x122d8

// Reserved address 0x122dc

// Register GPIO_Y_ENABLE_CONFIG_07_0
#define GPIO_Y_ENABLE_CONFIG_07_0                       _MK_ADDR_CONST(0x122e0)
#define GPIO_Y_ENABLE_CONFIG_07_0_SECURE                        0x0
#define GPIO_Y_ENABLE_CONFIG_07_0_DUAL                  0x0
#define GPIO_Y_ENABLE_CONFIG_07_0_SCR                   GPIO_Y_SCR_07_0
#define GPIO_Y_ENABLE_CONFIG_07_0_WORD_COUNT                    0x1
#define GPIO_Y_ENABLE_CONFIG_07_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_07_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Y_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Y_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_07_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_07_0_IN_OUT_RANGE                  1:1
#define GPIO_Y_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Y_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_07_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_07_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Y_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Y_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Y_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_Y_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Y_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Y_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_Y_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Y_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Y_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_Y_DEBOUNCE_THRESHOLD_07_0
#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0                  _MK_ADDR_CONST(0x122e4)
#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_SECURE                   0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_DUAL                     0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_SCR                      GPIO_Y_SCR_07_0
#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                       0x1
#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_Y_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_Y_INPUT_07_0
#define GPIO_Y_INPUT_07_0                       _MK_ADDR_CONST(0x122e8)
#define GPIO_Y_INPUT_07_0_SECURE                        0x0
#define GPIO_Y_INPUT_07_0_DUAL                  0x0
#define GPIO_Y_INPUT_07_0_SCR                   GPIO_Y_SCR_07_0
#define GPIO_Y_INPUT_07_0_WORD_COUNT                    0x1
#define GPIO_Y_INPUT_07_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_07_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_07_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_07_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_07_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Y_INPUT_07_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_07_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Y_INPUT_07_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_Y_INPUT_07_0_GPIO_IN_SHIFT)
#define GPIO_Y_INPUT_07_0_GPIO_IN_RANGE                 0:0
#define GPIO_Y_INPUT_07_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Y_INPUT_07_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_07_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_07_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_07_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_07_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_Y_OUTPUT_CONTROL_07_0
#define GPIO_Y_OUTPUT_CONTROL_07_0                      _MK_ADDR_CONST(0x122ec)
#define GPIO_Y_OUTPUT_CONTROL_07_0_SECURE                       0x0
#define GPIO_Y_OUTPUT_CONTROL_07_0_DUAL                         0x0
#define GPIO_Y_OUTPUT_CONTROL_07_0_SCR                  GPIO_Y_SCR_07_0
#define GPIO_Y_OUTPUT_CONTROL_07_0_WORD_COUNT                   0x1
#define GPIO_Y_OUTPUT_CONTROL_07_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_07_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_07_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_07_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Y_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Y_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Y_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_Y_OUTPUT_VALUE_07_0
#define GPIO_Y_OUTPUT_VALUE_07_0                        _MK_ADDR_CONST(0x122f0)
#define GPIO_Y_OUTPUT_VALUE_07_0_SECURE                         0x0
#define GPIO_Y_OUTPUT_VALUE_07_0_DUAL                   0x0
#define GPIO_Y_OUTPUT_VALUE_07_0_SCR                    GPIO_Y_SCR_07_0
#define GPIO_Y_OUTPUT_VALUE_07_0_WORD_COUNT                     0x1
#define GPIO_Y_OUTPUT_VALUE_07_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_07_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_07_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_07_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Y_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Y_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Y_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_Y_INTERRUPT_CLEAR_07_0
#define GPIO_Y_INTERRUPT_CLEAR_07_0                     _MK_ADDR_CONST(0x122f4)
#define GPIO_Y_INTERRUPT_CLEAR_07_0_SECURE                      0x0
#define GPIO_Y_INTERRUPT_CLEAR_07_0_DUAL                        0x0
#define GPIO_Y_INTERRUPT_CLEAR_07_0_SCR                         GPIO_Y_SCR_07_0
#define GPIO_Y_INTERRUPT_CLEAR_07_0_WORD_COUNT                  0x1
#define GPIO_Y_INTERRUPT_CLEAR_07_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_07_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_07_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_07_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Y_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Y_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Y_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Y_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x122f8

// Reserved address 0x122fc

// Register GPIO_Y_INTERRUPT_STATUS_G0_0
#define GPIO_Y_INTERRUPT_STATUS_G0_0                    _MK_ADDR_CONST(0x12300)
#define GPIO_Y_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_Y_INTERRUPT_STATUS_G0_0_DUAL                       0x0
#define GPIO_Y_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_Y_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_Y_INTERRUPT_STATUS_G0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G0_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_Y_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G0_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Y_INTERRUPT_STATUS_G0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_Y_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Y_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_Y_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Y_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_Y_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_Y_INTERRUPT_STATUS_G1_0
#define GPIO_Y_INTERRUPT_STATUS_G1_0                    _MK_ADDR_CONST(0x12304)
#define GPIO_Y_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_Y_INTERRUPT_STATUS_G1_0_DUAL                       0x0
#define GPIO_Y_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_Y_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_Y_INTERRUPT_STATUS_G1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G1_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_Y_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G1_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Y_INTERRUPT_STATUS_G1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_Y_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Y_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_Y_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Y_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_Y_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_Y_INTERRUPT_STATUS_G2_0
#define GPIO_Y_INTERRUPT_STATUS_G2_0                    _MK_ADDR_CONST(0x12308)
#define GPIO_Y_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_Y_INTERRUPT_STATUS_G2_0_DUAL                       0x0
#define GPIO_Y_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_Y_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_Y_INTERRUPT_STATUS_G2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G2_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_Y_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G2_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Y_INTERRUPT_STATUS_G2_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_Y_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Y_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_Y_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Y_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_Y_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_Y_INTERRUPT_STATUS_G3_0
#define GPIO_Y_INTERRUPT_STATUS_G3_0                    _MK_ADDR_CONST(0x1230c)
#define GPIO_Y_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_Y_INTERRUPT_STATUS_G3_0_DUAL                       0x0
#define GPIO_Y_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_Y_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_Y_INTERRUPT_STATUS_G3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G3_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_Y_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G3_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Y_INTERRUPT_STATUS_G3_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_Y_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Y_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_Y_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Y_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_Y_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_Y_INTERRUPT_STATUS_G4_0
#define GPIO_Y_INTERRUPT_STATUS_G4_0                    _MK_ADDR_CONST(0x12310)
#define GPIO_Y_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_Y_INTERRUPT_STATUS_G4_0_DUAL                       0x0
#define GPIO_Y_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_Y_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_Y_INTERRUPT_STATUS_G4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G4_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_Y_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G4_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Y_INTERRUPT_STATUS_G4_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_Y_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Y_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_Y_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Y_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_Y_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_Y_INTERRUPT_STATUS_G5_0
#define GPIO_Y_INTERRUPT_STATUS_G5_0                    _MK_ADDR_CONST(0x12314)
#define GPIO_Y_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_Y_INTERRUPT_STATUS_G5_0_DUAL                       0x0
#define GPIO_Y_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_Y_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_Y_INTERRUPT_STATUS_G5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G5_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_Y_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G5_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Y_INTERRUPT_STATUS_G5_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_Y_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Y_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_Y_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Y_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_Y_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_Y_INTERRUPT_STATUS_G6_0
#define GPIO_Y_INTERRUPT_STATUS_G6_0                    _MK_ADDR_CONST(0x12318)
#define GPIO_Y_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_Y_INTERRUPT_STATUS_G6_0_DUAL                       0x0
#define GPIO_Y_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_Y_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_Y_INTERRUPT_STATUS_G6_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G6_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_Y_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G6_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Y_INTERRUPT_STATUS_G6_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_Y_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Y_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_Y_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Y_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_Y_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_Y_INTERRUPT_STATUS_G7_0
#define GPIO_Y_INTERRUPT_STATUS_G7_0                    _MK_ADDR_CONST(0x1231c)
#define GPIO_Y_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_Y_INTERRUPT_STATUS_G7_0_DUAL                       0x0
#define GPIO_Y_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_Y_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_Y_INTERRUPT_STATUS_G7_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G7_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_Y_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G7_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Y_INTERRUPT_STATUS_G7_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_Y_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Y_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_Y_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Y_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_Y_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Reserved address 0x12320

// Reserved address 0x12324

// Reserved address 0x12328

// Reserved address 0x1232c

// Reserved address 0x12330

// Reserved address 0x12334

// Reserved address 0x12338

// Reserved address 0x1233c

// Reserved address 0x12340

// Reserved address 0x12344

// Reserved address 0x12348

// Reserved address 0x1234c

// Reserved address 0x12350

// Reserved address 0x12354

// Reserved address 0x12358

// Reserved address 0x1235c

// Reserved address 0x12360

// Reserved address 0x12364

// Reserved address 0x12368

// Reserved address 0x1236c

// Reserved address 0x12370

// Reserved address 0x12374

// Reserved address 0x12378

// Reserved address 0x1237c

// Reserved address 0x12380

// Reserved address 0x12384

// Reserved address 0x12388

// Reserved address 0x1238c

// Reserved address 0x12390

// Reserved address 0x12394

// Reserved address 0x12398

// Reserved address 0x1239c

// Reserved address 0x123a0

// Reserved address 0x123a4

// Reserved address 0x123a8

// Reserved address 0x123ac

// Reserved address 0x123b0

// Reserved address 0x123b4

// Reserved address 0x123b8

// Reserved address 0x123bc

// Reserved address 0x123c0

// Reserved address 0x123c4

// Reserved address 0x123c8

// Reserved address 0x123cc

// Reserved address 0x123d0

// Reserved address 0x123d4

// Reserved address 0x123d8

// Reserved address 0x123dc

// Reserved address 0x123e0

// Reserved address 0x123e4

// Reserved address 0x123e8

// Reserved address 0x123ec

// Reserved address 0x123f0

// Reserved address 0x123f4

// Reserved address 0x123f8

// Reserved address 0x123fc

// Register GPIO_Z_ENABLE_CONFIG_00_0
#define GPIO_Z_ENABLE_CONFIG_00_0                       _MK_ADDR_CONST(0x12400)
#define GPIO_Z_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_Z_ENABLE_CONFIG_00_0_DUAL                  0x0
#define GPIO_Z_ENABLE_CONFIG_00_0_SCR                   GPIO_Z_SCR_00_0
#define GPIO_Z_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_Z_ENABLE_CONFIG_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Z_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_Z_ENABLE_CONFIG_00_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Z_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Z_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Z_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_Z_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_Z_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Z_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_00_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_00_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Z_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Z_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Z_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_Z_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Z_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Z_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_Z_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Z_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Z_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_Z_DEBOUNCE_THRESHOLD_00_0
#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0                  _MK_ADDR_CONST(0x12404)
#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_Z_SCR_00_0
#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_Z_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_Z_INPUT_00_0
#define GPIO_Z_INPUT_00_0                       _MK_ADDR_CONST(0x12408)
#define GPIO_Z_INPUT_00_0_SECURE                        0x0
#define GPIO_Z_INPUT_00_0_DUAL                  0x0
#define GPIO_Z_INPUT_00_0_SCR                   GPIO_Z_SCR_00_0
#define GPIO_Z_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_Z_INPUT_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_00_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_00_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Z_INPUT_00_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_00_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Z_INPUT_00_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_Z_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_Z_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_Z_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Z_INPUT_00_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_00_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_Z_OUTPUT_CONTROL_00_0
#define GPIO_Z_OUTPUT_CONTROL_00_0                      _MK_ADDR_CONST(0x1240c)
#define GPIO_Z_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_Z_OUTPUT_CONTROL_00_0_DUAL                         0x0
#define GPIO_Z_OUTPUT_CONTROL_00_0_SCR                  GPIO_Z_SCR_00_0
#define GPIO_Z_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_Z_OUTPUT_CONTROL_00_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_00_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_00_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_00_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Z_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Z_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Z_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_Z_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_Z_OUTPUT_VALUE_00_0
#define GPIO_Z_OUTPUT_VALUE_00_0                        _MK_ADDR_CONST(0x12410)
#define GPIO_Z_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_Z_OUTPUT_VALUE_00_0_DUAL                   0x0
#define GPIO_Z_OUTPUT_VALUE_00_0_SCR                    GPIO_Z_SCR_00_0
#define GPIO_Z_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_Z_OUTPUT_VALUE_00_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_00_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_00_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_00_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Z_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Z_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Z_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Z_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_Z_INTERRUPT_CLEAR_00_0
#define GPIO_Z_INTERRUPT_CLEAR_00_0                     _MK_ADDR_CONST(0x12414)
#define GPIO_Z_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_Z_INTERRUPT_CLEAR_00_0_DUAL                        0x0
#define GPIO_Z_INTERRUPT_CLEAR_00_0_SCR                         GPIO_Z_SCR_00_0
#define GPIO_Z_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_Z_INTERRUPT_CLEAR_00_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_00_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_00_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_00_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Z_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Z_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Z_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Z_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_Z_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x12418

// Reserved address 0x1241c

// Register GPIO_Z_ENABLE_CONFIG_01_0
#define GPIO_Z_ENABLE_CONFIG_01_0                       _MK_ADDR_CONST(0x12420)
#define GPIO_Z_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_Z_ENABLE_CONFIG_01_0_DUAL                  0x0
#define GPIO_Z_ENABLE_CONFIG_01_0_SCR                   GPIO_Z_SCR_01_0
#define GPIO_Z_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_Z_ENABLE_CONFIG_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Z_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_Z_ENABLE_CONFIG_01_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Z_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Z_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Z_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_Z_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_Z_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Z_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_01_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_01_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Z_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Z_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Z_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_Z_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Z_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Z_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_Z_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Z_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Z_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_Z_DEBOUNCE_THRESHOLD_01_0
#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0                  _MK_ADDR_CONST(0x12424)
#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_Z_SCR_01_0
#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_Z_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_Z_INPUT_01_0
#define GPIO_Z_INPUT_01_0                       _MK_ADDR_CONST(0x12428)
#define GPIO_Z_INPUT_01_0_SECURE                        0x0
#define GPIO_Z_INPUT_01_0_DUAL                  0x0
#define GPIO_Z_INPUT_01_0_SCR                   GPIO_Z_SCR_01_0
#define GPIO_Z_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_Z_INPUT_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_01_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_01_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Z_INPUT_01_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_01_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Z_INPUT_01_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_Z_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_Z_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_Z_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Z_INPUT_01_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_01_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_Z_OUTPUT_CONTROL_01_0
#define GPIO_Z_OUTPUT_CONTROL_01_0                      _MK_ADDR_CONST(0x1242c)
#define GPIO_Z_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_Z_OUTPUT_CONTROL_01_0_DUAL                         0x0
#define GPIO_Z_OUTPUT_CONTROL_01_0_SCR                  GPIO_Z_SCR_01_0
#define GPIO_Z_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_Z_OUTPUT_CONTROL_01_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_01_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_01_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_01_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Z_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Z_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Z_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_Z_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_Z_OUTPUT_VALUE_01_0
#define GPIO_Z_OUTPUT_VALUE_01_0                        _MK_ADDR_CONST(0x12430)
#define GPIO_Z_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_Z_OUTPUT_VALUE_01_0_DUAL                   0x0
#define GPIO_Z_OUTPUT_VALUE_01_0_SCR                    GPIO_Z_SCR_01_0
#define GPIO_Z_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_Z_OUTPUT_VALUE_01_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_01_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_01_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_01_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Z_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Z_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Z_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Z_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_Z_INTERRUPT_CLEAR_01_0
#define GPIO_Z_INTERRUPT_CLEAR_01_0                     _MK_ADDR_CONST(0x12434)
#define GPIO_Z_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_Z_INTERRUPT_CLEAR_01_0_DUAL                        0x0
#define GPIO_Z_INTERRUPT_CLEAR_01_0_SCR                         GPIO_Z_SCR_01_0
#define GPIO_Z_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_Z_INTERRUPT_CLEAR_01_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_01_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_01_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_01_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Z_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Z_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Z_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Z_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_Z_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x12438

// Reserved address 0x1243c

// Register GPIO_Z_ENABLE_CONFIG_02_0
#define GPIO_Z_ENABLE_CONFIG_02_0                       _MK_ADDR_CONST(0x12440)
#define GPIO_Z_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_Z_ENABLE_CONFIG_02_0_DUAL                  0x0
#define GPIO_Z_ENABLE_CONFIG_02_0_SCR                   GPIO_Z_SCR_02_0
#define GPIO_Z_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_Z_ENABLE_CONFIG_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Z_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_Z_ENABLE_CONFIG_02_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Z_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Z_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Z_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_Z_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_Z_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Z_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_02_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_02_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Z_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Z_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Z_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_Z_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Z_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Z_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_Z_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Z_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Z_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_Z_DEBOUNCE_THRESHOLD_02_0
#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0                  _MK_ADDR_CONST(0x12444)
#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_Z_SCR_02_0
#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_Z_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_Z_INPUT_02_0
#define GPIO_Z_INPUT_02_0                       _MK_ADDR_CONST(0x12448)
#define GPIO_Z_INPUT_02_0_SECURE                        0x0
#define GPIO_Z_INPUT_02_0_DUAL                  0x0
#define GPIO_Z_INPUT_02_0_SCR                   GPIO_Z_SCR_02_0
#define GPIO_Z_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_Z_INPUT_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_02_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_02_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Z_INPUT_02_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_02_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Z_INPUT_02_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_Z_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_Z_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_Z_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Z_INPUT_02_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_02_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_Z_OUTPUT_CONTROL_02_0
#define GPIO_Z_OUTPUT_CONTROL_02_0                      _MK_ADDR_CONST(0x1244c)
#define GPIO_Z_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_Z_OUTPUT_CONTROL_02_0_DUAL                         0x0
#define GPIO_Z_OUTPUT_CONTROL_02_0_SCR                  GPIO_Z_SCR_02_0
#define GPIO_Z_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_Z_OUTPUT_CONTROL_02_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_02_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_02_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_02_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Z_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Z_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Z_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_Z_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_Z_OUTPUT_VALUE_02_0
#define GPIO_Z_OUTPUT_VALUE_02_0                        _MK_ADDR_CONST(0x12450)
#define GPIO_Z_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_Z_OUTPUT_VALUE_02_0_DUAL                   0x0
#define GPIO_Z_OUTPUT_VALUE_02_0_SCR                    GPIO_Z_SCR_02_0
#define GPIO_Z_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_Z_OUTPUT_VALUE_02_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_02_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_02_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_02_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Z_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Z_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Z_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Z_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_Z_INTERRUPT_CLEAR_02_0
#define GPIO_Z_INTERRUPT_CLEAR_02_0                     _MK_ADDR_CONST(0x12454)
#define GPIO_Z_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_Z_INTERRUPT_CLEAR_02_0_DUAL                        0x0
#define GPIO_Z_INTERRUPT_CLEAR_02_0_SCR                         GPIO_Z_SCR_02_0
#define GPIO_Z_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_Z_INTERRUPT_CLEAR_02_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_02_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_02_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_02_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Z_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Z_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Z_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Z_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_Z_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x12458

// Reserved address 0x1245c

// Register GPIO_Z_ENABLE_CONFIG_03_0
#define GPIO_Z_ENABLE_CONFIG_03_0                       _MK_ADDR_CONST(0x12460)
#define GPIO_Z_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_Z_ENABLE_CONFIG_03_0_DUAL                  0x0
#define GPIO_Z_ENABLE_CONFIG_03_0_SCR                   GPIO_Z_SCR_03_0
#define GPIO_Z_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_Z_ENABLE_CONFIG_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Z_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_Z_ENABLE_CONFIG_03_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Z_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Z_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Z_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_Z_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_Z_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Z_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_03_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_03_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Z_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Z_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Z_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_Z_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Z_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Z_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_Z_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Z_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Z_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_Z_DEBOUNCE_THRESHOLD_03_0
#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0                  _MK_ADDR_CONST(0x12464)
#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_Z_SCR_03_0
#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_Z_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_Z_INPUT_03_0
#define GPIO_Z_INPUT_03_0                       _MK_ADDR_CONST(0x12468)
#define GPIO_Z_INPUT_03_0_SECURE                        0x0
#define GPIO_Z_INPUT_03_0_DUAL                  0x0
#define GPIO_Z_INPUT_03_0_SCR                   GPIO_Z_SCR_03_0
#define GPIO_Z_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_Z_INPUT_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_03_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_03_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Z_INPUT_03_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_03_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Z_INPUT_03_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_Z_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_Z_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_Z_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Z_INPUT_03_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_03_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_Z_OUTPUT_CONTROL_03_0
#define GPIO_Z_OUTPUT_CONTROL_03_0                      _MK_ADDR_CONST(0x1246c)
#define GPIO_Z_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_Z_OUTPUT_CONTROL_03_0_DUAL                         0x0
#define GPIO_Z_OUTPUT_CONTROL_03_0_SCR                  GPIO_Z_SCR_03_0
#define GPIO_Z_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_Z_OUTPUT_CONTROL_03_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_03_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_03_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_03_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Z_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Z_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Z_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_Z_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_Z_OUTPUT_VALUE_03_0
#define GPIO_Z_OUTPUT_VALUE_03_0                        _MK_ADDR_CONST(0x12470)
#define GPIO_Z_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_Z_OUTPUT_VALUE_03_0_DUAL                   0x0
#define GPIO_Z_OUTPUT_VALUE_03_0_SCR                    GPIO_Z_SCR_03_0
#define GPIO_Z_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_Z_OUTPUT_VALUE_03_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_03_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_03_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_03_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Z_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Z_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Z_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Z_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_Z_INTERRUPT_CLEAR_03_0
#define GPIO_Z_INTERRUPT_CLEAR_03_0                     _MK_ADDR_CONST(0x12474)
#define GPIO_Z_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_Z_INTERRUPT_CLEAR_03_0_DUAL                        0x0
#define GPIO_Z_INTERRUPT_CLEAR_03_0_SCR                         GPIO_Z_SCR_03_0
#define GPIO_Z_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_Z_INTERRUPT_CLEAR_03_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_03_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_03_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_03_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Z_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Z_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Z_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Z_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_Z_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x12478

// Reserved address 0x1247c

// Register GPIO_Z_ENABLE_CONFIG_04_0
#define GPIO_Z_ENABLE_CONFIG_04_0                       _MK_ADDR_CONST(0x12480)
#define GPIO_Z_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_Z_ENABLE_CONFIG_04_0_DUAL                  0x0
#define GPIO_Z_ENABLE_CONFIG_04_0_SCR                   GPIO_Z_SCR_04_0
#define GPIO_Z_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_Z_ENABLE_CONFIG_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Z_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_Z_ENABLE_CONFIG_04_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Z_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Z_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Z_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_Z_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_Z_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Z_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_04_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_04_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Z_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Z_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Z_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_Z_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Z_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Z_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_Z_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Z_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Z_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_Z_DEBOUNCE_THRESHOLD_04_0
#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0                  _MK_ADDR_CONST(0x12484)
#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_DUAL                     0x0
#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_Z_SCR_04_0
#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_Z_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_Z_INPUT_04_0
#define GPIO_Z_INPUT_04_0                       _MK_ADDR_CONST(0x12488)
#define GPIO_Z_INPUT_04_0_SECURE                        0x0
#define GPIO_Z_INPUT_04_0_DUAL                  0x0
#define GPIO_Z_INPUT_04_0_SCR                   GPIO_Z_SCR_04_0
#define GPIO_Z_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_Z_INPUT_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_04_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_04_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Z_INPUT_04_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_04_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Z_INPUT_04_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_Z_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_Z_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_Z_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Z_INPUT_04_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_04_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_Z_OUTPUT_CONTROL_04_0
#define GPIO_Z_OUTPUT_CONTROL_04_0                      _MK_ADDR_CONST(0x1248c)
#define GPIO_Z_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_Z_OUTPUT_CONTROL_04_0_DUAL                         0x0
#define GPIO_Z_OUTPUT_CONTROL_04_0_SCR                  GPIO_Z_SCR_04_0
#define GPIO_Z_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_Z_OUTPUT_CONTROL_04_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_04_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_04_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_04_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Z_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Z_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Z_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_Z_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_Z_OUTPUT_VALUE_04_0
#define GPIO_Z_OUTPUT_VALUE_04_0                        _MK_ADDR_CONST(0x12490)
#define GPIO_Z_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_Z_OUTPUT_VALUE_04_0_DUAL                   0x0
#define GPIO_Z_OUTPUT_VALUE_04_0_SCR                    GPIO_Z_SCR_04_0
#define GPIO_Z_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_Z_OUTPUT_VALUE_04_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_04_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_04_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_04_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Z_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Z_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Z_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Z_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_Z_INTERRUPT_CLEAR_04_0
#define GPIO_Z_INTERRUPT_CLEAR_04_0                     _MK_ADDR_CONST(0x12494)
#define GPIO_Z_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_Z_INTERRUPT_CLEAR_04_0_DUAL                        0x0
#define GPIO_Z_INTERRUPT_CLEAR_04_0_SCR                         GPIO_Z_SCR_04_0
#define GPIO_Z_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_Z_INTERRUPT_CLEAR_04_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_04_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_04_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_04_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Z_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Z_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Z_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Z_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_Z_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x12498

// Reserved address 0x1249c

// Register GPIO_Z_ENABLE_CONFIG_05_0
#define GPIO_Z_ENABLE_CONFIG_05_0                       _MK_ADDR_CONST(0x124a0)
#define GPIO_Z_ENABLE_CONFIG_05_0_SECURE                        0x0
#define GPIO_Z_ENABLE_CONFIG_05_0_DUAL                  0x0
#define GPIO_Z_ENABLE_CONFIG_05_0_SCR                   GPIO_Z_SCR_05_0
#define GPIO_Z_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
#define GPIO_Z_ENABLE_CONFIG_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Z_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_Z_ENABLE_CONFIG_05_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Z_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Z_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Z_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_Z_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
#define GPIO_Z_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Z_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_05_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_05_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Z_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Z_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Z_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_Z_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Z_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Z_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_Z_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Z_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Z_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_Z_DEBOUNCE_THRESHOLD_05_0
#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0                  _MK_ADDR_CONST(0x124a4)
#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_DUAL                     0x0
#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_Z_SCR_05_0
#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_Z_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_Z_INPUT_05_0
#define GPIO_Z_INPUT_05_0                       _MK_ADDR_CONST(0x124a8)
#define GPIO_Z_INPUT_05_0_SECURE                        0x0
#define GPIO_Z_INPUT_05_0_DUAL                  0x0
#define GPIO_Z_INPUT_05_0_SCR                   GPIO_Z_SCR_05_0
#define GPIO_Z_INPUT_05_0_WORD_COUNT                    0x1
#define GPIO_Z_INPUT_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_05_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_05_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Z_INPUT_05_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_05_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Z_INPUT_05_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_Z_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_Z_INPUT_05_0_GPIO_IN_RANGE                 0:0
#define GPIO_Z_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Z_INPUT_05_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_05_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_Z_OUTPUT_CONTROL_05_0
#define GPIO_Z_OUTPUT_CONTROL_05_0                      _MK_ADDR_CONST(0x124ac)
#define GPIO_Z_OUTPUT_CONTROL_05_0_SECURE                       0x0
#define GPIO_Z_OUTPUT_CONTROL_05_0_DUAL                         0x0
#define GPIO_Z_OUTPUT_CONTROL_05_0_SCR                  GPIO_Z_SCR_05_0
#define GPIO_Z_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
#define GPIO_Z_OUTPUT_CONTROL_05_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_05_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_05_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_05_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Z_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Z_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Z_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_Z_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_Z_OUTPUT_VALUE_05_0
#define GPIO_Z_OUTPUT_VALUE_05_0                        _MK_ADDR_CONST(0x124b0)
#define GPIO_Z_OUTPUT_VALUE_05_0_SECURE                         0x0
#define GPIO_Z_OUTPUT_VALUE_05_0_DUAL                   0x0
#define GPIO_Z_OUTPUT_VALUE_05_0_SCR                    GPIO_Z_SCR_05_0
#define GPIO_Z_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
#define GPIO_Z_OUTPUT_VALUE_05_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_05_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_05_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_05_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Z_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Z_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Z_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Z_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_Z_INTERRUPT_CLEAR_05_0
#define GPIO_Z_INTERRUPT_CLEAR_05_0                     _MK_ADDR_CONST(0x124b4)
#define GPIO_Z_INTERRUPT_CLEAR_05_0_SECURE                      0x0
#define GPIO_Z_INTERRUPT_CLEAR_05_0_DUAL                        0x0
#define GPIO_Z_INTERRUPT_CLEAR_05_0_SCR                         GPIO_Z_SCR_05_0
#define GPIO_Z_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
#define GPIO_Z_INTERRUPT_CLEAR_05_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_05_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_05_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_05_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Z_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Z_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Z_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Z_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_Z_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x124b8

// Reserved address 0x124bc

// Register GPIO_Z_ENABLE_CONFIG_06_0
#define GPIO_Z_ENABLE_CONFIG_06_0                       _MK_ADDR_CONST(0x124c0)
#define GPIO_Z_ENABLE_CONFIG_06_0_SECURE                        0x0
#define GPIO_Z_ENABLE_CONFIG_06_0_DUAL                  0x0
#define GPIO_Z_ENABLE_CONFIG_06_0_SCR                   GPIO_Z_SCR_06_0
#define GPIO_Z_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
#define GPIO_Z_ENABLE_CONFIG_06_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Z_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_Z_ENABLE_CONFIG_06_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Z_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Z_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Z_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_Z_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
#define GPIO_Z_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Z_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_06_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_06_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Z_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Z_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Z_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_Z_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Z_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Z_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_Z_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Z_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Z_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_Z_DEBOUNCE_THRESHOLD_06_0
#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0                  _MK_ADDR_CONST(0x124c4)
#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_DUAL                     0x0
#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_Z_SCR_06_0
#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_Z_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_Z_INPUT_06_0
#define GPIO_Z_INPUT_06_0                       _MK_ADDR_CONST(0x124c8)
#define GPIO_Z_INPUT_06_0_SECURE                        0x0
#define GPIO_Z_INPUT_06_0_DUAL                  0x0
#define GPIO_Z_INPUT_06_0_SCR                   GPIO_Z_SCR_06_0
#define GPIO_Z_INPUT_06_0_WORD_COUNT                    0x1
#define GPIO_Z_INPUT_06_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_06_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_06_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_06_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_06_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Z_INPUT_06_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_06_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Z_INPUT_06_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_Z_INPUT_06_0_GPIO_IN_SHIFT)
#define GPIO_Z_INPUT_06_0_GPIO_IN_RANGE                 0:0
#define GPIO_Z_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Z_INPUT_06_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_06_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_06_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_06_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_Z_OUTPUT_CONTROL_06_0
#define GPIO_Z_OUTPUT_CONTROL_06_0                      _MK_ADDR_CONST(0x124cc)
#define GPIO_Z_OUTPUT_CONTROL_06_0_SECURE                       0x0
#define GPIO_Z_OUTPUT_CONTROL_06_0_DUAL                         0x0
#define GPIO_Z_OUTPUT_CONTROL_06_0_SCR                  GPIO_Z_SCR_06_0
#define GPIO_Z_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
#define GPIO_Z_OUTPUT_CONTROL_06_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_06_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_06_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_06_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Z_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Z_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Z_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_Z_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_Z_OUTPUT_VALUE_06_0
#define GPIO_Z_OUTPUT_VALUE_06_0                        _MK_ADDR_CONST(0x124d0)
#define GPIO_Z_OUTPUT_VALUE_06_0_SECURE                         0x0
#define GPIO_Z_OUTPUT_VALUE_06_0_DUAL                   0x0
#define GPIO_Z_OUTPUT_VALUE_06_0_SCR                    GPIO_Z_SCR_06_0
#define GPIO_Z_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
#define GPIO_Z_OUTPUT_VALUE_06_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_06_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_06_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_06_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Z_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Z_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Z_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Z_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_Z_INTERRUPT_CLEAR_06_0
#define GPIO_Z_INTERRUPT_CLEAR_06_0                     _MK_ADDR_CONST(0x124d4)
#define GPIO_Z_INTERRUPT_CLEAR_06_0_SECURE                      0x0
#define GPIO_Z_INTERRUPT_CLEAR_06_0_DUAL                        0x0
#define GPIO_Z_INTERRUPT_CLEAR_06_0_SCR                         GPIO_Z_SCR_06_0
#define GPIO_Z_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
#define GPIO_Z_INTERRUPT_CLEAR_06_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_06_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_06_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_06_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Z_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Z_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Z_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Z_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_Z_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x124d8

// Reserved address 0x124dc

// Register GPIO_Z_ENABLE_CONFIG_07_0
#define GPIO_Z_ENABLE_CONFIG_07_0                       _MK_ADDR_CONST(0x124e0)
#define GPIO_Z_ENABLE_CONFIG_07_0_SECURE                        0x0
#define GPIO_Z_ENABLE_CONFIG_07_0_DUAL                  0x0
#define GPIO_Z_ENABLE_CONFIG_07_0_SCR                   GPIO_Z_SCR_07_0
#define GPIO_Z_ENABLE_CONFIG_07_0_WORD_COUNT                    0x1
#define GPIO_Z_ENABLE_CONFIG_07_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Z_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_Z_ENABLE_CONFIG_07_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Z_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Z_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Z_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_Z_ENABLE_CONFIG_07_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_07_0_IN_OUT_RANGE                  1:1
#define GPIO_Z_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Z_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_07_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_07_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Z_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Z_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Z_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_Z_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Z_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Z_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_Z_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Z_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Z_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_Z_DEBOUNCE_THRESHOLD_07_0
#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0                  _MK_ADDR_CONST(0x124e4)
#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_SECURE                   0x0
#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_DUAL                     0x0
#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_SCR                      GPIO_Z_SCR_07_0
#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                       0x1
#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_Z_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_Z_INPUT_07_0
#define GPIO_Z_INPUT_07_0                       _MK_ADDR_CONST(0x124e8)
#define GPIO_Z_INPUT_07_0_SECURE                        0x0
#define GPIO_Z_INPUT_07_0_DUAL                  0x0
#define GPIO_Z_INPUT_07_0_SCR                   GPIO_Z_SCR_07_0
#define GPIO_Z_INPUT_07_0_WORD_COUNT                    0x1
#define GPIO_Z_INPUT_07_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_07_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_07_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_07_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_07_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Z_INPUT_07_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_07_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Z_INPUT_07_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_Z_INPUT_07_0_GPIO_IN_SHIFT)
#define GPIO_Z_INPUT_07_0_GPIO_IN_RANGE                 0:0
#define GPIO_Z_INPUT_07_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Z_INPUT_07_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_07_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_07_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_07_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_07_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_Z_OUTPUT_CONTROL_07_0
#define GPIO_Z_OUTPUT_CONTROL_07_0                      _MK_ADDR_CONST(0x124ec)
#define GPIO_Z_OUTPUT_CONTROL_07_0_SECURE                       0x0
#define GPIO_Z_OUTPUT_CONTROL_07_0_DUAL                         0x0
#define GPIO_Z_OUTPUT_CONTROL_07_0_SCR                  GPIO_Z_SCR_07_0
#define GPIO_Z_OUTPUT_CONTROL_07_0_WORD_COUNT                   0x1
#define GPIO_Z_OUTPUT_CONTROL_07_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_07_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_07_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_07_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Z_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Z_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Z_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Z_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_Z_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_Z_OUTPUT_VALUE_07_0
#define GPIO_Z_OUTPUT_VALUE_07_0                        _MK_ADDR_CONST(0x124f0)
#define GPIO_Z_OUTPUT_VALUE_07_0_SECURE                         0x0
#define GPIO_Z_OUTPUT_VALUE_07_0_DUAL                   0x0
#define GPIO_Z_OUTPUT_VALUE_07_0_SCR                    GPIO_Z_SCR_07_0
#define GPIO_Z_OUTPUT_VALUE_07_0_WORD_COUNT                     0x1
#define GPIO_Z_OUTPUT_VALUE_07_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_07_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_07_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_07_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Z_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Z_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Z_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Z_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_Z_INTERRUPT_CLEAR_07_0
#define GPIO_Z_INTERRUPT_CLEAR_07_0                     _MK_ADDR_CONST(0x124f4)
#define GPIO_Z_INTERRUPT_CLEAR_07_0_SECURE                      0x0
#define GPIO_Z_INTERRUPT_CLEAR_07_0_DUAL                        0x0
#define GPIO_Z_INTERRUPT_CLEAR_07_0_SCR                         GPIO_Z_SCR_07_0
#define GPIO_Z_INTERRUPT_CLEAR_07_0_WORD_COUNT                  0x1
#define GPIO_Z_INTERRUPT_CLEAR_07_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_07_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_07_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_07_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Z_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Z_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Z_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Z_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_Z_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x124f8

// Reserved address 0x124fc

// Register GPIO_Z_INTERRUPT_STATUS_G0_0
#define GPIO_Z_INTERRUPT_STATUS_G0_0                    _MK_ADDR_CONST(0x12500)
#define GPIO_Z_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_Z_INTERRUPT_STATUS_G0_0_DUAL                       0x0
#define GPIO_Z_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_Z_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_Z_INTERRUPT_STATUS_G0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G0_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_Z_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G0_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Z_INTERRUPT_STATUS_G0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_Z_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Z_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_Z_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Z_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_Z_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_Z_INTERRUPT_STATUS_G1_0
#define GPIO_Z_INTERRUPT_STATUS_G1_0                    _MK_ADDR_CONST(0x12504)
#define GPIO_Z_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_Z_INTERRUPT_STATUS_G1_0_DUAL                       0x0
#define GPIO_Z_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_Z_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_Z_INTERRUPT_STATUS_G1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G1_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_Z_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G1_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Z_INTERRUPT_STATUS_G1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_Z_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Z_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_Z_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Z_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_Z_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_Z_INTERRUPT_STATUS_G2_0
#define GPIO_Z_INTERRUPT_STATUS_G2_0                    _MK_ADDR_CONST(0x12508)
#define GPIO_Z_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_Z_INTERRUPT_STATUS_G2_0_DUAL                       0x0
#define GPIO_Z_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_Z_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_Z_INTERRUPT_STATUS_G2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G2_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_Z_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G2_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Z_INTERRUPT_STATUS_G2_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_Z_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Z_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_Z_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Z_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_Z_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_Z_INTERRUPT_STATUS_G3_0
#define GPIO_Z_INTERRUPT_STATUS_G3_0                    _MK_ADDR_CONST(0x1250c)
#define GPIO_Z_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_Z_INTERRUPT_STATUS_G3_0_DUAL                       0x0
#define GPIO_Z_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_Z_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_Z_INTERRUPT_STATUS_G3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G3_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_Z_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G3_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Z_INTERRUPT_STATUS_G3_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_Z_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Z_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_Z_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Z_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_Z_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_Z_INTERRUPT_STATUS_G4_0
#define GPIO_Z_INTERRUPT_STATUS_G4_0                    _MK_ADDR_CONST(0x12510)
#define GPIO_Z_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_Z_INTERRUPT_STATUS_G4_0_DUAL                       0x0
#define GPIO_Z_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_Z_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_Z_INTERRUPT_STATUS_G4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G4_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_Z_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G4_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Z_INTERRUPT_STATUS_G4_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_Z_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Z_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_Z_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Z_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_Z_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_Z_INTERRUPT_STATUS_G5_0
#define GPIO_Z_INTERRUPT_STATUS_G5_0                    _MK_ADDR_CONST(0x12514)
#define GPIO_Z_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_Z_INTERRUPT_STATUS_G5_0_DUAL                       0x0
#define GPIO_Z_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_Z_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_Z_INTERRUPT_STATUS_G5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G5_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_Z_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G5_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Z_INTERRUPT_STATUS_G5_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_Z_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Z_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_Z_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Z_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_Z_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_Z_INTERRUPT_STATUS_G6_0
#define GPIO_Z_INTERRUPT_STATUS_G6_0                    _MK_ADDR_CONST(0x12518)
#define GPIO_Z_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_Z_INTERRUPT_STATUS_G6_0_DUAL                       0x0
#define GPIO_Z_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_Z_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_Z_INTERRUPT_STATUS_G6_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G6_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_Z_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G6_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Z_INTERRUPT_STATUS_G6_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_Z_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Z_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_Z_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Z_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_Z_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_Z_INTERRUPT_STATUS_G7_0
#define GPIO_Z_INTERRUPT_STATUS_G7_0                    _MK_ADDR_CONST(0x1251c)
#define GPIO_Z_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_Z_INTERRUPT_STATUS_G7_0_DUAL                       0x0
#define GPIO_Z_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_Z_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_Z_INTERRUPT_STATUS_G7_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G7_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_Z_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G7_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Z_INTERRUPT_STATUS_G7_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_Z_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Z_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_Z_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Z_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_Z_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Reserved address 0x12520

// Reserved address 0x12524

// Reserved address 0x12528

// Reserved address 0x1252c

// Reserved address 0x12530

// Reserved address 0x12534

// Reserved address 0x12538

// Reserved address 0x1253c

// Reserved address 0x12540

// Reserved address 0x12544

// Reserved address 0x12548

// Reserved address 0x1254c

// Reserved address 0x12550

// Reserved address 0x12554

// Reserved address 0x12558

// Reserved address 0x1255c

// Reserved address 0x12560

// Reserved address 0x12564

// Reserved address 0x12568

// Reserved address 0x1256c

// Reserved address 0x12570

// Reserved address 0x12574

// Reserved address 0x12578

// Reserved address 0x1257c

// Reserved address 0x12580

// Reserved address 0x12584

// Reserved address 0x12588

// Reserved address 0x1258c

// Reserved address 0x12590

// Reserved address 0x12594

// Reserved address 0x12598

// Reserved address 0x1259c

// Reserved address 0x125a0

// Reserved address 0x125a4

// Reserved address 0x125a8

// Reserved address 0x125ac

// Reserved address 0x125b0

// Reserved address 0x125b4

// Reserved address 0x125b8

// Reserved address 0x125bc

// Reserved address 0x125c0

// Reserved address 0x125c4

// Reserved address 0x125c8

// Reserved address 0x125cc

// Reserved address 0x125d0

// Reserved address 0x125d4

// Reserved address 0x125d8

// Reserved address 0x125dc

// Reserved address 0x125e0

// Reserved address 0x125e4

// Reserved address 0x125e8

// Reserved address 0x125ec

// Reserved address 0x125f0

// Reserved address 0x125f4

// Reserved address 0x125f8

// Reserved address 0x125fc

// Register GPIO_M_ENABLE_CONFIG_00_0
#define GPIO_M_ENABLE_CONFIG_00_0                       _MK_ADDR_CONST(0x12600)
#define GPIO_M_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_M_ENABLE_CONFIG_00_0_DUAL                  0x0
#define GPIO_M_ENABLE_CONFIG_00_0_SCR                   GPIO_M_SCR_00_0
#define GPIO_M_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_M_ENABLE_CONFIG_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_00_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_M_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_M_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_M_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_M_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_M_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_M_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_M_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_M_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_00_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_00_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_M_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_M_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_M_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_M_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_M_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_M_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_M_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_M_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_M_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_M_DEBOUNCE_THRESHOLD_00_0
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0                  _MK_ADDR_CONST(0x12604)
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_M_SCR_00_0
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_M_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_M_INPUT_00_0
#define GPIO_M_INPUT_00_0                       _MK_ADDR_CONST(0x12608)
#define GPIO_M_INPUT_00_0_SECURE                        0x0
#define GPIO_M_INPUT_00_0_DUAL                  0x0
#define GPIO_M_INPUT_00_0_SCR                   GPIO_M_SCR_00_0
#define GPIO_M_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_M_INPUT_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_00_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_00_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_M_INPUT_00_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_00_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_M_INPUT_00_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_M_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_M_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_M_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_M_INPUT_00_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_00_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_M_OUTPUT_CONTROL_00_0
#define GPIO_M_OUTPUT_CONTROL_00_0                      _MK_ADDR_CONST(0x1260c)
#define GPIO_M_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_M_OUTPUT_CONTROL_00_0_DUAL                         0x0
#define GPIO_M_OUTPUT_CONTROL_00_0_SCR                  GPIO_M_SCR_00_0
#define GPIO_M_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_M_OUTPUT_CONTROL_00_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_00_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_00_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_00_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_M_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_M_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_M_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_M_OUTPUT_VALUE_00_0
#define GPIO_M_OUTPUT_VALUE_00_0                        _MK_ADDR_CONST(0x12610)
#define GPIO_M_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_M_OUTPUT_VALUE_00_0_DUAL                   0x0
#define GPIO_M_OUTPUT_VALUE_00_0_SCR                    GPIO_M_SCR_00_0
#define GPIO_M_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_M_OUTPUT_VALUE_00_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_00_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_00_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_00_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_M_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_M_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_M_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_M_INTERRUPT_CLEAR_00_0
#define GPIO_M_INTERRUPT_CLEAR_00_0                     _MK_ADDR_CONST(0x12614)
#define GPIO_M_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_M_INTERRUPT_CLEAR_00_0_DUAL                        0x0
#define GPIO_M_INTERRUPT_CLEAR_00_0_SCR                         GPIO_M_SCR_00_0
#define GPIO_M_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_M_INTERRUPT_CLEAR_00_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_00_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_00_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_00_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_M_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_M_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_M_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_M_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x12618

// Reserved address 0x1261c

// Register GPIO_M_ENABLE_CONFIG_01_0
#define GPIO_M_ENABLE_CONFIG_01_0                       _MK_ADDR_CONST(0x12620)
#define GPIO_M_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_M_ENABLE_CONFIG_01_0_DUAL                  0x0
#define GPIO_M_ENABLE_CONFIG_01_0_SCR                   GPIO_M_SCR_01_0
#define GPIO_M_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_M_ENABLE_CONFIG_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_01_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_M_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_M_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_M_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_M_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_M_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_M_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_M_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_M_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_01_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_01_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_M_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_M_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_M_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_M_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_M_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_M_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_M_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_M_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_M_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_M_DEBOUNCE_THRESHOLD_01_0
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0                  _MK_ADDR_CONST(0x12624)
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_M_SCR_01_0
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_M_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_M_INPUT_01_0
#define GPIO_M_INPUT_01_0                       _MK_ADDR_CONST(0x12628)
#define GPIO_M_INPUT_01_0_SECURE                        0x0
#define GPIO_M_INPUT_01_0_DUAL                  0x0
#define GPIO_M_INPUT_01_0_SCR                   GPIO_M_SCR_01_0
#define GPIO_M_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_M_INPUT_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_01_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_01_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_M_INPUT_01_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_01_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_M_INPUT_01_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_M_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_M_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_M_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_M_INPUT_01_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_01_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_M_OUTPUT_CONTROL_01_0
#define GPIO_M_OUTPUT_CONTROL_01_0                      _MK_ADDR_CONST(0x1262c)
#define GPIO_M_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_M_OUTPUT_CONTROL_01_0_DUAL                         0x0
#define GPIO_M_OUTPUT_CONTROL_01_0_SCR                  GPIO_M_SCR_01_0
#define GPIO_M_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_M_OUTPUT_CONTROL_01_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_01_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_01_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_01_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_M_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_M_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_M_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_M_OUTPUT_VALUE_01_0
#define GPIO_M_OUTPUT_VALUE_01_0                        _MK_ADDR_CONST(0x12630)
#define GPIO_M_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_M_OUTPUT_VALUE_01_0_DUAL                   0x0
#define GPIO_M_OUTPUT_VALUE_01_0_SCR                    GPIO_M_SCR_01_0
#define GPIO_M_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_M_OUTPUT_VALUE_01_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_01_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_01_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_01_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_M_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_M_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_M_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_M_INTERRUPT_CLEAR_01_0
#define GPIO_M_INTERRUPT_CLEAR_01_0                     _MK_ADDR_CONST(0x12634)
#define GPIO_M_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_M_INTERRUPT_CLEAR_01_0_DUAL                        0x0
#define GPIO_M_INTERRUPT_CLEAR_01_0_SCR                         GPIO_M_SCR_01_0
#define GPIO_M_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_M_INTERRUPT_CLEAR_01_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_01_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_01_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_01_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_M_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_M_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_M_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_M_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x12638

// Reserved address 0x1263c

// Register GPIO_M_ENABLE_CONFIG_02_0
#define GPIO_M_ENABLE_CONFIG_02_0                       _MK_ADDR_CONST(0x12640)
#define GPIO_M_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_M_ENABLE_CONFIG_02_0_DUAL                  0x0
#define GPIO_M_ENABLE_CONFIG_02_0_SCR                   GPIO_M_SCR_02_0
#define GPIO_M_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_M_ENABLE_CONFIG_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_02_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_M_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_M_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_M_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_M_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_M_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_M_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_M_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_M_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_02_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_02_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_M_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_M_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_M_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_M_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_M_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_M_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_M_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_M_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_M_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_M_DEBOUNCE_THRESHOLD_02_0
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0                  _MK_ADDR_CONST(0x12644)
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_M_SCR_02_0
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_M_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_M_INPUT_02_0
#define GPIO_M_INPUT_02_0                       _MK_ADDR_CONST(0x12648)
#define GPIO_M_INPUT_02_0_SECURE                        0x0
#define GPIO_M_INPUT_02_0_DUAL                  0x0
#define GPIO_M_INPUT_02_0_SCR                   GPIO_M_SCR_02_0
#define GPIO_M_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_M_INPUT_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_02_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_02_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_M_INPUT_02_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_02_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_M_INPUT_02_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_M_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_M_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_M_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_M_INPUT_02_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_02_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_M_OUTPUT_CONTROL_02_0
#define GPIO_M_OUTPUT_CONTROL_02_0                      _MK_ADDR_CONST(0x1264c)
#define GPIO_M_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_M_OUTPUT_CONTROL_02_0_DUAL                         0x0
#define GPIO_M_OUTPUT_CONTROL_02_0_SCR                  GPIO_M_SCR_02_0
#define GPIO_M_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_M_OUTPUT_CONTROL_02_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_02_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_02_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_02_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_M_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_M_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_M_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_M_OUTPUT_VALUE_02_0
#define GPIO_M_OUTPUT_VALUE_02_0                        _MK_ADDR_CONST(0x12650)
#define GPIO_M_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_M_OUTPUT_VALUE_02_0_DUAL                   0x0
#define GPIO_M_OUTPUT_VALUE_02_0_SCR                    GPIO_M_SCR_02_0
#define GPIO_M_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_M_OUTPUT_VALUE_02_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_02_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_02_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_02_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_M_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_M_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_M_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_M_INTERRUPT_CLEAR_02_0
#define GPIO_M_INTERRUPT_CLEAR_02_0                     _MK_ADDR_CONST(0x12654)
#define GPIO_M_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_M_INTERRUPT_CLEAR_02_0_DUAL                        0x0
#define GPIO_M_INTERRUPT_CLEAR_02_0_SCR                         GPIO_M_SCR_02_0
#define GPIO_M_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_M_INTERRUPT_CLEAR_02_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_02_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_02_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_02_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_M_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_M_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_M_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_M_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x12658

// Reserved address 0x1265c

// Register GPIO_M_ENABLE_CONFIG_03_0
#define GPIO_M_ENABLE_CONFIG_03_0                       _MK_ADDR_CONST(0x12660)
#define GPIO_M_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_M_ENABLE_CONFIG_03_0_DUAL                  0x0
#define GPIO_M_ENABLE_CONFIG_03_0_SCR                   GPIO_M_SCR_03_0
#define GPIO_M_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_M_ENABLE_CONFIG_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_03_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_M_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_M_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_M_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_M_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_M_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_M_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_M_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_M_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_03_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_03_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_M_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_M_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_M_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_M_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_M_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_M_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_M_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_M_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_M_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_M_DEBOUNCE_THRESHOLD_03_0
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0                  _MK_ADDR_CONST(0x12664)
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_M_SCR_03_0
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_M_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_M_INPUT_03_0
#define GPIO_M_INPUT_03_0                       _MK_ADDR_CONST(0x12668)
#define GPIO_M_INPUT_03_0_SECURE                        0x0
#define GPIO_M_INPUT_03_0_DUAL                  0x0
#define GPIO_M_INPUT_03_0_SCR                   GPIO_M_SCR_03_0
#define GPIO_M_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_M_INPUT_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_03_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_03_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_M_INPUT_03_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_03_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_M_INPUT_03_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_M_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_M_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_M_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_M_INPUT_03_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_03_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_M_OUTPUT_CONTROL_03_0
#define GPIO_M_OUTPUT_CONTROL_03_0                      _MK_ADDR_CONST(0x1266c)
#define GPIO_M_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_M_OUTPUT_CONTROL_03_0_DUAL                         0x0
#define GPIO_M_OUTPUT_CONTROL_03_0_SCR                  GPIO_M_SCR_03_0
#define GPIO_M_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_M_OUTPUT_CONTROL_03_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_03_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_03_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_03_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_M_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_M_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_M_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_M_OUTPUT_VALUE_03_0
#define GPIO_M_OUTPUT_VALUE_03_0                        _MK_ADDR_CONST(0x12670)
#define GPIO_M_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_M_OUTPUT_VALUE_03_0_DUAL                   0x0
#define GPIO_M_OUTPUT_VALUE_03_0_SCR                    GPIO_M_SCR_03_0
#define GPIO_M_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_M_OUTPUT_VALUE_03_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_03_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_03_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_03_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_M_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_M_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_M_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_M_INTERRUPT_CLEAR_03_0
#define GPIO_M_INTERRUPT_CLEAR_03_0                     _MK_ADDR_CONST(0x12674)
#define GPIO_M_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_M_INTERRUPT_CLEAR_03_0_DUAL                        0x0
#define GPIO_M_INTERRUPT_CLEAR_03_0_SCR                         GPIO_M_SCR_03_0
#define GPIO_M_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_M_INTERRUPT_CLEAR_03_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_03_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_03_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_03_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_M_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_M_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_M_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_M_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x12678

// Reserved address 0x1267c

// Register GPIO_M_ENABLE_CONFIG_04_0
#define GPIO_M_ENABLE_CONFIG_04_0                       _MK_ADDR_CONST(0x12680)
#define GPIO_M_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_M_ENABLE_CONFIG_04_0_DUAL                  0x0
#define GPIO_M_ENABLE_CONFIG_04_0_SCR                   GPIO_M_SCR_04_0
#define GPIO_M_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_M_ENABLE_CONFIG_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_04_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_M_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_M_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_M_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_M_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_M_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_M_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_M_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_M_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_04_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_04_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_M_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_M_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_M_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_M_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_M_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_M_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_M_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_M_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_M_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_M_DEBOUNCE_THRESHOLD_04_0
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0                  _MK_ADDR_CONST(0x12684)
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_DUAL                     0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_M_SCR_04_0
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_M_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_M_INPUT_04_0
#define GPIO_M_INPUT_04_0                       _MK_ADDR_CONST(0x12688)
#define GPIO_M_INPUT_04_0_SECURE                        0x0
#define GPIO_M_INPUT_04_0_DUAL                  0x0
#define GPIO_M_INPUT_04_0_SCR                   GPIO_M_SCR_04_0
#define GPIO_M_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_M_INPUT_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_04_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_04_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_M_INPUT_04_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_04_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_M_INPUT_04_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_M_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_M_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_M_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_M_INPUT_04_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_04_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_M_OUTPUT_CONTROL_04_0
#define GPIO_M_OUTPUT_CONTROL_04_0                      _MK_ADDR_CONST(0x1268c)
#define GPIO_M_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_M_OUTPUT_CONTROL_04_0_DUAL                         0x0
#define GPIO_M_OUTPUT_CONTROL_04_0_SCR                  GPIO_M_SCR_04_0
#define GPIO_M_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_M_OUTPUT_CONTROL_04_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_04_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_04_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_04_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_M_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_M_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_M_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_M_OUTPUT_VALUE_04_0
#define GPIO_M_OUTPUT_VALUE_04_0                        _MK_ADDR_CONST(0x12690)
#define GPIO_M_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_M_OUTPUT_VALUE_04_0_DUAL                   0x0
#define GPIO_M_OUTPUT_VALUE_04_0_SCR                    GPIO_M_SCR_04_0
#define GPIO_M_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_M_OUTPUT_VALUE_04_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_04_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_04_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_04_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_M_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_M_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_M_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_M_INTERRUPT_CLEAR_04_0
#define GPIO_M_INTERRUPT_CLEAR_04_0                     _MK_ADDR_CONST(0x12694)
#define GPIO_M_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_M_INTERRUPT_CLEAR_04_0_DUAL                        0x0
#define GPIO_M_INTERRUPT_CLEAR_04_0_SCR                         GPIO_M_SCR_04_0
#define GPIO_M_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_M_INTERRUPT_CLEAR_04_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_04_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_04_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_04_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_M_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_M_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_M_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_M_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x12698

// Reserved address 0x1269c

// Register GPIO_M_ENABLE_CONFIG_05_0
#define GPIO_M_ENABLE_CONFIG_05_0                       _MK_ADDR_CONST(0x126a0)
#define GPIO_M_ENABLE_CONFIG_05_0_SECURE                        0x0
#define GPIO_M_ENABLE_CONFIG_05_0_DUAL                  0x0
#define GPIO_M_ENABLE_CONFIG_05_0_SCR                   GPIO_M_SCR_05_0
#define GPIO_M_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
#define GPIO_M_ENABLE_CONFIG_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_05_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_M_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_M_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_M_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_M_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_M_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_M_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
#define GPIO_M_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
#define GPIO_M_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_05_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_05_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_M_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_M_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_M_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_M_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_M_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_M_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_M_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_M_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_M_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_M_DEBOUNCE_THRESHOLD_05_0
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0                  _MK_ADDR_CONST(0x126a4)
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_DUAL                     0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_M_SCR_05_0
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_M_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_M_INPUT_05_0
#define GPIO_M_INPUT_05_0                       _MK_ADDR_CONST(0x126a8)
#define GPIO_M_INPUT_05_0_SECURE                        0x0
#define GPIO_M_INPUT_05_0_DUAL                  0x0
#define GPIO_M_INPUT_05_0_SCR                   GPIO_M_SCR_05_0
#define GPIO_M_INPUT_05_0_WORD_COUNT                    0x1
#define GPIO_M_INPUT_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_05_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_05_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_M_INPUT_05_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_05_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_M_INPUT_05_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_M_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_M_INPUT_05_0_GPIO_IN_RANGE                 0:0
#define GPIO_M_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_M_INPUT_05_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_05_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_M_OUTPUT_CONTROL_05_0
#define GPIO_M_OUTPUT_CONTROL_05_0                      _MK_ADDR_CONST(0x126ac)
#define GPIO_M_OUTPUT_CONTROL_05_0_SECURE                       0x0
#define GPIO_M_OUTPUT_CONTROL_05_0_DUAL                         0x0
#define GPIO_M_OUTPUT_CONTROL_05_0_SCR                  GPIO_M_SCR_05_0
#define GPIO_M_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
#define GPIO_M_OUTPUT_CONTROL_05_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_05_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_05_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_05_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_M_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_M_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_M_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_M_OUTPUT_VALUE_05_0
#define GPIO_M_OUTPUT_VALUE_05_0                        _MK_ADDR_CONST(0x126b0)
#define GPIO_M_OUTPUT_VALUE_05_0_SECURE                         0x0
#define GPIO_M_OUTPUT_VALUE_05_0_DUAL                   0x0
#define GPIO_M_OUTPUT_VALUE_05_0_SCR                    GPIO_M_SCR_05_0
#define GPIO_M_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
#define GPIO_M_OUTPUT_VALUE_05_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_05_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_05_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_05_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_M_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_M_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_M_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_M_INTERRUPT_CLEAR_05_0
#define GPIO_M_INTERRUPT_CLEAR_05_0                     _MK_ADDR_CONST(0x126b4)
#define GPIO_M_INTERRUPT_CLEAR_05_0_SECURE                      0x0
#define GPIO_M_INTERRUPT_CLEAR_05_0_DUAL                        0x0
#define GPIO_M_INTERRUPT_CLEAR_05_0_SCR                         GPIO_M_SCR_05_0
#define GPIO_M_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
#define GPIO_M_INTERRUPT_CLEAR_05_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_05_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_05_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_05_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_M_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_M_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_M_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_M_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x126b8

// Reserved address 0x126bc

// Register GPIO_M_ENABLE_CONFIG_06_0
#define GPIO_M_ENABLE_CONFIG_06_0                       _MK_ADDR_CONST(0x126c0)
#define GPIO_M_ENABLE_CONFIG_06_0_SECURE                        0x0
#define GPIO_M_ENABLE_CONFIG_06_0_DUAL                  0x0
#define GPIO_M_ENABLE_CONFIG_06_0_SCR                   GPIO_M_SCR_06_0
#define GPIO_M_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
#define GPIO_M_ENABLE_CONFIG_06_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_06_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_M_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
#define GPIO_M_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_M_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_M_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_M_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
#define GPIO_M_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
#define GPIO_M_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
#define GPIO_M_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_06_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_06_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_M_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_M_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_M_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_M_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_M_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_M_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_M_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_M_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_M_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_M_DEBOUNCE_THRESHOLD_06_0
#define GPIO_M_DEBOUNCE_THRESHOLD_06_0                  _MK_ADDR_CONST(0x126c4)
#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_DUAL                     0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_M_SCR_06_0
#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_M_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_M_INPUT_06_0
#define GPIO_M_INPUT_06_0                       _MK_ADDR_CONST(0x126c8)
#define GPIO_M_INPUT_06_0_SECURE                        0x0
#define GPIO_M_INPUT_06_0_DUAL                  0x0
#define GPIO_M_INPUT_06_0_SCR                   GPIO_M_SCR_06_0
#define GPIO_M_INPUT_06_0_WORD_COUNT                    0x1
#define GPIO_M_INPUT_06_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_06_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_06_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_06_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_06_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_M_INPUT_06_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_06_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_M_INPUT_06_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_M_INPUT_06_0_GPIO_IN_SHIFT)
#define GPIO_M_INPUT_06_0_GPIO_IN_RANGE                 0:0
#define GPIO_M_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_M_INPUT_06_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_06_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_06_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_06_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_M_OUTPUT_CONTROL_06_0
#define GPIO_M_OUTPUT_CONTROL_06_0                      _MK_ADDR_CONST(0x126cc)
#define GPIO_M_OUTPUT_CONTROL_06_0_SECURE                       0x0
#define GPIO_M_OUTPUT_CONTROL_06_0_DUAL                         0x0
#define GPIO_M_OUTPUT_CONTROL_06_0_SCR                  GPIO_M_SCR_06_0
#define GPIO_M_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
#define GPIO_M_OUTPUT_CONTROL_06_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_06_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_06_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_06_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_M_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_M_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_M_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_M_OUTPUT_VALUE_06_0
#define GPIO_M_OUTPUT_VALUE_06_0                        _MK_ADDR_CONST(0x126d0)
#define GPIO_M_OUTPUT_VALUE_06_0_SECURE                         0x0
#define GPIO_M_OUTPUT_VALUE_06_0_DUAL                   0x0
#define GPIO_M_OUTPUT_VALUE_06_0_SCR                    GPIO_M_SCR_06_0
#define GPIO_M_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
#define GPIO_M_OUTPUT_VALUE_06_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_06_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_06_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_06_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_M_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_M_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_M_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_M_INTERRUPT_CLEAR_06_0
#define GPIO_M_INTERRUPT_CLEAR_06_0                     _MK_ADDR_CONST(0x126d4)
#define GPIO_M_INTERRUPT_CLEAR_06_0_SECURE                      0x0
#define GPIO_M_INTERRUPT_CLEAR_06_0_DUAL                        0x0
#define GPIO_M_INTERRUPT_CLEAR_06_0_SCR                         GPIO_M_SCR_06_0
#define GPIO_M_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
#define GPIO_M_INTERRUPT_CLEAR_06_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_06_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_06_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_06_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_M_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_M_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_M_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_M_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x126d8

// Reserved address 0x126dc

// Register GPIO_M_ENABLE_CONFIG_07_0
#define GPIO_M_ENABLE_CONFIG_07_0                       _MK_ADDR_CONST(0x126e0)
#define GPIO_M_ENABLE_CONFIG_07_0_SECURE                        0x0
#define GPIO_M_ENABLE_CONFIG_07_0_DUAL                  0x0
#define GPIO_M_ENABLE_CONFIG_07_0_SCR                   GPIO_M_SCR_07_0
#define GPIO_M_ENABLE_CONFIG_07_0_WORD_COUNT                    0x1
#define GPIO_M_ENABLE_CONFIG_07_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_07_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_M_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
#define GPIO_M_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_M_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_M_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_M_ENABLE_CONFIG_07_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
#define GPIO_M_ENABLE_CONFIG_07_0_IN_OUT_RANGE                  1:1
#define GPIO_M_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                        0x0
#define GPIO_M_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_07_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_07_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_M_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_M_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_M_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_M_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_M_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_M_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_M_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_M_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_M_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_M_DEBOUNCE_THRESHOLD_07_0
#define GPIO_M_DEBOUNCE_THRESHOLD_07_0                  _MK_ADDR_CONST(0x126e4)
#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_SECURE                   0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_DUAL                     0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_SCR                      GPIO_M_SCR_07_0
#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                       0x1
#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_M_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_M_INPUT_07_0
#define GPIO_M_INPUT_07_0                       _MK_ADDR_CONST(0x126e8)
#define GPIO_M_INPUT_07_0_SECURE                        0x0
#define GPIO_M_INPUT_07_0_DUAL                  0x0
#define GPIO_M_INPUT_07_0_SCR                   GPIO_M_SCR_07_0
#define GPIO_M_INPUT_07_0_WORD_COUNT                    0x1
#define GPIO_M_INPUT_07_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_07_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_07_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_07_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_07_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_M_INPUT_07_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_07_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_M_INPUT_07_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_M_INPUT_07_0_GPIO_IN_SHIFT)
#define GPIO_M_INPUT_07_0_GPIO_IN_RANGE                 0:0
#define GPIO_M_INPUT_07_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_M_INPUT_07_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_07_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_07_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_07_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_07_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_M_OUTPUT_CONTROL_07_0
#define GPIO_M_OUTPUT_CONTROL_07_0                      _MK_ADDR_CONST(0x126ec)
#define GPIO_M_OUTPUT_CONTROL_07_0_SECURE                       0x0
#define GPIO_M_OUTPUT_CONTROL_07_0_DUAL                         0x0
#define GPIO_M_OUTPUT_CONTROL_07_0_SCR                  GPIO_M_SCR_07_0
#define GPIO_M_OUTPUT_CONTROL_07_0_WORD_COUNT                   0x1
#define GPIO_M_OUTPUT_CONTROL_07_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_07_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_07_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_07_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_M_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_M_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_M_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_M_OUTPUT_VALUE_07_0
#define GPIO_M_OUTPUT_VALUE_07_0                        _MK_ADDR_CONST(0x126f0)
#define GPIO_M_OUTPUT_VALUE_07_0_SECURE                         0x0
#define GPIO_M_OUTPUT_VALUE_07_0_DUAL                   0x0
#define GPIO_M_OUTPUT_VALUE_07_0_SCR                    GPIO_M_SCR_07_0
#define GPIO_M_OUTPUT_VALUE_07_0_WORD_COUNT                     0x1
#define GPIO_M_OUTPUT_VALUE_07_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_07_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_07_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_07_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_M_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_M_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_M_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_M_INTERRUPT_CLEAR_07_0
#define GPIO_M_INTERRUPT_CLEAR_07_0                     _MK_ADDR_CONST(0x126f4)
#define GPIO_M_INTERRUPT_CLEAR_07_0_SECURE                      0x0
#define GPIO_M_INTERRUPT_CLEAR_07_0_DUAL                        0x0
#define GPIO_M_INTERRUPT_CLEAR_07_0_SCR                         GPIO_M_SCR_07_0
#define GPIO_M_INTERRUPT_CLEAR_07_0_WORD_COUNT                  0x1
#define GPIO_M_INTERRUPT_CLEAR_07_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_07_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_07_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_07_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_M_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_M_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_M_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_M_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x126f8

// Reserved address 0x126fc

// Register GPIO_M_INTERRUPT_STATUS_G0_0
#define GPIO_M_INTERRUPT_STATUS_G0_0                    _MK_ADDR_CONST(0x12700)
#define GPIO_M_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_M_INTERRUPT_STATUS_G0_0_DUAL                       0x0
#define GPIO_M_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_M_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_M_INTERRUPT_STATUS_G0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G0_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_M_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G0_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_M_INTERRUPT_STATUS_G0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_M_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_M_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_M_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_M_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_M_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_M_INTERRUPT_STATUS_G1_0
#define GPIO_M_INTERRUPT_STATUS_G1_0                    _MK_ADDR_CONST(0x12704)
#define GPIO_M_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_M_INTERRUPT_STATUS_G1_0_DUAL                       0x0
#define GPIO_M_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_M_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_M_INTERRUPT_STATUS_G1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G1_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_M_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G1_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_M_INTERRUPT_STATUS_G1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_M_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_M_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_M_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_M_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_M_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_M_INTERRUPT_STATUS_G2_0
#define GPIO_M_INTERRUPT_STATUS_G2_0                    _MK_ADDR_CONST(0x12708)
#define GPIO_M_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_M_INTERRUPT_STATUS_G2_0_DUAL                       0x0
#define GPIO_M_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_M_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_M_INTERRUPT_STATUS_G2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G2_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_M_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G2_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_M_INTERRUPT_STATUS_G2_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_M_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_M_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_M_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_M_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_M_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_M_INTERRUPT_STATUS_G3_0
#define GPIO_M_INTERRUPT_STATUS_G3_0                    _MK_ADDR_CONST(0x1270c)
#define GPIO_M_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_M_INTERRUPT_STATUS_G3_0_DUAL                       0x0
#define GPIO_M_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_M_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_M_INTERRUPT_STATUS_G3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G3_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_M_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G3_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_M_INTERRUPT_STATUS_G3_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_M_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_M_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_M_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_M_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_M_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_M_INTERRUPT_STATUS_G4_0
#define GPIO_M_INTERRUPT_STATUS_G4_0                    _MK_ADDR_CONST(0x12710)
#define GPIO_M_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_M_INTERRUPT_STATUS_G4_0_DUAL                       0x0
#define GPIO_M_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_M_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_M_INTERRUPT_STATUS_G4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G4_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_M_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G4_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_M_INTERRUPT_STATUS_G4_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_M_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_M_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_M_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_M_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_M_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_M_INTERRUPT_STATUS_G5_0
#define GPIO_M_INTERRUPT_STATUS_G5_0                    _MK_ADDR_CONST(0x12714)
#define GPIO_M_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_M_INTERRUPT_STATUS_G5_0_DUAL                       0x0
#define GPIO_M_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_M_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_M_INTERRUPT_STATUS_G5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G5_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_M_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G5_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_M_INTERRUPT_STATUS_G5_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_M_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_M_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_M_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_M_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_M_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_M_INTERRUPT_STATUS_G6_0
#define GPIO_M_INTERRUPT_STATUS_G6_0                    _MK_ADDR_CONST(0x12718)
#define GPIO_M_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_M_INTERRUPT_STATUS_G6_0_DUAL                       0x0
#define GPIO_M_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_M_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_M_INTERRUPT_STATUS_G6_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G6_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_M_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G6_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_M_INTERRUPT_STATUS_G6_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_M_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_M_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_M_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_M_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_M_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_M_INTERRUPT_STATUS_G7_0
#define GPIO_M_INTERRUPT_STATUS_G7_0                    _MK_ADDR_CONST(0x1271c)
#define GPIO_M_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_M_INTERRUPT_STATUS_G7_0_DUAL                       0x0
#define GPIO_M_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_M_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_M_INTERRUPT_STATUS_G7_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G7_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_M_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G7_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_M_INTERRUPT_STATUS_G7_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_M_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_M_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_M_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_M_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_M_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Reserved address 0x12720

// Reserved address 0x12724

// Reserved address 0x12728

// Reserved address 0x1272c

// Reserved address 0x12730

// Reserved address 0x12734

// Reserved address 0x12738

// Reserved address 0x1273c

// Reserved address 0x12740

// Reserved address 0x12744

// Reserved address 0x12748

// Reserved address 0x1274c

// Reserved address 0x12750

// Reserved address 0x12754

// Reserved address 0x12758

// Reserved address 0x1275c

// Reserved address 0x12760

// Reserved address 0x12764

// Reserved address 0x12768

// Reserved address 0x1276c

// Reserved address 0x12770

// Reserved address 0x12774

// Reserved address 0x12778

// Reserved address 0x1277c

// Reserved address 0x12780

// Reserved address 0x12784

// Reserved address 0x12788

// Reserved address 0x1278c

// Reserved address 0x12790

// Reserved address 0x12794

// Reserved address 0x12798

// Reserved address 0x1279c

// Reserved address 0x127a0

// Reserved address 0x127a4

// Reserved address 0x127a8

// Reserved address 0x127ac

// Reserved address 0x127b0

// Reserved address 0x127b4

// Reserved address 0x127b8

// Reserved address 0x127bc

// Reserved address 0x127c0

// Reserved address 0x127c4

// Reserved address 0x127c8

// Reserved address 0x127cc

// Reserved address 0x127d0

// Reserved address 0x127d4

// Reserved address 0x127d8

// Reserved address 0x127dc

// Reserved address 0x127e0

// Reserved address 0x127e4

// Reserved address 0x127e8

// Reserved address 0x127ec

// Reserved address 0x127f0

// Reserved address 0x127f4

// Reserved address 0x127f8

// Reserved address 0x127fc

// Register GPIO_N_ENABLE_CONFIG_00_0
#define GPIO_N_ENABLE_CONFIG_00_0                       _MK_ADDR_CONST(0x12800)
#define GPIO_N_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_N_ENABLE_CONFIG_00_0_DUAL                  0x0
#define GPIO_N_ENABLE_CONFIG_00_0_SCR                   GPIO_N_SCR_00_0
#define GPIO_N_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_N_ENABLE_CONFIG_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_N_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_N_ENABLE_CONFIG_00_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_N_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_N_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_N_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_N_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_N_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_N_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_N_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_N_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_N_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_00_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_00_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_N_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_N_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_N_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_N_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_N_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_N_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_N_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_N_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_N_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_N_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_N_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_N_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_N_DEBOUNCE_THRESHOLD_00_0
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0                  _MK_ADDR_CONST(0x12804)
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_N_SCR_00_0
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_N_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_N_INPUT_00_0
#define GPIO_N_INPUT_00_0                       _MK_ADDR_CONST(0x12808)
#define GPIO_N_INPUT_00_0_SECURE                        0x0
#define GPIO_N_INPUT_00_0_DUAL                  0x0
#define GPIO_N_INPUT_00_0_SCR                   GPIO_N_SCR_00_0
#define GPIO_N_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_N_INPUT_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_00_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_00_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_N_INPUT_00_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_00_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_N_INPUT_00_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_N_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_N_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_N_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_N_INPUT_00_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_00_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_N_OUTPUT_CONTROL_00_0
#define GPIO_N_OUTPUT_CONTROL_00_0                      _MK_ADDR_CONST(0x1280c)
#define GPIO_N_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_N_OUTPUT_CONTROL_00_0_DUAL                         0x0
#define GPIO_N_OUTPUT_CONTROL_00_0_SCR                  GPIO_N_SCR_00_0
#define GPIO_N_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_N_OUTPUT_CONTROL_00_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_00_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_00_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_00_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_N_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_N_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_N_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_N_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_N_OUTPUT_VALUE_00_0
#define GPIO_N_OUTPUT_VALUE_00_0                        _MK_ADDR_CONST(0x12810)
#define GPIO_N_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_N_OUTPUT_VALUE_00_0_DUAL                   0x0
#define GPIO_N_OUTPUT_VALUE_00_0_SCR                    GPIO_N_SCR_00_0
#define GPIO_N_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_N_OUTPUT_VALUE_00_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_00_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_00_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_00_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_N_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_N_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_N_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_N_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_N_INTERRUPT_CLEAR_00_0
#define GPIO_N_INTERRUPT_CLEAR_00_0                     _MK_ADDR_CONST(0x12814)
#define GPIO_N_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_N_INTERRUPT_CLEAR_00_0_DUAL                        0x0
#define GPIO_N_INTERRUPT_CLEAR_00_0_SCR                         GPIO_N_SCR_00_0
#define GPIO_N_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_N_INTERRUPT_CLEAR_00_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_00_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_00_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_00_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_N_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_N_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_N_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_N_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_N_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x12818

// Reserved address 0x1281c

// Register GPIO_N_ENABLE_CONFIG_01_0
#define GPIO_N_ENABLE_CONFIG_01_0                       _MK_ADDR_CONST(0x12820)
#define GPIO_N_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_N_ENABLE_CONFIG_01_0_DUAL                  0x0
#define GPIO_N_ENABLE_CONFIG_01_0_SCR                   GPIO_N_SCR_01_0
#define GPIO_N_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_N_ENABLE_CONFIG_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_N_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_N_ENABLE_CONFIG_01_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_N_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_N_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_N_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_N_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_N_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_N_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_N_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_N_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_N_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_01_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_01_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_N_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_N_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_N_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_N_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_N_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_N_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_N_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_N_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_N_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_N_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_N_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_N_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_N_DEBOUNCE_THRESHOLD_01_0
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0                  _MK_ADDR_CONST(0x12824)
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_N_SCR_01_0
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_N_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_N_INPUT_01_0
#define GPIO_N_INPUT_01_0                       _MK_ADDR_CONST(0x12828)
#define GPIO_N_INPUT_01_0_SECURE                        0x0
#define GPIO_N_INPUT_01_0_DUAL                  0x0
#define GPIO_N_INPUT_01_0_SCR                   GPIO_N_SCR_01_0
#define GPIO_N_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_N_INPUT_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_01_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_01_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_N_INPUT_01_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_01_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_N_INPUT_01_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_N_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_N_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_N_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_N_INPUT_01_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_01_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_N_OUTPUT_CONTROL_01_0
#define GPIO_N_OUTPUT_CONTROL_01_0                      _MK_ADDR_CONST(0x1282c)
#define GPIO_N_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_N_OUTPUT_CONTROL_01_0_DUAL                         0x0
#define GPIO_N_OUTPUT_CONTROL_01_0_SCR                  GPIO_N_SCR_01_0
#define GPIO_N_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_N_OUTPUT_CONTROL_01_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_01_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_01_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_01_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_N_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_N_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_N_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_N_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_N_OUTPUT_VALUE_01_0
#define GPIO_N_OUTPUT_VALUE_01_0                        _MK_ADDR_CONST(0x12830)
#define GPIO_N_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_N_OUTPUT_VALUE_01_0_DUAL                   0x0
#define GPIO_N_OUTPUT_VALUE_01_0_SCR                    GPIO_N_SCR_01_0
#define GPIO_N_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_N_OUTPUT_VALUE_01_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_01_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_01_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_01_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_N_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_N_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_N_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_N_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_N_INTERRUPT_CLEAR_01_0
#define GPIO_N_INTERRUPT_CLEAR_01_0                     _MK_ADDR_CONST(0x12834)
#define GPIO_N_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_N_INTERRUPT_CLEAR_01_0_DUAL                        0x0
#define GPIO_N_INTERRUPT_CLEAR_01_0_SCR                         GPIO_N_SCR_01_0
#define GPIO_N_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_N_INTERRUPT_CLEAR_01_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_01_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_01_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_01_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_N_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_N_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_N_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_N_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_N_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x12838

// Reserved address 0x1283c

// Register GPIO_N_ENABLE_CONFIG_02_0
#define GPIO_N_ENABLE_CONFIG_02_0                       _MK_ADDR_CONST(0x12840)
#define GPIO_N_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_N_ENABLE_CONFIG_02_0_DUAL                  0x0
#define GPIO_N_ENABLE_CONFIG_02_0_SCR                   GPIO_N_SCR_02_0
#define GPIO_N_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_N_ENABLE_CONFIG_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_N_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_N_ENABLE_CONFIG_02_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_N_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_N_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_N_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_N_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_N_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_N_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_N_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_N_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_N_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_02_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_02_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_N_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_N_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_N_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_N_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_N_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_N_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_N_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_N_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_N_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_N_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_N_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_N_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_N_DEBOUNCE_THRESHOLD_02_0
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0                  _MK_ADDR_CONST(0x12844)
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_N_SCR_02_0
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_N_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_N_INPUT_02_0
#define GPIO_N_INPUT_02_0                       _MK_ADDR_CONST(0x12848)
#define GPIO_N_INPUT_02_0_SECURE                        0x0
#define GPIO_N_INPUT_02_0_DUAL                  0x0
#define GPIO_N_INPUT_02_0_SCR                   GPIO_N_SCR_02_0
#define GPIO_N_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_N_INPUT_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_02_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_02_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_N_INPUT_02_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_02_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_N_INPUT_02_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_N_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_N_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_N_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_N_INPUT_02_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_02_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_N_OUTPUT_CONTROL_02_0
#define GPIO_N_OUTPUT_CONTROL_02_0                      _MK_ADDR_CONST(0x1284c)
#define GPIO_N_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_N_OUTPUT_CONTROL_02_0_DUAL                         0x0
#define GPIO_N_OUTPUT_CONTROL_02_0_SCR                  GPIO_N_SCR_02_0
#define GPIO_N_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_N_OUTPUT_CONTROL_02_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_02_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_02_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_02_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_N_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_N_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_N_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_N_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_N_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_N_OUTPUT_VALUE_02_0
#define GPIO_N_OUTPUT_VALUE_02_0                        _MK_ADDR_CONST(0x12850)
#define GPIO_N_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_N_OUTPUT_VALUE_02_0_DUAL                   0x0
#define GPIO_N_OUTPUT_VALUE_02_0_SCR                    GPIO_N_SCR_02_0
#define GPIO_N_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_N_OUTPUT_VALUE_02_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_02_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_02_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_02_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_N_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_N_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_N_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_N_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_N_INTERRUPT_CLEAR_02_0
#define GPIO_N_INTERRUPT_CLEAR_02_0                     _MK_ADDR_CONST(0x12854)
#define GPIO_N_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_N_INTERRUPT_CLEAR_02_0_DUAL                        0x0
#define GPIO_N_INTERRUPT_CLEAR_02_0_SCR                         GPIO_N_SCR_02_0
#define GPIO_N_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_N_INTERRUPT_CLEAR_02_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_02_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_02_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_02_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_N_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_N_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_N_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_N_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_N_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x12858

// Reserved address 0x1285c

// Reserved address 0x12860

// Reserved address 0x12864

// Reserved address 0x12868

// Reserved address 0x1286c

// Reserved address 0x12870

// Reserved address 0x12874

// Reserved address 0x12878

// Reserved address 0x1287c

// Reserved address 0x12880

// Reserved address 0x12884

// Reserved address 0x12888

// Reserved address 0x1288c

// Reserved address 0x12890

// Reserved address 0x12894

// Reserved address 0x12898

// Reserved address 0x1289c

// Reserved address 0x128a0

// Reserved address 0x128a4

// Reserved address 0x128a8

// Reserved address 0x128ac

// Reserved address 0x128b0

// Reserved address 0x128b4

// Reserved address 0x128b8

// Reserved address 0x128bc

// Reserved address 0x128c0

// Reserved address 0x128c4

// Reserved address 0x128c8

// Reserved address 0x128cc

// Reserved address 0x128d0

// Reserved address 0x128d4

// Reserved address 0x128d8

// Reserved address 0x128dc

// Reserved address 0x128e0

// Reserved address 0x128e4

// Reserved address 0x128e8

// Reserved address 0x128ec

// Reserved address 0x128f0

// Reserved address 0x128f4

// Reserved address 0x128f8

// Reserved address 0x128fc

// Register GPIO_N_INTERRUPT_STATUS_G0_0
#define GPIO_N_INTERRUPT_STATUS_G0_0                    _MK_ADDR_CONST(0x12900)
#define GPIO_N_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_N_INTERRUPT_STATUS_G0_0_DUAL                       0x0
#define GPIO_N_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_N_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_N_INTERRUPT_STATUS_G0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G0_0_RESET_MASK                         _MK_MASK_CONST(0x7)
#define GPIO_N_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G0_0_READ_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_N_INTERRUPT_STATUS_G0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7, GPIO_N_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_N_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        2:0
#define GPIO_N_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_N_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
#define GPIO_N_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_N_INTERRUPT_STATUS_G1_0
#define GPIO_N_INTERRUPT_STATUS_G1_0                    _MK_ADDR_CONST(0x12904)
#define GPIO_N_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_N_INTERRUPT_STATUS_G1_0_DUAL                       0x0
#define GPIO_N_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_N_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_N_INTERRUPT_STATUS_G1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G1_0_RESET_MASK                         _MK_MASK_CONST(0x7)
#define GPIO_N_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G1_0_READ_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_N_INTERRUPT_STATUS_G1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7, GPIO_N_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_N_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        2:0
#define GPIO_N_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_N_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
#define GPIO_N_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_N_INTERRUPT_STATUS_G2_0
#define GPIO_N_INTERRUPT_STATUS_G2_0                    _MK_ADDR_CONST(0x12908)
#define GPIO_N_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_N_INTERRUPT_STATUS_G2_0_DUAL                       0x0
#define GPIO_N_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_N_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_N_INTERRUPT_STATUS_G2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G2_0_RESET_MASK                         _MK_MASK_CONST(0x7)
#define GPIO_N_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G2_0_READ_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_N_INTERRUPT_STATUS_G2_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7, GPIO_N_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_N_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        2:0
#define GPIO_N_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_N_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
#define GPIO_N_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_N_INTERRUPT_STATUS_G3_0
#define GPIO_N_INTERRUPT_STATUS_G3_0                    _MK_ADDR_CONST(0x1290c)
#define GPIO_N_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_N_INTERRUPT_STATUS_G3_0_DUAL                       0x0
#define GPIO_N_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_N_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_N_INTERRUPT_STATUS_G3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G3_0_RESET_MASK                         _MK_MASK_CONST(0x7)
#define GPIO_N_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G3_0_READ_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_N_INTERRUPT_STATUS_G3_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7, GPIO_N_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_N_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        2:0
#define GPIO_N_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_N_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
#define GPIO_N_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_N_INTERRUPT_STATUS_G4_0
#define GPIO_N_INTERRUPT_STATUS_G4_0                    _MK_ADDR_CONST(0x12910)
#define GPIO_N_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_N_INTERRUPT_STATUS_G4_0_DUAL                       0x0
#define GPIO_N_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_N_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_N_INTERRUPT_STATUS_G4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G4_0_RESET_MASK                         _MK_MASK_CONST(0x7)
#define GPIO_N_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G4_0_READ_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_N_INTERRUPT_STATUS_G4_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7, GPIO_N_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_N_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        2:0
#define GPIO_N_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_N_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
#define GPIO_N_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_N_INTERRUPT_STATUS_G5_0
#define GPIO_N_INTERRUPT_STATUS_G5_0                    _MK_ADDR_CONST(0x12914)
#define GPIO_N_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_N_INTERRUPT_STATUS_G5_0_DUAL                       0x0
#define GPIO_N_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_N_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_N_INTERRUPT_STATUS_G5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G5_0_RESET_MASK                         _MK_MASK_CONST(0x7)
#define GPIO_N_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G5_0_READ_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_N_INTERRUPT_STATUS_G5_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7, GPIO_N_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_N_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        2:0
#define GPIO_N_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_N_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
#define GPIO_N_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_N_INTERRUPT_STATUS_G6_0
#define GPIO_N_INTERRUPT_STATUS_G6_0                    _MK_ADDR_CONST(0x12918)
#define GPIO_N_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_N_INTERRUPT_STATUS_G6_0_DUAL                       0x0
#define GPIO_N_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_N_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_N_INTERRUPT_STATUS_G6_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G6_0_RESET_MASK                         _MK_MASK_CONST(0x7)
#define GPIO_N_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G6_0_READ_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_N_INTERRUPT_STATUS_G6_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7, GPIO_N_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_N_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        2:0
#define GPIO_N_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_N_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
#define GPIO_N_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_N_INTERRUPT_STATUS_G7_0
#define GPIO_N_INTERRUPT_STATUS_G7_0                    _MK_ADDR_CONST(0x1291c)
#define GPIO_N_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_N_INTERRUPT_STATUS_G7_0_DUAL                       0x0
#define GPIO_N_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_N_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_N_INTERRUPT_STATUS_G7_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G7_0_RESET_MASK                         _MK_MASK_CONST(0x7)
#define GPIO_N_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G7_0_READ_MASK                  _MK_MASK_CONST(0x7)
#define GPIO_N_INTERRUPT_STATUS_G7_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x7, GPIO_N_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_N_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        2:0
#define GPIO_N_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_N_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
#define GPIO_N_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Reserved address 0x12920

// Reserved address 0x12924

// Reserved address 0x12928

// Reserved address 0x1292c

// Reserved address 0x12930

// Reserved address 0x12934

// Reserved address 0x12938

// Reserved address 0x1293c

// Reserved address 0x12940

// Reserved address 0x12944

// Reserved address 0x12948

// Reserved address 0x1294c

// Reserved address 0x12950

// Reserved address 0x12954

// Reserved address 0x12958

// Reserved address 0x1295c

// Reserved address 0x12960

// Reserved address 0x12964

// Reserved address 0x12968

// Reserved address 0x1296c

// Reserved address 0x12970

// Reserved address 0x12974

// Reserved address 0x12978

// Reserved address 0x1297c

// Reserved address 0x12980

// Reserved address 0x12984

// Reserved address 0x12988

// Reserved address 0x1298c

// Reserved address 0x12990

// Reserved address 0x12994

// Reserved address 0x12998

// Reserved address 0x1299c

// Reserved address 0x129a0

// Reserved address 0x129a4

// Reserved address 0x129a8

// Reserved address 0x129ac

// Reserved address 0x129b0

// Reserved address 0x129b4

// Reserved address 0x129b8

// Reserved address 0x129bc

// Reserved address 0x129c0

// Reserved address 0x129c4

// Reserved address 0x129c8

// Reserved address 0x129cc

// Reserved address 0x129d0

// Reserved address 0x129d4

// Reserved address 0x129d8

// Reserved address 0x129dc

// Reserved address 0x129e0

// Reserved address 0x129e4

// Reserved address 0x129e8

// Reserved address 0x129ec

// Reserved address 0x129f0

// Reserved address 0x129f4

// Reserved address 0x129f8

// Reserved address 0x129fc

// Register GPIO_P_ENABLE_CONFIG_00_0
#define GPIO_P_ENABLE_CONFIG_00_0                       _MK_ADDR_CONST(0x12a00)
#define GPIO_P_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_P_ENABLE_CONFIG_00_0_DUAL                  0x0
#define GPIO_P_ENABLE_CONFIG_00_0_SCR                   GPIO_P_SCR_00_0
#define GPIO_P_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_P_ENABLE_CONFIG_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_00_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_P_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_P_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_P_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_P_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_P_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_P_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_P_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_P_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_00_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_00_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_P_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_P_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_P_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_P_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_P_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_P_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_P_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_P_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_P_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_P_DEBOUNCE_THRESHOLD_00_0
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0                  _MK_ADDR_CONST(0x12a04)
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_P_SCR_00_0
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_P_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_P_INPUT_00_0
#define GPIO_P_INPUT_00_0                       _MK_ADDR_CONST(0x12a08)
#define GPIO_P_INPUT_00_0_SECURE                        0x0
#define GPIO_P_INPUT_00_0_DUAL                  0x0
#define GPIO_P_INPUT_00_0_SCR                   GPIO_P_SCR_00_0
#define GPIO_P_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_P_INPUT_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_00_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_00_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_P_INPUT_00_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_00_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_P_INPUT_00_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_P_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_P_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_P_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_P_INPUT_00_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_00_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_P_OUTPUT_CONTROL_00_0
#define GPIO_P_OUTPUT_CONTROL_00_0                      _MK_ADDR_CONST(0x12a0c)
#define GPIO_P_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_P_OUTPUT_CONTROL_00_0_DUAL                         0x0
#define GPIO_P_OUTPUT_CONTROL_00_0_SCR                  GPIO_P_SCR_00_0
#define GPIO_P_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_P_OUTPUT_CONTROL_00_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_00_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_00_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_00_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_P_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_P_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_P_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_P_OUTPUT_VALUE_00_0
#define GPIO_P_OUTPUT_VALUE_00_0                        _MK_ADDR_CONST(0x12a10)
#define GPIO_P_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_P_OUTPUT_VALUE_00_0_DUAL                   0x0
#define GPIO_P_OUTPUT_VALUE_00_0_SCR                    GPIO_P_SCR_00_0
#define GPIO_P_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_P_OUTPUT_VALUE_00_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_00_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_00_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_00_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_P_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_P_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_P_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_P_INTERRUPT_CLEAR_00_0
#define GPIO_P_INTERRUPT_CLEAR_00_0                     _MK_ADDR_CONST(0x12a14)
#define GPIO_P_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_P_INTERRUPT_CLEAR_00_0_DUAL                        0x0
#define GPIO_P_INTERRUPT_CLEAR_00_0_SCR                         GPIO_P_SCR_00_0
#define GPIO_P_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_P_INTERRUPT_CLEAR_00_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_00_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_00_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_00_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_P_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_P_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_P_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_P_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x12a18

// Reserved address 0x12a1c

// Register GPIO_P_ENABLE_CONFIG_01_0
#define GPIO_P_ENABLE_CONFIG_01_0                       _MK_ADDR_CONST(0x12a20)
#define GPIO_P_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_P_ENABLE_CONFIG_01_0_DUAL                  0x0
#define GPIO_P_ENABLE_CONFIG_01_0_SCR                   GPIO_P_SCR_01_0
#define GPIO_P_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_P_ENABLE_CONFIG_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_01_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_P_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_P_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_P_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_P_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_P_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_P_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_P_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_P_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_01_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_01_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_P_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_P_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_P_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_P_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_P_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_P_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_P_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_P_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_P_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_P_DEBOUNCE_THRESHOLD_01_0
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0                  _MK_ADDR_CONST(0x12a24)
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_P_SCR_01_0
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_P_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_P_INPUT_01_0
#define GPIO_P_INPUT_01_0                       _MK_ADDR_CONST(0x12a28)
#define GPIO_P_INPUT_01_0_SECURE                        0x0
#define GPIO_P_INPUT_01_0_DUAL                  0x0
#define GPIO_P_INPUT_01_0_SCR                   GPIO_P_SCR_01_0
#define GPIO_P_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_P_INPUT_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_01_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_01_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_P_INPUT_01_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_01_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_P_INPUT_01_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_P_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_P_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_P_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_P_INPUT_01_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_01_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_P_OUTPUT_CONTROL_01_0
#define GPIO_P_OUTPUT_CONTROL_01_0                      _MK_ADDR_CONST(0x12a2c)
#define GPIO_P_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_P_OUTPUT_CONTROL_01_0_DUAL                         0x0
#define GPIO_P_OUTPUT_CONTROL_01_0_SCR                  GPIO_P_SCR_01_0
#define GPIO_P_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_P_OUTPUT_CONTROL_01_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_01_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_01_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_01_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_P_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_P_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_P_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_P_OUTPUT_VALUE_01_0
#define GPIO_P_OUTPUT_VALUE_01_0                        _MK_ADDR_CONST(0x12a30)
#define GPIO_P_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_P_OUTPUT_VALUE_01_0_DUAL                   0x0
#define GPIO_P_OUTPUT_VALUE_01_0_SCR                    GPIO_P_SCR_01_0
#define GPIO_P_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_P_OUTPUT_VALUE_01_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_01_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_01_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_01_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_P_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_P_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_P_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_P_INTERRUPT_CLEAR_01_0
#define GPIO_P_INTERRUPT_CLEAR_01_0                     _MK_ADDR_CONST(0x12a34)
#define GPIO_P_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_P_INTERRUPT_CLEAR_01_0_DUAL                        0x0
#define GPIO_P_INTERRUPT_CLEAR_01_0_SCR                         GPIO_P_SCR_01_0
#define GPIO_P_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_P_INTERRUPT_CLEAR_01_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_01_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_01_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_01_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_P_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_P_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_P_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_P_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x12a38

// Reserved address 0x12a3c

// Register GPIO_P_ENABLE_CONFIG_02_0
#define GPIO_P_ENABLE_CONFIG_02_0                       _MK_ADDR_CONST(0x12a40)
#define GPIO_P_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_P_ENABLE_CONFIG_02_0_DUAL                  0x0
#define GPIO_P_ENABLE_CONFIG_02_0_SCR                   GPIO_P_SCR_02_0
#define GPIO_P_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_P_ENABLE_CONFIG_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_02_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_P_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_P_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_P_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_P_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_P_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_P_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_P_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_P_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_02_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_02_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_P_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_P_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_P_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_P_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_P_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_P_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_P_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_P_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_P_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_P_DEBOUNCE_THRESHOLD_02_0
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0                  _MK_ADDR_CONST(0x12a44)
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_P_SCR_02_0
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_P_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_P_INPUT_02_0
#define GPIO_P_INPUT_02_0                       _MK_ADDR_CONST(0x12a48)
#define GPIO_P_INPUT_02_0_SECURE                        0x0
#define GPIO_P_INPUT_02_0_DUAL                  0x0
#define GPIO_P_INPUT_02_0_SCR                   GPIO_P_SCR_02_0
#define GPIO_P_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_P_INPUT_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_02_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_02_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_P_INPUT_02_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_02_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_P_INPUT_02_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_P_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_P_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_P_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_P_INPUT_02_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_02_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_P_OUTPUT_CONTROL_02_0
#define GPIO_P_OUTPUT_CONTROL_02_0                      _MK_ADDR_CONST(0x12a4c)
#define GPIO_P_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_P_OUTPUT_CONTROL_02_0_DUAL                         0x0
#define GPIO_P_OUTPUT_CONTROL_02_0_SCR                  GPIO_P_SCR_02_0
#define GPIO_P_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_P_OUTPUT_CONTROL_02_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_02_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_02_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_02_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_P_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_P_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_P_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_P_OUTPUT_VALUE_02_0
#define GPIO_P_OUTPUT_VALUE_02_0                        _MK_ADDR_CONST(0x12a50)
#define GPIO_P_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_P_OUTPUT_VALUE_02_0_DUAL                   0x0
#define GPIO_P_OUTPUT_VALUE_02_0_SCR                    GPIO_P_SCR_02_0
#define GPIO_P_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_P_OUTPUT_VALUE_02_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_02_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_02_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_02_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_P_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_P_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_P_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_P_INTERRUPT_CLEAR_02_0
#define GPIO_P_INTERRUPT_CLEAR_02_0                     _MK_ADDR_CONST(0x12a54)
#define GPIO_P_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_P_INTERRUPT_CLEAR_02_0_DUAL                        0x0
#define GPIO_P_INTERRUPT_CLEAR_02_0_SCR                         GPIO_P_SCR_02_0
#define GPIO_P_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_P_INTERRUPT_CLEAR_02_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_02_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_02_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_02_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_P_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_P_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_P_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_P_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x12a58

// Reserved address 0x12a5c

// Register GPIO_P_ENABLE_CONFIG_03_0
#define GPIO_P_ENABLE_CONFIG_03_0                       _MK_ADDR_CONST(0x12a60)
#define GPIO_P_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_P_ENABLE_CONFIG_03_0_DUAL                  0x0
#define GPIO_P_ENABLE_CONFIG_03_0_SCR                   GPIO_P_SCR_03_0
#define GPIO_P_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_P_ENABLE_CONFIG_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_03_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_P_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_P_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_P_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_P_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_P_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_P_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_P_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_P_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_03_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_03_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_P_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_P_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_P_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_P_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_P_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_P_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_P_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_P_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_P_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_P_DEBOUNCE_THRESHOLD_03_0
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0                  _MK_ADDR_CONST(0x12a64)
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_P_SCR_03_0
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_P_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_P_INPUT_03_0
#define GPIO_P_INPUT_03_0                       _MK_ADDR_CONST(0x12a68)
#define GPIO_P_INPUT_03_0_SECURE                        0x0
#define GPIO_P_INPUT_03_0_DUAL                  0x0
#define GPIO_P_INPUT_03_0_SCR                   GPIO_P_SCR_03_0
#define GPIO_P_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_P_INPUT_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_03_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_03_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_P_INPUT_03_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_03_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_P_INPUT_03_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_P_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_P_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_P_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_P_INPUT_03_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_03_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_P_OUTPUT_CONTROL_03_0
#define GPIO_P_OUTPUT_CONTROL_03_0                      _MK_ADDR_CONST(0x12a6c)
#define GPIO_P_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_P_OUTPUT_CONTROL_03_0_DUAL                         0x0
#define GPIO_P_OUTPUT_CONTROL_03_0_SCR                  GPIO_P_SCR_03_0
#define GPIO_P_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_P_OUTPUT_CONTROL_03_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_03_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_03_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_03_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_P_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_P_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_P_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_P_OUTPUT_VALUE_03_0
#define GPIO_P_OUTPUT_VALUE_03_0                        _MK_ADDR_CONST(0x12a70)
#define GPIO_P_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_P_OUTPUT_VALUE_03_0_DUAL                   0x0
#define GPIO_P_OUTPUT_VALUE_03_0_SCR                    GPIO_P_SCR_03_0
#define GPIO_P_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_P_OUTPUT_VALUE_03_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_03_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_03_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_03_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_P_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_P_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_P_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_P_INTERRUPT_CLEAR_03_0
#define GPIO_P_INTERRUPT_CLEAR_03_0                     _MK_ADDR_CONST(0x12a74)
#define GPIO_P_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_P_INTERRUPT_CLEAR_03_0_DUAL                        0x0
#define GPIO_P_INTERRUPT_CLEAR_03_0_SCR                         GPIO_P_SCR_03_0
#define GPIO_P_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_P_INTERRUPT_CLEAR_03_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_03_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_03_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_03_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_P_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_P_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_P_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_P_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x12a78

// Reserved address 0x12a7c

// Register GPIO_P_ENABLE_CONFIG_04_0
#define GPIO_P_ENABLE_CONFIG_04_0                       _MK_ADDR_CONST(0x12a80)
#define GPIO_P_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_P_ENABLE_CONFIG_04_0_DUAL                  0x0
#define GPIO_P_ENABLE_CONFIG_04_0_SCR                   GPIO_P_SCR_04_0
#define GPIO_P_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_P_ENABLE_CONFIG_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_04_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_P_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_P_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_P_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_P_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_P_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_P_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_P_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_P_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_04_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_04_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_P_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_P_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_P_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_P_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_P_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_P_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_P_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_P_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_P_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_P_DEBOUNCE_THRESHOLD_04_0
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0                  _MK_ADDR_CONST(0x12a84)
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_DUAL                     0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_P_SCR_04_0
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_P_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_P_INPUT_04_0
#define GPIO_P_INPUT_04_0                       _MK_ADDR_CONST(0x12a88)
#define GPIO_P_INPUT_04_0_SECURE                        0x0
#define GPIO_P_INPUT_04_0_DUAL                  0x0
#define GPIO_P_INPUT_04_0_SCR                   GPIO_P_SCR_04_0
#define GPIO_P_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_P_INPUT_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_04_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_04_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_P_INPUT_04_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_04_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_P_INPUT_04_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_P_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_P_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_P_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_P_INPUT_04_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_04_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_P_OUTPUT_CONTROL_04_0
#define GPIO_P_OUTPUT_CONTROL_04_0                      _MK_ADDR_CONST(0x12a8c)
#define GPIO_P_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_P_OUTPUT_CONTROL_04_0_DUAL                         0x0
#define GPIO_P_OUTPUT_CONTROL_04_0_SCR                  GPIO_P_SCR_04_0
#define GPIO_P_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_P_OUTPUT_CONTROL_04_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_04_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_04_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_04_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_P_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_P_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_P_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_P_OUTPUT_VALUE_04_0
#define GPIO_P_OUTPUT_VALUE_04_0                        _MK_ADDR_CONST(0x12a90)
#define GPIO_P_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_P_OUTPUT_VALUE_04_0_DUAL                   0x0
#define GPIO_P_OUTPUT_VALUE_04_0_SCR                    GPIO_P_SCR_04_0
#define GPIO_P_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_P_OUTPUT_VALUE_04_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_04_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_04_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_04_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_P_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_P_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_P_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_P_INTERRUPT_CLEAR_04_0
#define GPIO_P_INTERRUPT_CLEAR_04_0                     _MK_ADDR_CONST(0x12a94)
#define GPIO_P_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_P_INTERRUPT_CLEAR_04_0_DUAL                        0x0
#define GPIO_P_INTERRUPT_CLEAR_04_0_SCR                         GPIO_P_SCR_04_0
#define GPIO_P_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_P_INTERRUPT_CLEAR_04_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_04_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_04_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_04_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_P_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_P_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_P_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_P_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x12a98

// Reserved address 0x12a9c

// Register GPIO_P_ENABLE_CONFIG_05_0
#define GPIO_P_ENABLE_CONFIG_05_0                       _MK_ADDR_CONST(0x12aa0)
#define GPIO_P_ENABLE_CONFIG_05_0_SECURE                        0x0
#define GPIO_P_ENABLE_CONFIG_05_0_DUAL                  0x0
#define GPIO_P_ENABLE_CONFIG_05_0_SCR                   GPIO_P_SCR_05_0
#define GPIO_P_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
#define GPIO_P_ENABLE_CONFIG_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_05_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_P_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_P_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_P_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_P_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_P_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_P_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
#define GPIO_P_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
#define GPIO_P_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_05_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_05_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_P_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_P_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_P_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_P_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_P_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_P_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_P_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_P_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_P_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_P_DEBOUNCE_THRESHOLD_05_0
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0                  _MK_ADDR_CONST(0x12aa4)
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_DUAL                     0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_P_SCR_05_0
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_P_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_P_INPUT_05_0
#define GPIO_P_INPUT_05_0                       _MK_ADDR_CONST(0x12aa8)
#define GPIO_P_INPUT_05_0_SECURE                        0x0
#define GPIO_P_INPUT_05_0_DUAL                  0x0
#define GPIO_P_INPUT_05_0_SCR                   GPIO_P_SCR_05_0
#define GPIO_P_INPUT_05_0_WORD_COUNT                    0x1
#define GPIO_P_INPUT_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_05_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_05_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_P_INPUT_05_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_05_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_P_INPUT_05_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_P_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_P_INPUT_05_0_GPIO_IN_RANGE                 0:0
#define GPIO_P_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_P_INPUT_05_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_05_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_P_OUTPUT_CONTROL_05_0
#define GPIO_P_OUTPUT_CONTROL_05_0                      _MK_ADDR_CONST(0x12aac)
#define GPIO_P_OUTPUT_CONTROL_05_0_SECURE                       0x0
#define GPIO_P_OUTPUT_CONTROL_05_0_DUAL                         0x0
#define GPIO_P_OUTPUT_CONTROL_05_0_SCR                  GPIO_P_SCR_05_0
#define GPIO_P_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
#define GPIO_P_OUTPUT_CONTROL_05_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_05_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_05_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_05_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_P_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_P_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_P_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_P_OUTPUT_VALUE_05_0
#define GPIO_P_OUTPUT_VALUE_05_0                        _MK_ADDR_CONST(0x12ab0)
#define GPIO_P_OUTPUT_VALUE_05_0_SECURE                         0x0
#define GPIO_P_OUTPUT_VALUE_05_0_DUAL                   0x0
#define GPIO_P_OUTPUT_VALUE_05_0_SCR                    GPIO_P_SCR_05_0
#define GPIO_P_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
#define GPIO_P_OUTPUT_VALUE_05_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_05_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_05_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_05_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_P_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_P_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_P_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_P_INTERRUPT_CLEAR_05_0
#define GPIO_P_INTERRUPT_CLEAR_05_0                     _MK_ADDR_CONST(0x12ab4)
#define GPIO_P_INTERRUPT_CLEAR_05_0_SECURE                      0x0
#define GPIO_P_INTERRUPT_CLEAR_05_0_DUAL                        0x0
#define GPIO_P_INTERRUPT_CLEAR_05_0_SCR                         GPIO_P_SCR_05_0
#define GPIO_P_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
#define GPIO_P_INTERRUPT_CLEAR_05_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_05_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_05_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_05_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_P_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_P_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_P_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_P_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x12ab8

// Reserved address 0x12abc

// Register GPIO_P_ENABLE_CONFIG_06_0
#define GPIO_P_ENABLE_CONFIG_06_0                       _MK_ADDR_CONST(0x12ac0)
#define GPIO_P_ENABLE_CONFIG_06_0_SECURE                        0x0
#define GPIO_P_ENABLE_CONFIG_06_0_DUAL                  0x0
#define GPIO_P_ENABLE_CONFIG_06_0_SCR                   GPIO_P_SCR_06_0
#define GPIO_P_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
#define GPIO_P_ENABLE_CONFIG_06_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_06_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_P_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
#define GPIO_P_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_P_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_P_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_P_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
#define GPIO_P_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
#define GPIO_P_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
#define GPIO_P_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_06_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_06_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_P_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_P_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_P_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_P_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_P_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_P_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_P_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_P_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_P_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_P_DEBOUNCE_THRESHOLD_06_0
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0                  _MK_ADDR_CONST(0x12ac4)
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_DUAL                     0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_P_SCR_06_0
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_P_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_P_INPUT_06_0
#define GPIO_P_INPUT_06_0                       _MK_ADDR_CONST(0x12ac8)
#define GPIO_P_INPUT_06_0_SECURE                        0x0
#define GPIO_P_INPUT_06_0_DUAL                  0x0
#define GPIO_P_INPUT_06_0_SCR                   GPIO_P_SCR_06_0
#define GPIO_P_INPUT_06_0_WORD_COUNT                    0x1
#define GPIO_P_INPUT_06_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_06_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_06_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_06_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_06_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_P_INPUT_06_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_06_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_P_INPUT_06_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_P_INPUT_06_0_GPIO_IN_SHIFT)
#define GPIO_P_INPUT_06_0_GPIO_IN_RANGE                 0:0
#define GPIO_P_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_P_INPUT_06_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_06_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_06_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_06_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_P_OUTPUT_CONTROL_06_0
#define GPIO_P_OUTPUT_CONTROL_06_0                      _MK_ADDR_CONST(0x12acc)
#define GPIO_P_OUTPUT_CONTROL_06_0_SECURE                       0x0
#define GPIO_P_OUTPUT_CONTROL_06_0_DUAL                         0x0
#define GPIO_P_OUTPUT_CONTROL_06_0_SCR                  GPIO_P_SCR_06_0
#define GPIO_P_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
#define GPIO_P_OUTPUT_CONTROL_06_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_06_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_06_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_06_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_P_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_P_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_P_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_P_OUTPUT_VALUE_06_0
#define GPIO_P_OUTPUT_VALUE_06_0                        _MK_ADDR_CONST(0x12ad0)
#define GPIO_P_OUTPUT_VALUE_06_0_SECURE                         0x0
#define GPIO_P_OUTPUT_VALUE_06_0_DUAL                   0x0
#define GPIO_P_OUTPUT_VALUE_06_0_SCR                    GPIO_P_SCR_06_0
#define GPIO_P_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
#define GPIO_P_OUTPUT_VALUE_06_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_06_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_06_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_06_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_P_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_P_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_P_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_P_INTERRUPT_CLEAR_06_0
#define GPIO_P_INTERRUPT_CLEAR_06_0                     _MK_ADDR_CONST(0x12ad4)
#define GPIO_P_INTERRUPT_CLEAR_06_0_SECURE                      0x0
#define GPIO_P_INTERRUPT_CLEAR_06_0_DUAL                        0x0
#define GPIO_P_INTERRUPT_CLEAR_06_0_SCR                         GPIO_P_SCR_06_0
#define GPIO_P_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
#define GPIO_P_INTERRUPT_CLEAR_06_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_06_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_06_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_06_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_P_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_P_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_P_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_P_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x12ad8

// Reserved address 0x12adc

// Register GPIO_P_ENABLE_CONFIG_07_0
#define GPIO_P_ENABLE_CONFIG_07_0                       _MK_ADDR_CONST(0x12ae0)
#define GPIO_P_ENABLE_CONFIG_07_0_SECURE                        0x0
#define GPIO_P_ENABLE_CONFIG_07_0_DUAL                  0x0
#define GPIO_P_ENABLE_CONFIG_07_0_SCR                   GPIO_P_SCR_07_0
#define GPIO_P_ENABLE_CONFIG_07_0_WORD_COUNT                    0x1
#define GPIO_P_ENABLE_CONFIG_07_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_07_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_P_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
#define GPIO_P_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_P_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_P_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_P_ENABLE_CONFIG_07_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
#define GPIO_P_ENABLE_CONFIG_07_0_IN_OUT_RANGE                  1:1
#define GPIO_P_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                        0x0
#define GPIO_P_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_07_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_07_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_P_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_P_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_P_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_P_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_P_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_P_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_P_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_P_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_P_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_P_DEBOUNCE_THRESHOLD_07_0
#define GPIO_P_DEBOUNCE_THRESHOLD_07_0                  _MK_ADDR_CONST(0x12ae4)
#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_SECURE                   0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_DUAL                     0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_SCR                      GPIO_P_SCR_07_0
#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                       0x1
#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_P_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_P_INPUT_07_0
#define GPIO_P_INPUT_07_0                       _MK_ADDR_CONST(0x12ae8)
#define GPIO_P_INPUT_07_0_SECURE                        0x0
#define GPIO_P_INPUT_07_0_DUAL                  0x0
#define GPIO_P_INPUT_07_0_SCR                   GPIO_P_SCR_07_0
#define GPIO_P_INPUT_07_0_WORD_COUNT                    0x1
#define GPIO_P_INPUT_07_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_07_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_07_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_07_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_07_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_P_INPUT_07_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_07_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_P_INPUT_07_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_P_INPUT_07_0_GPIO_IN_SHIFT)
#define GPIO_P_INPUT_07_0_GPIO_IN_RANGE                 0:0
#define GPIO_P_INPUT_07_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_P_INPUT_07_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_07_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_07_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_07_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_07_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_P_OUTPUT_CONTROL_07_0
#define GPIO_P_OUTPUT_CONTROL_07_0                      _MK_ADDR_CONST(0x12aec)
#define GPIO_P_OUTPUT_CONTROL_07_0_SECURE                       0x0
#define GPIO_P_OUTPUT_CONTROL_07_0_DUAL                         0x0
#define GPIO_P_OUTPUT_CONTROL_07_0_SCR                  GPIO_P_SCR_07_0
#define GPIO_P_OUTPUT_CONTROL_07_0_WORD_COUNT                   0x1
#define GPIO_P_OUTPUT_CONTROL_07_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_07_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_07_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_07_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_P_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_P_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_P_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_P_OUTPUT_VALUE_07_0
#define GPIO_P_OUTPUT_VALUE_07_0                        _MK_ADDR_CONST(0x12af0)
#define GPIO_P_OUTPUT_VALUE_07_0_SECURE                         0x0
#define GPIO_P_OUTPUT_VALUE_07_0_DUAL                   0x0
#define GPIO_P_OUTPUT_VALUE_07_0_SCR                    GPIO_P_SCR_07_0
#define GPIO_P_OUTPUT_VALUE_07_0_WORD_COUNT                     0x1
#define GPIO_P_OUTPUT_VALUE_07_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_07_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_07_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_07_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_P_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_P_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_P_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_P_INTERRUPT_CLEAR_07_0
#define GPIO_P_INTERRUPT_CLEAR_07_0                     _MK_ADDR_CONST(0x12af4)
#define GPIO_P_INTERRUPT_CLEAR_07_0_SECURE                      0x0
#define GPIO_P_INTERRUPT_CLEAR_07_0_DUAL                        0x0
#define GPIO_P_INTERRUPT_CLEAR_07_0_SCR                         GPIO_P_SCR_07_0
#define GPIO_P_INTERRUPT_CLEAR_07_0_WORD_COUNT                  0x1
#define GPIO_P_INTERRUPT_CLEAR_07_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_07_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_07_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_07_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_P_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_P_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_P_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_P_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x12af8

// Reserved address 0x12afc

// Register GPIO_P_INTERRUPT_STATUS_G0_0
#define GPIO_P_INTERRUPT_STATUS_G0_0                    _MK_ADDR_CONST(0x12b00)
#define GPIO_P_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_P_INTERRUPT_STATUS_G0_0_DUAL                       0x0
#define GPIO_P_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_P_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_P_INTERRUPT_STATUS_G0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G0_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_P_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G0_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_P_INTERRUPT_STATUS_G0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_P_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_P_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_P_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_P_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_P_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_P_INTERRUPT_STATUS_G1_0
#define GPIO_P_INTERRUPT_STATUS_G1_0                    _MK_ADDR_CONST(0x12b04)
#define GPIO_P_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_P_INTERRUPT_STATUS_G1_0_DUAL                       0x0
#define GPIO_P_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_P_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_P_INTERRUPT_STATUS_G1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G1_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_P_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G1_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_P_INTERRUPT_STATUS_G1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_P_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_P_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_P_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_P_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_P_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_P_INTERRUPT_STATUS_G2_0
#define GPIO_P_INTERRUPT_STATUS_G2_0                    _MK_ADDR_CONST(0x12b08)
#define GPIO_P_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_P_INTERRUPT_STATUS_G2_0_DUAL                       0x0
#define GPIO_P_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_P_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_P_INTERRUPT_STATUS_G2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G2_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_P_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G2_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_P_INTERRUPT_STATUS_G2_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_P_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_P_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_P_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_P_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_P_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_P_INTERRUPT_STATUS_G3_0
#define GPIO_P_INTERRUPT_STATUS_G3_0                    _MK_ADDR_CONST(0x12b0c)
#define GPIO_P_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_P_INTERRUPT_STATUS_G3_0_DUAL                       0x0
#define GPIO_P_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_P_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_P_INTERRUPT_STATUS_G3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G3_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_P_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G3_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_P_INTERRUPT_STATUS_G3_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_P_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_P_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_P_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_P_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_P_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_P_INTERRUPT_STATUS_G4_0
#define GPIO_P_INTERRUPT_STATUS_G4_0                    _MK_ADDR_CONST(0x12b10)
#define GPIO_P_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_P_INTERRUPT_STATUS_G4_0_DUAL                       0x0
#define GPIO_P_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_P_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_P_INTERRUPT_STATUS_G4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G4_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_P_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G4_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_P_INTERRUPT_STATUS_G4_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_P_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_P_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_P_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_P_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_P_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_P_INTERRUPT_STATUS_G5_0
#define GPIO_P_INTERRUPT_STATUS_G5_0                    _MK_ADDR_CONST(0x12b14)
#define GPIO_P_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_P_INTERRUPT_STATUS_G5_0_DUAL                       0x0
#define GPIO_P_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_P_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_P_INTERRUPT_STATUS_G5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G5_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_P_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G5_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_P_INTERRUPT_STATUS_G5_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_P_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_P_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_P_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_P_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_P_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_P_INTERRUPT_STATUS_G6_0
#define GPIO_P_INTERRUPT_STATUS_G6_0                    _MK_ADDR_CONST(0x12b18)
#define GPIO_P_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_P_INTERRUPT_STATUS_G6_0_DUAL                       0x0
#define GPIO_P_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_P_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_P_INTERRUPT_STATUS_G6_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G6_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_P_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G6_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_P_INTERRUPT_STATUS_G6_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_P_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_P_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_P_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_P_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_P_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_P_INTERRUPT_STATUS_G7_0
#define GPIO_P_INTERRUPT_STATUS_G7_0                    _MK_ADDR_CONST(0x12b1c)
#define GPIO_P_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_P_INTERRUPT_STATUS_G7_0_DUAL                       0x0
#define GPIO_P_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_P_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_P_INTERRUPT_STATUS_G7_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G7_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_P_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G7_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_P_INTERRUPT_STATUS_G7_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_P_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_P_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_P_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_P_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_P_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Reserved address 0x12b20

// Reserved address 0x12b24

// Reserved address 0x12b28

// Reserved address 0x12b2c

// Reserved address 0x12b30

// Reserved address 0x12b34

// Reserved address 0x12b38

// Reserved address 0x12b3c

// Reserved address 0x12b40

// Reserved address 0x12b44

// Reserved address 0x12b48

// Reserved address 0x12b4c

// Reserved address 0x12b50

// Reserved address 0x12b54

// Reserved address 0x12b58

// Reserved address 0x12b5c

// Reserved address 0x12b60

// Reserved address 0x12b64

// Reserved address 0x12b68

// Reserved address 0x12b6c

// Reserved address 0x12b70

// Reserved address 0x12b74

// Reserved address 0x12b78

// Reserved address 0x12b7c

// Reserved address 0x12b80

// Reserved address 0x12b84

// Reserved address 0x12b88

// Reserved address 0x12b8c

// Reserved address 0x12b90

// Reserved address 0x12b94

// Reserved address 0x12b98

// Reserved address 0x12b9c

// Reserved address 0x12ba0

// Reserved address 0x12ba4

// Reserved address 0x12ba8

// Reserved address 0x12bac

// Reserved address 0x12bb0

// Reserved address 0x12bb4

// Reserved address 0x12bb8

// Reserved address 0x12bbc

// Reserved address 0x12bc0

// Reserved address 0x12bc4

// Reserved address 0x12bc8

// Reserved address 0x12bcc

// Reserved address 0x12bd0

// Reserved address 0x12bd4

// Reserved address 0x12bd8

// Reserved address 0x12bdc

// Reserved address 0x12be0

// Reserved address 0x12be4

// Reserved address 0x12be8

// Reserved address 0x12bec

// Reserved address 0x12bf0

// Reserved address 0x12bf4

// Reserved address 0x12bf8

// Reserved address 0x12bfc

// Register GPIO_Q_ENABLE_CONFIG_00_0
#define GPIO_Q_ENABLE_CONFIG_00_0                       _MK_ADDR_CONST(0x12c00)
#define GPIO_Q_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_Q_ENABLE_CONFIG_00_0_DUAL                  0x0
#define GPIO_Q_ENABLE_CONFIG_00_0_SCR                   GPIO_Q_SCR_00_0
#define GPIO_Q_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_Q_ENABLE_CONFIG_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_00_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Q_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Q_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_Q_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Q_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_00_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_00_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Q_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Q_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Q_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_Q_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Q_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Q_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_Q_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Q_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Q_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_Q_DEBOUNCE_THRESHOLD_00_0
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0                  _MK_ADDR_CONST(0x12c04)
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_Q_SCR_00_0
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_Q_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_Q_INPUT_00_0
#define GPIO_Q_INPUT_00_0                       _MK_ADDR_CONST(0x12c08)
#define GPIO_Q_INPUT_00_0_SECURE                        0x0
#define GPIO_Q_INPUT_00_0_DUAL                  0x0
#define GPIO_Q_INPUT_00_0_SCR                   GPIO_Q_SCR_00_0
#define GPIO_Q_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_Q_INPUT_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_00_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_00_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Q_INPUT_00_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_00_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Q_INPUT_00_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_Q_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_Q_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_Q_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Q_INPUT_00_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_00_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_Q_OUTPUT_CONTROL_00_0
#define GPIO_Q_OUTPUT_CONTROL_00_0                      _MK_ADDR_CONST(0x12c0c)
#define GPIO_Q_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_Q_OUTPUT_CONTROL_00_0_DUAL                         0x0
#define GPIO_Q_OUTPUT_CONTROL_00_0_SCR                  GPIO_Q_SCR_00_0
#define GPIO_Q_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_Q_OUTPUT_CONTROL_00_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_00_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_00_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_00_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Q_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Q_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Q_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_Q_OUTPUT_VALUE_00_0
#define GPIO_Q_OUTPUT_VALUE_00_0                        _MK_ADDR_CONST(0x12c10)
#define GPIO_Q_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_Q_OUTPUT_VALUE_00_0_DUAL                   0x0
#define GPIO_Q_OUTPUT_VALUE_00_0_SCR                    GPIO_Q_SCR_00_0
#define GPIO_Q_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_Q_OUTPUT_VALUE_00_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_00_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_00_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_00_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Q_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Q_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Q_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_Q_INTERRUPT_CLEAR_00_0
#define GPIO_Q_INTERRUPT_CLEAR_00_0                     _MK_ADDR_CONST(0x12c14)
#define GPIO_Q_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_Q_INTERRUPT_CLEAR_00_0_DUAL                        0x0
#define GPIO_Q_INTERRUPT_CLEAR_00_0_SCR                         GPIO_Q_SCR_00_0
#define GPIO_Q_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_Q_INTERRUPT_CLEAR_00_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_00_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_00_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_00_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Q_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Q_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Q_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Q_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x12c18

// Reserved address 0x12c1c

// Register GPIO_Q_ENABLE_CONFIG_01_0
#define GPIO_Q_ENABLE_CONFIG_01_0                       _MK_ADDR_CONST(0x12c20)
#define GPIO_Q_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_Q_ENABLE_CONFIG_01_0_DUAL                  0x0
#define GPIO_Q_ENABLE_CONFIG_01_0_SCR                   GPIO_Q_SCR_01_0
#define GPIO_Q_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_Q_ENABLE_CONFIG_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_01_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Q_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Q_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_Q_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Q_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_01_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_01_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Q_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Q_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Q_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_Q_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Q_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Q_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_Q_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Q_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Q_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_Q_DEBOUNCE_THRESHOLD_01_0
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0                  _MK_ADDR_CONST(0x12c24)
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_Q_SCR_01_0
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_Q_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_Q_INPUT_01_0
#define GPIO_Q_INPUT_01_0                       _MK_ADDR_CONST(0x12c28)
#define GPIO_Q_INPUT_01_0_SECURE                        0x0
#define GPIO_Q_INPUT_01_0_DUAL                  0x0
#define GPIO_Q_INPUT_01_0_SCR                   GPIO_Q_SCR_01_0
#define GPIO_Q_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_Q_INPUT_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_01_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_01_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Q_INPUT_01_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_01_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Q_INPUT_01_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_Q_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_Q_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_Q_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Q_INPUT_01_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_01_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_Q_OUTPUT_CONTROL_01_0
#define GPIO_Q_OUTPUT_CONTROL_01_0                      _MK_ADDR_CONST(0x12c2c)
#define GPIO_Q_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_Q_OUTPUT_CONTROL_01_0_DUAL                         0x0
#define GPIO_Q_OUTPUT_CONTROL_01_0_SCR                  GPIO_Q_SCR_01_0
#define GPIO_Q_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_Q_OUTPUT_CONTROL_01_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_01_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_01_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_01_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Q_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Q_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Q_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_Q_OUTPUT_VALUE_01_0
#define GPIO_Q_OUTPUT_VALUE_01_0                        _MK_ADDR_CONST(0x12c30)
#define GPIO_Q_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_Q_OUTPUT_VALUE_01_0_DUAL                   0x0
#define GPIO_Q_OUTPUT_VALUE_01_0_SCR                    GPIO_Q_SCR_01_0
#define GPIO_Q_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_Q_OUTPUT_VALUE_01_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_01_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_01_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_01_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Q_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Q_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Q_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_Q_INTERRUPT_CLEAR_01_0
#define GPIO_Q_INTERRUPT_CLEAR_01_0                     _MK_ADDR_CONST(0x12c34)
#define GPIO_Q_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_Q_INTERRUPT_CLEAR_01_0_DUAL                        0x0
#define GPIO_Q_INTERRUPT_CLEAR_01_0_SCR                         GPIO_Q_SCR_01_0
#define GPIO_Q_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_Q_INTERRUPT_CLEAR_01_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_01_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_01_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_01_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Q_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Q_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Q_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Q_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x12c38

// Reserved address 0x12c3c

// Register GPIO_Q_ENABLE_CONFIG_02_0
#define GPIO_Q_ENABLE_CONFIG_02_0                       _MK_ADDR_CONST(0x12c40)
#define GPIO_Q_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_Q_ENABLE_CONFIG_02_0_DUAL                  0x0
#define GPIO_Q_ENABLE_CONFIG_02_0_SCR                   GPIO_Q_SCR_02_0
#define GPIO_Q_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_Q_ENABLE_CONFIG_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_02_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Q_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Q_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_Q_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Q_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_02_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_02_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Q_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Q_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Q_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_Q_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Q_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Q_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_Q_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Q_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Q_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_Q_DEBOUNCE_THRESHOLD_02_0
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0                  _MK_ADDR_CONST(0x12c44)
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_Q_SCR_02_0
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_Q_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_Q_INPUT_02_0
#define GPIO_Q_INPUT_02_0                       _MK_ADDR_CONST(0x12c48)
#define GPIO_Q_INPUT_02_0_SECURE                        0x0
#define GPIO_Q_INPUT_02_0_DUAL                  0x0
#define GPIO_Q_INPUT_02_0_SCR                   GPIO_Q_SCR_02_0
#define GPIO_Q_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_Q_INPUT_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_02_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_02_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Q_INPUT_02_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_02_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Q_INPUT_02_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_Q_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_Q_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_Q_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Q_INPUT_02_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_02_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_Q_OUTPUT_CONTROL_02_0
#define GPIO_Q_OUTPUT_CONTROL_02_0                      _MK_ADDR_CONST(0x12c4c)
#define GPIO_Q_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_Q_OUTPUT_CONTROL_02_0_DUAL                         0x0
#define GPIO_Q_OUTPUT_CONTROL_02_0_SCR                  GPIO_Q_SCR_02_0
#define GPIO_Q_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_Q_OUTPUT_CONTROL_02_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_02_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_02_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_02_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Q_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Q_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Q_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_Q_OUTPUT_VALUE_02_0
#define GPIO_Q_OUTPUT_VALUE_02_0                        _MK_ADDR_CONST(0x12c50)
#define GPIO_Q_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_Q_OUTPUT_VALUE_02_0_DUAL                   0x0
#define GPIO_Q_OUTPUT_VALUE_02_0_SCR                    GPIO_Q_SCR_02_0
#define GPIO_Q_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_Q_OUTPUT_VALUE_02_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_02_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_02_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_02_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Q_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Q_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Q_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_Q_INTERRUPT_CLEAR_02_0
#define GPIO_Q_INTERRUPT_CLEAR_02_0                     _MK_ADDR_CONST(0x12c54)
#define GPIO_Q_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_Q_INTERRUPT_CLEAR_02_0_DUAL                        0x0
#define GPIO_Q_INTERRUPT_CLEAR_02_0_SCR                         GPIO_Q_SCR_02_0
#define GPIO_Q_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_Q_INTERRUPT_CLEAR_02_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_02_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_02_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_02_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Q_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Q_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Q_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Q_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x12c58

// Reserved address 0x12c5c

// Register GPIO_Q_ENABLE_CONFIG_03_0
#define GPIO_Q_ENABLE_CONFIG_03_0                       _MK_ADDR_CONST(0x12c60)
#define GPIO_Q_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_Q_ENABLE_CONFIG_03_0_DUAL                  0x0
#define GPIO_Q_ENABLE_CONFIG_03_0_SCR                   GPIO_Q_SCR_03_0
#define GPIO_Q_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_Q_ENABLE_CONFIG_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_03_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Q_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Q_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_Q_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Q_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_03_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_03_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Q_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Q_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Q_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_Q_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Q_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Q_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_Q_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Q_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Q_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_Q_DEBOUNCE_THRESHOLD_03_0
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0                  _MK_ADDR_CONST(0x12c64)
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_Q_SCR_03_0
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_Q_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_Q_INPUT_03_0
#define GPIO_Q_INPUT_03_0                       _MK_ADDR_CONST(0x12c68)
#define GPIO_Q_INPUT_03_0_SECURE                        0x0
#define GPIO_Q_INPUT_03_0_DUAL                  0x0
#define GPIO_Q_INPUT_03_0_SCR                   GPIO_Q_SCR_03_0
#define GPIO_Q_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_Q_INPUT_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_03_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_03_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Q_INPUT_03_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_03_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Q_INPUT_03_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_Q_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_Q_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_Q_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Q_INPUT_03_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_03_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_Q_OUTPUT_CONTROL_03_0
#define GPIO_Q_OUTPUT_CONTROL_03_0                      _MK_ADDR_CONST(0x12c6c)
#define GPIO_Q_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_Q_OUTPUT_CONTROL_03_0_DUAL                         0x0
#define GPIO_Q_OUTPUT_CONTROL_03_0_SCR                  GPIO_Q_SCR_03_0
#define GPIO_Q_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_Q_OUTPUT_CONTROL_03_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_03_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_03_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_03_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Q_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Q_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Q_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_Q_OUTPUT_VALUE_03_0
#define GPIO_Q_OUTPUT_VALUE_03_0                        _MK_ADDR_CONST(0x12c70)
#define GPIO_Q_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_Q_OUTPUT_VALUE_03_0_DUAL                   0x0
#define GPIO_Q_OUTPUT_VALUE_03_0_SCR                    GPIO_Q_SCR_03_0
#define GPIO_Q_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_Q_OUTPUT_VALUE_03_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_03_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_03_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_03_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Q_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Q_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Q_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_Q_INTERRUPT_CLEAR_03_0
#define GPIO_Q_INTERRUPT_CLEAR_03_0                     _MK_ADDR_CONST(0x12c74)
#define GPIO_Q_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_Q_INTERRUPT_CLEAR_03_0_DUAL                        0x0
#define GPIO_Q_INTERRUPT_CLEAR_03_0_SCR                         GPIO_Q_SCR_03_0
#define GPIO_Q_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_Q_INTERRUPT_CLEAR_03_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_03_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_03_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_03_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Q_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Q_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Q_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Q_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x12c78

// Reserved address 0x12c7c

// Register GPIO_Q_ENABLE_CONFIG_04_0
#define GPIO_Q_ENABLE_CONFIG_04_0                       _MK_ADDR_CONST(0x12c80)
#define GPIO_Q_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_Q_ENABLE_CONFIG_04_0_DUAL                  0x0
#define GPIO_Q_ENABLE_CONFIG_04_0_SCR                   GPIO_Q_SCR_04_0
#define GPIO_Q_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_Q_ENABLE_CONFIG_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_04_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Q_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Q_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_Q_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Q_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_04_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_04_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Q_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Q_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Q_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_Q_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Q_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Q_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_Q_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Q_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Q_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_Q_DEBOUNCE_THRESHOLD_04_0
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0                  _MK_ADDR_CONST(0x12c84)
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_DUAL                     0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_Q_SCR_04_0
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_Q_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_Q_INPUT_04_0
#define GPIO_Q_INPUT_04_0                       _MK_ADDR_CONST(0x12c88)
#define GPIO_Q_INPUT_04_0_SECURE                        0x0
#define GPIO_Q_INPUT_04_0_DUAL                  0x0
#define GPIO_Q_INPUT_04_0_SCR                   GPIO_Q_SCR_04_0
#define GPIO_Q_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_Q_INPUT_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_04_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_04_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Q_INPUT_04_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_04_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Q_INPUT_04_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_Q_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_Q_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_Q_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Q_INPUT_04_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_04_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_Q_OUTPUT_CONTROL_04_0
#define GPIO_Q_OUTPUT_CONTROL_04_0                      _MK_ADDR_CONST(0x12c8c)
#define GPIO_Q_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_Q_OUTPUT_CONTROL_04_0_DUAL                         0x0
#define GPIO_Q_OUTPUT_CONTROL_04_0_SCR                  GPIO_Q_SCR_04_0
#define GPIO_Q_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_Q_OUTPUT_CONTROL_04_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_04_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_04_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_04_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Q_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Q_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Q_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_Q_OUTPUT_VALUE_04_0
#define GPIO_Q_OUTPUT_VALUE_04_0                        _MK_ADDR_CONST(0x12c90)
#define GPIO_Q_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_Q_OUTPUT_VALUE_04_0_DUAL                   0x0
#define GPIO_Q_OUTPUT_VALUE_04_0_SCR                    GPIO_Q_SCR_04_0
#define GPIO_Q_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_Q_OUTPUT_VALUE_04_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_04_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_04_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_04_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Q_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Q_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Q_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_Q_INTERRUPT_CLEAR_04_0
#define GPIO_Q_INTERRUPT_CLEAR_04_0                     _MK_ADDR_CONST(0x12c94)
#define GPIO_Q_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_Q_INTERRUPT_CLEAR_04_0_DUAL                        0x0
#define GPIO_Q_INTERRUPT_CLEAR_04_0_SCR                         GPIO_Q_SCR_04_0
#define GPIO_Q_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_Q_INTERRUPT_CLEAR_04_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_04_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_04_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_04_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Q_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Q_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Q_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Q_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x12c98

// Reserved address 0x12c9c

// Register GPIO_Q_ENABLE_CONFIG_05_0
#define GPIO_Q_ENABLE_CONFIG_05_0                       _MK_ADDR_CONST(0x12ca0)
#define GPIO_Q_ENABLE_CONFIG_05_0_SECURE                        0x0
#define GPIO_Q_ENABLE_CONFIG_05_0_DUAL                  0x0
#define GPIO_Q_ENABLE_CONFIG_05_0_SCR                   GPIO_Q_SCR_05_0
#define GPIO_Q_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
#define GPIO_Q_ENABLE_CONFIG_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_05_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Q_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Q_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
#define GPIO_Q_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Q_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_05_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_05_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Q_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Q_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Q_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_Q_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Q_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Q_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_Q_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Q_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Q_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_Q_DEBOUNCE_THRESHOLD_05_0
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0                  _MK_ADDR_CONST(0x12ca4)
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_DUAL                     0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_Q_SCR_05_0
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_Q_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_Q_INPUT_05_0
#define GPIO_Q_INPUT_05_0                       _MK_ADDR_CONST(0x12ca8)
#define GPIO_Q_INPUT_05_0_SECURE                        0x0
#define GPIO_Q_INPUT_05_0_DUAL                  0x0
#define GPIO_Q_INPUT_05_0_SCR                   GPIO_Q_SCR_05_0
#define GPIO_Q_INPUT_05_0_WORD_COUNT                    0x1
#define GPIO_Q_INPUT_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_05_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_05_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Q_INPUT_05_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_05_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Q_INPUT_05_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_Q_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_Q_INPUT_05_0_GPIO_IN_RANGE                 0:0
#define GPIO_Q_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Q_INPUT_05_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_05_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_Q_OUTPUT_CONTROL_05_0
#define GPIO_Q_OUTPUT_CONTROL_05_0                      _MK_ADDR_CONST(0x12cac)
#define GPIO_Q_OUTPUT_CONTROL_05_0_SECURE                       0x0
#define GPIO_Q_OUTPUT_CONTROL_05_0_DUAL                         0x0
#define GPIO_Q_OUTPUT_CONTROL_05_0_SCR                  GPIO_Q_SCR_05_0
#define GPIO_Q_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
#define GPIO_Q_OUTPUT_CONTROL_05_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_05_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_05_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_05_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Q_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Q_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Q_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_Q_OUTPUT_VALUE_05_0
#define GPIO_Q_OUTPUT_VALUE_05_0                        _MK_ADDR_CONST(0x12cb0)
#define GPIO_Q_OUTPUT_VALUE_05_0_SECURE                         0x0
#define GPIO_Q_OUTPUT_VALUE_05_0_DUAL                   0x0
#define GPIO_Q_OUTPUT_VALUE_05_0_SCR                    GPIO_Q_SCR_05_0
#define GPIO_Q_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
#define GPIO_Q_OUTPUT_VALUE_05_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_05_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_05_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_05_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Q_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Q_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Q_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_Q_INTERRUPT_CLEAR_05_0
#define GPIO_Q_INTERRUPT_CLEAR_05_0                     _MK_ADDR_CONST(0x12cb4)
#define GPIO_Q_INTERRUPT_CLEAR_05_0_SECURE                      0x0
#define GPIO_Q_INTERRUPT_CLEAR_05_0_DUAL                        0x0
#define GPIO_Q_INTERRUPT_CLEAR_05_0_SCR                         GPIO_Q_SCR_05_0
#define GPIO_Q_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
#define GPIO_Q_INTERRUPT_CLEAR_05_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_05_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_05_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_05_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Q_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Q_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Q_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Q_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x12cb8

// Reserved address 0x12cbc

// Register GPIO_Q_ENABLE_CONFIG_06_0
#define GPIO_Q_ENABLE_CONFIG_06_0                       _MK_ADDR_CONST(0x12cc0)
#define GPIO_Q_ENABLE_CONFIG_06_0_SECURE                        0x0
#define GPIO_Q_ENABLE_CONFIG_06_0_DUAL                  0x0
#define GPIO_Q_ENABLE_CONFIG_06_0_SCR                   GPIO_Q_SCR_06_0
#define GPIO_Q_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
#define GPIO_Q_ENABLE_CONFIG_06_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_06_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Q_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Q_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
#define GPIO_Q_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Q_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_06_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_06_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Q_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Q_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Q_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_Q_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Q_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Q_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_Q_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Q_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Q_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_Q_DEBOUNCE_THRESHOLD_06_0
#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0                  _MK_ADDR_CONST(0x12cc4)
#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_DUAL                     0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_Q_SCR_06_0
#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_Q_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_Q_INPUT_06_0
#define GPIO_Q_INPUT_06_0                       _MK_ADDR_CONST(0x12cc8)
#define GPIO_Q_INPUT_06_0_SECURE                        0x0
#define GPIO_Q_INPUT_06_0_DUAL                  0x0
#define GPIO_Q_INPUT_06_0_SCR                   GPIO_Q_SCR_06_0
#define GPIO_Q_INPUT_06_0_WORD_COUNT                    0x1
#define GPIO_Q_INPUT_06_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_06_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_06_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_06_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_06_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Q_INPUT_06_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_06_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Q_INPUT_06_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_Q_INPUT_06_0_GPIO_IN_SHIFT)
#define GPIO_Q_INPUT_06_0_GPIO_IN_RANGE                 0:0
#define GPIO_Q_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Q_INPUT_06_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_06_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_06_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_06_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_Q_OUTPUT_CONTROL_06_0
#define GPIO_Q_OUTPUT_CONTROL_06_0                      _MK_ADDR_CONST(0x12ccc)
#define GPIO_Q_OUTPUT_CONTROL_06_0_SECURE                       0x0
#define GPIO_Q_OUTPUT_CONTROL_06_0_DUAL                         0x0
#define GPIO_Q_OUTPUT_CONTROL_06_0_SCR                  GPIO_Q_SCR_06_0
#define GPIO_Q_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
#define GPIO_Q_OUTPUT_CONTROL_06_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_06_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_06_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_06_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Q_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Q_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Q_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_Q_OUTPUT_VALUE_06_0
#define GPIO_Q_OUTPUT_VALUE_06_0                        _MK_ADDR_CONST(0x12cd0)
#define GPIO_Q_OUTPUT_VALUE_06_0_SECURE                         0x0
#define GPIO_Q_OUTPUT_VALUE_06_0_DUAL                   0x0
#define GPIO_Q_OUTPUT_VALUE_06_0_SCR                    GPIO_Q_SCR_06_0
#define GPIO_Q_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
#define GPIO_Q_OUTPUT_VALUE_06_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_06_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_06_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_06_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Q_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Q_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Q_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_Q_INTERRUPT_CLEAR_06_0
#define GPIO_Q_INTERRUPT_CLEAR_06_0                     _MK_ADDR_CONST(0x12cd4)
#define GPIO_Q_INTERRUPT_CLEAR_06_0_SECURE                      0x0
#define GPIO_Q_INTERRUPT_CLEAR_06_0_DUAL                        0x0
#define GPIO_Q_INTERRUPT_CLEAR_06_0_SCR                         GPIO_Q_SCR_06_0
#define GPIO_Q_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
#define GPIO_Q_INTERRUPT_CLEAR_06_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_06_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_06_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_06_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Q_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Q_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Q_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Q_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x12cd8

// Reserved address 0x12cdc

// Register GPIO_Q_ENABLE_CONFIG_07_0
#define GPIO_Q_ENABLE_CONFIG_07_0                       _MK_ADDR_CONST(0x12ce0)
#define GPIO_Q_ENABLE_CONFIG_07_0_SECURE                        0x0
#define GPIO_Q_ENABLE_CONFIG_07_0_DUAL                  0x0
#define GPIO_Q_ENABLE_CONFIG_07_0_SCR                   GPIO_Q_SCR_07_0
#define GPIO_Q_ENABLE_CONFIG_07_0_WORD_COUNT                    0x1
#define GPIO_Q_ENABLE_CONFIG_07_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_07_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Q_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Q_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_07_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_07_0_IN_OUT_RANGE                  1:1
#define GPIO_Q_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Q_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_07_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_07_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_Q_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Q_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Q_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_Q_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Q_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Q_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_Q_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Q_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Q_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_Q_DEBOUNCE_THRESHOLD_07_0
#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0                  _MK_ADDR_CONST(0x12ce4)
#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_SECURE                   0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_DUAL                     0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_SCR                      GPIO_Q_SCR_07_0
#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                       0x1
#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_Q_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_Q_INPUT_07_0
#define GPIO_Q_INPUT_07_0                       _MK_ADDR_CONST(0x12ce8)
#define GPIO_Q_INPUT_07_0_SECURE                        0x0
#define GPIO_Q_INPUT_07_0_DUAL                  0x0
#define GPIO_Q_INPUT_07_0_SCR                   GPIO_Q_SCR_07_0
#define GPIO_Q_INPUT_07_0_WORD_COUNT                    0x1
#define GPIO_Q_INPUT_07_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_07_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_07_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_07_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_07_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Q_INPUT_07_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_07_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_Q_INPUT_07_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_Q_INPUT_07_0_GPIO_IN_SHIFT)
#define GPIO_Q_INPUT_07_0_GPIO_IN_RANGE                 0:0
#define GPIO_Q_INPUT_07_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Q_INPUT_07_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_07_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_07_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_07_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_07_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_Q_OUTPUT_CONTROL_07_0
#define GPIO_Q_OUTPUT_CONTROL_07_0                      _MK_ADDR_CONST(0x12cec)
#define GPIO_Q_OUTPUT_CONTROL_07_0_SECURE                       0x0
#define GPIO_Q_OUTPUT_CONTROL_07_0_DUAL                         0x0
#define GPIO_Q_OUTPUT_CONTROL_07_0_SCR                  GPIO_Q_SCR_07_0
#define GPIO_Q_OUTPUT_CONTROL_07_0_WORD_COUNT                   0x1
#define GPIO_Q_OUTPUT_CONTROL_07_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_07_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_07_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_07_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Q_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Q_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Q_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_Q_OUTPUT_VALUE_07_0
#define GPIO_Q_OUTPUT_VALUE_07_0                        _MK_ADDR_CONST(0x12cf0)
#define GPIO_Q_OUTPUT_VALUE_07_0_SECURE                         0x0
#define GPIO_Q_OUTPUT_VALUE_07_0_DUAL                   0x0
#define GPIO_Q_OUTPUT_VALUE_07_0_SCR                    GPIO_Q_SCR_07_0
#define GPIO_Q_OUTPUT_VALUE_07_0_WORD_COUNT                     0x1
#define GPIO_Q_OUTPUT_VALUE_07_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_07_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_07_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_07_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Q_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Q_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Q_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_Q_INTERRUPT_CLEAR_07_0
#define GPIO_Q_INTERRUPT_CLEAR_07_0                     _MK_ADDR_CONST(0x12cf4)
#define GPIO_Q_INTERRUPT_CLEAR_07_0_SECURE                      0x0
#define GPIO_Q_INTERRUPT_CLEAR_07_0_DUAL                        0x0
#define GPIO_Q_INTERRUPT_CLEAR_07_0_SCR                         GPIO_Q_SCR_07_0
#define GPIO_Q_INTERRUPT_CLEAR_07_0_WORD_COUNT                  0x1
#define GPIO_Q_INTERRUPT_CLEAR_07_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_07_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_07_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_07_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_Q_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Q_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Q_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Q_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x12cf8

// Reserved address 0x12cfc

// Register GPIO_Q_INTERRUPT_STATUS_G0_0
#define GPIO_Q_INTERRUPT_STATUS_G0_0                    _MK_ADDR_CONST(0x12d00)
#define GPIO_Q_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_Q_INTERRUPT_STATUS_G0_0_DUAL                       0x0
#define GPIO_Q_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_Q_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_Q_INTERRUPT_STATUS_G0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G0_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_Q_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G0_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Q_INTERRUPT_STATUS_G0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_Q_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Q_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_Q_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Q_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_Q_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_Q_INTERRUPT_STATUS_G1_0
#define GPIO_Q_INTERRUPT_STATUS_G1_0                    _MK_ADDR_CONST(0x12d04)
#define GPIO_Q_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_Q_INTERRUPT_STATUS_G1_0_DUAL                       0x0
#define GPIO_Q_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_Q_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_Q_INTERRUPT_STATUS_G1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G1_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_Q_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G1_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Q_INTERRUPT_STATUS_G1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_Q_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Q_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_Q_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Q_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_Q_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_Q_INTERRUPT_STATUS_G2_0
#define GPIO_Q_INTERRUPT_STATUS_G2_0                    _MK_ADDR_CONST(0x12d08)
#define GPIO_Q_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_Q_INTERRUPT_STATUS_G2_0_DUAL                       0x0
#define GPIO_Q_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_Q_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_Q_INTERRUPT_STATUS_G2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G2_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_Q_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G2_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Q_INTERRUPT_STATUS_G2_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_Q_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Q_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_Q_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Q_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_Q_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_Q_INTERRUPT_STATUS_G3_0
#define GPIO_Q_INTERRUPT_STATUS_G3_0                    _MK_ADDR_CONST(0x12d0c)
#define GPIO_Q_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_Q_INTERRUPT_STATUS_G3_0_DUAL                       0x0
#define GPIO_Q_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_Q_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_Q_INTERRUPT_STATUS_G3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G3_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_Q_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G3_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Q_INTERRUPT_STATUS_G3_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_Q_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Q_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_Q_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Q_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_Q_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_Q_INTERRUPT_STATUS_G4_0
#define GPIO_Q_INTERRUPT_STATUS_G4_0                    _MK_ADDR_CONST(0x12d10)
#define GPIO_Q_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_Q_INTERRUPT_STATUS_G4_0_DUAL                       0x0
#define GPIO_Q_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_Q_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_Q_INTERRUPT_STATUS_G4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G4_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_Q_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G4_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Q_INTERRUPT_STATUS_G4_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_Q_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Q_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_Q_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Q_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_Q_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_Q_INTERRUPT_STATUS_G5_0
#define GPIO_Q_INTERRUPT_STATUS_G5_0                    _MK_ADDR_CONST(0x12d14)
#define GPIO_Q_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_Q_INTERRUPT_STATUS_G5_0_DUAL                       0x0
#define GPIO_Q_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_Q_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_Q_INTERRUPT_STATUS_G5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G5_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_Q_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G5_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Q_INTERRUPT_STATUS_G5_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_Q_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Q_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_Q_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Q_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_Q_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_Q_INTERRUPT_STATUS_G6_0
#define GPIO_Q_INTERRUPT_STATUS_G6_0                    _MK_ADDR_CONST(0x12d18)
#define GPIO_Q_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_Q_INTERRUPT_STATUS_G6_0_DUAL                       0x0
#define GPIO_Q_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_Q_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_Q_INTERRUPT_STATUS_G6_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G6_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_Q_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G6_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Q_INTERRUPT_STATUS_G6_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_Q_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Q_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_Q_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Q_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_Q_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_Q_INTERRUPT_STATUS_G7_0
#define GPIO_Q_INTERRUPT_STATUS_G7_0                    _MK_ADDR_CONST(0x12d1c)
#define GPIO_Q_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_Q_INTERRUPT_STATUS_G7_0_DUAL                       0x0
#define GPIO_Q_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_Q_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_Q_INTERRUPT_STATUS_G7_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G7_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_Q_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G7_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_Q_INTERRUPT_STATUS_G7_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_Q_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Q_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_Q_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Q_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_Q_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Reserved address 0x12d20

// Reserved address 0x12d24

// Reserved address 0x12d28

// Reserved address 0x12d2c

// Reserved address 0x12d30

// Reserved address 0x12d34

// Reserved address 0x12d38

// Reserved address 0x12d3c

// Reserved address 0x12d40

// Reserved address 0x12d44

// Reserved address 0x12d48

// Reserved address 0x12d4c

// Reserved address 0x12d50

// Reserved address 0x12d54

// Reserved address 0x12d58

// Reserved address 0x12d5c

// Reserved address 0x12d60

// Reserved address 0x12d64

// Reserved address 0x12d68

// Reserved address 0x12d6c

// Reserved address 0x12d70

// Reserved address 0x12d74

// Reserved address 0x12d78

// Reserved address 0x12d7c

// Reserved address 0x12d80

// Reserved address 0x12d84

// Reserved address 0x12d88

// Reserved address 0x12d8c

// Reserved address 0x12d90

// Reserved address 0x12d94

// Reserved address 0x12d98

// Reserved address 0x12d9c

// Reserved address 0x12da0

// Reserved address 0x12da4

// Reserved address 0x12da8

// Reserved address 0x12dac

// Reserved address 0x12db0

// Reserved address 0x12db4

// Reserved address 0x12db8

// Reserved address 0x12dbc

// Reserved address 0x12dc0

// Reserved address 0x12dc4

// Reserved address 0x12dc8

// Reserved address 0x12dcc

// Reserved address 0x12dd0

// Reserved address 0x12dd4

// Reserved address 0x12dd8

// Reserved address 0x12ddc

// Reserved address 0x12de0

// Reserved address 0x12de4

// Reserved address 0x12de8

// Reserved address 0x12dec

// Reserved address 0x12df0

// Reserved address 0x12df4

// Reserved address 0x12df8

// Reserved address 0x12dfc

// Register GPIO_R_ENABLE_CONFIG_00_0
#define GPIO_R_ENABLE_CONFIG_00_0                       _MK_ADDR_CONST(0x12e00)
#define GPIO_R_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_R_ENABLE_CONFIG_00_0_DUAL                  0x0
#define GPIO_R_ENABLE_CONFIG_00_0_SCR                   GPIO_R_SCR_00_0
#define GPIO_R_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_R_ENABLE_CONFIG_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_R_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_R_ENABLE_CONFIG_00_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_R_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_R_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_R_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_R_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_R_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_R_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_R_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_R_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_R_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_00_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_00_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_R_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_R_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_R_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_R_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_R_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_R_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_R_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_R_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_R_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_R_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_R_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_R_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_R_DEBOUNCE_THRESHOLD_00_0
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0                  _MK_ADDR_CONST(0x12e04)
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_R_SCR_00_0
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_R_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_R_INPUT_00_0
#define GPIO_R_INPUT_00_0                       _MK_ADDR_CONST(0x12e08)
#define GPIO_R_INPUT_00_0_SECURE                        0x0
#define GPIO_R_INPUT_00_0_DUAL                  0x0
#define GPIO_R_INPUT_00_0_SCR                   GPIO_R_SCR_00_0
#define GPIO_R_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_R_INPUT_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_00_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_00_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_R_INPUT_00_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_00_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_R_INPUT_00_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_R_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_R_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_R_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_R_INPUT_00_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_00_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_R_OUTPUT_CONTROL_00_0
#define GPIO_R_OUTPUT_CONTROL_00_0                      _MK_ADDR_CONST(0x12e0c)
#define GPIO_R_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_R_OUTPUT_CONTROL_00_0_DUAL                         0x0
#define GPIO_R_OUTPUT_CONTROL_00_0_SCR                  GPIO_R_SCR_00_0
#define GPIO_R_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_R_OUTPUT_CONTROL_00_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_00_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_00_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_00_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_R_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_R_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_R_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_R_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_R_OUTPUT_VALUE_00_0
#define GPIO_R_OUTPUT_VALUE_00_0                        _MK_ADDR_CONST(0x12e10)
#define GPIO_R_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_R_OUTPUT_VALUE_00_0_DUAL                   0x0
#define GPIO_R_OUTPUT_VALUE_00_0_SCR                    GPIO_R_SCR_00_0
#define GPIO_R_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_R_OUTPUT_VALUE_00_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_00_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_00_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_00_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_R_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_R_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_R_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_R_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_R_INTERRUPT_CLEAR_00_0
#define GPIO_R_INTERRUPT_CLEAR_00_0                     _MK_ADDR_CONST(0x12e14)
#define GPIO_R_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_R_INTERRUPT_CLEAR_00_0_DUAL                        0x0
#define GPIO_R_INTERRUPT_CLEAR_00_0_SCR                         GPIO_R_SCR_00_0
#define GPIO_R_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_R_INTERRUPT_CLEAR_00_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_00_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_00_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_00_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_R_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_R_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_R_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_R_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_R_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x12e18

// Reserved address 0x12e1c

// Register GPIO_R_ENABLE_CONFIG_01_0
#define GPIO_R_ENABLE_CONFIG_01_0                       _MK_ADDR_CONST(0x12e20)
#define GPIO_R_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_R_ENABLE_CONFIG_01_0_DUAL                  0x0
#define GPIO_R_ENABLE_CONFIG_01_0_SCR                   GPIO_R_SCR_01_0
#define GPIO_R_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_R_ENABLE_CONFIG_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_R_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_R_ENABLE_CONFIG_01_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_R_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_R_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_R_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_R_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_R_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_R_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_R_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_R_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_R_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_01_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_01_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_R_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_R_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_R_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_R_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_R_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_R_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_R_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_R_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_R_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_R_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_R_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_R_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_R_DEBOUNCE_THRESHOLD_01_0
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0                  _MK_ADDR_CONST(0x12e24)
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_R_SCR_01_0
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_R_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_R_INPUT_01_0
#define GPIO_R_INPUT_01_0                       _MK_ADDR_CONST(0x12e28)
#define GPIO_R_INPUT_01_0_SECURE                        0x0
#define GPIO_R_INPUT_01_0_DUAL                  0x0
#define GPIO_R_INPUT_01_0_SCR                   GPIO_R_SCR_01_0
#define GPIO_R_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_R_INPUT_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_01_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_01_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_R_INPUT_01_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_01_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_R_INPUT_01_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_R_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_R_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_R_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_R_INPUT_01_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_01_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_R_OUTPUT_CONTROL_01_0
#define GPIO_R_OUTPUT_CONTROL_01_0                      _MK_ADDR_CONST(0x12e2c)
#define GPIO_R_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_R_OUTPUT_CONTROL_01_0_DUAL                         0x0
#define GPIO_R_OUTPUT_CONTROL_01_0_SCR                  GPIO_R_SCR_01_0
#define GPIO_R_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_R_OUTPUT_CONTROL_01_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_01_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_01_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_01_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_R_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_R_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_R_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_R_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_R_OUTPUT_VALUE_01_0
#define GPIO_R_OUTPUT_VALUE_01_0                        _MK_ADDR_CONST(0x12e30)
#define GPIO_R_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_R_OUTPUT_VALUE_01_0_DUAL                   0x0
#define GPIO_R_OUTPUT_VALUE_01_0_SCR                    GPIO_R_SCR_01_0
#define GPIO_R_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_R_OUTPUT_VALUE_01_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_01_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_01_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_01_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_R_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_R_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_R_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_R_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_R_INTERRUPT_CLEAR_01_0
#define GPIO_R_INTERRUPT_CLEAR_01_0                     _MK_ADDR_CONST(0x12e34)
#define GPIO_R_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_R_INTERRUPT_CLEAR_01_0_DUAL                        0x0
#define GPIO_R_INTERRUPT_CLEAR_01_0_SCR                         GPIO_R_SCR_01_0
#define GPIO_R_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_R_INTERRUPT_CLEAR_01_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_01_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_01_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_01_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_R_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_R_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_R_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_R_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_R_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x12e38

// Reserved address 0x12e3c

// Register GPIO_R_ENABLE_CONFIG_02_0
#define GPIO_R_ENABLE_CONFIG_02_0                       _MK_ADDR_CONST(0x12e40)
#define GPIO_R_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_R_ENABLE_CONFIG_02_0_DUAL                  0x0
#define GPIO_R_ENABLE_CONFIG_02_0_SCR                   GPIO_R_SCR_02_0
#define GPIO_R_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_R_ENABLE_CONFIG_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_R_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_R_ENABLE_CONFIG_02_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_R_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_R_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_R_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_R_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_R_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_R_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_R_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_R_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_R_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_02_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_02_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_R_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_R_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_R_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_R_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_R_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_R_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_R_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_R_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_R_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_R_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_R_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_R_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_R_DEBOUNCE_THRESHOLD_02_0
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0                  _MK_ADDR_CONST(0x12e44)
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_R_SCR_02_0
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_R_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_R_INPUT_02_0
#define GPIO_R_INPUT_02_0                       _MK_ADDR_CONST(0x12e48)
#define GPIO_R_INPUT_02_0_SECURE                        0x0
#define GPIO_R_INPUT_02_0_DUAL                  0x0
#define GPIO_R_INPUT_02_0_SCR                   GPIO_R_SCR_02_0
#define GPIO_R_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_R_INPUT_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_02_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_02_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_R_INPUT_02_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_02_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_R_INPUT_02_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_R_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_R_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_R_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_R_INPUT_02_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_02_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_R_OUTPUT_CONTROL_02_0
#define GPIO_R_OUTPUT_CONTROL_02_0                      _MK_ADDR_CONST(0x12e4c)
#define GPIO_R_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_R_OUTPUT_CONTROL_02_0_DUAL                         0x0
#define GPIO_R_OUTPUT_CONTROL_02_0_SCR                  GPIO_R_SCR_02_0
#define GPIO_R_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_R_OUTPUT_CONTROL_02_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_02_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_02_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_02_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_R_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_R_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_R_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_R_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_R_OUTPUT_VALUE_02_0
#define GPIO_R_OUTPUT_VALUE_02_0                        _MK_ADDR_CONST(0x12e50)
#define GPIO_R_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_R_OUTPUT_VALUE_02_0_DUAL                   0x0
#define GPIO_R_OUTPUT_VALUE_02_0_SCR                    GPIO_R_SCR_02_0
#define GPIO_R_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_R_OUTPUT_VALUE_02_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_02_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_02_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_02_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_R_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_R_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_R_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_R_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_R_INTERRUPT_CLEAR_02_0
#define GPIO_R_INTERRUPT_CLEAR_02_0                     _MK_ADDR_CONST(0x12e54)
#define GPIO_R_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_R_INTERRUPT_CLEAR_02_0_DUAL                        0x0
#define GPIO_R_INTERRUPT_CLEAR_02_0_SCR                         GPIO_R_SCR_02_0
#define GPIO_R_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_R_INTERRUPT_CLEAR_02_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_02_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_02_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_02_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_R_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_R_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_R_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_R_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_R_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x12e58

// Reserved address 0x12e5c

// Register GPIO_R_ENABLE_CONFIG_03_0
#define GPIO_R_ENABLE_CONFIG_03_0                       _MK_ADDR_CONST(0x12e60)
#define GPIO_R_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_R_ENABLE_CONFIG_03_0_DUAL                  0x0
#define GPIO_R_ENABLE_CONFIG_03_0_SCR                   GPIO_R_SCR_03_0
#define GPIO_R_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_R_ENABLE_CONFIG_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_R_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_R_ENABLE_CONFIG_03_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_R_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_R_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_R_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_R_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_R_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_R_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_R_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_R_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_R_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_03_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_03_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_R_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_R_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_R_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_R_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_R_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_R_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_R_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_R_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_R_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_R_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_R_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_R_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_R_DEBOUNCE_THRESHOLD_03_0
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0                  _MK_ADDR_CONST(0x12e64)
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_R_SCR_03_0
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_R_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_R_INPUT_03_0
#define GPIO_R_INPUT_03_0                       _MK_ADDR_CONST(0x12e68)
#define GPIO_R_INPUT_03_0_SECURE                        0x0
#define GPIO_R_INPUT_03_0_DUAL                  0x0
#define GPIO_R_INPUT_03_0_SCR                   GPIO_R_SCR_03_0
#define GPIO_R_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_R_INPUT_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_03_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_03_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_R_INPUT_03_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_03_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_R_INPUT_03_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_R_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_R_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_R_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_R_INPUT_03_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_03_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_R_OUTPUT_CONTROL_03_0
#define GPIO_R_OUTPUT_CONTROL_03_0                      _MK_ADDR_CONST(0x12e6c)
#define GPIO_R_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_R_OUTPUT_CONTROL_03_0_DUAL                         0x0
#define GPIO_R_OUTPUT_CONTROL_03_0_SCR                  GPIO_R_SCR_03_0
#define GPIO_R_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_R_OUTPUT_CONTROL_03_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_03_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_03_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_03_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_R_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_R_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_R_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_R_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_R_OUTPUT_VALUE_03_0
#define GPIO_R_OUTPUT_VALUE_03_0                        _MK_ADDR_CONST(0x12e70)
#define GPIO_R_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_R_OUTPUT_VALUE_03_0_DUAL                   0x0
#define GPIO_R_OUTPUT_VALUE_03_0_SCR                    GPIO_R_SCR_03_0
#define GPIO_R_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_R_OUTPUT_VALUE_03_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_03_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_03_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_03_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_R_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_R_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_R_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_R_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_R_INTERRUPT_CLEAR_03_0
#define GPIO_R_INTERRUPT_CLEAR_03_0                     _MK_ADDR_CONST(0x12e74)
#define GPIO_R_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_R_INTERRUPT_CLEAR_03_0_DUAL                        0x0
#define GPIO_R_INTERRUPT_CLEAR_03_0_SCR                         GPIO_R_SCR_03_0
#define GPIO_R_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_R_INTERRUPT_CLEAR_03_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_03_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_03_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_03_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_R_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_R_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_R_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_R_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_R_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x12e78

// Reserved address 0x12e7c

// Register GPIO_R_ENABLE_CONFIG_04_0
#define GPIO_R_ENABLE_CONFIG_04_0                       _MK_ADDR_CONST(0x12e80)
#define GPIO_R_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_R_ENABLE_CONFIG_04_0_DUAL                  0x0
#define GPIO_R_ENABLE_CONFIG_04_0_SCR                   GPIO_R_SCR_04_0
#define GPIO_R_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_R_ENABLE_CONFIG_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_R_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_R_ENABLE_CONFIG_04_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_R_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_R_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_R_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_R_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_R_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_R_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_R_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_R_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_R_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_04_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_04_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_R_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_R_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_R_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_R_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_R_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_R_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_R_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_R_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_R_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_R_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_R_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_R_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_R_DEBOUNCE_THRESHOLD_04_0
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0                  _MK_ADDR_CONST(0x12e84)
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_DUAL                     0x0
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_R_SCR_04_0
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_R_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_R_INPUT_04_0
#define GPIO_R_INPUT_04_0                       _MK_ADDR_CONST(0x12e88)
#define GPIO_R_INPUT_04_0_SECURE                        0x0
#define GPIO_R_INPUT_04_0_DUAL                  0x0
#define GPIO_R_INPUT_04_0_SCR                   GPIO_R_SCR_04_0
#define GPIO_R_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_R_INPUT_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_04_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_04_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_R_INPUT_04_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_04_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_R_INPUT_04_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_R_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_R_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_R_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_R_INPUT_04_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_04_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_R_OUTPUT_CONTROL_04_0
#define GPIO_R_OUTPUT_CONTROL_04_0                      _MK_ADDR_CONST(0x12e8c)
#define GPIO_R_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_R_OUTPUT_CONTROL_04_0_DUAL                         0x0
#define GPIO_R_OUTPUT_CONTROL_04_0_SCR                  GPIO_R_SCR_04_0
#define GPIO_R_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_R_OUTPUT_CONTROL_04_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_04_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_04_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_04_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_R_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_R_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_R_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_R_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_R_OUTPUT_VALUE_04_0
#define GPIO_R_OUTPUT_VALUE_04_0                        _MK_ADDR_CONST(0x12e90)
#define GPIO_R_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_R_OUTPUT_VALUE_04_0_DUAL                   0x0
#define GPIO_R_OUTPUT_VALUE_04_0_SCR                    GPIO_R_SCR_04_0
#define GPIO_R_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_R_OUTPUT_VALUE_04_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_04_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_04_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_04_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_R_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_R_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_R_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_R_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_R_INTERRUPT_CLEAR_04_0
#define GPIO_R_INTERRUPT_CLEAR_04_0                     _MK_ADDR_CONST(0x12e94)
#define GPIO_R_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_R_INTERRUPT_CLEAR_04_0_DUAL                        0x0
#define GPIO_R_INTERRUPT_CLEAR_04_0_SCR                         GPIO_R_SCR_04_0
#define GPIO_R_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_R_INTERRUPT_CLEAR_04_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_04_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_04_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_04_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_R_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_R_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_R_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_R_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_R_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x12e98

// Reserved address 0x12e9c

// Register GPIO_R_ENABLE_CONFIG_05_0
#define GPIO_R_ENABLE_CONFIG_05_0                       _MK_ADDR_CONST(0x12ea0)
#define GPIO_R_ENABLE_CONFIG_05_0_SECURE                        0x0
#define GPIO_R_ENABLE_CONFIG_05_0_DUAL                  0x0
#define GPIO_R_ENABLE_CONFIG_05_0_SCR                   GPIO_R_SCR_05_0
#define GPIO_R_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
#define GPIO_R_ENABLE_CONFIG_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_R_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_R_ENABLE_CONFIG_05_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_R_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_R_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_R_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_R_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_R_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_R_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_R_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
#define GPIO_R_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
#define GPIO_R_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_05_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_05_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_R_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_R_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_R_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_R_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_R_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_R_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_R_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_R_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_R_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_R_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_R_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_R_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_R_DEBOUNCE_THRESHOLD_05_0
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0                  _MK_ADDR_CONST(0x12ea4)
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_DUAL                     0x0
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_R_SCR_05_0
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_R_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_R_INPUT_05_0
#define GPIO_R_INPUT_05_0                       _MK_ADDR_CONST(0x12ea8)
#define GPIO_R_INPUT_05_0_SECURE                        0x0
#define GPIO_R_INPUT_05_0_DUAL                  0x0
#define GPIO_R_INPUT_05_0_SCR                   GPIO_R_SCR_05_0
#define GPIO_R_INPUT_05_0_WORD_COUNT                    0x1
#define GPIO_R_INPUT_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_05_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_05_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_R_INPUT_05_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_05_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_R_INPUT_05_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_R_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_R_INPUT_05_0_GPIO_IN_RANGE                 0:0
#define GPIO_R_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_R_INPUT_05_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_05_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_R_OUTPUT_CONTROL_05_0
#define GPIO_R_OUTPUT_CONTROL_05_0                      _MK_ADDR_CONST(0x12eac)
#define GPIO_R_OUTPUT_CONTROL_05_0_SECURE                       0x0
#define GPIO_R_OUTPUT_CONTROL_05_0_DUAL                         0x0
#define GPIO_R_OUTPUT_CONTROL_05_0_SCR                  GPIO_R_SCR_05_0
#define GPIO_R_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
#define GPIO_R_OUTPUT_CONTROL_05_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_05_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_05_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_05_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_R_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_R_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_R_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_R_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_R_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_R_OUTPUT_VALUE_05_0
#define GPIO_R_OUTPUT_VALUE_05_0                        _MK_ADDR_CONST(0x12eb0)
#define GPIO_R_OUTPUT_VALUE_05_0_SECURE                         0x0
#define GPIO_R_OUTPUT_VALUE_05_0_DUAL                   0x0
#define GPIO_R_OUTPUT_VALUE_05_0_SCR                    GPIO_R_SCR_05_0
#define GPIO_R_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
#define GPIO_R_OUTPUT_VALUE_05_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_05_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_05_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_05_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_R_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_R_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_R_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_R_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_R_INTERRUPT_CLEAR_05_0
#define GPIO_R_INTERRUPT_CLEAR_05_0                     _MK_ADDR_CONST(0x12eb4)
#define GPIO_R_INTERRUPT_CLEAR_05_0_SECURE                      0x0
#define GPIO_R_INTERRUPT_CLEAR_05_0_DUAL                        0x0
#define GPIO_R_INTERRUPT_CLEAR_05_0_SCR                         GPIO_R_SCR_05_0
#define GPIO_R_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
#define GPIO_R_INTERRUPT_CLEAR_05_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_05_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_05_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_05_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_R_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_R_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_R_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_R_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_R_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x12eb8

// Reserved address 0x12ebc

// Reserved address 0x12ec0

// Reserved address 0x12ec4

// Reserved address 0x12ec8

// Reserved address 0x12ecc

// Reserved address 0x12ed0

// Reserved address 0x12ed4

// Reserved address 0x12ed8

// Reserved address 0x12edc

// Reserved address 0x12ee0

// Reserved address 0x12ee4

// Reserved address 0x12ee8

// Reserved address 0x12eec

// Reserved address 0x12ef0

// Reserved address 0x12ef4

// Reserved address 0x12ef8

// Reserved address 0x12efc

// Register GPIO_R_INTERRUPT_STATUS_G0_0
#define GPIO_R_INTERRUPT_STATUS_G0_0                    _MK_ADDR_CONST(0x12f00)
#define GPIO_R_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_R_INTERRUPT_STATUS_G0_0_DUAL                       0x0
#define GPIO_R_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_R_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_R_INTERRUPT_STATUS_G0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G0_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G0_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_R_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_R_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_R_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_R_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_R_INTERRUPT_STATUS_G1_0
#define GPIO_R_INTERRUPT_STATUS_G1_0                    _MK_ADDR_CONST(0x12f04)
#define GPIO_R_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_R_INTERRUPT_STATUS_G1_0_DUAL                       0x0
#define GPIO_R_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_R_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_R_INTERRUPT_STATUS_G1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G1_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G1_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_R_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_R_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_R_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_R_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_R_INTERRUPT_STATUS_G2_0
#define GPIO_R_INTERRUPT_STATUS_G2_0                    _MK_ADDR_CONST(0x12f08)
#define GPIO_R_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_R_INTERRUPT_STATUS_G2_0_DUAL                       0x0
#define GPIO_R_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_R_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_R_INTERRUPT_STATUS_G2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G2_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G2_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G2_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_R_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_R_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_R_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_R_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_R_INTERRUPT_STATUS_G3_0
#define GPIO_R_INTERRUPT_STATUS_G3_0                    _MK_ADDR_CONST(0x12f0c)
#define GPIO_R_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_R_INTERRUPT_STATUS_G3_0_DUAL                       0x0
#define GPIO_R_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_R_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_R_INTERRUPT_STATUS_G3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G3_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G3_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G3_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_R_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_R_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_R_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_R_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_R_INTERRUPT_STATUS_G4_0
#define GPIO_R_INTERRUPT_STATUS_G4_0                    _MK_ADDR_CONST(0x12f10)
#define GPIO_R_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_R_INTERRUPT_STATUS_G4_0_DUAL                       0x0
#define GPIO_R_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_R_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_R_INTERRUPT_STATUS_G4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G4_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G4_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G4_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_R_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_R_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_R_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_R_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_R_INTERRUPT_STATUS_G5_0
#define GPIO_R_INTERRUPT_STATUS_G5_0                    _MK_ADDR_CONST(0x12f14)
#define GPIO_R_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_R_INTERRUPT_STATUS_G5_0_DUAL                       0x0
#define GPIO_R_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_R_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_R_INTERRUPT_STATUS_G5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G5_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G5_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G5_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_R_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_R_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_R_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_R_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_R_INTERRUPT_STATUS_G6_0
#define GPIO_R_INTERRUPT_STATUS_G6_0                    _MK_ADDR_CONST(0x12f18)
#define GPIO_R_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_R_INTERRUPT_STATUS_G6_0_DUAL                       0x0
#define GPIO_R_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_R_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_R_INTERRUPT_STATUS_G6_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G6_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G6_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G6_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_R_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_R_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_R_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_R_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_R_INTERRUPT_STATUS_G7_0
#define GPIO_R_INTERRUPT_STATUS_G7_0                    _MK_ADDR_CONST(0x12f1c)
#define GPIO_R_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_R_INTERRUPT_STATUS_G7_0_DUAL                       0x0
#define GPIO_R_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_R_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_R_INTERRUPT_STATUS_G7_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G7_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G7_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G7_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_R_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_R_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_R_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_R_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Reserved address 0x12f20

// Reserved address 0x12f24

// Reserved address 0x12f28

// Reserved address 0x12f2c

// Reserved address 0x12f30

// Reserved address 0x12f34

// Reserved address 0x12f38

// Reserved address 0x12f3c

// Reserved address 0x12f40

// Reserved address 0x12f44

// Reserved address 0x12f48

// Reserved address 0x12f4c

// Reserved address 0x12f50

// Reserved address 0x12f54

// Reserved address 0x12f58

// Reserved address 0x12f5c

// Reserved address 0x12f60

// Reserved address 0x12f64

// Reserved address 0x12f68

// Reserved address 0x12f6c

// Reserved address 0x12f70

// Reserved address 0x12f74

// Reserved address 0x12f78

// Reserved address 0x12f7c

// Reserved address 0x12f80

// Reserved address 0x12f84

// Reserved address 0x12f88

// Reserved address 0x12f8c

// Reserved address 0x12f90

// Reserved address 0x12f94

// Reserved address 0x12f98

// Reserved address 0x12f9c

// Reserved address 0x12fa0

// Reserved address 0x12fa4

// Reserved address 0x12fa8

// Reserved address 0x12fac

// Reserved address 0x12fb0

// Reserved address 0x12fb4

// Reserved address 0x12fb8

// Reserved address 0x12fbc

// Reserved address 0x12fc0

// Reserved address 0x12fc4

// Reserved address 0x12fc8

// Reserved address 0x12fcc

// Reserved address 0x12fd0

// Reserved address 0x12fd4

// Reserved address 0x12fd8

// Reserved address 0x12fdc

// Reserved address 0x12fe0

// Reserved address 0x12fe4

// Reserved address 0x12fe8

// Reserved address 0x12fec

// Reserved address 0x12ff0

// Reserved address 0x12ff4

// Reserved address 0x12ff8

// Reserved address 0x12ffc

// Register GPIO_K_ENABLE_CONFIG_00_0
#define GPIO_K_ENABLE_CONFIG_00_0                       _MK_ADDR_CONST(0x13000)
#define GPIO_K_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_K_ENABLE_CONFIG_00_0_DUAL                  0x0
#define GPIO_K_ENABLE_CONFIG_00_0_SCR                   GPIO_K_SCR_00_0
#define GPIO_K_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_K_ENABLE_CONFIG_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_K_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_K_ENABLE_CONFIG_00_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_K_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_K_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_K_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_K_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_K_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_K_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_K_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_K_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_K_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_00_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_00_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_K_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_K_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_K_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_K_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_K_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_K_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_K_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_K_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_K_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_K_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_K_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_K_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_K_DEBOUNCE_THRESHOLD_00_0
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0                  _MK_ADDR_CONST(0x13004)
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_K_SCR_00_0
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_K_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_K_INPUT_00_0
#define GPIO_K_INPUT_00_0                       _MK_ADDR_CONST(0x13008)
#define GPIO_K_INPUT_00_0_SECURE                        0x0
#define GPIO_K_INPUT_00_0_DUAL                  0x0
#define GPIO_K_INPUT_00_0_SCR                   GPIO_K_SCR_00_0
#define GPIO_K_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_K_INPUT_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_00_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_00_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_K_INPUT_00_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_00_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_K_INPUT_00_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_K_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_K_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_K_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_K_INPUT_00_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_00_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_K_OUTPUT_CONTROL_00_0
#define GPIO_K_OUTPUT_CONTROL_00_0                      _MK_ADDR_CONST(0x1300c)
#define GPIO_K_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_K_OUTPUT_CONTROL_00_0_DUAL                         0x0
#define GPIO_K_OUTPUT_CONTROL_00_0_SCR                  GPIO_K_SCR_00_0
#define GPIO_K_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_K_OUTPUT_CONTROL_00_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_00_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_00_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_00_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_K_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_K_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_K_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_K_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_K_OUTPUT_VALUE_00_0
#define GPIO_K_OUTPUT_VALUE_00_0                        _MK_ADDR_CONST(0x13010)
#define GPIO_K_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_K_OUTPUT_VALUE_00_0_DUAL                   0x0
#define GPIO_K_OUTPUT_VALUE_00_0_SCR                    GPIO_K_SCR_00_0
#define GPIO_K_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_K_OUTPUT_VALUE_00_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_00_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_00_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_00_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_K_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_K_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_K_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_K_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_K_INTERRUPT_CLEAR_00_0
#define GPIO_K_INTERRUPT_CLEAR_00_0                     _MK_ADDR_CONST(0x13014)
#define GPIO_K_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_K_INTERRUPT_CLEAR_00_0_DUAL                        0x0
#define GPIO_K_INTERRUPT_CLEAR_00_0_SCR                         GPIO_K_SCR_00_0
#define GPIO_K_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_K_INTERRUPT_CLEAR_00_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_00_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_00_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_00_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_K_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_K_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_K_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_K_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_K_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x13018

// Reserved address 0x1301c

// Register GPIO_K_ENABLE_CONFIG_01_0
#define GPIO_K_ENABLE_CONFIG_01_0                       _MK_ADDR_CONST(0x13020)
#define GPIO_K_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_K_ENABLE_CONFIG_01_0_DUAL                  0x0
#define GPIO_K_ENABLE_CONFIG_01_0_SCR                   GPIO_K_SCR_01_0
#define GPIO_K_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_K_ENABLE_CONFIG_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_K_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_K_ENABLE_CONFIG_01_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_K_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_K_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_K_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_K_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_K_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_K_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_K_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_K_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_K_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_01_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_01_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_K_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_K_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_K_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_K_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_K_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_K_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_K_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_K_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_K_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_K_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_K_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_K_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_K_DEBOUNCE_THRESHOLD_01_0
#define GPIO_K_DEBOUNCE_THRESHOLD_01_0                  _MK_ADDR_CONST(0x13024)
#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_K_SCR_01_0
#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_K_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_K_INPUT_01_0
#define GPIO_K_INPUT_01_0                       _MK_ADDR_CONST(0x13028)
#define GPIO_K_INPUT_01_0_SECURE                        0x0
#define GPIO_K_INPUT_01_0_DUAL                  0x0
#define GPIO_K_INPUT_01_0_SCR                   GPIO_K_SCR_01_0
#define GPIO_K_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_K_INPUT_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_01_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_01_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_K_INPUT_01_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_01_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_K_INPUT_01_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_K_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_K_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_K_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_K_INPUT_01_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_01_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_K_OUTPUT_CONTROL_01_0
#define GPIO_K_OUTPUT_CONTROL_01_0                      _MK_ADDR_CONST(0x1302c)
#define GPIO_K_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_K_OUTPUT_CONTROL_01_0_DUAL                         0x0
#define GPIO_K_OUTPUT_CONTROL_01_0_SCR                  GPIO_K_SCR_01_0
#define GPIO_K_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_K_OUTPUT_CONTROL_01_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_01_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_01_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_01_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_K_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_K_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_K_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_K_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_K_OUTPUT_VALUE_01_0
#define GPIO_K_OUTPUT_VALUE_01_0                        _MK_ADDR_CONST(0x13030)
#define GPIO_K_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_K_OUTPUT_VALUE_01_0_DUAL                   0x0
#define GPIO_K_OUTPUT_VALUE_01_0_SCR                    GPIO_K_SCR_01_0
#define GPIO_K_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_K_OUTPUT_VALUE_01_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_01_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_01_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_01_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_K_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_K_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_K_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_K_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_K_INTERRUPT_CLEAR_01_0
#define GPIO_K_INTERRUPT_CLEAR_01_0                     _MK_ADDR_CONST(0x13034)
#define GPIO_K_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_K_INTERRUPT_CLEAR_01_0_DUAL                        0x0
#define GPIO_K_INTERRUPT_CLEAR_01_0_SCR                         GPIO_K_SCR_01_0
#define GPIO_K_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_K_INTERRUPT_CLEAR_01_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_01_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_01_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_01_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_K_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_K_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_K_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_K_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_K_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x13038

// Reserved address 0x1303c

// Register GPIO_K_ENABLE_CONFIG_02_0
#define GPIO_K_ENABLE_CONFIG_02_0                       _MK_ADDR_CONST(0x13040)
#define GPIO_K_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_K_ENABLE_CONFIG_02_0_DUAL                  0x0
#define GPIO_K_ENABLE_CONFIG_02_0_SCR                   GPIO_K_SCR_02_0
#define GPIO_K_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_K_ENABLE_CONFIG_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_K_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_K_ENABLE_CONFIG_02_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_K_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_K_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_K_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_K_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_K_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_K_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_K_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_K_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_K_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_02_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_02_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_K_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_K_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_K_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_K_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_K_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_K_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_K_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_K_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_K_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_K_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_K_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_K_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_K_DEBOUNCE_THRESHOLD_02_0
#define GPIO_K_DEBOUNCE_THRESHOLD_02_0                  _MK_ADDR_CONST(0x13044)
#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_K_SCR_02_0
#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_K_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_K_INPUT_02_0
#define GPIO_K_INPUT_02_0                       _MK_ADDR_CONST(0x13048)
#define GPIO_K_INPUT_02_0_SECURE                        0x0
#define GPIO_K_INPUT_02_0_DUAL                  0x0
#define GPIO_K_INPUT_02_0_SCR                   GPIO_K_SCR_02_0
#define GPIO_K_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_K_INPUT_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_02_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_02_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_K_INPUT_02_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_02_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_K_INPUT_02_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_K_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_K_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_K_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_K_INPUT_02_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_02_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_K_OUTPUT_CONTROL_02_0
#define GPIO_K_OUTPUT_CONTROL_02_0                      _MK_ADDR_CONST(0x1304c)
#define GPIO_K_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_K_OUTPUT_CONTROL_02_0_DUAL                         0x0
#define GPIO_K_OUTPUT_CONTROL_02_0_SCR                  GPIO_K_SCR_02_0
#define GPIO_K_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_K_OUTPUT_CONTROL_02_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_02_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_02_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_02_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_K_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_K_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_K_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_K_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_K_OUTPUT_VALUE_02_0
#define GPIO_K_OUTPUT_VALUE_02_0                        _MK_ADDR_CONST(0x13050)
#define GPIO_K_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_K_OUTPUT_VALUE_02_0_DUAL                   0x0
#define GPIO_K_OUTPUT_VALUE_02_0_SCR                    GPIO_K_SCR_02_0
#define GPIO_K_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_K_OUTPUT_VALUE_02_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_02_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_02_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_02_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_K_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_K_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_K_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_K_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_K_INTERRUPT_CLEAR_02_0
#define GPIO_K_INTERRUPT_CLEAR_02_0                     _MK_ADDR_CONST(0x13054)
#define GPIO_K_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_K_INTERRUPT_CLEAR_02_0_DUAL                        0x0
#define GPIO_K_INTERRUPT_CLEAR_02_0_SCR                         GPIO_K_SCR_02_0
#define GPIO_K_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_K_INTERRUPT_CLEAR_02_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_02_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_02_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_02_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_K_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_K_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_K_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_K_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_K_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x13058

// Reserved address 0x1305c

// Register GPIO_K_ENABLE_CONFIG_03_0
#define GPIO_K_ENABLE_CONFIG_03_0                       _MK_ADDR_CONST(0x13060)
#define GPIO_K_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_K_ENABLE_CONFIG_03_0_DUAL                  0x0
#define GPIO_K_ENABLE_CONFIG_03_0_SCR                   GPIO_K_SCR_03_0
#define GPIO_K_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_K_ENABLE_CONFIG_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_K_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_K_ENABLE_CONFIG_03_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_K_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_K_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_K_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_K_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_K_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_K_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_K_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_K_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_K_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_03_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_03_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_K_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_K_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_K_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_K_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_K_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_K_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_K_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_K_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_K_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_K_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_K_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_K_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_K_DEBOUNCE_THRESHOLD_03_0
#define GPIO_K_DEBOUNCE_THRESHOLD_03_0                  _MK_ADDR_CONST(0x13064)
#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_K_SCR_03_0
#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_K_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_K_INPUT_03_0
#define GPIO_K_INPUT_03_0                       _MK_ADDR_CONST(0x13068)
#define GPIO_K_INPUT_03_0_SECURE                        0x0
#define GPIO_K_INPUT_03_0_DUAL                  0x0
#define GPIO_K_INPUT_03_0_SCR                   GPIO_K_SCR_03_0
#define GPIO_K_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_K_INPUT_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_03_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_03_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_K_INPUT_03_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_03_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_K_INPUT_03_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_K_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_K_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_K_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_K_INPUT_03_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_03_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_K_OUTPUT_CONTROL_03_0
#define GPIO_K_OUTPUT_CONTROL_03_0                      _MK_ADDR_CONST(0x1306c)
#define GPIO_K_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_K_OUTPUT_CONTROL_03_0_DUAL                         0x0
#define GPIO_K_OUTPUT_CONTROL_03_0_SCR                  GPIO_K_SCR_03_0
#define GPIO_K_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_K_OUTPUT_CONTROL_03_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_03_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_03_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_03_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_K_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_K_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_K_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_K_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_K_OUTPUT_VALUE_03_0
#define GPIO_K_OUTPUT_VALUE_03_0                        _MK_ADDR_CONST(0x13070)
#define GPIO_K_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_K_OUTPUT_VALUE_03_0_DUAL                   0x0
#define GPIO_K_OUTPUT_VALUE_03_0_SCR                    GPIO_K_SCR_03_0
#define GPIO_K_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_K_OUTPUT_VALUE_03_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_03_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_03_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_03_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_K_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_K_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_K_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_K_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_K_INTERRUPT_CLEAR_03_0
#define GPIO_K_INTERRUPT_CLEAR_03_0                     _MK_ADDR_CONST(0x13074)
#define GPIO_K_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_K_INTERRUPT_CLEAR_03_0_DUAL                        0x0
#define GPIO_K_INTERRUPT_CLEAR_03_0_SCR                         GPIO_K_SCR_03_0
#define GPIO_K_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_K_INTERRUPT_CLEAR_03_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_03_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_03_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_03_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_K_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_K_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_K_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_K_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_K_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x13078

// Reserved address 0x1307c

// Register GPIO_K_ENABLE_CONFIG_04_0
#define GPIO_K_ENABLE_CONFIG_04_0                       _MK_ADDR_CONST(0x13080)
#define GPIO_K_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_K_ENABLE_CONFIG_04_0_DUAL                  0x0
#define GPIO_K_ENABLE_CONFIG_04_0_SCR                   GPIO_K_SCR_04_0
#define GPIO_K_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_K_ENABLE_CONFIG_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_K_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_K_ENABLE_CONFIG_04_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_K_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_K_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_K_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_K_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_K_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_K_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_K_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_K_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_K_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_04_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_04_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_K_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_K_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_K_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_K_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_K_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_K_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_K_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_K_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_K_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_K_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_K_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_K_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_K_DEBOUNCE_THRESHOLD_04_0
#define GPIO_K_DEBOUNCE_THRESHOLD_04_0                  _MK_ADDR_CONST(0x13084)
#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_DUAL                     0x0
#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_K_SCR_04_0
#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_K_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_K_INPUT_04_0
#define GPIO_K_INPUT_04_0                       _MK_ADDR_CONST(0x13088)
#define GPIO_K_INPUT_04_0_SECURE                        0x0
#define GPIO_K_INPUT_04_0_DUAL                  0x0
#define GPIO_K_INPUT_04_0_SCR                   GPIO_K_SCR_04_0
#define GPIO_K_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_K_INPUT_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_04_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_04_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_K_INPUT_04_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_04_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_K_INPUT_04_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_K_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_K_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_K_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_K_INPUT_04_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_04_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_K_OUTPUT_CONTROL_04_0
#define GPIO_K_OUTPUT_CONTROL_04_0                      _MK_ADDR_CONST(0x1308c)
#define GPIO_K_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_K_OUTPUT_CONTROL_04_0_DUAL                         0x0
#define GPIO_K_OUTPUT_CONTROL_04_0_SCR                  GPIO_K_SCR_04_0
#define GPIO_K_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_K_OUTPUT_CONTROL_04_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_04_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_04_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_04_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_K_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_K_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_K_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_K_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_K_OUTPUT_VALUE_04_0
#define GPIO_K_OUTPUT_VALUE_04_0                        _MK_ADDR_CONST(0x13090)
#define GPIO_K_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_K_OUTPUT_VALUE_04_0_DUAL                   0x0
#define GPIO_K_OUTPUT_VALUE_04_0_SCR                    GPIO_K_SCR_04_0
#define GPIO_K_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_K_OUTPUT_VALUE_04_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_04_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_04_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_04_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_K_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_K_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_K_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_K_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_K_INTERRUPT_CLEAR_04_0
#define GPIO_K_INTERRUPT_CLEAR_04_0                     _MK_ADDR_CONST(0x13094)
#define GPIO_K_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_K_INTERRUPT_CLEAR_04_0_DUAL                        0x0
#define GPIO_K_INTERRUPT_CLEAR_04_0_SCR                         GPIO_K_SCR_04_0
#define GPIO_K_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_K_INTERRUPT_CLEAR_04_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_04_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_04_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_04_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_K_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_K_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_K_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_K_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_K_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x13098

// Reserved address 0x1309c

// Register GPIO_K_ENABLE_CONFIG_05_0
#define GPIO_K_ENABLE_CONFIG_05_0                       _MK_ADDR_CONST(0x130a0)
#define GPIO_K_ENABLE_CONFIG_05_0_SECURE                        0x0
#define GPIO_K_ENABLE_CONFIG_05_0_DUAL                  0x0
#define GPIO_K_ENABLE_CONFIG_05_0_SCR                   GPIO_K_SCR_05_0
#define GPIO_K_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
#define GPIO_K_ENABLE_CONFIG_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_K_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_K_ENABLE_CONFIG_05_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_K_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_K_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_K_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_K_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_K_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_K_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_K_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
#define GPIO_K_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
#define GPIO_K_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_05_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_05_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_K_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_K_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_K_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_K_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_K_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_K_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_K_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_K_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_K_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_K_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_K_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_K_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_K_DEBOUNCE_THRESHOLD_05_0
#define GPIO_K_DEBOUNCE_THRESHOLD_05_0                  _MK_ADDR_CONST(0x130a4)
#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_DUAL                     0x0
#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_K_SCR_05_0
#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_K_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_K_INPUT_05_0
#define GPIO_K_INPUT_05_0                       _MK_ADDR_CONST(0x130a8)
#define GPIO_K_INPUT_05_0_SECURE                        0x0
#define GPIO_K_INPUT_05_0_DUAL                  0x0
#define GPIO_K_INPUT_05_0_SCR                   GPIO_K_SCR_05_0
#define GPIO_K_INPUT_05_0_WORD_COUNT                    0x1
#define GPIO_K_INPUT_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_05_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_05_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_K_INPUT_05_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_05_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_K_INPUT_05_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_K_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_K_INPUT_05_0_GPIO_IN_RANGE                 0:0
#define GPIO_K_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_K_INPUT_05_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_05_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_K_OUTPUT_CONTROL_05_0
#define GPIO_K_OUTPUT_CONTROL_05_0                      _MK_ADDR_CONST(0x130ac)
#define GPIO_K_OUTPUT_CONTROL_05_0_SECURE                       0x0
#define GPIO_K_OUTPUT_CONTROL_05_0_DUAL                         0x0
#define GPIO_K_OUTPUT_CONTROL_05_0_SCR                  GPIO_K_SCR_05_0
#define GPIO_K_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
#define GPIO_K_OUTPUT_CONTROL_05_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_05_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_05_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_05_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_K_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_K_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_K_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_K_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_K_OUTPUT_VALUE_05_0
#define GPIO_K_OUTPUT_VALUE_05_0                        _MK_ADDR_CONST(0x130b0)
#define GPIO_K_OUTPUT_VALUE_05_0_SECURE                         0x0
#define GPIO_K_OUTPUT_VALUE_05_0_DUAL                   0x0
#define GPIO_K_OUTPUT_VALUE_05_0_SCR                    GPIO_K_SCR_05_0
#define GPIO_K_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
#define GPIO_K_OUTPUT_VALUE_05_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_05_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_05_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_05_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_K_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_K_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_K_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_K_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_K_INTERRUPT_CLEAR_05_0
#define GPIO_K_INTERRUPT_CLEAR_05_0                     _MK_ADDR_CONST(0x130b4)
#define GPIO_K_INTERRUPT_CLEAR_05_0_SECURE                      0x0
#define GPIO_K_INTERRUPT_CLEAR_05_0_DUAL                        0x0
#define GPIO_K_INTERRUPT_CLEAR_05_0_SCR                         GPIO_K_SCR_05_0
#define GPIO_K_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
#define GPIO_K_INTERRUPT_CLEAR_05_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_05_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_05_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_05_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_K_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_K_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_K_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_K_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_K_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x130b8

// Reserved address 0x130bc

// Register GPIO_K_ENABLE_CONFIG_06_0
#define GPIO_K_ENABLE_CONFIG_06_0                       _MK_ADDR_CONST(0x130c0)
#define GPIO_K_ENABLE_CONFIG_06_0_SECURE                        0x0
#define GPIO_K_ENABLE_CONFIG_06_0_DUAL                  0x0
#define GPIO_K_ENABLE_CONFIG_06_0_SCR                   GPIO_K_SCR_06_0
#define GPIO_K_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
#define GPIO_K_ENABLE_CONFIG_06_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_K_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_K_ENABLE_CONFIG_06_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_K_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_K_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
#define GPIO_K_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_K_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_K_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_K_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
#define GPIO_K_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
#define GPIO_K_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
#define GPIO_K_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_06_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_06_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_K_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_K_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_K_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_K_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_K_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_K_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_K_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_K_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_K_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_K_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_K_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_K_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_K_DEBOUNCE_THRESHOLD_06_0
#define GPIO_K_DEBOUNCE_THRESHOLD_06_0                  _MK_ADDR_CONST(0x130c4)
#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_DUAL                     0x0
#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_K_SCR_06_0
#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_K_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_K_INPUT_06_0
#define GPIO_K_INPUT_06_0                       _MK_ADDR_CONST(0x130c8)
#define GPIO_K_INPUT_06_0_SECURE                        0x0
#define GPIO_K_INPUT_06_0_DUAL                  0x0
#define GPIO_K_INPUT_06_0_SCR                   GPIO_K_SCR_06_0
#define GPIO_K_INPUT_06_0_WORD_COUNT                    0x1
#define GPIO_K_INPUT_06_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_06_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_06_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_06_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_06_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_K_INPUT_06_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_06_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_K_INPUT_06_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_K_INPUT_06_0_GPIO_IN_SHIFT)
#define GPIO_K_INPUT_06_0_GPIO_IN_RANGE                 0:0
#define GPIO_K_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_K_INPUT_06_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_06_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_06_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_06_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_K_OUTPUT_CONTROL_06_0
#define GPIO_K_OUTPUT_CONTROL_06_0                      _MK_ADDR_CONST(0x130cc)
#define GPIO_K_OUTPUT_CONTROL_06_0_SECURE                       0x0
#define GPIO_K_OUTPUT_CONTROL_06_0_DUAL                         0x0
#define GPIO_K_OUTPUT_CONTROL_06_0_SCR                  GPIO_K_SCR_06_0
#define GPIO_K_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
#define GPIO_K_OUTPUT_CONTROL_06_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_06_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_06_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_06_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_K_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_K_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_K_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_K_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_K_OUTPUT_VALUE_06_0
#define GPIO_K_OUTPUT_VALUE_06_0                        _MK_ADDR_CONST(0x130d0)
#define GPIO_K_OUTPUT_VALUE_06_0_SECURE                         0x0
#define GPIO_K_OUTPUT_VALUE_06_0_DUAL                   0x0
#define GPIO_K_OUTPUT_VALUE_06_0_SCR                    GPIO_K_SCR_06_0
#define GPIO_K_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
#define GPIO_K_OUTPUT_VALUE_06_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_06_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_06_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_06_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_K_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_K_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_K_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_K_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_K_INTERRUPT_CLEAR_06_0
#define GPIO_K_INTERRUPT_CLEAR_06_0                     _MK_ADDR_CONST(0x130d4)
#define GPIO_K_INTERRUPT_CLEAR_06_0_SECURE                      0x0
#define GPIO_K_INTERRUPT_CLEAR_06_0_DUAL                        0x0
#define GPIO_K_INTERRUPT_CLEAR_06_0_SCR                         GPIO_K_SCR_06_0
#define GPIO_K_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
#define GPIO_K_INTERRUPT_CLEAR_06_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_06_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_06_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_06_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_K_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_K_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_K_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_K_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_K_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x130d8

// Reserved address 0x130dc

// Register GPIO_K_ENABLE_CONFIG_07_0
#define GPIO_K_ENABLE_CONFIG_07_0                       _MK_ADDR_CONST(0x130e0)
#define GPIO_K_ENABLE_CONFIG_07_0_SECURE                        0x0
#define GPIO_K_ENABLE_CONFIG_07_0_DUAL                  0x0
#define GPIO_K_ENABLE_CONFIG_07_0_SCR                   GPIO_K_SCR_07_0
#define GPIO_K_ENABLE_CONFIG_07_0_WORD_COUNT                    0x1
#define GPIO_K_ENABLE_CONFIG_07_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_K_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_K_ENABLE_CONFIG_07_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_K_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_K_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
#define GPIO_K_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_K_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_K_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_K_ENABLE_CONFIG_07_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
#define GPIO_K_ENABLE_CONFIG_07_0_IN_OUT_RANGE                  1:1
#define GPIO_K_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                        0x0
#define GPIO_K_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_07_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_07_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_K_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_K_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_K_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_K_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_K_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_K_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_K_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_K_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_K_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_K_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_K_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_K_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_K_DEBOUNCE_THRESHOLD_07_0
#define GPIO_K_DEBOUNCE_THRESHOLD_07_0                  _MK_ADDR_CONST(0x130e4)
#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_SECURE                   0x0
#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_DUAL                     0x0
#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_SCR                      GPIO_K_SCR_07_0
#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                       0x1
#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_K_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_K_INPUT_07_0
#define GPIO_K_INPUT_07_0                       _MK_ADDR_CONST(0x130e8)
#define GPIO_K_INPUT_07_0_SECURE                        0x0
#define GPIO_K_INPUT_07_0_DUAL                  0x0
#define GPIO_K_INPUT_07_0_SCR                   GPIO_K_SCR_07_0
#define GPIO_K_INPUT_07_0_WORD_COUNT                    0x1
#define GPIO_K_INPUT_07_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_07_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_07_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_07_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_07_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_K_INPUT_07_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_07_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_K_INPUT_07_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_K_INPUT_07_0_GPIO_IN_SHIFT)
#define GPIO_K_INPUT_07_0_GPIO_IN_RANGE                 0:0
#define GPIO_K_INPUT_07_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_K_INPUT_07_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_07_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_07_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_07_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_07_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_K_OUTPUT_CONTROL_07_0
#define GPIO_K_OUTPUT_CONTROL_07_0                      _MK_ADDR_CONST(0x130ec)
#define GPIO_K_OUTPUT_CONTROL_07_0_SECURE                       0x0
#define GPIO_K_OUTPUT_CONTROL_07_0_DUAL                         0x0
#define GPIO_K_OUTPUT_CONTROL_07_0_SCR                  GPIO_K_SCR_07_0
#define GPIO_K_OUTPUT_CONTROL_07_0_WORD_COUNT                   0x1
#define GPIO_K_OUTPUT_CONTROL_07_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_07_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_07_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_07_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_K_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_K_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_K_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_K_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_K_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_K_OUTPUT_VALUE_07_0
#define GPIO_K_OUTPUT_VALUE_07_0                        _MK_ADDR_CONST(0x130f0)
#define GPIO_K_OUTPUT_VALUE_07_0_SECURE                         0x0
#define GPIO_K_OUTPUT_VALUE_07_0_DUAL                   0x0
#define GPIO_K_OUTPUT_VALUE_07_0_SCR                    GPIO_K_SCR_07_0
#define GPIO_K_OUTPUT_VALUE_07_0_WORD_COUNT                     0x1
#define GPIO_K_OUTPUT_VALUE_07_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_07_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_07_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_07_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_K_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_K_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_K_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_K_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_K_INTERRUPT_CLEAR_07_0
#define GPIO_K_INTERRUPT_CLEAR_07_0                     _MK_ADDR_CONST(0x130f4)
#define GPIO_K_INTERRUPT_CLEAR_07_0_SECURE                      0x0
#define GPIO_K_INTERRUPT_CLEAR_07_0_DUAL                        0x0
#define GPIO_K_INTERRUPT_CLEAR_07_0_SCR                         GPIO_K_SCR_07_0
#define GPIO_K_INTERRUPT_CLEAR_07_0_WORD_COUNT                  0x1
#define GPIO_K_INTERRUPT_CLEAR_07_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_07_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_07_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_07_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_K_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_K_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_K_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_K_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_K_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x130f8

// Reserved address 0x130fc

// Register GPIO_K_INTERRUPT_STATUS_G0_0
#define GPIO_K_INTERRUPT_STATUS_G0_0                    _MK_ADDR_CONST(0x13100)
#define GPIO_K_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_K_INTERRUPT_STATUS_G0_0_DUAL                       0x0
#define GPIO_K_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_K_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_K_INTERRUPT_STATUS_G0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G0_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_K_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G0_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_K_INTERRUPT_STATUS_G0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_K_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_K_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_K_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_K_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_K_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_K_INTERRUPT_STATUS_G1_0
#define GPIO_K_INTERRUPT_STATUS_G1_0                    _MK_ADDR_CONST(0x13104)
#define GPIO_K_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_K_INTERRUPT_STATUS_G1_0_DUAL                       0x0
#define GPIO_K_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_K_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_K_INTERRUPT_STATUS_G1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G1_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_K_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G1_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_K_INTERRUPT_STATUS_G1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_K_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_K_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_K_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_K_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_K_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_K_INTERRUPT_STATUS_G2_0
#define GPIO_K_INTERRUPT_STATUS_G2_0                    _MK_ADDR_CONST(0x13108)
#define GPIO_K_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_K_INTERRUPT_STATUS_G2_0_DUAL                       0x0
#define GPIO_K_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_K_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_K_INTERRUPT_STATUS_G2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G2_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_K_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G2_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_K_INTERRUPT_STATUS_G2_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_K_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_K_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_K_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_K_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_K_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_K_INTERRUPT_STATUS_G3_0
#define GPIO_K_INTERRUPT_STATUS_G3_0                    _MK_ADDR_CONST(0x1310c)
#define GPIO_K_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_K_INTERRUPT_STATUS_G3_0_DUAL                       0x0
#define GPIO_K_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_K_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_K_INTERRUPT_STATUS_G3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G3_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_K_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G3_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_K_INTERRUPT_STATUS_G3_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_K_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_K_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_K_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_K_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_K_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_K_INTERRUPT_STATUS_G4_0
#define GPIO_K_INTERRUPT_STATUS_G4_0                    _MK_ADDR_CONST(0x13110)
#define GPIO_K_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_K_INTERRUPT_STATUS_G4_0_DUAL                       0x0
#define GPIO_K_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_K_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_K_INTERRUPT_STATUS_G4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G4_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_K_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G4_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_K_INTERRUPT_STATUS_G4_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_K_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_K_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_K_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_K_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_K_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_K_INTERRUPT_STATUS_G5_0
#define GPIO_K_INTERRUPT_STATUS_G5_0                    _MK_ADDR_CONST(0x13114)
#define GPIO_K_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_K_INTERRUPT_STATUS_G5_0_DUAL                       0x0
#define GPIO_K_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_K_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_K_INTERRUPT_STATUS_G5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G5_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_K_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G5_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_K_INTERRUPT_STATUS_G5_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_K_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_K_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_K_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_K_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_K_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_K_INTERRUPT_STATUS_G6_0
#define GPIO_K_INTERRUPT_STATUS_G6_0                    _MK_ADDR_CONST(0x13118)
#define GPIO_K_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_K_INTERRUPT_STATUS_G6_0_DUAL                       0x0
#define GPIO_K_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_K_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_K_INTERRUPT_STATUS_G6_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G6_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_K_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G6_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_K_INTERRUPT_STATUS_G6_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_K_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_K_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_K_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_K_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_K_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_K_INTERRUPT_STATUS_G7_0
#define GPIO_K_INTERRUPT_STATUS_G7_0                    _MK_ADDR_CONST(0x1311c)
#define GPIO_K_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_K_INTERRUPT_STATUS_G7_0_DUAL                       0x0
#define GPIO_K_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_K_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_K_INTERRUPT_STATUS_G7_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G7_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_K_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G7_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_K_INTERRUPT_STATUS_G7_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_K_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_K_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_K_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_K_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_K_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Reserved address 0x13120

// Reserved address 0x13124

// Reserved address 0x13128

// Reserved address 0x1312c

// Reserved address 0x13130

// Reserved address 0x13134

// Reserved address 0x13138

// Reserved address 0x1313c

// Reserved address 0x13140

// Reserved address 0x13144

// Reserved address 0x13148

// Reserved address 0x1314c

// Reserved address 0x13150

// Reserved address 0x13154

// Reserved address 0x13158

// Reserved address 0x1315c

// Reserved address 0x13160

// Reserved address 0x13164

// Reserved address 0x13168

// Reserved address 0x1316c

// Reserved address 0x13170

// Reserved address 0x13174

// Reserved address 0x13178

// Reserved address 0x1317c

// Reserved address 0x13180

// Reserved address 0x13184

// Reserved address 0x13188

// Reserved address 0x1318c

// Reserved address 0x13190

// Reserved address 0x13194

// Reserved address 0x13198

// Reserved address 0x1319c

// Reserved address 0x131a0

// Reserved address 0x131a4

// Reserved address 0x131a8

// Reserved address 0x131ac

// Reserved address 0x131b0

// Reserved address 0x131b4

// Reserved address 0x131b8

// Reserved address 0x131bc

// Reserved address 0x131c0

// Reserved address 0x131c4

// Reserved address 0x131c8

// Reserved address 0x131cc

// Reserved address 0x131d0

// Reserved address 0x131d4

// Reserved address 0x131d8

// Reserved address 0x131dc

// Reserved address 0x131e0

// Reserved address 0x131e4

// Reserved address 0x131e8

// Reserved address 0x131ec

// Reserved address 0x131f0

// Reserved address 0x131f4

// Reserved address 0x131f8

// Reserved address 0x131fc

// Register GPIO_L_ENABLE_CONFIG_00_0
#define GPIO_L_ENABLE_CONFIG_00_0                       _MK_ADDR_CONST(0x13200)
#define GPIO_L_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_L_ENABLE_CONFIG_00_0_DUAL                  0x0
#define GPIO_L_ENABLE_CONFIG_00_0_SCR                   GPIO_L_SCR_00_0
#define GPIO_L_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_L_ENABLE_CONFIG_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_L_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_L_ENABLE_CONFIG_00_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_L_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_L_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_L_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_L_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_L_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_L_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_L_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_L_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_L_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_00_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_00_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_L_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_L_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_L_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_L_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_L_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_L_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_L_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_L_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_L_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_L_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_L_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_L_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_L_DEBOUNCE_THRESHOLD_00_0
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0                  _MK_ADDR_CONST(0x13204)
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_L_SCR_00_0
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_L_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_L_INPUT_00_0
#define GPIO_L_INPUT_00_0                       _MK_ADDR_CONST(0x13208)
#define GPIO_L_INPUT_00_0_SECURE                        0x0
#define GPIO_L_INPUT_00_0_DUAL                  0x0
#define GPIO_L_INPUT_00_0_SCR                   GPIO_L_SCR_00_0
#define GPIO_L_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_L_INPUT_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_00_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_00_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_L_INPUT_00_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_00_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_L_INPUT_00_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_L_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_L_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_L_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_L_INPUT_00_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_00_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_L_OUTPUT_CONTROL_00_0
#define GPIO_L_OUTPUT_CONTROL_00_0                      _MK_ADDR_CONST(0x1320c)
#define GPIO_L_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_L_OUTPUT_CONTROL_00_0_DUAL                         0x0
#define GPIO_L_OUTPUT_CONTROL_00_0_SCR                  GPIO_L_SCR_00_0
#define GPIO_L_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_L_OUTPUT_CONTROL_00_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_00_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_00_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_00_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_L_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_L_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_L_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_L_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_L_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_L_OUTPUT_VALUE_00_0
#define GPIO_L_OUTPUT_VALUE_00_0                        _MK_ADDR_CONST(0x13210)
#define GPIO_L_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_L_OUTPUT_VALUE_00_0_DUAL                   0x0
#define GPIO_L_OUTPUT_VALUE_00_0_SCR                    GPIO_L_SCR_00_0
#define GPIO_L_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_L_OUTPUT_VALUE_00_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_00_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_00_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_00_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_L_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_L_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_L_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_L_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_L_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_L_INTERRUPT_CLEAR_00_0
#define GPIO_L_INTERRUPT_CLEAR_00_0                     _MK_ADDR_CONST(0x13214)
#define GPIO_L_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_L_INTERRUPT_CLEAR_00_0_DUAL                        0x0
#define GPIO_L_INTERRUPT_CLEAR_00_0_SCR                         GPIO_L_SCR_00_0
#define GPIO_L_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_L_INTERRUPT_CLEAR_00_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_00_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_00_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_00_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_L_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_L_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_L_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_L_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_L_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x13218

// Reserved address 0x1321c

// Register GPIO_L_ENABLE_CONFIG_01_0
#define GPIO_L_ENABLE_CONFIG_01_0                       _MK_ADDR_CONST(0x13220)
#define GPIO_L_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_L_ENABLE_CONFIG_01_0_DUAL                  0x0
#define GPIO_L_ENABLE_CONFIG_01_0_SCR                   GPIO_L_SCR_01_0
#define GPIO_L_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_L_ENABLE_CONFIG_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_L_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_L_ENABLE_CONFIG_01_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_L_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_L_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_L_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_L_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_L_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_L_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_L_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_L_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_L_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_01_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_01_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_L_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_L_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_L_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_L_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_L_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_L_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_L_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_L_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_L_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_L_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_L_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_L_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_L_DEBOUNCE_THRESHOLD_01_0
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0                  _MK_ADDR_CONST(0x13224)
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_L_SCR_01_0
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_L_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_L_INPUT_01_0
#define GPIO_L_INPUT_01_0                       _MK_ADDR_CONST(0x13228)
#define GPIO_L_INPUT_01_0_SECURE                        0x0
#define GPIO_L_INPUT_01_0_DUAL                  0x0
#define GPIO_L_INPUT_01_0_SCR                   GPIO_L_SCR_01_0
#define GPIO_L_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_L_INPUT_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_01_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_01_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_L_INPUT_01_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_01_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_L_INPUT_01_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_L_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_L_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_L_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_L_INPUT_01_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_01_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_L_OUTPUT_CONTROL_01_0
#define GPIO_L_OUTPUT_CONTROL_01_0                      _MK_ADDR_CONST(0x1322c)
#define GPIO_L_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_L_OUTPUT_CONTROL_01_0_DUAL                         0x0
#define GPIO_L_OUTPUT_CONTROL_01_0_SCR                  GPIO_L_SCR_01_0
#define GPIO_L_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_L_OUTPUT_CONTROL_01_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_01_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_01_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_01_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_L_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_L_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_L_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_L_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_L_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_L_OUTPUT_VALUE_01_0
#define GPIO_L_OUTPUT_VALUE_01_0                        _MK_ADDR_CONST(0x13230)
#define GPIO_L_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_L_OUTPUT_VALUE_01_0_DUAL                   0x0
#define GPIO_L_OUTPUT_VALUE_01_0_SCR                    GPIO_L_SCR_01_0
#define GPIO_L_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_L_OUTPUT_VALUE_01_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_01_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_01_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_01_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_L_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_L_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_L_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_L_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_L_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_L_INTERRUPT_CLEAR_01_0
#define GPIO_L_INTERRUPT_CLEAR_01_0                     _MK_ADDR_CONST(0x13234)
#define GPIO_L_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_L_INTERRUPT_CLEAR_01_0_DUAL                        0x0
#define GPIO_L_INTERRUPT_CLEAR_01_0_SCR                         GPIO_L_SCR_01_0
#define GPIO_L_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_L_INTERRUPT_CLEAR_01_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_01_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_01_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_01_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_L_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_L_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_L_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_L_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_L_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x13238

// Reserved address 0x1323c

// Register GPIO_L_ENABLE_CONFIG_02_0
#define GPIO_L_ENABLE_CONFIG_02_0                       _MK_ADDR_CONST(0x13240)
#define GPIO_L_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_L_ENABLE_CONFIG_02_0_DUAL                  0x0
#define GPIO_L_ENABLE_CONFIG_02_0_SCR                   GPIO_L_SCR_02_0
#define GPIO_L_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_L_ENABLE_CONFIG_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_L_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_L_ENABLE_CONFIG_02_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_L_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_L_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_L_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_L_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_L_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_L_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_L_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_L_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_L_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_02_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_02_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_L_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_L_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_L_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_L_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_L_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_L_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_L_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_L_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_L_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_L_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_L_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_L_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_L_DEBOUNCE_THRESHOLD_02_0
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0                  _MK_ADDR_CONST(0x13244)
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_L_SCR_02_0
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_L_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_L_INPUT_02_0
#define GPIO_L_INPUT_02_0                       _MK_ADDR_CONST(0x13248)
#define GPIO_L_INPUT_02_0_SECURE                        0x0
#define GPIO_L_INPUT_02_0_DUAL                  0x0
#define GPIO_L_INPUT_02_0_SCR                   GPIO_L_SCR_02_0
#define GPIO_L_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_L_INPUT_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_02_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_02_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_L_INPUT_02_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_02_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_L_INPUT_02_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_L_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_L_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_L_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_L_INPUT_02_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_02_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_L_OUTPUT_CONTROL_02_0
#define GPIO_L_OUTPUT_CONTROL_02_0                      _MK_ADDR_CONST(0x1324c)
#define GPIO_L_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_L_OUTPUT_CONTROL_02_0_DUAL                         0x0
#define GPIO_L_OUTPUT_CONTROL_02_0_SCR                  GPIO_L_SCR_02_0
#define GPIO_L_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_L_OUTPUT_CONTROL_02_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_02_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_02_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_02_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_L_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_L_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_L_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_L_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_L_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_L_OUTPUT_VALUE_02_0
#define GPIO_L_OUTPUT_VALUE_02_0                        _MK_ADDR_CONST(0x13250)
#define GPIO_L_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_L_OUTPUT_VALUE_02_0_DUAL                   0x0
#define GPIO_L_OUTPUT_VALUE_02_0_SCR                    GPIO_L_SCR_02_0
#define GPIO_L_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_L_OUTPUT_VALUE_02_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_02_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_02_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_02_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_L_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_L_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_L_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_L_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_L_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_L_INTERRUPT_CLEAR_02_0
#define GPIO_L_INTERRUPT_CLEAR_02_0                     _MK_ADDR_CONST(0x13254)
#define GPIO_L_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_L_INTERRUPT_CLEAR_02_0_DUAL                        0x0
#define GPIO_L_INTERRUPT_CLEAR_02_0_SCR                         GPIO_L_SCR_02_0
#define GPIO_L_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_L_INTERRUPT_CLEAR_02_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_02_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_02_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_02_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_L_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_L_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_L_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_L_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_L_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x13258

// Reserved address 0x1325c

// Register GPIO_L_ENABLE_CONFIG_03_0
#define GPIO_L_ENABLE_CONFIG_03_0                       _MK_ADDR_CONST(0x13260)
#define GPIO_L_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_L_ENABLE_CONFIG_03_0_DUAL                  0x0
#define GPIO_L_ENABLE_CONFIG_03_0_SCR                   GPIO_L_SCR_03_0
#define GPIO_L_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_L_ENABLE_CONFIG_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_L_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_L_ENABLE_CONFIG_03_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_L_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_L_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_L_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_L_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_L_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_L_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_L_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_L_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_L_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_03_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_03_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_L_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_L_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_L_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_L_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_L_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_L_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_L_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_L_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_L_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_L_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_L_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_L_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_L_DEBOUNCE_THRESHOLD_03_0
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0                  _MK_ADDR_CONST(0x13264)
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_L_SCR_03_0
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_L_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_L_INPUT_03_0
#define GPIO_L_INPUT_03_0                       _MK_ADDR_CONST(0x13268)
#define GPIO_L_INPUT_03_0_SECURE                        0x0
#define GPIO_L_INPUT_03_0_DUAL                  0x0
#define GPIO_L_INPUT_03_0_SCR                   GPIO_L_SCR_03_0
#define GPIO_L_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_L_INPUT_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_03_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_03_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_L_INPUT_03_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_03_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_L_INPUT_03_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_L_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_L_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_L_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_L_INPUT_03_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_03_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_L_OUTPUT_CONTROL_03_0
#define GPIO_L_OUTPUT_CONTROL_03_0                      _MK_ADDR_CONST(0x1326c)
#define GPIO_L_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_L_OUTPUT_CONTROL_03_0_DUAL                         0x0
#define GPIO_L_OUTPUT_CONTROL_03_0_SCR                  GPIO_L_SCR_03_0
#define GPIO_L_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_L_OUTPUT_CONTROL_03_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_03_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_03_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_03_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_L_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_L_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_L_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_L_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_L_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_L_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_L_OUTPUT_VALUE_03_0
#define GPIO_L_OUTPUT_VALUE_03_0                        _MK_ADDR_CONST(0x13270)
#define GPIO_L_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_L_OUTPUT_VALUE_03_0_DUAL                   0x0
#define GPIO_L_OUTPUT_VALUE_03_0_SCR                    GPIO_L_SCR_03_0
#define GPIO_L_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_L_OUTPUT_VALUE_03_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_03_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_03_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_03_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_L_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_L_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_L_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_L_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_L_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_L_INTERRUPT_CLEAR_03_0
#define GPIO_L_INTERRUPT_CLEAR_03_0                     _MK_ADDR_CONST(0x13274)
#define GPIO_L_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_L_INTERRUPT_CLEAR_03_0_DUAL                        0x0
#define GPIO_L_INTERRUPT_CLEAR_03_0_SCR                         GPIO_L_SCR_03_0
#define GPIO_L_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_L_INTERRUPT_CLEAR_03_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_03_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_03_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_03_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_L_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_L_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_L_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_L_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_L_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x13278

// Reserved address 0x1327c

// Reserved address 0x13280

// Reserved address 0x13284

// Reserved address 0x13288

// Reserved address 0x1328c

// Reserved address 0x13290

// Reserved address 0x13294

// Reserved address 0x13298

// Reserved address 0x1329c

// Reserved address 0x132a0

// Reserved address 0x132a4

// Reserved address 0x132a8

// Reserved address 0x132ac

// Reserved address 0x132b0

// Reserved address 0x132b4

// Reserved address 0x132b8

// Reserved address 0x132bc

// Reserved address 0x132c0

// Reserved address 0x132c4

// Reserved address 0x132c8

// Reserved address 0x132cc

// Reserved address 0x132d0

// Reserved address 0x132d4

// Reserved address 0x132d8

// Reserved address 0x132dc

// Reserved address 0x132e0

// Reserved address 0x132e4

// Reserved address 0x132e8

// Reserved address 0x132ec

// Reserved address 0x132f0

// Reserved address 0x132f4

// Reserved address 0x132f8

// Reserved address 0x132fc

// Register GPIO_L_INTERRUPT_STATUS_G0_0
#define GPIO_L_INTERRUPT_STATUS_G0_0                    _MK_ADDR_CONST(0x13300)
#define GPIO_L_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_L_INTERRUPT_STATUS_G0_0_DUAL                       0x0
#define GPIO_L_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_L_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_L_INTERRUPT_STATUS_G0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G0_0_RESET_MASK                         _MK_MASK_CONST(0xf)
#define GPIO_L_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G0_0_READ_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_L_INTERRUPT_STATUS_G0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xf, GPIO_L_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_L_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
#define GPIO_L_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_L_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define GPIO_L_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_L_INTERRUPT_STATUS_G1_0
#define GPIO_L_INTERRUPT_STATUS_G1_0                    _MK_ADDR_CONST(0x13304)
#define GPIO_L_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_L_INTERRUPT_STATUS_G1_0_DUAL                       0x0
#define GPIO_L_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_L_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_L_INTERRUPT_STATUS_G1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G1_0_RESET_MASK                         _MK_MASK_CONST(0xf)
#define GPIO_L_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G1_0_READ_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_L_INTERRUPT_STATUS_G1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xf, GPIO_L_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_L_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
#define GPIO_L_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_L_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define GPIO_L_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_L_INTERRUPT_STATUS_G2_0
#define GPIO_L_INTERRUPT_STATUS_G2_0                    _MK_ADDR_CONST(0x13308)
#define GPIO_L_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_L_INTERRUPT_STATUS_G2_0_DUAL                       0x0
#define GPIO_L_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_L_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_L_INTERRUPT_STATUS_G2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G2_0_RESET_MASK                         _MK_MASK_CONST(0xf)
#define GPIO_L_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G2_0_READ_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_L_INTERRUPT_STATUS_G2_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xf, GPIO_L_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_L_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
#define GPIO_L_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_L_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define GPIO_L_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_L_INTERRUPT_STATUS_G3_0
#define GPIO_L_INTERRUPT_STATUS_G3_0                    _MK_ADDR_CONST(0x1330c)
#define GPIO_L_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_L_INTERRUPT_STATUS_G3_0_DUAL                       0x0
#define GPIO_L_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_L_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_L_INTERRUPT_STATUS_G3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G3_0_RESET_MASK                         _MK_MASK_CONST(0xf)
#define GPIO_L_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G3_0_READ_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_L_INTERRUPT_STATUS_G3_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xf, GPIO_L_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_L_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
#define GPIO_L_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_L_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define GPIO_L_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_L_INTERRUPT_STATUS_G4_0
#define GPIO_L_INTERRUPT_STATUS_G4_0                    _MK_ADDR_CONST(0x13310)
#define GPIO_L_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_L_INTERRUPT_STATUS_G4_0_DUAL                       0x0
#define GPIO_L_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_L_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_L_INTERRUPT_STATUS_G4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G4_0_RESET_MASK                         _MK_MASK_CONST(0xf)
#define GPIO_L_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G4_0_READ_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_L_INTERRUPT_STATUS_G4_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xf, GPIO_L_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_L_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
#define GPIO_L_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_L_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define GPIO_L_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_L_INTERRUPT_STATUS_G5_0
#define GPIO_L_INTERRUPT_STATUS_G5_0                    _MK_ADDR_CONST(0x13314)
#define GPIO_L_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_L_INTERRUPT_STATUS_G5_0_DUAL                       0x0
#define GPIO_L_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_L_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_L_INTERRUPT_STATUS_G5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G5_0_RESET_MASK                         _MK_MASK_CONST(0xf)
#define GPIO_L_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G5_0_READ_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_L_INTERRUPT_STATUS_G5_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xf, GPIO_L_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_L_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
#define GPIO_L_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_L_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define GPIO_L_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_L_INTERRUPT_STATUS_G6_0
#define GPIO_L_INTERRUPT_STATUS_G6_0                    _MK_ADDR_CONST(0x13318)
#define GPIO_L_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_L_INTERRUPT_STATUS_G6_0_DUAL                       0x0
#define GPIO_L_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_L_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_L_INTERRUPT_STATUS_G6_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G6_0_RESET_MASK                         _MK_MASK_CONST(0xf)
#define GPIO_L_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G6_0_READ_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_L_INTERRUPT_STATUS_G6_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xf, GPIO_L_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_L_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
#define GPIO_L_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_L_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define GPIO_L_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_L_INTERRUPT_STATUS_G7_0
#define GPIO_L_INTERRUPT_STATUS_G7_0                    _MK_ADDR_CONST(0x1331c)
#define GPIO_L_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_L_INTERRUPT_STATUS_G7_0_DUAL                       0x0
#define GPIO_L_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_L_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_L_INTERRUPT_STATUS_G7_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G7_0_RESET_MASK                         _MK_MASK_CONST(0xf)
#define GPIO_L_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G7_0_READ_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_L_INTERRUPT_STATUS_G7_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xf, GPIO_L_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_L_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
#define GPIO_L_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_L_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define GPIO_L_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Reserved address 0x13320

// Reserved address 0x13324

// Reserved address 0x13328

// Reserved address 0x1332c

// Reserved address 0x13330

// Reserved address 0x13334

// Reserved address 0x13338

// Reserved address 0x1333c

// Reserved address 0x13340

// Reserved address 0x13344

// Reserved address 0x13348

// Reserved address 0x1334c

// Reserved address 0x13350

// Reserved address 0x13354

// Reserved address 0x13358

// Reserved address 0x1335c

// Reserved address 0x13360

// Reserved address 0x13364

// Reserved address 0x13368

// Reserved address 0x1336c

// Reserved address 0x13370

// Reserved address 0x13374

// Reserved address 0x13378

// Reserved address 0x1337c

// Reserved address 0x13380

// Reserved address 0x13384

// Reserved address 0x13388

// Reserved address 0x1338c

// Reserved address 0x13390

// Reserved address 0x13394

// Reserved address 0x13398

// Reserved address 0x1339c

// Reserved address 0x133a0

// Reserved address 0x133a4

// Reserved address 0x133a8

// Reserved address 0x133ac

// Reserved address 0x133b0

// Reserved address 0x133b4

// Reserved address 0x133b8

// Reserved address 0x133bc

// Reserved address 0x133c0

// Reserved address 0x133c4

// Reserved address 0x133c8

// Reserved address 0x133cc

// Reserved address 0x133d0

// Reserved address 0x133d4

// Reserved address 0x133d8

// Reserved address 0x133dc

// Reserved address 0x133e0

// Reserved address 0x133e4

// Reserved address 0x133e8

// Reserved address 0x133ec

// Reserved address 0x133f0

// Reserved address 0x133f4

// Reserved address 0x133f8

// Reserved address 0x133fc

// Register GPIO_FF_ENABLE_CONFIG_00_0
#define GPIO_FF_ENABLE_CONFIG_00_0                      _MK_ADDR_CONST(0x13400)
#define GPIO_FF_ENABLE_CONFIG_00_0_SECURE                       0x0
#define GPIO_FF_ENABLE_CONFIG_00_0_DUAL                         0x0
#define GPIO_FF_ENABLE_CONFIG_00_0_SCR                  GPIO_FF_SCR_00_0
#define GPIO_FF_ENABLE_CONFIG_00_0_WORD_COUNT                   0x1
#define GPIO_FF_ENABLE_CONFIG_00_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_00_0_RESET_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_FF_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_00_0_READ_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_FF_ENABLE_CONFIG_00_0_WRITE_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_FF_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                    _MK_SHIFT_CONST(0)
#define GPIO_FF_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                    _MK_FIELD_CONST(0x1, GPIO_FF_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_FF_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_FF_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_FF_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_FF_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_FF_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                  _MK_ENUM_CONST(0)
#define GPIO_FF_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                   _MK_ENUM_CONST(1)

#define GPIO_FF_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                 _MK_SHIFT_CONST(1)
#define GPIO_FF_ENABLE_CONFIG_00_0_IN_OUT_FIELD                 _MK_FIELD_CONST(0x1, GPIO_FF_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_FF_ENABLE_CONFIG_00_0_IN_OUT_RANGE                 1:1
#define GPIO_FF_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                       0x0
#define GPIO_FF_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_FF_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define GPIO_FF_ENABLE_CONFIG_00_0_IN_OUT_IN                    _MK_ENUM_CONST(0)
#define GPIO_FF_ENABLE_CONFIG_00_0_IN_OUT_OUT                   _MK_ENUM_CONST(1)

#define GPIO_FF_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                   _MK_SHIFT_CONST(2)
#define GPIO_FF_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                   _MK_FIELD_CONST(0x3, GPIO_FF_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_FF_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_FF_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_FF_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define GPIO_FF_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_FF_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                      _MK_ENUM_CONST(0)
#define GPIO_FF_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                   _MK_ENUM_CONST(1)
#define GPIO_FF_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                     _MK_ENUM_CONST(2)
#define GPIO_FF_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                     _MK_ENUM_CONST(3)

#define GPIO_FF_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                  _MK_SHIFT_CONST(4)
#define GPIO_FF_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                  _MK_FIELD_CONST(0x1, GPIO_FF_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_FF_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_FF_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_FF_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_FF_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_FF_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        _MK_ENUM_CONST(0)
#define GPIO_FF_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        _MK_ENUM_CONST(1)

#define GPIO_FF_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                      _MK_SHIFT_CONST(5)
#define GPIO_FF_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_FF_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_FF_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_FF_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_FF_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_FF_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_FF_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_FF_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_FF_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                     _MK_SHIFT_CONST(6)
#define GPIO_FF_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                     _MK_FIELD_CONST(0x1, GPIO_FF_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_FF_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_FF_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_FF_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_FF_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_FF_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_FF_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_FF_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                  _MK_SHIFT_CONST(7)
#define GPIO_FF_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                  _MK_FIELD_CONST(0x1, GPIO_FF_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_FF_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_FF_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_FF_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_FF_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_FF_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                        _MK_ENUM_CONST(0)
#define GPIO_FF_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                 _MK_ENUM_CONST(1)


// Register GPIO_FF_DEBOUNCE_THRESHOLD_00_0
#define GPIO_FF_DEBOUNCE_THRESHOLD_00_0                 _MK_ADDR_CONST(0x13404)
#define GPIO_FF_DEBOUNCE_THRESHOLD_00_0_SECURE                  0x0
#define GPIO_FF_DEBOUNCE_THRESHOLD_00_0_DUAL                    0x0
#define GPIO_FF_DEBOUNCE_THRESHOLD_00_0_SCR                     GPIO_FF_SCR_00_0
#define GPIO_FF_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                      0x1
#define GPIO_FF_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_FF_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                      _MK_MASK_CONST(0xff)
#define GPIO_FF_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_FF_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_FF_DEBOUNCE_THRESHOLD_00_0_READ_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_FF_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                      _MK_MASK_CONST(0xff)
#define GPIO_FF_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_FF_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                        _MK_FIELD_CONST(0xff, GPIO_FF_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_FF_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_FF_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_FF_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_FF_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_FF_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_FF_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_FF_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_FF_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_FF_INPUT_00_0
#define GPIO_FF_INPUT_00_0                      _MK_ADDR_CONST(0x13408)
#define GPIO_FF_INPUT_00_0_SECURE                       0x0
#define GPIO_FF_INPUT_00_0_DUAL                         0x0
#define GPIO_FF_INPUT_00_0_SCR                  GPIO_FF_SCR_00_0
#define GPIO_FF_INPUT_00_0_WORD_COUNT                   0x1
#define GPIO_FF_INPUT_00_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_FF_INPUT_00_0_RESET_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_FF_INPUT_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_FF_INPUT_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_FF_INPUT_00_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_FF_INPUT_00_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_FF_INPUT_00_0_GPIO_IN_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_FF_INPUT_00_0_GPIO_IN_FIELD                        _MK_FIELD_CONST(0x1, GPIO_FF_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_FF_INPUT_00_0_GPIO_IN_RANGE                        0:0
#define GPIO_FF_INPUT_00_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_FF_INPUT_00_0_GPIO_IN_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_FF_INPUT_00_0_GPIO_IN_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_FF_INPUT_00_0_GPIO_IN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_FF_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_FF_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_FF_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_FF_OUTPUT_CONTROL_00_0
#define GPIO_FF_OUTPUT_CONTROL_00_0                     _MK_ADDR_CONST(0x1340c)
#define GPIO_FF_OUTPUT_CONTROL_00_0_SECURE                      0x0
#define GPIO_FF_OUTPUT_CONTROL_00_0_DUAL                        0x0
#define GPIO_FF_OUTPUT_CONTROL_00_0_SCR                         GPIO_FF_SCR_00_0
#define GPIO_FF_OUTPUT_CONTROL_00_0_WORD_COUNT                  0x1
#define GPIO_FF_OUTPUT_CONTROL_00_0_RESET_VAL                   _MK_MASK_CONST(0x1)
#define GPIO_FF_OUTPUT_CONTROL_00_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_FF_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_FF_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_FF_OUTPUT_CONTROL_00_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_FF_OUTPUT_CONTROL_00_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_FF_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                      _MK_SHIFT_CONST(0)
#define GPIO_FF_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                      _MK_FIELD_CONST(0x1, GPIO_FF_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_FF_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_FF_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_FF_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                    _MK_MASK_CONST(0x1)
#define GPIO_FF_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_FF_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_FF_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_FF_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_FF_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                     _MK_ENUM_CONST(0)
#define GPIO_FF_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                    _MK_ENUM_CONST(1)


// Register GPIO_FF_OUTPUT_VALUE_00_0
#define GPIO_FF_OUTPUT_VALUE_00_0                       _MK_ADDR_CONST(0x13410)
#define GPIO_FF_OUTPUT_VALUE_00_0_SECURE                        0x0
#define GPIO_FF_OUTPUT_VALUE_00_0_DUAL                  0x0
#define GPIO_FF_OUTPUT_VALUE_00_0_SCR                   GPIO_FF_SCR_00_0
#define GPIO_FF_OUTPUT_VALUE_00_0_WORD_COUNT                    0x1
#define GPIO_FF_OUTPUT_VALUE_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_FF_OUTPUT_VALUE_00_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_FF_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_FF_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_FF_OUTPUT_VALUE_00_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_FF_OUTPUT_VALUE_00_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_FF_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                    _MK_SHIFT_CONST(0)
#define GPIO_FF_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                    _MK_FIELD_CONST(0x1, GPIO_FF_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_FF_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_FF_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_FF_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_FF_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_FF_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_FF_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_FF_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_FF_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register GPIO_FF_INTERRUPT_CLEAR_00_0
#define GPIO_FF_INTERRUPT_CLEAR_00_0                    _MK_ADDR_CONST(0x13414)
#define GPIO_FF_INTERRUPT_CLEAR_00_0_SECURE                     0x0
#define GPIO_FF_INTERRUPT_CLEAR_00_0_DUAL                       0x0
#define GPIO_FF_INTERRUPT_CLEAR_00_0_SCR                        GPIO_FF_SCR_00_0
#define GPIO_FF_INTERRUPT_CLEAR_00_0_WORD_COUNT                         0x1
#define GPIO_FF_INTERRUPT_CLEAR_00_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_CLEAR_00_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define GPIO_FF_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_CLEAR_00_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_FF_INTERRUPT_CLEAR_00_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define GPIO_FF_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_FF_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                 _MK_FIELD_CONST(0x1, GPIO_FF_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_FF_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_FF_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_FF_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_FF_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define GPIO_FF_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     _MK_ENUM_CONST(0)
#define GPIO_FF_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                 _MK_ENUM_CONST(1)


// Reserved address 0x13418

// Reserved address 0x1341c

// Register GPIO_FF_ENABLE_CONFIG_01_0
#define GPIO_FF_ENABLE_CONFIG_01_0                      _MK_ADDR_CONST(0x13420)
#define GPIO_FF_ENABLE_CONFIG_01_0_SECURE                       0x0
#define GPIO_FF_ENABLE_CONFIG_01_0_DUAL                         0x0
#define GPIO_FF_ENABLE_CONFIG_01_0_SCR                  GPIO_FF_SCR_01_0
#define GPIO_FF_ENABLE_CONFIG_01_0_WORD_COUNT                   0x1
#define GPIO_FF_ENABLE_CONFIG_01_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_01_0_RESET_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_FF_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_01_0_READ_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_FF_ENABLE_CONFIG_01_0_WRITE_MASK                   _MK_MASK_CONST(0xff)
#define GPIO_FF_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                    _MK_SHIFT_CONST(0)
#define GPIO_FF_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                    _MK_FIELD_CONST(0x1, GPIO_FF_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_FF_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_FF_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_FF_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_FF_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_FF_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                  _MK_ENUM_CONST(0)
#define GPIO_FF_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                   _MK_ENUM_CONST(1)

#define GPIO_FF_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                 _MK_SHIFT_CONST(1)
#define GPIO_FF_ENABLE_CONFIG_01_0_IN_OUT_FIELD                 _MK_FIELD_CONST(0x1, GPIO_FF_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_FF_ENABLE_CONFIG_01_0_IN_OUT_RANGE                 1:1
#define GPIO_FF_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                       0x0
#define GPIO_FF_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_FF_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define GPIO_FF_ENABLE_CONFIG_01_0_IN_OUT_IN                    _MK_ENUM_CONST(0)
#define GPIO_FF_ENABLE_CONFIG_01_0_IN_OUT_OUT                   _MK_ENUM_CONST(1)

#define GPIO_FF_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                   _MK_SHIFT_CONST(2)
#define GPIO_FF_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                   _MK_FIELD_CONST(0x3, GPIO_FF_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_FF_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_FF_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_FF_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define GPIO_FF_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_FF_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                      _MK_ENUM_CONST(0)
#define GPIO_FF_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                   _MK_ENUM_CONST(1)
#define GPIO_FF_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                     _MK_ENUM_CONST(2)
#define GPIO_FF_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                     _MK_ENUM_CONST(3)

#define GPIO_FF_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                  _MK_SHIFT_CONST(4)
#define GPIO_FF_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                  _MK_FIELD_CONST(0x1, GPIO_FF_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_FF_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_FF_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_FF_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_FF_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_FF_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        _MK_ENUM_CONST(0)
#define GPIO_FF_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        _MK_ENUM_CONST(1)

#define GPIO_FF_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                      _MK_SHIFT_CONST(5)
#define GPIO_FF_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_FF_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_FF_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_FF_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_FF_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_FF_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_FF_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_FF_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_FF_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                     _MK_SHIFT_CONST(6)
#define GPIO_FF_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                     _MK_FIELD_CONST(0x1, GPIO_FF_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_FF_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_FF_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_FF_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_FF_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_FF_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_FF_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_FF_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                  _MK_SHIFT_CONST(7)
#define GPIO_FF_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                  _MK_FIELD_CONST(0x1, GPIO_FF_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_FF_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_FF_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_FF_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_FF_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_FF_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_FF_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                        _MK_ENUM_CONST(0)
#define GPIO_FF_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                 _MK_ENUM_CONST(1)


// Register GPIO_FF_DEBOUNCE_THRESHOLD_01_0
#define GPIO_FF_DEBOUNCE_THRESHOLD_01_0                 _MK_ADDR_CONST(0x13424)
#define GPIO_FF_DEBOUNCE_THRESHOLD_01_0_SECURE                  0x0
#define GPIO_FF_DEBOUNCE_THRESHOLD_01_0_DUAL                    0x0
#define GPIO_FF_DEBOUNCE_THRESHOLD_01_0_SCR                     GPIO_FF_SCR_01_0
#define GPIO_FF_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                      0x1
#define GPIO_FF_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_FF_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                      _MK_MASK_CONST(0xff)
#define GPIO_FF_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_FF_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_FF_DEBOUNCE_THRESHOLD_01_0_READ_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_FF_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                      _MK_MASK_CONST(0xff)
#define GPIO_FF_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_FF_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                        _MK_FIELD_CONST(0xff, GPIO_FF_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_FF_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_FF_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_FF_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_FF_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_FF_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_FF_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_FF_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_FF_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_FF_INPUT_01_0
#define GPIO_FF_INPUT_01_0                      _MK_ADDR_CONST(0x13428)
#define GPIO_FF_INPUT_01_0_SECURE                       0x0
#define GPIO_FF_INPUT_01_0_DUAL                         0x0
#define GPIO_FF_INPUT_01_0_SCR                  GPIO_FF_SCR_01_0
#define GPIO_FF_INPUT_01_0_WORD_COUNT                   0x1
#define GPIO_FF_INPUT_01_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_FF_INPUT_01_0_RESET_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_FF_INPUT_01_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_FF_INPUT_01_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_FF_INPUT_01_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_FF_INPUT_01_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_FF_INPUT_01_0_GPIO_IN_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_FF_INPUT_01_0_GPIO_IN_FIELD                        _MK_FIELD_CONST(0x1, GPIO_FF_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_FF_INPUT_01_0_GPIO_IN_RANGE                        0:0
#define GPIO_FF_INPUT_01_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_FF_INPUT_01_0_GPIO_IN_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_FF_INPUT_01_0_GPIO_IN_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_FF_INPUT_01_0_GPIO_IN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_FF_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_FF_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_FF_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_FF_OUTPUT_CONTROL_01_0
#define GPIO_FF_OUTPUT_CONTROL_01_0                     _MK_ADDR_CONST(0x1342c)
#define GPIO_FF_OUTPUT_CONTROL_01_0_SECURE                      0x0
#define GPIO_FF_OUTPUT_CONTROL_01_0_DUAL                        0x0
#define GPIO_FF_OUTPUT_CONTROL_01_0_SCR                         GPIO_FF_SCR_01_0
#define GPIO_FF_OUTPUT_CONTROL_01_0_WORD_COUNT                  0x1
#define GPIO_FF_OUTPUT_CONTROL_01_0_RESET_VAL                   _MK_MASK_CONST(0x1)
#define GPIO_FF_OUTPUT_CONTROL_01_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_FF_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_FF_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_FF_OUTPUT_CONTROL_01_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_FF_OUTPUT_CONTROL_01_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_FF_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                      _MK_SHIFT_CONST(0)
#define GPIO_FF_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                      _MK_FIELD_CONST(0x1, GPIO_FF_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_FF_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_FF_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_FF_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                    _MK_MASK_CONST(0x1)
#define GPIO_FF_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_FF_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_FF_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_FF_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_FF_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                     _MK_ENUM_CONST(0)
#define GPIO_FF_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                    _MK_ENUM_CONST(1)


// Register GPIO_FF_OUTPUT_VALUE_01_0
#define GPIO_FF_OUTPUT_VALUE_01_0                       _MK_ADDR_CONST(0x13430)
#define GPIO_FF_OUTPUT_VALUE_01_0_SECURE                        0x0
#define GPIO_FF_OUTPUT_VALUE_01_0_DUAL                  0x0
#define GPIO_FF_OUTPUT_VALUE_01_0_SCR                   GPIO_FF_SCR_01_0
#define GPIO_FF_OUTPUT_VALUE_01_0_WORD_COUNT                    0x1
#define GPIO_FF_OUTPUT_VALUE_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_FF_OUTPUT_VALUE_01_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_FF_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_FF_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_FF_OUTPUT_VALUE_01_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_FF_OUTPUT_VALUE_01_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_FF_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                    _MK_SHIFT_CONST(0)
#define GPIO_FF_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                    _MK_FIELD_CONST(0x1, GPIO_FF_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_FF_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_FF_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_FF_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_FF_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_FF_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_FF_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_FF_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_FF_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register GPIO_FF_INTERRUPT_CLEAR_01_0
#define GPIO_FF_INTERRUPT_CLEAR_01_0                    _MK_ADDR_CONST(0x13434)
#define GPIO_FF_INTERRUPT_CLEAR_01_0_SECURE                     0x0
#define GPIO_FF_INTERRUPT_CLEAR_01_0_DUAL                       0x0
#define GPIO_FF_INTERRUPT_CLEAR_01_0_SCR                        GPIO_FF_SCR_01_0
#define GPIO_FF_INTERRUPT_CLEAR_01_0_WORD_COUNT                         0x1
#define GPIO_FF_INTERRUPT_CLEAR_01_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_CLEAR_01_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define GPIO_FF_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_CLEAR_01_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_FF_INTERRUPT_CLEAR_01_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define GPIO_FF_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_FF_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                 _MK_FIELD_CONST(0x1, GPIO_FF_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_FF_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_FF_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_FF_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_FF_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define GPIO_FF_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     _MK_ENUM_CONST(0)
#define GPIO_FF_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                 _MK_ENUM_CONST(1)


// Reserved address 0x13438

// Reserved address 0x1343c

// Reserved address 0x13440

// Reserved address 0x13444

// Reserved address 0x13448

// Reserved address 0x1344c

// Reserved address 0x13450

// Reserved address 0x13454

// Reserved address 0x13458

// Reserved address 0x1345c

// Reserved address 0x13460

// Reserved address 0x13464

// Reserved address 0x13468

// Reserved address 0x1346c

// Reserved address 0x13470

// Reserved address 0x13474

// Reserved address 0x13478

// Reserved address 0x1347c

// Reserved address 0x13480

// Reserved address 0x13484

// Reserved address 0x13488

// Reserved address 0x1348c

// Reserved address 0x13490

// Reserved address 0x13494

// Reserved address 0x13498

// Reserved address 0x1349c

// Reserved address 0x134a0

// Reserved address 0x134a4

// Reserved address 0x134a8

// Reserved address 0x134ac

// Reserved address 0x134b0

// Reserved address 0x134b4

// Reserved address 0x134b8

// Reserved address 0x134bc

// Reserved address 0x134c0

// Reserved address 0x134c4

// Reserved address 0x134c8

// Reserved address 0x134cc

// Reserved address 0x134d0

// Reserved address 0x134d4

// Reserved address 0x134d8

// Reserved address 0x134dc

// Reserved address 0x134e0

// Reserved address 0x134e4

// Reserved address 0x134e8

// Reserved address 0x134ec

// Reserved address 0x134f0

// Reserved address 0x134f4

// Reserved address 0x134f8

// Reserved address 0x134fc

// Register GPIO_FF_INTERRUPT_STATUS_G0_0
#define GPIO_FF_INTERRUPT_STATUS_G0_0                   _MK_ADDR_CONST(0x13500)
#define GPIO_FF_INTERRUPT_STATUS_G0_0_SECURE                    0x0
#define GPIO_FF_INTERRUPT_STATUS_G0_0_DUAL                      0x0
#define GPIO_FF_INTERRUPT_STATUS_G0_0_SCR                       0
#define GPIO_FF_INTERRUPT_STATUS_G0_0_WORD_COUNT                        0x1
#define GPIO_FF_INTERRUPT_STATUS_G0_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G0_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_FF_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G0_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_FF_INTERRUPT_STATUS_G0_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_FF_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                       _MK_FIELD_CONST(0x3, GPIO_FF_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_FF_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                       1:0
#define GPIO_FF_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_FF_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_FF_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_FF_INTERRUPT_STATUS_G1_0
#define GPIO_FF_INTERRUPT_STATUS_G1_0                   _MK_ADDR_CONST(0x13504)
#define GPIO_FF_INTERRUPT_STATUS_G1_0_SECURE                    0x0
#define GPIO_FF_INTERRUPT_STATUS_G1_0_DUAL                      0x0
#define GPIO_FF_INTERRUPT_STATUS_G1_0_SCR                       0
#define GPIO_FF_INTERRUPT_STATUS_G1_0_WORD_COUNT                        0x1
#define GPIO_FF_INTERRUPT_STATUS_G1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G1_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_FF_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G1_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_FF_INTERRUPT_STATUS_G1_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_FF_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                       _MK_FIELD_CONST(0x3, GPIO_FF_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_FF_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                       1:0
#define GPIO_FF_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_FF_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_FF_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_FF_INTERRUPT_STATUS_G2_0
#define GPIO_FF_INTERRUPT_STATUS_G2_0                   _MK_ADDR_CONST(0x13508)
#define GPIO_FF_INTERRUPT_STATUS_G2_0_SECURE                    0x0
#define GPIO_FF_INTERRUPT_STATUS_G2_0_DUAL                      0x0
#define GPIO_FF_INTERRUPT_STATUS_G2_0_SCR                       0
#define GPIO_FF_INTERRUPT_STATUS_G2_0_WORD_COUNT                        0x1
#define GPIO_FF_INTERRUPT_STATUS_G2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G2_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_FF_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G2_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_FF_INTERRUPT_STATUS_G2_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_FF_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                       _MK_FIELD_CONST(0x3, GPIO_FF_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_FF_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                       1:0
#define GPIO_FF_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_FF_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_FF_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_FF_INTERRUPT_STATUS_G3_0
#define GPIO_FF_INTERRUPT_STATUS_G3_0                   _MK_ADDR_CONST(0x1350c)
#define GPIO_FF_INTERRUPT_STATUS_G3_0_SECURE                    0x0
#define GPIO_FF_INTERRUPT_STATUS_G3_0_DUAL                      0x0
#define GPIO_FF_INTERRUPT_STATUS_G3_0_SCR                       0
#define GPIO_FF_INTERRUPT_STATUS_G3_0_WORD_COUNT                        0x1
#define GPIO_FF_INTERRUPT_STATUS_G3_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G3_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_FF_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G3_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_FF_INTERRUPT_STATUS_G3_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_FF_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                       _MK_FIELD_CONST(0x3, GPIO_FF_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_FF_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                       1:0
#define GPIO_FF_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_FF_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_FF_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_FF_INTERRUPT_STATUS_G4_0
#define GPIO_FF_INTERRUPT_STATUS_G4_0                   _MK_ADDR_CONST(0x13510)
#define GPIO_FF_INTERRUPT_STATUS_G4_0_SECURE                    0x0
#define GPIO_FF_INTERRUPT_STATUS_G4_0_DUAL                      0x0
#define GPIO_FF_INTERRUPT_STATUS_G4_0_SCR                       0
#define GPIO_FF_INTERRUPT_STATUS_G4_0_WORD_COUNT                        0x1
#define GPIO_FF_INTERRUPT_STATUS_G4_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G4_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_FF_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G4_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_FF_INTERRUPT_STATUS_G4_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_FF_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                       _MK_FIELD_CONST(0x3, GPIO_FF_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_FF_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                       1:0
#define GPIO_FF_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_FF_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_FF_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_FF_INTERRUPT_STATUS_G5_0
#define GPIO_FF_INTERRUPT_STATUS_G5_0                   _MK_ADDR_CONST(0x13514)
#define GPIO_FF_INTERRUPT_STATUS_G5_0_SECURE                    0x0
#define GPIO_FF_INTERRUPT_STATUS_G5_0_DUAL                      0x0
#define GPIO_FF_INTERRUPT_STATUS_G5_0_SCR                       0
#define GPIO_FF_INTERRUPT_STATUS_G5_0_WORD_COUNT                        0x1
#define GPIO_FF_INTERRUPT_STATUS_G5_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G5_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_FF_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G5_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_FF_INTERRUPT_STATUS_G5_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_FF_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                       _MK_FIELD_CONST(0x3, GPIO_FF_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_FF_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                       1:0
#define GPIO_FF_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_FF_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_FF_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_FF_INTERRUPT_STATUS_G6_0
#define GPIO_FF_INTERRUPT_STATUS_G6_0                   _MK_ADDR_CONST(0x13518)
#define GPIO_FF_INTERRUPT_STATUS_G6_0_SECURE                    0x0
#define GPIO_FF_INTERRUPT_STATUS_G6_0_DUAL                      0x0
#define GPIO_FF_INTERRUPT_STATUS_G6_0_SCR                       0
#define GPIO_FF_INTERRUPT_STATUS_G6_0_WORD_COUNT                        0x1
#define GPIO_FF_INTERRUPT_STATUS_G6_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G6_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_FF_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G6_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_FF_INTERRUPT_STATUS_G6_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_FF_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                       _MK_FIELD_CONST(0x3, GPIO_FF_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_FF_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                       1:0
#define GPIO_FF_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_FF_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_FF_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register GPIO_FF_INTERRUPT_STATUS_G7_0
#define GPIO_FF_INTERRUPT_STATUS_G7_0                   _MK_ADDR_CONST(0x1351c)
#define GPIO_FF_INTERRUPT_STATUS_G7_0_SECURE                    0x0
#define GPIO_FF_INTERRUPT_STATUS_G7_0_DUAL                      0x0
#define GPIO_FF_INTERRUPT_STATUS_G7_0_SCR                       0
#define GPIO_FF_INTERRUPT_STATUS_G7_0_WORD_COUNT                        0x1
#define GPIO_FF_INTERRUPT_STATUS_G7_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G7_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_FF_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G7_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_FF_INTERRUPT_STATUS_G7_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_FF_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                       _MK_FIELD_CONST(0x3, GPIO_FF_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_FF_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                       1:0
#define GPIO_FF_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_FF_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define GPIO_FF_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_FF_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Reserved address 0x13520

// Reserved address 0x13524

// Reserved address 0x13528

// Reserved address 0x1352c

// Reserved address 0x13530

// Reserved address 0x13534

// Reserved address 0x13538

// Reserved address 0x1353c

// Reserved address 0x13540

// Reserved address 0x13544

// Reserved address 0x13548

// Reserved address 0x1354c

// Reserved address 0x13550

// Reserved address 0x13554

// Reserved address 0x13558

// Reserved address 0x1355c

// Reserved address 0x13560

// Reserved address 0x13564

// Reserved address 0x13568

// Reserved address 0x1356c

// Reserved address 0x13570

// Reserved address 0x13574

// Reserved address 0x13578

// Reserved address 0x1357c

// Reserved address 0x13580

// Reserved address 0x13584

// Reserved address 0x13588

// Reserved address 0x1358c

// Reserved address 0x13590

// Reserved address 0x13594

// Reserved address 0x13598

// Reserved address 0x1359c

// Reserved address 0x135a0

// Reserved address 0x135a4

// Reserved address 0x135a8

// Reserved address 0x135ac

// Reserved address 0x135b0

// Reserved address 0x135b4

// Reserved address 0x135b8

// Reserved address 0x135bc

// Reserved address 0x135c0

// Reserved address 0x135c4

// Reserved address 0x135c8

// Reserved address 0x135cc

// Reserved address 0x135d0

// Reserved address 0x135d4

// Reserved address 0x135d8

// Reserved address 0x135dc

// Reserved address 0x135e0

// Reserved address 0x135e4

// Reserved address 0x135e8

// Reserved address 0x135ec

// Reserved address 0x135f0

// Reserved address 0x135f4

// Reserved address 0x135f8

// Reserved address 0x135fc

// Register GPIO_S_ENABLE_CONFIG_00_0
#define GPIO_S_ENABLE_CONFIG_00_0                       _MK_ADDR_CONST(0x13600)
#define GPIO_S_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_S_ENABLE_CONFIG_00_0_DUAL                  0x0
#define GPIO_S_ENABLE_CONFIG_00_0_SCR                   GPIO_S_SCR_00_0
#define GPIO_S_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_S_ENABLE_CONFIG_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_00_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_S_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_00_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_S_ENABLE_CONFIG_00_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_S_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_S_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_S_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_S_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_S_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_S_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_S_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_S_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_S_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_S_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_S_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_S_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_00_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_00_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_S_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_S_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_S_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_S_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_S_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_S_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_S_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_S_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_S_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_S_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_S_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_S_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_S_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_S_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_S_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_S_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_S_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_S_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_S_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_S_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_S_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_S_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_S_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_S_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_S_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_S_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_S_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_S_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_S_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_S_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_S_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_S_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_S_DEBOUNCE_THRESHOLD_00_0
#define GPIO_S_DEBOUNCE_THRESHOLD_00_0                  _MK_ADDR_CONST(0x13604)
#define GPIO_S_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_S_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
#define GPIO_S_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_S_SCR_00_0
#define GPIO_S_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_S_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_S_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_S_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_S_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_S_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_S_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_S_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_S_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_S_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_S_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_S_INPUT_00_0
#define GPIO_S_INPUT_00_0                       _MK_ADDR_CONST(0x13608)
#define GPIO_S_INPUT_00_0_SECURE                        0x0
#define GPIO_S_INPUT_00_0_DUAL                  0x0
#define GPIO_S_INPUT_00_0_SCR                   GPIO_S_SCR_00_0
#define GPIO_S_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_S_INPUT_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_00_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_00_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_S_INPUT_00_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_00_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_S_INPUT_00_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_S_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_S_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_S_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_S_INPUT_00_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_00_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_S_OUTPUT_CONTROL_00_0
#define GPIO_S_OUTPUT_CONTROL_00_0                      _MK_ADDR_CONST(0x1360c)
#define GPIO_S_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_S_OUTPUT_CONTROL_00_0_DUAL                         0x0
#define GPIO_S_OUTPUT_CONTROL_00_0_SCR                  GPIO_S_SCR_00_0
#define GPIO_S_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_S_OUTPUT_CONTROL_00_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_00_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_CONTROL_00_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_00_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_S_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_S_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_S_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_S_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_S_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_S_OUTPUT_VALUE_00_0
#define GPIO_S_OUTPUT_VALUE_00_0                        _MK_ADDR_CONST(0x13610)
#define GPIO_S_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_S_OUTPUT_VALUE_00_0_DUAL                   0x0
#define GPIO_S_OUTPUT_VALUE_00_0_SCR                    GPIO_S_SCR_00_0
#define GPIO_S_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_S_OUTPUT_VALUE_00_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_00_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_00_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_VALUE_00_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_S_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_S_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_S_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_S_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_S_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_S_INTERRUPT_CLEAR_00_0
#define GPIO_S_INTERRUPT_CLEAR_00_0                     _MK_ADDR_CONST(0x13614)
#define GPIO_S_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_S_INTERRUPT_CLEAR_00_0_DUAL                        0x0
#define GPIO_S_INTERRUPT_CLEAR_00_0_SCR                         GPIO_S_SCR_00_0
#define GPIO_S_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_S_INTERRUPT_CLEAR_00_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_00_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_S_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_00_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_S_INTERRUPT_CLEAR_00_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_S_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_S_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_S_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_S_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_S_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_S_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_S_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_S_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_S_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x13618

// Reserved address 0x1361c

// Register GPIO_S_ENABLE_CONFIG_01_0
#define GPIO_S_ENABLE_CONFIG_01_0                       _MK_ADDR_CONST(0x13620)
#define GPIO_S_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_S_ENABLE_CONFIG_01_0_DUAL                  0x0
#define GPIO_S_ENABLE_CONFIG_01_0_SCR                   GPIO_S_SCR_01_0
#define GPIO_S_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_S_ENABLE_CONFIG_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_01_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_S_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_01_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_S_ENABLE_CONFIG_01_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_S_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_S_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_S_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_S_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_S_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_S_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_S_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_S_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_S_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_S_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_S_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_S_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_01_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_01_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_S_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_S_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_S_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_S_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_S_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_S_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_S_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_S_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_S_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_S_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_S_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_S_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_S_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_S_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_S_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_S_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_S_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_S_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_S_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_S_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_S_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_S_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_S_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_S_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_S_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_S_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_S_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_S_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_S_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_S_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_S_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_S_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_S_DEBOUNCE_THRESHOLD_01_0
#define GPIO_S_DEBOUNCE_THRESHOLD_01_0                  _MK_ADDR_CONST(0x13624)
#define GPIO_S_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_S_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
#define GPIO_S_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_S_SCR_01_0
#define GPIO_S_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_S_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_S_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_S_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_S_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_S_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_S_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_S_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_S_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_S_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_S_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_S_INPUT_01_0
#define GPIO_S_INPUT_01_0                       _MK_ADDR_CONST(0x13628)
#define GPIO_S_INPUT_01_0_SECURE                        0x0
#define GPIO_S_INPUT_01_0_DUAL                  0x0
#define GPIO_S_INPUT_01_0_SCR                   GPIO_S_SCR_01_0
#define GPIO_S_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_S_INPUT_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_01_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_01_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_S_INPUT_01_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_01_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_S_INPUT_01_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_S_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_S_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_S_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_S_INPUT_01_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_01_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_S_OUTPUT_CONTROL_01_0
#define GPIO_S_OUTPUT_CONTROL_01_0                      _MK_ADDR_CONST(0x1362c)
#define GPIO_S_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_S_OUTPUT_CONTROL_01_0_DUAL                         0x0
#define GPIO_S_OUTPUT_CONTROL_01_0_SCR                  GPIO_S_SCR_01_0
#define GPIO_S_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_S_OUTPUT_CONTROL_01_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_01_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_CONTROL_01_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_01_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_S_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_S_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_S_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_S_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_S_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_S_OUTPUT_VALUE_01_0
#define GPIO_S_OUTPUT_VALUE_01_0                        _MK_ADDR_CONST(0x13630)
#define GPIO_S_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_S_OUTPUT_VALUE_01_0_DUAL                   0x0
#define GPIO_S_OUTPUT_VALUE_01_0_SCR                    GPIO_S_SCR_01_0
#define GPIO_S_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_S_OUTPUT_VALUE_01_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_01_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_01_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_VALUE_01_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_S_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_S_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_S_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_S_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_S_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_S_INTERRUPT_CLEAR_01_0
#define GPIO_S_INTERRUPT_CLEAR_01_0                     _MK_ADDR_CONST(0x13634)
#define GPIO_S_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_S_INTERRUPT_CLEAR_01_0_DUAL                        0x0
#define GPIO_S_INTERRUPT_CLEAR_01_0_SCR                         GPIO_S_SCR_01_0
#define GPIO_S_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_S_INTERRUPT_CLEAR_01_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_01_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_S_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_01_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_S_INTERRUPT_CLEAR_01_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_S_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_S_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_S_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_S_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_S_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_S_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_S_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_S_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_S_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x13638

// Reserved address 0x1363c

// Register GPIO_S_ENABLE_CONFIG_02_0
#define GPIO_S_ENABLE_CONFIG_02_0                       _MK_ADDR_CONST(0x13640)
#define GPIO_S_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_S_ENABLE_CONFIG_02_0_DUAL                  0x0
#define GPIO_S_ENABLE_CONFIG_02_0_SCR                   GPIO_S_SCR_02_0
#define GPIO_S_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_S_ENABLE_CONFIG_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_02_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_S_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_02_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_S_ENABLE_CONFIG_02_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_S_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_S_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_S_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_S_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_S_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_S_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_S_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_S_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_S_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_S_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_S_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_S_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_02_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_02_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_S_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_S_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_S_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_S_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_S_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_S_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_S_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_S_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_S_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_S_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_S_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_S_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_S_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_S_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_S_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_S_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_S_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_S_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_S_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_S_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_S_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_S_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_S_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_S_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_S_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_S_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_S_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_S_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_S_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_S_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_S_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_S_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_S_DEBOUNCE_THRESHOLD_02_0
#define GPIO_S_DEBOUNCE_THRESHOLD_02_0                  _MK_ADDR_CONST(0x13644)
#define GPIO_S_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_S_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
#define GPIO_S_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_S_SCR_02_0
#define GPIO_S_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_S_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_S_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_S_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_S_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_S_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_S_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_S_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_S_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_S_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_S_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_S_INPUT_02_0
#define GPIO_S_INPUT_02_0                       _MK_ADDR_CONST(0x13648)
#define GPIO_S_INPUT_02_0_SECURE                        0x0
#define GPIO_S_INPUT_02_0_DUAL                  0x0
#define GPIO_S_INPUT_02_0_SCR                   GPIO_S_SCR_02_0
#define GPIO_S_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_S_INPUT_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_02_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_02_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_S_INPUT_02_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_02_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_S_INPUT_02_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_S_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_S_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_S_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_S_INPUT_02_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_02_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_S_OUTPUT_CONTROL_02_0
#define GPIO_S_OUTPUT_CONTROL_02_0                      _MK_ADDR_CONST(0x1364c)
#define GPIO_S_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_S_OUTPUT_CONTROL_02_0_DUAL                         0x0
#define GPIO_S_OUTPUT_CONTROL_02_0_SCR                  GPIO_S_SCR_02_0
#define GPIO_S_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_S_OUTPUT_CONTROL_02_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_02_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_CONTROL_02_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_02_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_S_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_S_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_S_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_S_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_S_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_S_OUTPUT_VALUE_02_0
#define GPIO_S_OUTPUT_VALUE_02_0                        _MK_ADDR_CONST(0x13650)
#define GPIO_S_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_S_OUTPUT_VALUE_02_0_DUAL                   0x0
#define GPIO_S_OUTPUT_VALUE_02_0_SCR                    GPIO_S_SCR_02_0
#define GPIO_S_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_S_OUTPUT_VALUE_02_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_02_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_02_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_VALUE_02_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_S_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_S_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_S_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_S_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_S_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_S_INTERRUPT_CLEAR_02_0
#define GPIO_S_INTERRUPT_CLEAR_02_0                     _MK_ADDR_CONST(0x13654)
#define GPIO_S_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_S_INTERRUPT_CLEAR_02_0_DUAL                        0x0
#define GPIO_S_INTERRUPT_CLEAR_02_0_SCR                         GPIO_S_SCR_02_0
#define GPIO_S_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_S_INTERRUPT_CLEAR_02_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_02_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_S_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_02_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_S_INTERRUPT_CLEAR_02_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_S_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_S_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_S_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_S_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_S_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_S_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_S_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_S_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_S_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x13658

// Reserved address 0x1365c

// Register GPIO_S_ENABLE_CONFIG_03_0
#define GPIO_S_ENABLE_CONFIG_03_0                       _MK_ADDR_CONST(0x13660)
#define GPIO_S_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_S_ENABLE_CONFIG_03_0_DUAL                  0x0
#define GPIO_S_ENABLE_CONFIG_03_0_SCR                   GPIO_S_SCR_03_0
#define GPIO_S_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_S_ENABLE_CONFIG_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_03_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_S_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_03_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_S_ENABLE_CONFIG_03_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_S_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_S_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_S_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_S_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_S_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_S_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_S_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_S_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_S_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_S_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_S_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_S_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_03_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_03_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_S_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_S_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_S_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_S_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_S_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_S_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_S_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_S_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_S_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_S_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_S_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_S_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_S_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_S_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_S_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_S_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_S_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_S_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_S_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_S_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_S_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_S_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_S_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_S_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_S_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_S_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_S_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_S_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_S_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_S_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_S_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_S_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_S_DEBOUNCE_THRESHOLD_03_0
#define GPIO_S_DEBOUNCE_THRESHOLD_03_0                  _MK_ADDR_CONST(0x13664)
#define GPIO_S_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_S_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
#define GPIO_S_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_S_SCR_03_0
#define GPIO_S_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_S_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_S_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_S_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_S_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_S_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_S_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_S_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_S_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_S_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_S_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_S_INPUT_03_0
#define GPIO_S_INPUT_03_0                       _MK_ADDR_CONST(0x13668)
#define GPIO_S_INPUT_03_0_SECURE                        0x0
#define GPIO_S_INPUT_03_0_DUAL                  0x0
#define GPIO_S_INPUT_03_0_SCR                   GPIO_S_SCR_03_0
#define GPIO_S_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_S_INPUT_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_03_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_03_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_S_INPUT_03_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_03_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_S_INPUT_03_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_S_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_S_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_S_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_S_INPUT_03_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_03_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_S_OUTPUT_CONTROL_03_0
#define GPIO_S_OUTPUT_CONTROL_03_0                      _MK_ADDR_CONST(0x1366c)
#define GPIO_S_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_S_OUTPUT_CONTROL_03_0_DUAL                         0x0
#define GPIO_S_OUTPUT_CONTROL_03_0_SCR                  GPIO_S_SCR_03_0
#define GPIO_S_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_S_OUTPUT_CONTROL_03_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_03_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_CONTROL_03_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_03_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_S_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_S_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_S_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_S_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_S_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_S_OUTPUT_VALUE_03_0
#define GPIO_S_OUTPUT_VALUE_03_0                        _MK_ADDR_CONST(0x13670)
#define GPIO_S_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_S_OUTPUT_VALUE_03_0_DUAL                   0x0
#define GPIO_S_OUTPUT_VALUE_03_0_SCR                    GPIO_S_SCR_03_0
#define GPIO_S_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_S_OUTPUT_VALUE_03_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_03_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_03_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_VALUE_03_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_S_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_S_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_S_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_S_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_S_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_S_INTERRUPT_CLEAR_03_0
#define GPIO_S_INTERRUPT_CLEAR_03_0                     _MK_ADDR_CONST(0x13674)
#define GPIO_S_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_S_INTERRUPT_CLEAR_03_0_DUAL                        0x0
#define GPIO_S_INTERRUPT_CLEAR_03_0_SCR                         GPIO_S_SCR_03_0
#define GPIO_S_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_S_INTERRUPT_CLEAR_03_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_03_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_S_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_03_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_S_INTERRUPT_CLEAR_03_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_S_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_S_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_S_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_S_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_S_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_S_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_S_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_S_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_S_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x13678

// Reserved address 0x1367c

// Register GPIO_S_ENABLE_CONFIG_04_0
#define GPIO_S_ENABLE_CONFIG_04_0                       _MK_ADDR_CONST(0x13680)
#define GPIO_S_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_S_ENABLE_CONFIG_04_0_DUAL                  0x0
#define GPIO_S_ENABLE_CONFIG_04_0_SCR                   GPIO_S_SCR_04_0
#define GPIO_S_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_S_ENABLE_CONFIG_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_04_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_S_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_04_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_S_ENABLE_CONFIG_04_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_S_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_S_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_S_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_S_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_S_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_S_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_S_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_S_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_S_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_S_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_S_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_S_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_04_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_04_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_S_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_S_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_S_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_S_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_S_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_S_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_S_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_S_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_S_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_S_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_S_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_S_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_S_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_S_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_S_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_S_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_S_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_S_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_S_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_S_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_S_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_S_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_S_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_S_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_S_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_S_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_S_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_S_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_S_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_S_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_S_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_S_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_S_DEBOUNCE_THRESHOLD_04_0
#define GPIO_S_DEBOUNCE_THRESHOLD_04_0                  _MK_ADDR_CONST(0x13684)
#define GPIO_S_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_S_DEBOUNCE_THRESHOLD_04_0_DUAL                     0x0
#define GPIO_S_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_S_SCR_04_0
#define GPIO_S_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_S_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_S_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_S_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_S_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_S_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_S_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_S_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_S_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_S_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_S_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_S_INPUT_04_0
#define GPIO_S_INPUT_04_0                       _MK_ADDR_CONST(0x13688)
#define GPIO_S_INPUT_04_0_SECURE                        0x0
#define GPIO_S_INPUT_04_0_DUAL                  0x0
#define GPIO_S_INPUT_04_0_SCR                   GPIO_S_SCR_04_0
#define GPIO_S_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_S_INPUT_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_04_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_04_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_S_INPUT_04_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_04_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_S_INPUT_04_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_S_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_S_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_S_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_S_INPUT_04_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_04_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_S_OUTPUT_CONTROL_04_0
#define GPIO_S_OUTPUT_CONTROL_04_0                      _MK_ADDR_CONST(0x1368c)
#define GPIO_S_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_S_OUTPUT_CONTROL_04_0_DUAL                         0x0
#define GPIO_S_OUTPUT_CONTROL_04_0_SCR                  GPIO_S_SCR_04_0
#define GPIO_S_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_S_OUTPUT_CONTROL_04_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_04_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_CONTROL_04_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_04_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_S_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_S_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_S_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_S_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_S_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_S_OUTPUT_VALUE_04_0
#define GPIO_S_OUTPUT_VALUE_04_0                        _MK_ADDR_CONST(0x13690)
#define GPIO_S_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_S_OUTPUT_VALUE_04_0_DUAL                   0x0
#define GPIO_S_OUTPUT_VALUE_04_0_SCR                    GPIO_S_SCR_04_0
#define GPIO_S_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_S_OUTPUT_VALUE_04_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_04_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_04_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_VALUE_04_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_S_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_S_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_S_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_S_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_S_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_S_INTERRUPT_CLEAR_04_0
#define GPIO_S_INTERRUPT_CLEAR_04_0                     _MK_ADDR_CONST(0x13694)
#define GPIO_S_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_S_INTERRUPT_CLEAR_04_0_DUAL                        0x0
#define GPIO_S_INTERRUPT_CLEAR_04_0_SCR                         GPIO_S_SCR_04_0
#define GPIO_S_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_S_INTERRUPT_CLEAR_04_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_04_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_S_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_04_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_S_INTERRUPT_CLEAR_04_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_S_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_S_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_S_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_S_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_S_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_S_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_S_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_S_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_S_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x13698

// Reserved address 0x1369c

// Register GPIO_S_ENABLE_CONFIG_05_0
#define GPIO_S_ENABLE_CONFIG_05_0                       _MK_ADDR_CONST(0x136a0)
#define GPIO_S_ENABLE_CONFIG_05_0_SECURE                        0x0
#define GPIO_S_ENABLE_CONFIG_05_0_DUAL                  0x0
#define GPIO_S_ENABLE_CONFIG_05_0_SCR                   GPIO_S_SCR_05_0
#define GPIO_S_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
#define GPIO_S_ENABLE_CONFIG_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_05_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_S_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_05_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_S_ENABLE_CONFIG_05_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_S_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_S_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_S_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_S_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_S_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_S_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_S_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_S_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_S_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_S_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
#define GPIO_S_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
#define GPIO_S_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_05_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_05_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_S_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_S_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_S_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_S_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_S_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_S_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_S_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_S_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_S_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_S_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_S_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_S_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_S_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_S_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_S_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_S_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_S_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_S_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_S_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_S_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_S_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_S_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_S_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_S_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_S_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_S_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_S_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_S_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_S_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_S_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_S_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_S_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_S_DEBOUNCE_THRESHOLD_05_0
#define GPIO_S_DEBOUNCE_THRESHOLD_05_0                  _MK_ADDR_CONST(0x136a4)
#define GPIO_S_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
#define GPIO_S_DEBOUNCE_THRESHOLD_05_0_DUAL                     0x0
#define GPIO_S_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_S_SCR_05_0
#define GPIO_S_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
#define GPIO_S_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_S_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_S_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_S_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_S_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_S_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_S_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_S_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_S_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_S_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_S_INPUT_05_0
#define GPIO_S_INPUT_05_0                       _MK_ADDR_CONST(0x136a8)
#define GPIO_S_INPUT_05_0_SECURE                        0x0
#define GPIO_S_INPUT_05_0_DUAL                  0x0
#define GPIO_S_INPUT_05_0_SCR                   GPIO_S_SCR_05_0
#define GPIO_S_INPUT_05_0_WORD_COUNT                    0x1
#define GPIO_S_INPUT_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_05_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_05_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_S_INPUT_05_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_05_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_S_INPUT_05_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_S_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_S_INPUT_05_0_GPIO_IN_RANGE                 0:0
#define GPIO_S_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_S_INPUT_05_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_05_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_S_OUTPUT_CONTROL_05_0
#define GPIO_S_OUTPUT_CONTROL_05_0                      _MK_ADDR_CONST(0x136ac)
#define GPIO_S_OUTPUT_CONTROL_05_0_SECURE                       0x0
#define GPIO_S_OUTPUT_CONTROL_05_0_DUAL                         0x0
#define GPIO_S_OUTPUT_CONTROL_05_0_SCR                  GPIO_S_SCR_05_0
#define GPIO_S_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
#define GPIO_S_OUTPUT_CONTROL_05_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_05_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_CONTROL_05_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_05_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_S_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_S_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_S_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_S_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_S_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_S_OUTPUT_VALUE_05_0
#define GPIO_S_OUTPUT_VALUE_05_0                        _MK_ADDR_CONST(0x136b0)
#define GPIO_S_OUTPUT_VALUE_05_0_SECURE                         0x0
#define GPIO_S_OUTPUT_VALUE_05_0_DUAL                   0x0
#define GPIO_S_OUTPUT_VALUE_05_0_SCR                    GPIO_S_SCR_05_0
#define GPIO_S_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
#define GPIO_S_OUTPUT_VALUE_05_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_05_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_05_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_VALUE_05_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_S_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_S_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_S_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_S_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_S_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_S_INTERRUPT_CLEAR_05_0
#define GPIO_S_INTERRUPT_CLEAR_05_0                     _MK_ADDR_CONST(0x136b4)
#define GPIO_S_INTERRUPT_CLEAR_05_0_SECURE                      0x0
#define GPIO_S_INTERRUPT_CLEAR_05_0_DUAL                        0x0
#define GPIO_S_INTERRUPT_CLEAR_05_0_SCR                         GPIO_S_SCR_05_0
#define GPIO_S_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
#define GPIO_S_INTERRUPT_CLEAR_05_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_05_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_S_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_05_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_S_INTERRUPT_CLEAR_05_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_S_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_S_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_S_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_S_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_S_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_S_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_S_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_S_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_S_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x136b8

// Reserved address 0x136bc

// Register GPIO_S_ENABLE_CONFIG_06_0
#define GPIO_S_ENABLE_CONFIG_06_0                       _MK_ADDR_CONST(0x136c0)
#define GPIO_S_ENABLE_CONFIG_06_0_SECURE                        0x0
#define GPIO_S_ENABLE_CONFIG_06_0_DUAL                  0x0
#define GPIO_S_ENABLE_CONFIG_06_0_SCR                   GPIO_S_SCR_06_0
#define GPIO_S_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
#define GPIO_S_ENABLE_CONFIG_06_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_06_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_S_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_06_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_S_ENABLE_CONFIG_06_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_S_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_S_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_S_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
#define GPIO_S_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_S_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_S_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_06_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_06_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_S_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_S_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_S_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
#define GPIO_S_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
#define GPIO_S_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
#define GPIO_S_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_06_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_06_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_06_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_06_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_S_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_S_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_S_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
#define GPIO_S_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_S_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_S_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_S_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_S_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_S_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_S_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_S_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_S_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_S_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_S_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_S_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_S_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_S_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_S_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_S_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_S_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_S_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_S_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_S_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_S_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_S_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_S_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_S_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_S_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_S_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_S_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_S_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_S_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_S_DEBOUNCE_THRESHOLD_06_0
#define GPIO_S_DEBOUNCE_THRESHOLD_06_0                  _MK_ADDR_CONST(0x136c4)
#define GPIO_S_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
#define GPIO_S_DEBOUNCE_THRESHOLD_06_0_DUAL                     0x0
#define GPIO_S_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_S_SCR_06_0
#define GPIO_S_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
#define GPIO_S_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_S_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_S_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_S_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_S_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_S_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_S_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_S_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_S_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_S_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_S_INPUT_06_0
#define GPIO_S_INPUT_06_0                       _MK_ADDR_CONST(0x136c8)
#define GPIO_S_INPUT_06_0_SECURE                        0x0
#define GPIO_S_INPUT_06_0_DUAL                  0x0
#define GPIO_S_INPUT_06_0_SCR                   GPIO_S_SCR_06_0
#define GPIO_S_INPUT_06_0_WORD_COUNT                    0x1
#define GPIO_S_INPUT_06_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_06_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_06_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_06_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_06_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_S_INPUT_06_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_06_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_S_INPUT_06_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_S_INPUT_06_0_GPIO_IN_SHIFT)
#define GPIO_S_INPUT_06_0_GPIO_IN_RANGE                 0:0
#define GPIO_S_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_S_INPUT_06_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_06_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_06_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_06_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_S_OUTPUT_CONTROL_06_0
#define GPIO_S_OUTPUT_CONTROL_06_0                      _MK_ADDR_CONST(0x136cc)
#define GPIO_S_OUTPUT_CONTROL_06_0_SECURE                       0x0
#define GPIO_S_OUTPUT_CONTROL_06_0_DUAL                         0x0
#define GPIO_S_OUTPUT_CONTROL_06_0_SCR                  GPIO_S_SCR_06_0
#define GPIO_S_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
#define GPIO_S_OUTPUT_CONTROL_06_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_06_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_CONTROL_06_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_06_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_S_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_S_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_S_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_S_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_S_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_S_OUTPUT_VALUE_06_0
#define GPIO_S_OUTPUT_VALUE_06_0                        _MK_ADDR_CONST(0x136d0)
#define GPIO_S_OUTPUT_VALUE_06_0_SECURE                         0x0
#define GPIO_S_OUTPUT_VALUE_06_0_DUAL                   0x0
#define GPIO_S_OUTPUT_VALUE_06_0_SCR                    GPIO_S_SCR_06_0
#define GPIO_S_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
#define GPIO_S_OUTPUT_VALUE_06_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_06_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_06_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_VALUE_06_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_S_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_S_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_S_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_S_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_S_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_S_INTERRUPT_CLEAR_06_0
#define GPIO_S_INTERRUPT_CLEAR_06_0                     _MK_ADDR_CONST(0x136d4)
#define GPIO_S_INTERRUPT_CLEAR_06_0_SECURE                      0x0
#define GPIO_S_INTERRUPT_CLEAR_06_0_DUAL                        0x0
#define GPIO_S_INTERRUPT_CLEAR_06_0_SCR                         GPIO_S_SCR_06_0
#define GPIO_S_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
#define GPIO_S_INTERRUPT_CLEAR_06_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_06_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_S_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_06_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_S_INTERRUPT_CLEAR_06_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_S_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_S_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_S_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_S_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_S_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_S_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_S_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_S_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_S_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x136d8

// Reserved address 0x136dc

// Register GPIO_S_ENABLE_CONFIG_07_0
#define GPIO_S_ENABLE_CONFIG_07_0                       _MK_ADDR_CONST(0x136e0)
#define GPIO_S_ENABLE_CONFIG_07_0_SECURE                        0x0
#define GPIO_S_ENABLE_CONFIG_07_0_DUAL                  0x0
#define GPIO_S_ENABLE_CONFIG_07_0_SCR                   GPIO_S_SCR_07_0
#define GPIO_S_ENABLE_CONFIG_07_0_WORD_COUNT                    0x1
#define GPIO_S_ENABLE_CONFIG_07_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_07_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_S_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_07_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_S_ENABLE_CONFIG_07_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_S_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_S_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_S_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
#define GPIO_S_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_S_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_S_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_07_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_07_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_S_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_S_ENABLE_CONFIG_07_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_S_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
#define GPIO_S_ENABLE_CONFIG_07_0_IN_OUT_RANGE                  1:1
#define GPIO_S_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                        0x0
#define GPIO_S_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_07_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_07_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_07_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_07_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_S_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_S_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_S_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
#define GPIO_S_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_S_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_S_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_S_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_S_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_S_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_S_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_S_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_S_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_S_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_S_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_S_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_S_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_S_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_S_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_S_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_S_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_S_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_S_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_S_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_S_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_S_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_S_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_S_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_S_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_S_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_S_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_S_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_S_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_S_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_S_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_S_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_S_DEBOUNCE_THRESHOLD_07_0
#define GPIO_S_DEBOUNCE_THRESHOLD_07_0                  _MK_ADDR_CONST(0x136e4)
#define GPIO_S_DEBOUNCE_THRESHOLD_07_0_SECURE                   0x0
#define GPIO_S_DEBOUNCE_THRESHOLD_07_0_DUAL                     0x0
#define GPIO_S_DEBOUNCE_THRESHOLD_07_0_SCR                      GPIO_S_SCR_07_0
#define GPIO_S_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                       0x1
#define GPIO_S_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_S_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_07_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_S_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_S_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_S_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_S_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_S_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_S_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_S_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_S_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_S_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_S_INPUT_07_0
#define GPIO_S_INPUT_07_0                       _MK_ADDR_CONST(0x136e8)
#define GPIO_S_INPUT_07_0_SECURE                        0x0
#define GPIO_S_INPUT_07_0_DUAL                  0x0
#define GPIO_S_INPUT_07_0_SCR                   GPIO_S_SCR_07_0
#define GPIO_S_INPUT_07_0_WORD_COUNT                    0x1
#define GPIO_S_INPUT_07_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_07_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_07_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_07_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_07_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_S_INPUT_07_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_07_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_S_INPUT_07_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_S_INPUT_07_0_GPIO_IN_SHIFT)
#define GPIO_S_INPUT_07_0_GPIO_IN_RANGE                 0:0
#define GPIO_S_INPUT_07_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_S_INPUT_07_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_07_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_07_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_07_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_S_INPUT_07_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_S_OUTPUT_CONTROL_07_0
#define GPIO_S_OUTPUT_CONTROL_07_0                      _MK_ADDR_CONST(0x136ec)
#define GPIO_S_OUTPUT_CONTROL_07_0_SECURE                       0x0
#define GPIO_S_OUTPUT_CONTROL_07_0_DUAL                         0x0
#define GPIO_S_OUTPUT_CONTROL_07_0_SCR                  GPIO_S_SCR_07_0
#define GPIO_S_OUTPUT_CONTROL_07_0_WORD_COUNT                   0x1
#define GPIO_S_OUTPUT_CONTROL_07_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_07_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_CONTROL_07_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_07_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_S_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_S_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_S_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_S_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_S_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_S_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_S_OUTPUT_VALUE_07_0
#define GPIO_S_OUTPUT_VALUE_07_0                        _MK_ADDR_CONST(0x136f0)
#define GPIO_S_OUTPUT_VALUE_07_0_SECURE                         0x0
#define GPIO_S_OUTPUT_VALUE_07_0_DUAL                   0x0
#define GPIO_S_OUTPUT_VALUE_07_0_SCR                    GPIO_S_SCR_07_0
#define GPIO_S_OUTPUT_VALUE_07_0_WORD_COUNT                     0x1
#define GPIO_S_OUTPUT_VALUE_07_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_07_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_07_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_VALUE_07_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_S_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_S_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_S_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_S_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_S_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_S_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_S_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_S_INTERRUPT_CLEAR_07_0
#define GPIO_S_INTERRUPT_CLEAR_07_0                     _MK_ADDR_CONST(0x136f4)
#define GPIO_S_INTERRUPT_CLEAR_07_0_SECURE                      0x0
#define GPIO_S_INTERRUPT_CLEAR_07_0_DUAL                        0x0
#define GPIO_S_INTERRUPT_CLEAR_07_0_SCR                         GPIO_S_SCR_07_0
#define GPIO_S_INTERRUPT_CLEAR_07_0_WORD_COUNT                  0x1
#define GPIO_S_INTERRUPT_CLEAR_07_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_07_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_S_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_07_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_S_INTERRUPT_CLEAR_07_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_S_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_S_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_S_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_S_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_S_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_S_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_S_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_S_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_S_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x136f8

// Reserved address 0x136fc

// Register GPIO_S_INTERRUPT_STATUS_G0_0
#define GPIO_S_INTERRUPT_STATUS_G0_0                    _MK_ADDR_CONST(0x13700)
#define GPIO_S_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_S_INTERRUPT_STATUS_G0_0_DUAL                       0x0
#define GPIO_S_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_S_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_S_INTERRUPT_STATUS_G0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G0_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_S_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G0_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_S_INTERRUPT_STATUS_G0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_S_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_S_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_S_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_S_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_S_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_S_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_S_INTERRUPT_STATUS_G1_0
#define GPIO_S_INTERRUPT_STATUS_G1_0                    _MK_ADDR_CONST(0x13704)
#define GPIO_S_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_S_INTERRUPT_STATUS_G1_0_DUAL                       0x0
#define GPIO_S_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_S_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_S_INTERRUPT_STATUS_G1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G1_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_S_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G1_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_S_INTERRUPT_STATUS_G1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_S_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_S_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_S_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_S_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_S_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_S_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_S_INTERRUPT_STATUS_G2_0
#define GPIO_S_INTERRUPT_STATUS_G2_0                    _MK_ADDR_CONST(0x13708)
#define GPIO_S_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_S_INTERRUPT_STATUS_G2_0_DUAL                       0x0
#define GPIO_S_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_S_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_S_INTERRUPT_STATUS_G2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G2_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_S_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G2_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_S_INTERRUPT_STATUS_G2_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_S_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_S_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_S_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_S_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_S_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_S_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_S_INTERRUPT_STATUS_G3_0
#define GPIO_S_INTERRUPT_STATUS_G3_0                    _MK_ADDR_CONST(0x1370c)
#define GPIO_S_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_S_INTERRUPT_STATUS_G3_0_DUAL                       0x0
#define GPIO_S_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_S_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_S_INTERRUPT_STATUS_G3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G3_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_S_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G3_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_S_INTERRUPT_STATUS_G3_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_S_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_S_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_S_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_S_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_S_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_S_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_S_INTERRUPT_STATUS_G4_0
#define GPIO_S_INTERRUPT_STATUS_G4_0                    _MK_ADDR_CONST(0x13710)
#define GPIO_S_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_S_INTERRUPT_STATUS_G4_0_DUAL                       0x0
#define GPIO_S_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_S_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_S_INTERRUPT_STATUS_G4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G4_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_S_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G4_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_S_INTERRUPT_STATUS_G4_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_S_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_S_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_S_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_S_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_S_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_S_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_S_INTERRUPT_STATUS_G5_0
#define GPIO_S_INTERRUPT_STATUS_G5_0                    _MK_ADDR_CONST(0x13714)
#define GPIO_S_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_S_INTERRUPT_STATUS_G5_0_DUAL                       0x0
#define GPIO_S_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_S_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_S_INTERRUPT_STATUS_G5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G5_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_S_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G5_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_S_INTERRUPT_STATUS_G5_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_S_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_S_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_S_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_S_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_S_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_S_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_S_INTERRUPT_STATUS_G6_0
#define GPIO_S_INTERRUPT_STATUS_G6_0                    _MK_ADDR_CONST(0x13718)
#define GPIO_S_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_S_INTERRUPT_STATUS_G6_0_DUAL                       0x0
#define GPIO_S_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_S_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_S_INTERRUPT_STATUS_G6_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G6_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_S_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G6_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_S_INTERRUPT_STATUS_G6_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_S_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_S_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_S_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_S_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_S_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_S_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_S_INTERRUPT_STATUS_G7_0
#define GPIO_S_INTERRUPT_STATUS_G7_0                    _MK_ADDR_CONST(0x1371c)
#define GPIO_S_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_S_INTERRUPT_STATUS_G7_0_DUAL                       0x0
#define GPIO_S_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_S_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_S_INTERRUPT_STATUS_G7_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G7_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_S_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G7_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_S_INTERRUPT_STATUS_G7_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_S_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_S_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_S_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_S_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_S_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_S_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_S_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Reserved address 0x13720

// Reserved address 0x13724

// Reserved address 0x13728

// Reserved address 0x1372c

// Reserved address 0x13730

// Reserved address 0x13734

// Reserved address 0x13738

// Reserved address 0x1373c

// Reserved address 0x13740

// Reserved address 0x13744

// Reserved address 0x13748

// Reserved address 0x1374c

// Reserved address 0x13750

// Reserved address 0x13754

// Reserved address 0x13758

// Reserved address 0x1375c

// Reserved address 0x13760

// Reserved address 0x13764

// Reserved address 0x13768

// Reserved address 0x1376c

// Reserved address 0x13770

// Reserved address 0x13774

// Reserved address 0x13778

// Reserved address 0x1377c

// Reserved address 0x13780

// Reserved address 0x13784

// Reserved address 0x13788

// Reserved address 0x1378c

// Reserved address 0x13790

// Reserved address 0x13794

// Reserved address 0x13798

// Reserved address 0x1379c

// Reserved address 0x137a0

// Reserved address 0x137a4

// Reserved address 0x137a8

// Reserved address 0x137ac

// Reserved address 0x137b0

// Reserved address 0x137b4

// Reserved address 0x137b8

// Reserved address 0x137bc

// Reserved address 0x137c0

// Reserved address 0x137c4

// Reserved address 0x137c8

// Reserved address 0x137cc

// Reserved address 0x137d0

// Reserved address 0x137d4

// Reserved address 0x137d8

// Reserved address 0x137dc

// Reserved address 0x137e0

// Reserved address 0x137e4

// Reserved address 0x137e8

// Reserved address 0x137ec

// Reserved address 0x137f0

// Reserved address 0x137f4

// Reserved address 0x137f8

// Reserved address 0x137fc

// Register GPIO_T_ENABLE_CONFIG_00_0
#define GPIO_T_ENABLE_CONFIG_00_0                       _MK_ADDR_CONST(0x13800)
#define GPIO_T_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_T_ENABLE_CONFIG_00_0_DUAL                  0x0
#define GPIO_T_ENABLE_CONFIG_00_0_SCR                   GPIO_T_SCR_00_0
#define GPIO_T_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_T_ENABLE_CONFIG_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_T_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_T_ENABLE_CONFIG_00_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_T_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_T_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_T_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_T_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_T_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_T_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_T_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_T_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_T_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_00_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_00_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_T_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_T_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_T_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_T_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_T_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_T_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_T_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_T_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_T_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_T_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_T_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_T_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_T_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_T_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_T_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_T_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_T_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_T_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_T_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_T_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_T_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_T_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_T_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_T_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_T_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_T_DEBOUNCE_THRESHOLD_00_0
#define GPIO_T_DEBOUNCE_THRESHOLD_00_0                  _MK_ADDR_CONST(0x13804)
#define GPIO_T_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_T_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
#define GPIO_T_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_T_SCR_00_0
#define GPIO_T_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_T_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_T_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_T_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_T_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_T_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_T_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_T_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_T_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_T_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_T_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_T_INPUT_00_0
#define GPIO_T_INPUT_00_0                       _MK_ADDR_CONST(0x13808)
#define GPIO_T_INPUT_00_0_SECURE                        0x0
#define GPIO_T_INPUT_00_0_DUAL                  0x0
#define GPIO_T_INPUT_00_0_SCR                   GPIO_T_SCR_00_0
#define GPIO_T_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_T_INPUT_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_00_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_00_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_T_INPUT_00_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_00_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_T_INPUT_00_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_T_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_T_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_T_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_T_INPUT_00_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_00_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_T_OUTPUT_CONTROL_00_0
#define GPIO_T_OUTPUT_CONTROL_00_0                      _MK_ADDR_CONST(0x1380c)
#define GPIO_T_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_T_OUTPUT_CONTROL_00_0_DUAL                         0x0
#define GPIO_T_OUTPUT_CONTROL_00_0_SCR                  GPIO_T_SCR_00_0
#define GPIO_T_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_T_OUTPUT_CONTROL_00_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_00_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_00_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_00_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_T_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_T_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_T_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_T_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_T_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_T_OUTPUT_VALUE_00_0
#define GPIO_T_OUTPUT_VALUE_00_0                        _MK_ADDR_CONST(0x13810)
#define GPIO_T_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_T_OUTPUT_VALUE_00_0_DUAL                   0x0
#define GPIO_T_OUTPUT_VALUE_00_0_SCR                    GPIO_T_SCR_00_0
#define GPIO_T_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_T_OUTPUT_VALUE_00_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_00_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_00_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_VALUE_00_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_T_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_T_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_T_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_T_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_T_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_T_INTERRUPT_CLEAR_00_0
#define GPIO_T_INTERRUPT_CLEAR_00_0                     _MK_ADDR_CONST(0x13814)
#define GPIO_T_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_T_INTERRUPT_CLEAR_00_0_DUAL                        0x0
#define GPIO_T_INTERRUPT_CLEAR_00_0_SCR                         GPIO_T_SCR_00_0
#define GPIO_T_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_T_INTERRUPT_CLEAR_00_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_00_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_00_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_00_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_T_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_T_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_T_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_T_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_T_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_T_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x13818

// Reserved address 0x1381c

// Register GPIO_T_ENABLE_CONFIG_01_0
#define GPIO_T_ENABLE_CONFIG_01_0                       _MK_ADDR_CONST(0x13820)
#define GPIO_T_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_T_ENABLE_CONFIG_01_0_DUAL                  0x0
#define GPIO_T_ENABLE_CONFIG_01_0_SCR                   GPIO_T_SCR_01_0
#define GPIO_T_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_T_ENABLE_CONFIG_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_T_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_T_ENABLE_CONFIG_01_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_T_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_T_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_T_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_T_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_T_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_T_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_T_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_T_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_T_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_01_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_01_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_T_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_T_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_T_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_T_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_T_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_T_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_T_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_T_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_T_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_T_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_T_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_T_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_T_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_T_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_T_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_T_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_T_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_T_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_T_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_T_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_T_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_T_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_T_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_T_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_T_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_T_DEBOUNCE_THRESHOLD_01_0
#define GPIO_T_DEBOUNCE_THRESHOLD_01_0                  _MK_ADDR_CONST(0x13824)
#define GPIO_T_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_T_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
#define GPIO_T_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_T_SCR_01_0
#define GPIO_T_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_T_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_T_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_T_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_T_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_T_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_T_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_T_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_T_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_T_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_T_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_T_INPUT_01_0
#define GPIO_T_INPUT_01_0                       _MK_ADDR_CONST(0x13828)
#define GPIO_T_INPUT_01_0_SECURE                        0x0
#define GPIO_T_INPUT_01_0_DUAL                  0x0
#define GPIO_T_INPUT_01_0_SCR                   GPIO_T_SCR_01_0
#define GPIO_T_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_T_INPUT_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_01_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_01_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_T_INPUT_01_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_01_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_T_INPUT_01_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_T_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_T_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_T_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_T_INPUT_01_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_01_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_T_OUTPUT_CONTROL_01_0
#define GPIO_T_OUTPUT_CONTROL_01_0                      _MK_ADDR_CONST(0x1382c)
#define GPIO_T_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_T_OUTPUT_CONTROL_01_0_DUAL                         0x0
#define GPIO_T_OUTPUT_CONTROL_01_0_SCR                  GPIO_T_SCR_01_0
#define GPIO_T_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_T_OUTPUT_CONTROL_01_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_01_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_01_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_01_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_T_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_T_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_T_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_T_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_T_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_T_OUTPUT_VALUE_01_0
#define GPIO_T_OUTPUT_VALUE_01_0                        _MK_ADDR_CONST(0x13830)
#define GPIO_T_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_T_OUTPUT_VALUE_01_0_DUAL                   0x0
#define GPIO_T_OUTPUT_VALUE_01_0_SCR                    GPIO_T_SCR_01_0
#define GPIO_T_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_T_OUTPUT_VALUE_01_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_01_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_01_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_VALUE_01_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_T_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_T_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_T_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_T_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_T_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_T_INTERRUPT_CLEAR_01_0
#define GPIO_T_INTERRUPT_CLEAR_01_0                     _MK_ADDR_CONST(0x13834)
#define GPIO_T_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_T_INTERRUPT_CLEAR_01_0_DUAL                        0x0
#define GPIO_T_INTERRUPT_CLEAR_01_0_SCR                         GPIO_T_SCR_01_0
#define GPIO_T_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_T_INTERRUPT_CLEAR_01_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_01_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_01_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_01_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_T_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_T_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_T_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_T_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_T_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_T_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x13838

// Reserved address 0x1383c

// Register GPIO_T_ENABLE_CONFIG_02_0
#define GPIO_T_ENABLE_CONFIG_02_0                       _MK_ADDR_CONST(0x13840)
#define GPIO_T_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_T_ENABLE_CONFIG_02_0_DUAL                  0x0
#define GPIO_T_ENABLE_CONFIG_02_0_SCR                   GPIO_T_SCR_02_0
#define GPIO_T_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_T_ENABLE_CONFIG_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_T_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_T_ENABLE_CONFIG_02_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_T_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_T_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_T_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_T_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_T_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_T_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_T_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_T_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_T_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_02_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_02_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_T_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_T_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_T_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_T_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_T_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_T_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_T_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_T_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_T_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_T_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_T_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_T_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_T_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_T_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_T_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_T_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_T_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_T_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_T_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_T_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_T_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_T_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_T_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_T_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_T_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_T_DEBOUNCE_THRESHOLD_02_0
#define GPIO_T_DEBOUNCE_THRESHOLD_02_0                  _MK_ADDR_CONST(0x13844)
#define GPIO_T_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_T_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
#define GPIO_T_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_T_SCR_02_0
#define GPIO_T_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_T_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_T_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_T_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_T_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_T_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_T_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_T_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_T_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_T_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_T_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_T_INPUT_02_0
#define GPIO_T_INPUT_02_0                       _MK_ADDR_CONST(0x13848)
#define GPIO_T_INPUT_02_0_SECURE                        0x0
#define GPIO_T_INPUT_02_0_DUAL                  0x0
#define GPIO_T_INPUT_02_0_SCR                   GPIO_T_SCR_02_0
#define GPIO_T_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_T_INPUT_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_02_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_02_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_T_INPUT_02_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_02_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_T_INPUT_02_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_T_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_T_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_T_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_T_INPUT_02_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_02_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_T_OUTPUT_CONTROL_02_0
#define GPIO_T_OUTPUT_CONTROL_02_0                      _MK_ADDR_CONST(0x1384c)
#define GPIO_T_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_T_OUTPUT_CONTROL_02_0_DUAL                         0x0
#define GPIO_T_OUTPUT_CONTROL_02_0_SCR                  GPIO_T_SCR_02_0
#define GPIO_T_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_T_OUTPUT_CONTROL_02_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_02_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_02_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_02_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_T_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_T_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_T_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_T_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_T_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_T_OUTPUT_VALUE_02_0
#define GPIO_T_OUTPUT_VALUE_02_0                        _MK_ADDR_CONST(0x13850)
#define GPIO_T_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_T_OUTPUT_VALUE_02_0_DUAL                   0x0
#define GPIO_T_OUTPUT_VALUE_02_0_SCR                    GPIO_T_SCR_02_0
#define GPIO_T_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_T_OUTPUT_VALUE_02_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_02_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_02_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_VALUE_02_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_T_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_T_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_T_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_T_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_T_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_T_INTERRUPT_CLEAR_02_0
#define GPIO_T_INTERRUPT_CLEAR_02_0                     _MK_ADDR_CONST(0x13854)
#define GPIO_T_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_T_INTERRUPT_CLEAR_02_0_DUAL                        0x0
#define GPIO_T_INTERRUPT_CLEAR_02_0_SCR                         GPIO_T_SCR_02_0
#define GPIO_T_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_T_INTERRUPT_CLEAR_02_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_02_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_02_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_02_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_T_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_T_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_T_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_T_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_T_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_T_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x13858

// Reserved address 0x1385c

// Register GPIO_T_ENABLE_CONFIG_03_0
#define GPIO_T_ENABLE_CONFIG_03_0                       _MK_ADDR_CONST(0x13860)
#define GPIO_T_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_T_ENABLE_CONFIG_03_0_DUAL                  0x0
#define GPIO_T_ENABLE_CONFIG_03_0_SCR                   GPIO_T_SCR_03_0
#define GPIO_T_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_T_ENABLE_CONFIG_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_T_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_T_ENABLE_CONFIG_03_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_T_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_T_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_T_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_T_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_T_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_T_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_T_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_T_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_T_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_03_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_03_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_T_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_T_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_T_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_T_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_T_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_T_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_T_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_T_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_T_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_T_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_T_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_T_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_T_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_T_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_T_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_T_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_T_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_T_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_T_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_T_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_T_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_T_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_T_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_T_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_T_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_T_DEBOUNCE_THRESHOLD_03_0
#define GPIO_T_DEBOUNCE_THRESHOLD_03_0                  _MK_ADDR_CONST(0x13864)
#define GPIO_T_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_T_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
#define GPIO_T_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_T_SCR_03_0
#define GPIO_T_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_T_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_T_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_T_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_T_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_T_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_T_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_T_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_T_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_T_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_T_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_T_INPUT_03_0
#define GPIO_T_INPUT_03_0                       _MK_ADDR_CONST(0x13868)
#define GPIO_T_INPUT_03_0_SECURE                        0x0
#define GPIO_T_INPUT_03_0_DUAL                  0x0
#define GPIO_T_INPUT_03_0_SCR                   GPIO_T_SCR_03_0
#define GPIO_T_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_T_INPUT_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_03_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_03_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_T_INPUT_03_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_03_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_T_INPUT_03_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_T_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_T_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_T_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_T_INPUT_03_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_03_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_T_OUTPUT_CONTROL_03_0
#define GPIO_T_OUTPUT_CONTROL_03_0                      _MK_ADDR_CONST(0x1386c)
#define GPIO_T_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_T_OUTPUT_CONTROL_03_0_DUAL                         0x0
#define GPIO_T_OUTPUT_CONTROL_03_0_SCR                  GPIO_T_SCR_03_0
#define GPIO_T_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_T_OUTPUT_CONTROL_03_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_03_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_03_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_03_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_T_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_T_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_T_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_T_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_T_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_T_OUTPUT_VALUE_03_0
#define GPIO_T_OUTPUT_VALUE_03_0                        _MK_ADDR_CONST(0x13870)
#define GPIO_T_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_T_OUTPUT_VALUE_03_0_DUAL                   0x0
#define GPIO_T_OUTPUT_VALUE_03_0_SCR                    GPIO_T_SCR_03_0
#define GPIO_T_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_T_OUTPUT_VALUE_03_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_03_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_03_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_VALUE_03_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_T_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_T_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_T_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_T_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_T_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_T_INTERRUPT_CLEAR_03_0
#define GPIO_T_INTERRUPT_CLEAR_03_0                     _MK_ADDR_CONST(0x13874)
#define GPIO_T_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_T_INTERRUPT_CLEAR_03_0_DUAL                        0x0
#define GPIO_T_INTERRUPT_CLEAR_03_0_SCR                         GPIO_T_SCR_03_0
#define GPIO_T_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_T_INTERRUPT_CLEAR_03_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_03_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_03_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_03_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_T_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_T_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_T_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_T_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_T_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_T_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x13878

// Reserved address 0x1387c

// Register GPIO_T_ENABLE_CONFIG_04_0
#define GPIO_T_ENABLE_CONFIG_04_0                       _MK_ADDR_CONST(0x13880)
#define GPIO_T_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_T_ENABLE_CONFIG_04_0_DUAL                  0x0
#define GPIO_T_ENABLE_CONFIG_04_0_SCR                   GPIO_T_SCR_04_0
#define GPIO_T_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_T_ENABLE_CONFIG_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_04_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_T_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_04_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_T_ENABLE_CONFIG_04_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_T_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_T_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_T_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_T_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_T_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_T_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_T_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_T_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_T_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_04_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_04_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_T_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_T_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_T_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_T_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_T_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_T_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_T_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_T_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_T_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_T_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_T_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_T_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_T_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_T_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_T_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_T_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_T_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_T_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_T_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_T_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_T_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_T_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_T_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_T_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_T_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_T_DEBOUNCE_THRESHOLD_04_0
#define GPIO_T_DEBOUNCE_THRESHOLD_04_0                  _MK_ADDR_CONST(0x13884)
#define GPIO_T_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_T_DEBOUNCE_THRESHOLD_04_0_DUAL                     0x0
#define GPIO_T_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_T_SCR_04_0
#define GPIO_T_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_T_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_T_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_T_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_T_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_T_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_T_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_T_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_T_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_T_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_T_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_T_INPUT_04_0
#define GPIO_T_INPUT_04_0                       _MK_ADDR_CONST(0x13888)
#define GPIO_T_INPUT_04_0_SECURE                        0x0
#define GPIO_T_INPUT_04_0_DUAL                  0x0
#define GPIO_T_INPUT_04_0_SCR                   GPIO_T_SCR_04_0
#define GPIO_T_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_T_INPUT_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_04_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_04_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_T_INPUT_04_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_04_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_T_INPUT_04_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_T_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_T_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_T_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_T_INPUT_04_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_04_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_T_OUTPUT_CONTROL_04_0
#define GPIO_T_OUTPUT_CONTROL_04_0                      _MK_ADDR_CONST(0x1388c)
#define GPIO_T_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_T_OUTPUT_CONTROL_04_0_DUAL                         0x0
#define GPIO_T_OUTPUT_CONTROL_04_0_SCR                  GPIO_T_SCR_04_0
#define GPIO_T_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_T_OUTPUT_CONTROL_04_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_04_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_04_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_04_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_T_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_T_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_T_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_T_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_T_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_T_OUTPUT_VALUE_04_0
#define GPIO_T_OUTPUT_VALUE_04_0                        _MK_ADDR_CONST(0x13890)
#define GPIO_T_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_T_OUTPUT_VALUE_04_0_DUAL                   0x0
#define GPIO_T_OUTPUT_VALUE_04_0_SCR                    GPIO_T_SCR_04_0
#define GPIO_T_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_T_OUTPUT_VALUE_04_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_04_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_04_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_VALUE_04_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_T_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_T_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_T_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_T_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_T_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_T_INTERRUPT_CLEAR_04_0
#define GPIO_T_INTERRUPT_CLEAR_04_0                     _MK_ADDR_CONST(0x13894)
#define GPIO_T_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_T_INTERRUPT_CLEAR_04_0_DUAL                        0x0
#define GPIO_T_INTERRUPT_CLEAR_04_0_SCR                         GPIO_T_SCR_04_0
#define GPIO_T_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_T_INTERRUPT_CLEAR_04_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_04_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_04_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_04_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_T_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_T_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_T_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_T_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_T_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_T_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x13898

// Reserved address 0x1389c

// Register GPIO_T_ENABLE_CONFIG_05_0
#define GPIO_T_ENABLE_CONFIG_05_0                       _MK_ADDR_CONST(0x138a0)
#define GPIO_T_ENABLE_CONFIG_05_0_SECURE                        0x0
#define GPIO_T_ENABLE_CONFIG_05_0_DUAL                  0x0
#define GPIO_T_ENABLE_CONFIG_05_0_SCR                   GPIO_T_SCR_05_0
#define GPIO_T_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
#define GPIO_T_ENABLE_CONFIG_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_05_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_T_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_05_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_T_ENABLE_CONFIG_05_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_T_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_T_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_T_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_T_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_T_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_T_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_T_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
#define GPIO_T_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
#define GPIO_T_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_05_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_05_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_T_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_T_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_T_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_T_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_T_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_T_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_T_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_T_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_T_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_T_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_T_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_T_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_T_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_T_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_T_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_T_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_T_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_T_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_T_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_T_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_T_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_T_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_T_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_T_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_T_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_T_DEBOUNCE_THRESHOLD_05_0
#define GPIO_T_DEBOUNCE_THRESHOLD_05_0                  _MK_ADDR_CONST(0x138a4)
#define GPIO_T_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
#define GPIO_T_DEBOUNCE_THRESHOLD_05_0_DUAL                     0x0
#define GPIO_T_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_T_SCR_05_0
#define GPIO_T_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
#define GPIO_T_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_T_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_T_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_T_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_T_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_T_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_T_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_T_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_T_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_T_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_T_INPUT_05_0
#define GPIO_T_INPUT_05_0                       _MK_ADDR_CONST(0x138a8)
#define GPIO_T_INPUT_05_0_SECURE                        0x0
#define GPIO_T_INPUT_05_0_DUAL                  0x0
#define GPIO_T_INPUT_05_0_SCR                   GPIO_T_SCR_05_0
#define GPIO_T_INPUT_05_0_WORD_COUNT                    0x1
#define GPIO_T_INPUT_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_05_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_05_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_T_INPUT_05_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_05_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_T_INPUT_05_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_T_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_T_INPUT_05_0_GPIO_IN_RANGE                 0:0
#define GPIO_T_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_T_INPUT_05_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_05_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_T_OUTPUT_CONTROL_05_0
#define GPIO_T_OUTPUT_CONTROL_05_0                      _MK_ADDR_CONST(0x138ac)
#define GPIO_T_OUTPUT_CONTROL_05_0_SECURE                       0x0
#define GPIO_T_OUTPUT_CONTROL_05_0_DUAL                         0x0
#define GPIO_T_OUTPUT_CONTROL_05_0_SCR                  GPIO_T_SCR_05_0
#define GPIO_T_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
#define GPIO_T_OUTPUT_CONTROL_05_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_05_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_05_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_05_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_T_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_T_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_T_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_T_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_T_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_T_OUTPUT_VALUE_05_0
#define GPIO_T_OUTPUT_VALUE_05_0                        _MK_ADDR_CONST(0x138b0)
#define GPIO_T_OUTPUT_VALUE_05_0_SECURE                         0x0
#define GPIO_T_OUTPUT_VALUE_05_0_DUAL                   0x0
#define GPIO_T_OUTPUT_VALUE_05_0_SCR                    GPIO_T_SCR_05_0
#define GPIO_T_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
#define GPIO_T_OUTPUT_VALUE_05_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_05_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_05_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_VALUE_05_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_T_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_T_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_T_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_T_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_T_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_T_INTERRUPT_CLEAR_05_0
#define GPIO_T_INTERRUPT_CLEAR_05_0                     _MK_ADDR_CONST(0x138b4)
#define GPIO_T_INTERRUPT_CLEAR_05_0_SECURE                      0x0
#define GPIO_T_INTERRUPT_CLEAR_05_0_DUAL                        0x0
#define GPIO_T_INTERRUPT_CLEAR_05_0_SCR                         GPIO_T_SCR_05_0
#define GPIO_T_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
#define GPIO_T_INTERRUPT_CLEAR_05_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_05_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_05_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_05_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_T_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_T_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_T_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_T_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_T_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_T_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x138b8

// Reserved address 0x138bc

// Register GPIO_T_ENABLE_CONFIG_06_0
#define GPIO_T_ENABLE_CONFIG_06_0                       _MK_ADDR_CONST(0x138c0)
#define GPIO_T_ENABLE_CONFIG_06_0_SECURE                        0x0
#define GPIO_T_ENABLE_CONFIG_06_0_DUAL                  0x0
#define GPIO_T_ENABLE_CONFIG_06_0_SCR                   GPIO_T_SCR_06_0
#define GPIO_T_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
#define GPIO_T_ENABLE_CONFIG_06_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_06_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_T_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_06_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_T_ENABLE_CONFIG_06_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_T_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_T_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
#define GPIO_T_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_T_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_T_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_06_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_06_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_T_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
#define GPIO_T_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
#define GPIO_T_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
#define GPIO_T_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_06_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_06_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_06_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_06_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_T_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_T_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
#define GPIO_T_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_T_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_T_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_T_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_T_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_T_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_T_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_T_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_T_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_T_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_T_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_T_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_T_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_T_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_T_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_T_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_T_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_T_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_T_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_T_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_T_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_T_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_T_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_T_DEBOUNCE_THRESHOLD_06_0
#define GPIO_T_DEBOUNCE_THRESHOLD_06_0                  _MK_ADDR_CONST(0x138c4)
#define GPIO_T_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
#define GPIO_T_DEBOUNCE_THRESHOLD_06_0_DUAL                     0x0
#define GPIO_T_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_T_SCR_06_0
#define GPIO_T_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
#define GPIO_T_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_T_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_T_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_T_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_T_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_T_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_T_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_T_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_T_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_T_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_T_INPUT_06_0
#define GPIO_T_INPUT_06_0                       _MK_ADDR_CONST(0x138c8)
#define GPIO_T_INPUT_06_0_SECURE                        0x0
#define GPIO_T_INPUT_06_0_DUAL                  0x0
#define GPIO_T_INPUT_06_0_SCR                   GPIO_T_SCR_06_0
#define GPIO_T_INPUT_06_0_WORD_COUNT                    0x1
#define GPIO_T_INPUT_06_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_06_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_06_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_06_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_06_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_T_INPUT_06_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_06_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_T_INPUT_06_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_T_INPUT_06_0_GPIO_IN_SHIFT)
#define GPIO_T_INPUT_06_0_GPIO_IN_RANGE                 0:0
#define GPIO_T_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_T_INPUT_06_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_06_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_06_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_06_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_T_OUTPUT_CONTROL_06_0
#define GPIO_T_OUTPUT_CONTROL_06_0                      _MK_ADDR_CONST(0x138cc)
#define GPIO_T_OUTPUT_CONTROL_06_0_SECURE                       0x0
#define GPIO_T_OUTPUT_CONTROL_06_0_DUAL                         0x0
#define GPIO_T_OUTPUT_CONTROL_06_0_SCR                  GPIO_T_SCR_06_0
#define GPIO_T_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
#define GPIO_T_OUTPUT_CONTROL_06_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_06_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_06_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_06_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_T_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_T_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_T_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_T_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_T_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_T_OUTPUT_VALUE_06_0
#define GPIO_T_OUTPUT_VALUE_06_0                        _MK_ADDR_CONST(0x138d0)
#define GPIO_T_OUTPUT_VALUE_06_0_SECURE                         0x0
#define GPIO_T_OUTPUT_VALUE_06_0_DUAL                   0x0
#define GPIO_T_OUTPUT_VALUE_06_0_SCR                    GPIO_T_SCR_06_0
#define GPIO_T_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
#define GPIO_T_OUTPUT_VALUE_06_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_06_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_06_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_VALUE_06_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_T_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_T_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_T_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_T_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_T_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_T_INTERRUPT_CLEAR_06_0
#define GPIO_T_INTERRUPT_CLEAR_06_0                     _MK_ADDR_CONST(0x138d4)
#define GPIO_T_INTERRUPT_CLEAR_06_0_SECURE                      0x0
#define GPIO_T_INTERRUPT_CLEAR_06_0_DUAL                        0x0
#define GPIO_T_INTERRUPT_CLEAR_06_0_SCR                         GPIO_T_SCR_06_0
#define GPIO_T_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
#define GPIO_T_INTERRUPT_CLEAR_06_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_06_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_06_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_06_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_T_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_T_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_T_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_T_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_T_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_T_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x138d8

// Reserved address 0x138dc

// Register GPIO_T_ENABLE_CONFIG_07_0
#define GPIO_T_ENABLE_CONFIG_07_0                       _MK_ADDR_CONST(0x138e0)
#define GPIO_T_ENABLE_CONFIG_07_0_SECURE                        0x0
#define GPIO_T_ENABLE_CONFIG_07_0_DUAL                  0x0
#define GPIO_T_ENABLE_CONFIG_07_0_SCR                   GPIO_T_SCR_07_0
#define GPIO_T_ENABLE_CONFIG_07_0_WORD_COUNT                    0x1
#define GPIO_T_ENABLE_CONFIG_07_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_07_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_T_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_07_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_T_ENABLE_CONFIG_07_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_T_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_T_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
#define GPIO_T_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_T_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_T_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_07_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_07_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_T_ENABLE_CONFIG_07_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
#define GPIO_T_ENABLE_CONFIG_07_0_IN_OUT_RANGE                  1:1
#define GPIO_T_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                        0x0
#define GPIO_T_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_07_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_07_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_07_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_07_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_T_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_T_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
#define GPIO_T_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_T_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_T_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_T_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_T_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_T_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_T_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_T_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_T_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_T_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_T_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_T_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_T_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_T_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_T_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_T_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_T_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_T_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_T_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_T_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_T_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_T_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_T_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_T_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_T_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_T_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_T_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_T_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_T_DEBOUNCE_THRESHOLD_07_0
#define GPIO_T_DEBOUNCE_THRESHOLD_07_0                  _MK_ADDR_CONST(0x138e4)
#define GPIO_T_DEBOUNCE_THRESHOLD_07_0_SECURE                   0x0
#define GPIO_T_DEBOUNCE_THRESHOLD_07_0_DUAL                     0x0
#define GPIO_T_DEBOUNCE_THRESHOLD_07_0_SCR                      GPIO_T_SCR_07_0
#define GPIO_T_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                       0x1
#define GPIO_T_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_T_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_07_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_T_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_T_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_T_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_T_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_T_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_T_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_T_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_T_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_T_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_T_INPUT_07_0
#define GPIO_T_INPUT_07_0                       _MK_ADDR_CONST(0x138e8)
#define GPIO_T_INPUT_07_0_SECURE                        0x0
#define GPIO_T_INPUT_07_0_DUAL                  0x0
#define GPIO_T_INPUT_07_0_SCR                   GPIO_T_SCR_07_0
#define GPIO_T_INPUT_07_0_WORD_COUNT                    0x1
#define GPIO_T_INPUT_07_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_07_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_07_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_07_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_07_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_T_INPUT_07_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_07_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_T_INPUT_07_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_T_INPUT_07_0_GPIO_IN_SHIFT)
#define GPIO_T_INPUT_07_0_GPIO_IN_RANGE                 0:0
#define GPIO_T_INPUT_07_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_T_INPUT_07_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_07_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_07_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_07_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_T_INPUT_07_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_T_OUTPUT_CONTROL_07_0
#define GPIO_T_OUTPUT_CONTROL_07_0                      _MK_ADDR_CONST(0x138ec)
#define GPIO_T_OUTPUT_CONTROL_07_0_SECURE                       0x0
#define GPIO_T_OUTPUT_CONTROL_07_0_DUAL                         0x0
#define GPIO_T_OUTPUT_CONTROL_07_0_SCR                  GPIO_T_SCR_07_0
#define GPIO_T_OUTPUT_CONTROL_07_0_WORD_COUNT                   0x1
#define GPIO_T_OUTPUT_CONTROL_07_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_07_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_07_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_07_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_T_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_T_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_T_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_T_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_T_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_T_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_T_OUTPUT_VALUE_07_0
#define GPIO_T_OUTPUT_VALUE_07_0                        _MK_ADDR_CONST(0x138f0)
#define GPIO_T_OUTPUT_VALUE_07_0_SECURE                         0x0
#define GPIO_T_OUTPUT_VALUE_07_0_DUAL                   0x0
#define GPIO_T_OUTPUT_VALUE_07_0_SCR                    GPIO_T_SCR_07_0
#define GPIO_T_OUTPUT_VALUE_07_0_WORD_COUNT                     0x1
#define GPIO_T_OUTPUT_VALUE_07_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_07_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_07_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_VALUE_07_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_T_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_T_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_T_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_T_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_T_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_T_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_T_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_T_INTERRUPT_CLEAR_07_0
#define GPIO_T_INTERRUPT_CLEAR_07_0                     _MK_ADDR_CONST(0x138f4)
#define GPIO_T_INTERRUPT_CLEAR_07_0_SECURE                      0x0
#define GPIO_T_INTERRUPT_CLEAR_07_0_DUAL                        0x0
#define GPIO_T_INTERRUPT_CLEAR_07_0_SCR                         GPIO_T_SCR_07_0
#define GPIO_T_INTERRUPT_CLEAR_07_0_WORD_COUNT                  0x1
#define GPIO_T_INTERRUPT_CLEAR_07_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_07_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_07_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_07_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_T_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_T_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_T_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_T_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_T_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_T_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_T_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x138f8

// Reserved address 0x138fc

// Register GPIO_T_INTERRUPT_STATUS_G0_0
#define GPIO_T_INTERRUPT_STATUS_G0_0                    _MK_ADDR_CONST(0x13900)
#define GPIO_T_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_T_INTERRUPT_STATUS_G0_0_DUAL                       0x0
#define GPIO_T_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_T_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_T_INTERRUPT_STATUS_G0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G0_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_T_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G0_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_T_INTERRUPT_STATUS_G0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_T_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_T_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_T_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_T_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_T_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_T_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_T_INTERRUPT_STATUS_G1_0
#define GPIO_T_INTERRUPT_STATUS_G1_0                    _MK_ADDR_CONST(0x13904)
#define GPIO_T_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_T_INTERRUPT_STATUS_G1_0_DUAL                       0x0
#define GPIO_T_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_T_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_T_INTERRUPT_STATUS_G1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G1_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_T_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G1_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_T_INTERRUPT_STATUS_G1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_T_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_T_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_T_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_T_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_T_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_T_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_T_INTERRUPT_STATUS_G2_0
#define GPIO_T_INTERRUPT_STATUS_G2_0                    _MK_ADDR_CONST(0x13908)
#define GPIO_T_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_T_INTERRUPT_STATUS_G2_0_DUAL                       0x0
#define GPIO_T_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_T_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_T_INTERRUPT_STATUS_G2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G2_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_T_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G2_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_T_INTERRUPT_STATUS_G2_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_T_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_T_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_T_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_T_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_T_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_T_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_T_INTERRUPT_STATUS_G3_0
#define GPIO_T_INTERRUPT_STATUS_G3_0                    _MK_ADDR_CONST(0x1390c)
#define GPIO_T_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_T_INTERRUPT_STATUS_G3_0_DUAL                       0x0
#define GPIO_T_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_T_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_T_INTERRUPT_STATUS_G3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G3_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_T_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G3_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_T_INTERRUPT_STATUS_G3_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_T_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_T_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_T_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_T_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_T_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_T_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_T_INTERRUPT_STATUS_G4_0
#define GPIO_T_INTERRUPT_STATUS_G4_0                    _MK_ADDR_CONST(0x13910)
#define GPIO_T_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_T_INTERRUPT_STATUS_G4_0_DUAL                       0x0
#define GPIO_T_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_T_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_T_INTERRUPT_STATUS_G4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G4_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_T_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G4_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_T_INTERRUPT_STATUS_G4_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_T_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_T_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_T_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_T_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_T_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_T_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_T_INTERRUPT_STATUS_G5_0
#define GPIO_T_INTERRUPT_STATUS_G5_0                    _MK_ADDR_CONST(0x13914)
#define GPIO_T_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_T_INTERRUPT_STATUS_G5_0_DUAL                       0x0
#define GPIO_T_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_T_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_T_INTERRUPT_STATUS_G5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G5_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_T_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G5_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_T_INTERRUPT_STATUS_G5_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_T_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_T_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_T_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_T_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_T_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_T_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_T_INTERRUPT_STATUS_G6_0
#define GPIO_T_INTERRUPT_STATUS_G6_0                    _MK_ADDR_CONST(0x13918)
#define GPIO_T_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_T_INTERRUPT_STATUS_G6_0_DUAL                       0x0
#define GPIO_T_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_T_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_T_INTERRUPT_STATUS_G6_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G6_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_T_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G6_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_T_INTERRUPT_STATUS_G6_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_T_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_T_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_T_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_T_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_T_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_T_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_T_INTERRUPT_STATUS_G7_0
#define GPIO_T_INTERRUPT_STATUS_G7_0                    _MK_ADDR_CONST(0x1391c)
#define GPIO_T_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_T_INTERRUPT_STATUS_G7_0_DUAL                       0x0
#define GPIO_T_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_T_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_T_INTERRUPT_STATUS_G7_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G7_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_T_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G7_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_T_INTERRUPT_STATUS_G7_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_T_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_T_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_T_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_T_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_T_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_T_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_T_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Reserved address 0x13920

// Reserved address 0x13924

// Reserved address 0x13928

// Reserved address 0x1392c

// Reserved address 0x13930

// Reserved address 0x13934

// Reserved address 0x13938

// Reserved address 0x1393c

// Reserved address 0x13940

// Reserved address 0x13944

// Reserved address 0x13948

// Reserved address 0x1394c

// Reserved address 0x13950

// Reserved address 0x13954

// Reserved address 0x13958

// Reserved address 0x1395c

// Reserved address 0x13960

// Reserved address 0x13964

// Reserved address 0x13968

// Reserved address 0x1396c

// Reserved address 0x13970

// Reserved address 0x13974

// Reserved address 0x13978

// Reserved address 0x1397c

// Reserved address 0x13980

// Reserved address 0x13984

// Reserved address 0x13988

// Reserved address 0x1398c

// Reserved address 0x13990

// Reserved address 0x13994

// Reserved address 0x13998

// Reserved address 0x1399c

// Reserved address 0x139a0

// Reserved address 0x139a4

// Reserved address 0x139a8

// Reserved address 0x139ac

// Reserved address 0x139b0

// Reserved address 0x139b4

// Reserved address 0x139b8

// Reserved address 0x139bc

// Reserved address 0x139c0

// Reserved address 0x139c4

// Reserved address 0x139c8

// Reserved address 0x139cc

// Reserved address 0x139d0

// Reserved address 0x139d4

// Reserved address 0x139d8

// Reserved address 0x139dc

// Reserved address 0x139e0

// Reserved address 0x139e4

// Reserved address 0x139e8

// Reserved address 0x139ec

// Reserved address 0x139f0

// Reserved address 0x139f4

// Reserved address 0x139f8

// Reserved address 0x139fc

// Register GPIO_U_ENABLE_CONFIG_00_0
#define GPIO_U_ENABLE_CONFIG_00_0                       _MK_ADDR_CONST(0x13a00)
#define GPIO_U_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_U_ENABLE_CONFIG_00_0_DUAL                  0x0
#define GPIO_U_ENABLE_CONFIG_00_0_SCR                   GPIO_U_SCR_00_0
#define GPIO_U_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_U_ENABLE_CONFIG_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_U_ENABLE_CONFIG_00_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_U_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_U_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_U_ENABLE_CONFIG_00_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_U_ENABLE_CONFIG_00_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_U_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_U_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_U_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_U_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_U_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_U_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_U_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_U_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_U_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_U_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_U_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_U_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_U_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_U_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_U_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_U_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_U_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_U_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_U_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_U_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_U_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_U_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_U_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_U_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_U_ENABLE_CONFIG_00_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_U_ENABLE_CONFIG_00_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_U_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_U_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_U_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_U_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_U_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_U_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_U_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_U_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_U_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_U_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_U_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_U_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_U_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_U_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_U_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_U_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_U_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_U_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_U_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_U_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_U_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_U_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_U_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_U_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_U_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_U_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_U_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_U_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_U_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_U_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_U_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_U_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_U_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_U_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_U_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_U_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_U_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_U_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_U_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_U_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_U_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_U_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_U_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_U_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_U_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_U_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_U_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_U_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_U_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_U_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_U_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_U_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_U_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_U_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_U_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_U_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_U_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_U_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_U_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_U_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_U_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_U_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_U_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_U_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_U_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_U_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_U_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_U_DEBOUNCE_THRESHOLD_00_0
#define GPIO_U_DEBOUNCE_THRESHOLD_00_0                  _MK_ADDR_CONST(0x13a04)
#define GPIO_U_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_U_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
#define GPIO_U_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_U_SCR_00_0
#define GPIO_U_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_U_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_U_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_U_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_U_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_U_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_U_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_U_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_U_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_U_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_U_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_U_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_U_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_U_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_U_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_U_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_U_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_U_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_U_INPUT_00_0
#define GPIO_U_INPUT_00_0                       _MK_ADDR_CONST(0x13a08)
#define GPIO_U_INPUT_00_0_SECURE                        0x0
#define GPIO_U_INPUT_00_0_DUAL                  0x0
#define GPIO_U_INPUT_00_0_SCR                   GPIO_U_SCR_00_0
#define GPIO_U_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_U_INPUT_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_U_INPUT_00_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_U_INPUT_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_U_INPUT_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_U_INPUT_00_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_U_INPUT_00_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_U_INPUT_00_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_U_INPUT_00_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_U_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_U_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_U_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_U_INPUT_00_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_U_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_U_INPUT_00_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_U_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_U_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_U_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_U_OUTPUT_CONTROL_00_0
#define GPIO_U_OUTPUT_CONTROL_00_0                      _MK_ADDR_CONST(0x13a0c)
#define GPIO_U_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_U_OUTPUT_CONTROL_00_0_DUAL                         0x0
#define GPIO_U_OUTPUT_CONTROL_00_0_SCR                  GPIO_U_SCR_00_0
#define GPIO_U_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_U_OUTPUT_CONTROL_00_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_U_OUTPUT_CONTROL_00_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_U_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_U_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_U_OUTPUT_CONTROL_00_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_U_OUTPUT_CONTROL_00_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_U_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_U_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_U_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_U_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_U_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_U_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_U_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_U_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_U_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_U_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_U_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_U_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_U_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_U_OUTPUT_VALUE_00_0
#define GPIO_U_OUTPUT_VALUE_00_0                        _MK_ADDR_CONST(0x13a10)
#define GPIO_U_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_U_OUTPUT_VALUE_00_0_DUAL                   0x0
#define GPIO_U_OUTPUT_VALUE_00_0_SCR                    GPIO_U_SCR_00_0
#define GPIO_U_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_U_OUTPUT_VALUE_00_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_U_OUTPUT_VALUE_00_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_U_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_U_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_U_OUTPUT_VALUE_00_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_U_OUTPUT_VALUE_00_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_U_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_U_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_U_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_U_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_U_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_U_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_U_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_U_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_U_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_U_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_U_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_U_INTERRUPT_CLEAR_00_0
#define GPIO_U_INTERRUPT_CLEAR_00_0                     _MK_ADDR_CONST(0x13a14)
#define GPIO_U_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_U_INTERRUPT_CLEAR_00_0_DUAL                        0x0
#define GPIO_U_INTERRUPT_CLEAR_00_0_SCR                         GPIO_U_SCR_00_0
#define GPIO_U_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_U_INTERRUPT_CLEAR_00_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_CLEAR_00_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_U_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_CLEAR_00_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_U_INTERRUPT_CLEAR_00_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_U_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_U_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_U_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_U_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_U_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_U_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_U_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_U_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_U_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x13a18

// Reserved address 0x13a1c

// Reserved address 0x13a20

// Reserved address 0x13a24

// Reserved address 0x13a28

// Reserved address 0x13a2c

// Reserved address 0x13a30

// Reserved address 0x13a34

// Reserved address 0x13a38

// Reserved address 0x13a3c

// Reserved address 0x13a40

// Reserved address 0x13a44

// Reserved address 0x13a48

// Reserved address 0x13a4c

// Reserved address 0x13a50

// Reserved address 0x13a54

// Reserved address 0x13a58

// Reserved address 0x13a5c

// Reserved address 0x13a60

// Reserved address 0x13a64

// Reserved address 0x13a68

// Reserved address 0x13a6c

// Reserved address 0x13a70

// Reserved address 0x13a74

// Reserved address 0x13a78

// Reserved address 0x13a7c

// Reserved address 0x13a80

// Reserved address 0x13a84

// Reserved address 0x13a88

// Reserved address 0x13a8c

// Reserved address 0x13a90

// Reserved address 0x13a94

// Reserved address 0x13a98

// Reserved address 0x13a9c

// Reserved address 0x13aa0

// Reserved address 0x13aa4

// Reserved address 0x13aa8

// Reserved address 0x13aac

// Reserved address 0x13ab0

// Reserved address 0x13ab4

// Reserved address 0x13ab8

// Reserved address 0x13abc

// Reserved address 0x13ac0

// Reserved address 0x13ac4

// Reserved address 0x13ac8

// Reserved address 0x13acc

// Reserved address 0x13ad0

// Reserved address 0x13ad4

// Reserved address 0x13ad8

// Reserved address 0x13adc

// Reserved address 0x13ae0

// Reserved address 0x13ae4

// Reserved address 0x13ae8

// Reserved address 0x13aec

// Reserved address 0x13af0

// Reserved address 0x13af4

// Reserved address 0x13af8

// Reserved address 0x13afc

// Register GPIO_U_INTERRUPT_STATUS_G0_0
#define GPIO_U_INTERRUPT_STATUS_G0_0                    _MK_ADDR_CONST(0x13b00)
#define GPIO_U_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_U_INTERRUPT_STATUS_G0_0_DUAL                       0x0
#define GPIO_U_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_U_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_U_INTERRUPT_STATUS_G0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G0_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define GPIO_U_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G0_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_U_INTERRUPT_STATUS_G0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_U_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x1, GPIO_U_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_U_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        0:0
#define GPIO_U_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_U_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define GPIO_U_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_U_INTERRUPT_STATUS_G1_0
#define GPIO_U_INTERRUPT_STATUS_G1_0                    _MK_ADDR_CONST(0x13b04)
#define GPIO_U_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_U_INTERRUPT_STATUS_G1_0_DUAL                       0x0
#define GPIO_U_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_U_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_U_INTERRUPT_STATUS_G1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G1_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define GPIO_U_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G1_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_U_INTERRUPT_STATUS_G1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_U_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x1, GPIO_U_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_U_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        0:0
#define GPIO_U_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_U_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define GPIO_U_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_U_INTERRUPT_STATUS_G2_0
#define GPIO_U_INTERRUPT_STATUS_G2_0                    _MK_ADDR_CONST(0x13b08)
#define GPIO_U_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_U_INTERRUPT_STATUS_G2_0_DUAL                       0x0
#define GPIO_U_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_U_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_U_INTERRUPT_STATUS_G2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G2_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define GPIO_U_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G2_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_U_INTERRUPT_STATUS_G2_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_U_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x1, GPIO_U_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_U_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        0:0
#define GPIO_U_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_U_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define GPIO_U_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_U_INTERRUPT_STATUS_G3_0
#define GPIO_U_INTERRUPT_STATUS_G3_0                    _MK_ADDR_CONST(0x13b0c)
#define GPIO_U_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_U_INTERRUPT_STATUS_G3_0_DUAL                       0x0
#define GPIO_U_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_U_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_U_INTERRUPT_STATUS_G3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G3_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define GPIO_U_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G3_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_U_INTERRUPT_STATUS_G3_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_U_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x1, GPIO_U_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_U_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        0:0
#define GPIO_U_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_U_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define GPIO_U_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_U_INTERRUPT_STATUS_G4_0
#define GPIO_U_INTERRUPT_STATUS_G4_0                    _MK_ADDR_CONST(0x13b10)
#define GPIO_U_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_U_INTERRUPT_STATUS_G4_0_DUAL                       0x0
#define GPIO_U_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_U_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_U_INTERRUPT_STATUS_G4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G4_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define GPIO_U_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G4_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_U_INTERRUPT_STATUS_G4_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_U_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x1, GPIO_U_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_U_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        0:0
#define GPIO_U_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_U_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define GPIO_U_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_U_INTERRUPT_STATUS_G5_0
#define GPIO_U_INTERRUPT_STATUS_G5_0                    _MK_ADDR_CONST(0x13b14)
#define GPIO_U_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_U_INTERRUPT_STATUS_G5_0_DUAL                       0x0
#define GPIO_U_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_U_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_U_INTERRUPT_STATUS_G5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G5_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define GPIO_U_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G5_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_U_INTERRUPT_STATUS_G5_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_U_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x1, GPIO_U_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_U_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        0:0
#define GPIO_U_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_U_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define GPIO_U_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_U_INTERRUPT_STATUS_G6_0
#define GPIO_U_INTERRUPT_STATUS_G6_0                    _MK_ADDR_CONST(0x13b18)
#define GPIO_U_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_U_INTERRUPT_STATUS_G6_0_DUAL                       0x0
#define GPIO_U_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_U_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_U_INTERRUPT_STATUS_G6_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G6_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define GPIO_U_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G6_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_U_INTERRUPT_STATUS_G6_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_U_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x1, GPIO_U_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_U_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        0:0
#define GPIO_U_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_U_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define GPIO_U_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_U_INTERRUPT_STATUS_G7_0
#define GPIO_U_INTERRUPT_STATUS_G7_0                    _MK_ADDR_CONST(0x13b1c)
#define GPIO_U_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_U_INTERRUPT_STATUS_G7_0_DUAL                       0x0
#define GPIO_U_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_U_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_U_INTERRUPT_STATUS_G7_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G7_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define GPIO_U_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G7_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_U_INTERRUPT_STATUS_G7_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_U_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x1, GPIO_U_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_U_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        0:0
#define GPIO_U_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_U_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define GPIO_U_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_U_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Reserved address 0x13b20

// Reserved address 0x13b24

// Reserved address 0x13b28

// Reserved address 0x13b2c

// Reserved address 0x13b30

// Reserved address 0x13b34

// Reserved address 0x13b38

// Reserved address 0x13b3c

// Reserved address 0x13b40

// Reserved address 0x13b44

// Reserved address 0x13b48

// Reserved address 0x13b4c

// Reserved address 0x13b50

// Reserved address 0x13b54

// Reserved address 0x13b58

// Reserved address 0x13b5c

// Reserved address 0x13b60

// Reserved address 0x13b64

// Reserved address 0x13b68

// Reserved address 0x13b6c

// Reserved address 0x13b70

// Reserved address 0x13b74

// Reserved address 0x13b78

// Reserved address 0x13b7c

// Reserved address 0x13b80

// Reserved address 0x13b84

// Reserved address 0x13b88

// Reserved address 0x13b8c

// Reserved address 0x13b90

// Reserved address 0x13b94

// Reserved address 0x13b98

// Reserved address 0x13b9c

// Reserved address 0x13ba0

// Reserved address 0x13ba4

// Reserved address 0x13ba8

// Reserved address 0x13bac

// Reserved address 0x13bb0

// Reserved address 0x13bb4

// Reserved address 0x13bb8

// Reserved address 0x13bbc

// Reserved address 0x13bc0

// Reserved address 0x13bc4

// Reserved address 0x13bc8

// Reserved address 0x13bcc

// Reserved address 0x13bd0

// Reserved address 0x13bd4

// Reserved address 0x13bd8

// Reserved address 0x13bdc

// Reserved address 0x13be0

// Reserved address 0x13be4

// Reserved address 0x13be8

// Reserved address 0x13bec

// Reserved address 0x13bf0

// Reserved address 0x13bf4

// Reserved address 0x13bf8

// Reserved address 0x13bfc

// Register GPIO_G_ENABLE_CONFIG_00_0
#define GPIO_G_ENABLE_CONFIG_00_0                       _MK_ADDR_CONST(0x14000)
#define GPIO_G_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_G_ENABLE_CONFIG_00_0_DUAL                  0x0
#define GPIO_G_ENABLE_CONFIG_00_0_SCR                   GPIO_G_SCR_00_0
#define GPIO_G_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_G_ENABLE_CONFIG_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_00_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_G_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_G_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_G_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_G_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_G_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_G_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_G_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_G_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_00_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_00_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_G_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_G_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_G_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_G_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_G_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_G_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_G_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_G_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_G_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_G_DEBOUNCE_THRESHOLD_00_0
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0                  _MK_ADDR_CONST(0x14004)
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_G_SCR_00_0
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_G_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_G_INPUT_00_0
#define GPIO_G_INPUT_00_0                       _MK_ADDR_CONST(0x14008)
#define GPIO_G_INPUT_00_0_SECURE                        0x0
#define GPIO_G_INPUT_00_0_DUAL                  0x0
#define GPIO_G_INPUT_00_0_SCR                   GPIO_G_SCR_00_0
#define GPIO_G_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_G_INPUT_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_00_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_00_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_G_INPUT_00_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_00_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_G_INPUT_00_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_G_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_G_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_G_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_G_INPUT_00_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_00_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_G_OUTPUT_CONTROL_00_0
#define GPIO_G_OUTPUT_CONTROL_00_0                      _MK_ADDR_CONST(0x1400c)
#define GPIO_G_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_G_OUTPUT_CONTROL_00_0_DUAL                         0x0
#define GPIO_G_OUTPUT_CONTROL_00_0_SCR                  GPIO_G_SCR_00_0
#define GPIO_G_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_G_OUTPUT_CONTROL_00_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_00_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_00_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_00_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_G_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_G_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_G_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_G_OUTPUT_VALUE_00_0
#define GPIO_G_OUTPUT_VALUE_00_0                        _MK_ADDR_CONST(0x14010)
#define GPIO_G_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_G_OUTPUT_VALUE_00_0_DUAL                   0x0
#define GPIO_G_OUTPUT_VALUE_00_0_SCR                    GPIO_G_SCR_00_0
#define GPIO_G_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_G_OUTPUT_VALUE_00_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_00_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_00_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_00_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_G_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_G_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_G_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_G_INTERRUPT_CLEAR_00_0
#define GPIO_G_INTERRUPT_CLEAR_00_0                     _MK_ADDR_CONST(0x14014)
#define GPIO_G_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_G_INTERRUPT_CLEAR_00_0_DUAL                        0x0
#define GPIO_G_INTERRUPT_CLEAR_00_0_SCR                         GPIO_G_SCR_00_0
#define GPIO_G_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_G_INTERRUPT_CLEAR_00_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_00_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_00_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_00_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_G_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_G_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_G_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_G_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x14018

// Reserved address 0x1401c

// Register GPIO_G_ENABLE_CONFIG_01_0
#define GPIO_G_ENABLE_CONFIG_01_0                       _MK_ADDR_CONST(0x14020)
#define GPIO_G_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_G_ENABLE_CONFIG_01_0_DUAL                  0x0
#define GPIO_G_ENABLE_CONFIG_01_0_SCR                   GPIO_G_SCR_01_0
#define GPIO_G_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_G_ENABLE_CONFIG_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_01_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_G_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_G_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_G_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_G_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_G_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_G_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_G_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_G_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_01_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_01_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_G_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_G_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_G_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_G_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_G_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_G_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_G_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_G_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_G_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_G_DEBOUNCE_THRESHOLD_01_0
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0                  _MK_ADDR_CONST(0x14024)
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_G_SCR_01_0
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_G_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_G_INPUT_01_0
#define GPIO_G_INPUT_01_0                       _MK_ADDR_CONST(0x14028)
#define GPIO_G_INPUT_01_0_SECURE                        0x0
#define GPIO_G_INPUT_01_0_DUAL                  0x0
#define GPIO_G_INPUT_01_0_SCR                   GPIO_G_SCR_01_0
#define GPIO_G_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_G_INPUT_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_01_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_01_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_G_INPUT_01_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_01_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_G_INPUT_01_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_G_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_G_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_G_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_G_INPUT_01_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_01_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_G_OUTPUT_CONTROL_01_0
#define GPIO_G_OUTPUT_CONTROL_01_0                      _MK_ADDR_CONST(0x1402c)
#define GPIO_G_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_G_OUTPUT_CONTROL_01_0_DUAL                         0x0
#define GPIO_G_OUTPUT_CONTROL_01_0_SCR                  GPIO_G_SCR_01_0
#define GPIO_G_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_G_OUTPUT_CONTROL_01_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_01_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_01_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_01_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_G_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_G_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_G_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_G_OUTPUT_VALUE_01_0
#define GPIO_G_OUTPUT_VALUE_01_0                        _MK_ADDR_CONST(0x14030)
#define GPIO_G_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_G_OUTPUT_VALUE_01_0_DUAL                   0x0
#define GPIO_G_OUTPUT_VALUE_01_0_SCR                    GPIO_G_SCR_01_0
#define GPIO_G_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_G_OUTPUT_VALUE_01_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_01_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_01_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_01_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_G_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_G_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_G_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_G_INTERRUPT_CLEAR_01_0
#define GPIO_G_INTERRUPT_CLEAR_01_0                     _MK_ADDR_CONST(0x14034)
#define GPIO_G_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_G_INTERRUPT_CLEAR_01_0_DUAL                        0x0
#define GPIO_G_INTERRUPT_CLEAR_01_0_SCR                         GPIO_G_SCR_01_0
#define GPIO_G_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_G_INTERRUPT_CLEAR_01_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_01_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_01_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_01_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_G_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_G_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_G_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_G_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x14038

// Reserved address 0x1403c

// Register GPIO_G_ENABLE_CONFIG_02_0
#define GPIO_G_ENABLE_CONFIG_02_0                       _MK_ADDR_CONST(0x14040)
#define GPIO_G_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_G_ENABLE_CONFIG_02_0_DUAL                  0x0
#define GPIO_G_ENABLE_CONFIG_02_0_SCR                   GPIO_G_SCR_02_0
#define GPIO_G_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_G_ENABLE_CONFIG_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_02_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_G_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_G_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_G_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_G_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_G_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_G_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_G_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_G_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_02_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_02_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_G_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_G_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_G_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_G_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_G_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_G_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_G_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_G_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_G_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_G_DEBOUNCE_THRESHOLD_02_0
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0                  _MK_ADDR_CONST(0x14044)
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_G_SCR_02_0
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_G_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_G_INPUT_02_0
#define GPIO_G_INPUT_02_0                       _MK_ADDR_CONST(0x14048)
#define GPIO_G_INPUT_02_0_SECURE                        0x0
#define GPIO_G_INPUT_02_0_DUAL                  0x0
#define GPIO_G_INPUT_02_0_SCR                   GPIO_G_SCR_02_0
#define GPIO_G_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_G_INPUT_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_02_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_02_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_G_INPUT_02_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_02_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_G_INPUT_02_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_G_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_G_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_G_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_G_INPUT_02_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_02_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_G_OUTPUT_CONTROL_02_0
#define GPIO_G_OUTPUT_CONTROL_02_0                      _MK_ADDR_CONST(0x1404c)
#define GPIO_G_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_G_OUTPUT_CONTROL_02_0_DUAL                         0x0
#define GPIO_G_OUTPUT_CONTROL_02_0_SCR                  GPIO_G_SCR_02_0
#define GPIO_G_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_G_OUTPUT_CONTROL_02_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_02_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_02_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_02_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_G_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_G_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_G_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_G_OUTPUT_VALUE_02_0
#define GPIO_G_OUTPUT_VALUE_02_0                        _MK_ADDR_CONST(0x14050)
#define GPIO_G_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_G_OUTPUT_VALUE_02_0_DUAL                   0x0
#define GPIO_G_OUTPUT_VALUE_02_0_SCR                    GPIO_G_SCR_02_0
#define GPIO_G_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_G_OUTPUT_VALUE_02_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_02_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_02_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_02_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_G_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_G_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_G_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_G_INTERRUPT_CLEAR_02_0
#define GPIO_G_INTERRUPT_CLEAR_02_0                     _MK_ADDR_CONST(0x14054)
#define GPIO_G_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_G_INTERRUPT_CLEAR_02_0_DUAL                        0x0
#define GPIO_G_INTERRUPT_CLEAR_02_0_SCR                         GPIO_G_SCR_02_0
#define GPIO_G_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_G_INTERRUPT_CLEAR_02_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_02_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_02_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_02_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_G_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_G_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_G_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_G_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x14058

// Reserved address 0x1405c

// Register GPIO_G_ENABLE_CONFIG_03_0
#define GPIO_G_ENABLE_CONFIG_03_0                       _MK_ADDR_CONST(0x14060)
#define GPIO_G_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_G_ENABLE_CONFIG_03_0_DUAL                  0x0
#define GPIO_G_ENABLE_CONFIG_03_0_SCR                   GPIO_G_SCR_03_0
#define GPIO_G_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_G_ENABLE_CONFIG_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_03_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_G_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_G_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_G_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_G_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_G_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_G_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_G_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_G_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_03_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_03_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_G_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_G_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_G_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_G_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_G_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_G_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_G_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_G_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_G_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_G_DEBOUNCE_THRESHOLD_03_0
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0                  _MK_ADDR_CONST(0x14064)
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_G_SCR_03_0
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_G_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_G_INPUT_03_0
#define GPIO_G_INPUT_03_0                       _MK_ADDR_CONST(0x14068)
#define GPIO_G_INPUT_03_0_SECURE                        0x0
#define GPIO_G_INPUT_03_0_DUAL                  0x0
#define GPIO_G_INPUT_03_0_SCR                   GPIO_G_SCR_03_0
#define GPIO_G_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_G_INPUT_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_03_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_03_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_G_INPUT_03_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_03_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_G_INPUT_03_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_G_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_G_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_G_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_G_INPUT_03_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_03_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_G_OUTPUT_CONTROL_03_0
#define GPIO_G_OUTPUT_CONTROL_03_0                      _MK_ADDR_CONST(0x1406c)
#define GPIO_G_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_G_OUTPUT_CONTROL_03_0_DUAL                         0x0
#define GPIO_G_OUTPUT_CONTROL_03_0_SCR                  GPIO_G_SCR_03_0
#define GPIO_G_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_G_OUTPUT_CONTROL_03_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_03_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_03_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_03_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_G_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_G_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_G_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_G_OUTPUT_VALUE_03_0
#define GPIO_G_OUTPUT_VALUE_03_0                        _MK_ADDR_CONST(0x14070)
#define GPIO_G_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_G_OUTPUT_VALUE_03_0_DUAL                   0x0
#define GPIO_G_OUTPUT_VALUE_03_0_SCR                    GPIO_G_SCR_03_0
#define GPIO_G_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_G_OUTPUT_VALUE_03_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_03_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_03_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_03_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_G_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_G_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_G_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_G_INTERRUPT_CLEAR_03_0
#define GPIO_G_INTERRUPT_CLEAR_03_0                     _MK_ADDR_CONST(0x14074)
#define GPIO_G_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_G_INTERRUPT_CLEAR_03_0_DUAL                        0x0
#define GPIO_G_INTERRUPT_CLEAR_03_0_SCR                         GPIO_G_SCR_03_0
#define GPIO_G_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_G_INTERRUPT_CLEAR_03_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_03_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_03_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_03_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_G_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_G_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_G_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_G_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x14078

// Reserved address 0x1407c

// Register GPIO_G_ENABLE_CONFIG_04_0
#define GPIO_G_ENABLE_CONFIG_04_0                       _MK_ADDR_CONST(0x14080)
#define GPIO_G_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_G_ENABLE_CONFIG_04_0_DUAL                  0x0
#define GPIO_G_ENABLE_CONFIG_04_0_SCR                   GPIO_G_SCR_04_0
#define GPIO_G_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_G_ENABLE_CONFIG_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_04_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_G_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_G_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_G_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_G_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_G_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_G_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_G_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_G_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_04_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_04_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_G_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_G_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_G_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_G_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_G_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_G_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_G_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_G_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_G_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_G_DEBOUNCE_THRESHOLD_04_0
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0                  _MK_ADDR_CONST(0x14084)
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_DUAL                     0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_G_SCR_04_0
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_G_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_G_INPUT_04_0
#define GPIO_G_INPUT_04_0                       _MK_ADDR_CONST(0x14088)
#define GPIO_G_INPUT_04_0_SECURE                        0x0
#define GPIO_G_INPUT_04_0_DUAL                  0x0
#define GPIO_G_INPUT_04_0_SCR                   GPIO_G_SCR_04_0
#define GPIO_G_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_G_INPUT_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_04_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_04_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_G_INPUT_04_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_04_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_G_INPUT_04_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_G_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_G_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_G_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_G_INPUT_04_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_04_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_G_OUTPUT_CONTROL_04_0
#define GPIO_G_OUTPUT_CONTROL_04_0                      _MK_ADDR_CONST(0x1408c)
#define GPIO_G_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_G_OUTPUT_CONTROL_04_0_DUAL                         0x0
#define GPIO_G_OUTPUT_CONTROL_04_0_SCR                  GPIO_G_SCR_04_0
#define GPIO_G_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_G_OUTPUT_CONTROL_04_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_04_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_04_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_04_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_G_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_G_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_G_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_G_OUTPUT_VALUE_04_0
#define GPIO_G_OUTPUT_VALUE_04_0                        _MK_ADDR_CONST(0x14090)
#define GPIO_G_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_G_OUTPUT_VALUE_04_0_DUAL                   0x0
#define GPIO_G_OUTPUT_VALUE_04_0_SCR                    GPIO_G_SCR_04_0
#define GPIO_G_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_G_OUTPUT_VALUE_04_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_04_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_04_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_04_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_G_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_G_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_G_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_G_INTERRUPT_CLEAR_04_0
#define GPIO_G_INTERRUPT_CLEAR_04_0                     _MK_ADDR_CONST(0x14094)
#define GPIO_G_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_G_INTERRUPT_CLEAR_04_0_DUAL                        0x0
#define GPIO_G_INTERRUPT_CLEAR_04_0_SCR                         GPIO_G_SCR_04_0
#define GPIO_G_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_G_INTERRUPT_CLEAR_04_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_04_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_04_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_04_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_G_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_G_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_G_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_G_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x14098

// Reserved address 0x1409c

// Register GPIO_G_ENABLE_CONFIG_05_0
#define GPIO_G_ENABLE_CONFIG_05_0                       _MK_ADDR_CONST(0x140a0)
#define GPIO_G_ENABLE_CONFIG_05_0_SECURE                        0x0
#define GPIO_G_ENABLE_CONFIG_05_0_DUAL                  0x0
#define GPIO_G_ENABLE_CONFIG_05_0_SCR                   GPIO_G_SCR_05_0
#define GPIO_G_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
#define GPIO_G_ENABLE_CONFIG_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_05_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_G_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_G_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_G_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_G_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_G_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_G_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
#define GPIO_G_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
#define GPIO_G_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_05_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_05_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_G_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_G_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_G_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_G_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_G_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_G_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_G_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_G_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_G_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_G_DEBOUNCE_THRESHOLD_05_0
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0                  _MK_ADDR_CONST(0x140a4)
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_DUAL                     0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_G_SCR_05_0
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_G_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_G_INPUT_05_0
#define GPIO_G_INPUT_05_0                       _MK_ADDR_CONST(0x140a8)
#define GPIO_G_INPUT_05_0_SECURE                        0x0
#define GPIO_G_INPUT_05_0_DUAL                  0x0
#define GPIO_G_INPUT_05_0_SCR                   GPIO_G_SCR_05_0
#define GPIO_G_INPUT_05_0_WORD_COUNT                    0x1
#define GPIO_G_INPUT_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_05_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_05_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_G_INPUT_05_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_05_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_G_INPUT_05_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_G_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_G_INPUT_05_0_GPIO_IN_RANGE                 0:0
#define GPIO_G_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_G_INPUT_05_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_05_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_G_OUTPUT_CONTROL_05_0
#define GPIO_G_OUTPUT_CONTROL_05_0                      _MK_ADDR_CONST(0x140ac)
#define GPIO_G_OUTPUT_CONTROL_05_0_SECURE                       0x0
#define GPIO_G_OUTPUT_CONTROL_05_0_DUAL                         0x0
#define GPIO_G_OUTPUT_CONTROL_05_0_SCR                  GPIO_G_SCR_05_0
#define GPIO_G_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
#define GPIO_G_OUTPUT_CONTROL_05_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_05_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_05_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_05_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_G_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_G_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_G_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_G_OUTPUT_VALUE_05_0
#define GPIO_G_OUTPUT_VALUE_05_0                        _MK_ADDR_CONST(0x140b0)
#define GPIO_G_OUTPUT_VALUE_05_0_SECURE                         0x0
#define GPIO_G_OUTPUT_VALUE_05_0_DUAL                   0x0
#define GPIO_G_OUTPUT_VALUE_05_0_SCR                    GPIO_G_SCR_05_0
#define GPIO_G_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
#define GPIO_G_OUTPUT_VALUE_05_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_05_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_05_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_05_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_G_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_G_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_G_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_G_INTERRUPT_CLEAR_05_0
#define GPIO_G_INTERRUPT_CLEAR_05_0                     _MK_ADDR_CONST(0x140b4)
#define GPIO_G_INTERRUPT_CLEAR_05_0_SECURE                      0x0
#define GPIO_G_INTERRUPT_CLEAR_05_0_DUAL                        0x0
#define GPIO_G_INTERRUPT_CLEAR_05_0_SCR                         GPIO_G_SCR_05_0
#define GPIO_G_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
#define GPIO_G_INTERRUPT_CLEAR_05_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_05_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_05_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_05_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_G_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_G_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_G_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_G_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x140b8

// Reserved address 0x140bc

// Register GPIO_G_ENABLE_CONFIG_06_0
#define GPIO_G_ENABLE_CONFIG_06_0                       _MK_ADDR_CONST(0x140c0)
#define GPIO_G_ENABLE_CONFIG_06_0_SECURE                        0x0
#define GPIO_G_ENABLE_CONFIG_06_0_DUAL                  0x0
#define GPIO_G_ENABLE_CONFIG_06_0_SCR                   GPIO_G_SCR_06_0
#define GPIO_G_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
#define GPIO_G_ENABLE_CONFIG_06_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_06_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_G_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
#define GPIO_G_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_G_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_G_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_G_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
#define GPIO_G_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
#define GPIO_G_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
#define GPIO_G_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_06_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_06_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_G_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_G_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_G_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_G_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_G_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_G_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_G_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_G_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_G_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_G_DEBOUNCE_THRESHOLD_06_0
#define GPIO_G_DEBOUNCE_THRESHOLD_06_0                  _MK_ADDR_CONST(0x140c4)
#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_DUAL                     0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_G_SCR_06_0
#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_G_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_G_INPUT_06_0
#define GPIO_G_INPUT_06_0                       _MK_ADDR_CONST(0x140c8)
#define GPIO_G_INPUT_06_0_SECURE                        0x0
#define GPIO_G_INPUT_06_0_DUAL                  0x0
#define GPIO_G_INPUT_06_0_SCR                   GPIO_G_SCR_06_0
#define GPIO_G_INPUT_06_0_WORD_COUNT                    0x1
#define GPIO_G_INPUT_06_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_06_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_06_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_06_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_06_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_G_INPUT_06_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_06_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_G_INPUT_06_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_G_INPUT_06_0_GPIO_IN_SHIFT)
#define GPIO_G_INPUT_06_0_GPIO_IN_RANGE                 0:0
#define GPIO_G_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_G_INPUT_06_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_06_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_06_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_06_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_G_OUTPUT_CONTROL_06_0
#define GPIO_G_OUTPUT_CONTROL_06_0                      _MK_ADDR_CONST(0x140cc)
#define GPIO_G_OUTPUT_CONTROL_06_0_SECURE                       0x0
#define GPIO_G_OUTPUT_CONTROL_06_0_DUAL                         0x0
#define GPIO_G_OUTPUT_CONTROL_06_0_SCR                  GPIO_G_SCR_06_0
#define GPIO_G_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
#define GPIO_G_OUTPUT_CONTROL_06_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_06_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_06_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_06_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_G_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_G_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_G_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_G_OUTPUT_VALUE_06_0
#define GPIO_G_OUTPUT_VALUE_06_0                        _MK_ADDR_CONST(0x140d0)
#define GPIO_G_OUTPUT_VALUE_06_0_SECURE                         0x0
#define GPIO_G_OUTPUT_VALUE_06_0_DUAL                   0x0
#define GPIO_G_OUTPUT_VALUE_06_0_SCR                    GPIO_G_SCR_06_0
#define GPIO_G_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
#define GPIO_G_OUTPUT_VALUE_06_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_06_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_06_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_06_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_G_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_G_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_G_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_G_INTERRUPT_CLEAR_06_0
#define GPIO_G_INTERRUPT_CLEAR_06_0                     _MK_ADDR_CONST(0x140d4)
#define GPIO_G_INTERRUPT_CLEAR_06_0_SECURE                      0x0
#define GPIO_G_INTERRUPT_CLEAR_06_0_DUAL                        0x0
#define GPIO_G_INTERRUPT_CLEAR_06_0_SCR                         GPIO_G_SCR_06_0
#define GPIO_G_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
#define GPIO_G_INTERRUPT_CLEAR_06_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_06_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_06_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_06_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_G_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_G_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_G_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_G_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x140d8

// Reserved address 0x140dc

// Register GPIO_G_ENABLE_CONFIG_07_0
#define GPIO_G_ENABLE_CONFIG_07_0                       _MK_ADDR_CONST(0x140e0)
#define GPIO_G_ENABLE_CONFIG_07_0_SECURE                        0x0
#define GPIO_G_ENABLE_CONFIG_07_0_DUAL                  0x0
#define GPIO_G_ENABLE_CONFIG_07_0_SCR                   GPIO_G_SCR_07_0
#define GPIO_G_ENABLE_CONFIG_07_0_WORD_COUNT                    0x1
#define GPIO_G_ENABLE_CONFIG_07_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_07_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_G_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
#define GPIO_G_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_G_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_G_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_G_ENABLE_CONFIG_07_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
#define GPIO_G_ENABLE_CONFIG_07_0_IN_OUT_RANGE                  1:1
#define GPIO_G_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                        0x0
#define GPIO_G_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_07_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_07_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_G_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_G_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_G_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_G_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_G_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_G_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_G_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_G_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_G_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_G_DEBOUNCE_THRESHOLD_07_0
#define GPIO_G_DEBOUNCE_THRESHOLD_07_0                  _MK_ADDR_CONST(0x140e4)
#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_SECURE                   0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_DUAL                     0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_SCR                      GPIO_G_SCR_07_0
#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                       0x1
#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_G_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_G_INPUT_07_0
#define GPIO_G_INPUT_07_0                       _MK_ADDR_CONST(0x140e8)
#define GPIO_G_INPUT_07_0_SECURE                        0x0
#define GPIO_G_INPUT_07_0_DUAL                  0x0
#define GPIO_G_INPUT_07_0_SCR                   GPIO_G_SCR_07_0
#define GPIO_G_INPUT_07_0_WORD_COUNT                    0x1
#define GPIO_G_INPUT_07_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_07_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_07_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_07_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_07_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_G_INPUT_07_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_07_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_G_INPUT_07_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_G_INPUT_07_0_GPIO_IN_SHIFT)
#define GPIO_G_INPUT_07_0_GPIO_IN_RANGE                 0:0
#define GPIO_G_INPUT_07_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_G_INPUT_07_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_07_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_07_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_07_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_07_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_G_OUTPUT_CONTROL_07_0
#define GPIO_G_OUTPUT_CONTROL_07_0                      _MK_ADDR_CONST(0x140ec)
#define GPIO_G_OUTPUT_CONTROL_07_0_SECURE                       0x0
#define GPIO_G_OUTPUT_CONTROL_07_0_DUAL                         0x0
#define GPIO_G_OUTPUT_CONTROL_07_0_SCR                  GPIO_G_SCR_07_0
#define GPIO_G_OUTPUT_CONTROL_07_0_WORD_COUNT                   0x1
#define GPIO_G_OUTPUT_CONTROL_07_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_07_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_07_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_07_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_G_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_G_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_G_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_G_OUTPUT_VALUE_07_0
#define GPIO_G_OUTPUT_VALUE_07_0                        _MK_ADDR_CONST(0x140f0)
#define GPIO_G_OUTPUT_VALUE_07_0_SECURE                         0x0
#define GPIO_G_OUTPUT_VALUE_07_0_DUAL                   0x0
#define GPIO_G_OUTPUT_VALUE_07_0_SCR                    GPIO_G_SCR_07_0
#define GPIO_G_OUTPUT_VALUE_07_0_WORD_COUNT                     0x1
#define GPIO_G_OUTPUT_VALUE_07_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_07_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_07_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_07_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_G_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_G_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_G_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_G_INTERRUPT_CLEAR_07_0
#define GPIO_G_INTERRUPT_CLEAR_07_0                     _MK_ADDR_CONST(0x140f4)
#define GPIO_G_INTERRUPT_CLEAR_07_0_SECURE                      0x0
#define GPIO_G_INTERRUPT_CLEAR_07_0_DUAL                        0x0
#define GPIO_G_INTERRUPT_CLEAR_07_0_SCR                         GPIO_G_SCR_07_0
#define GPIO_G_INTERRUPT_CLEAR_07_0_WORD_COUNT                  0x1
#define GPIO_G_INTERRUPT_CLEAR_07_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_07_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_07_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_07_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_G_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_G_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_G_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_G_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x140f8

// Reserved address 0x140fc

// Register GPIO_G_INTERRUPT_STATUS_G0_0
#define GPIO_G_INTERRUPT_STATUS_G0_0                    _MK_ADDR_CONST(0x14100)
#define GPIO_G_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_G_INTERRUPT_STATUS_G0_0_DUAL                       0x0
#define GPIO_G_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_G_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_G_INTERRUPT_STATUS_G0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G0_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_G_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G0_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_G_INTERRUPT_STATUS_G0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_G_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_G_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_G_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_G_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_G_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_G_INTERRUPT_STATUS_G1_0
#define GPIO_G_INTERRUPT_STATUS_G1_0                    _MK_ADDR_CONST(0x14104)
#define GPIO_G_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_G_INTERRUPT_STATUS_G1_0_DUAL                       0x0
#define GPIO_G_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_G_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_G_INTERRUPT_STATUS_G1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G1_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_G_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G1_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_G_INTERRUPT_STATUS_G1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_G_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_G_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_G_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_G_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_G_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_G_INTERRUPT_STATUS_G2_0
#define GPIO_G_INTERRUPT_STATUS_G2_0                    _MK_ADDR_CONST(0x14108)
#define GPIO_G_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_G_INTERRUPT_STATUS_G2_0_DUAL                       0x0
#define GPIO_G_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_G_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_G_INTERRUPT_STATUS_G2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G2_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_G_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G2_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_G_INTERRUPT_STATUS_G2_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_G_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_G_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_G_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_G_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_G_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_G_INTERRUPT_STATUS_G3_0
#define GPIO_G_INTERRUPT_STATUS_G3_0                    _MK_ADDR_CONST(0x1410c)
#define GPIO_G_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_G_INTERRUPT_STATUS_G3_0_DUAL                       0x0
#define GPIO_G_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_G_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_G_INTERRUPT_STATUS_G3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G3_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_G_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G3_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_G_INTERRUPT_STATUS_G3_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_G_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_G_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_G_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_G_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_G_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_G_INTERRUPT_STATUS_G4_0
#define GPIO_G_INTERRUPT_STATUS_G4_0                    _MK_ADDR_CONST(0x14110)
#define GPIO_G_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_G_INTERRUPT_STATUS_G4_0_DUAL                       0x0
#define GPIO_G_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_G_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_G_INTERRUPT_STATUS_G4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G4_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_G_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G4_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_G_INTERRUPT_STATUS_G4_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_G_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_G_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_G_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_G_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_G_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_G_INTERRUPT_STATUS_G5_0
#define GPIO_G_INTERRUPT_STATUS_G5_0                    _MK_ADDR_CONST(0x14114)
#define GPIO_G_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_G_INTERRUPT_STATUS_G5_0_DUAL                       0x0
#define GPIO_G_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_G_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_G_INTERRUPT_STATUS_G5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G5_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_G_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G5_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_G_INTERRUPT_STATUS_G5_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_G_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_G_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_G_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_G_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_G_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_G_INTERRUPT_STATUS_G6_0
#define GPIO_G_INTERRUPT_STATUS_G6_0                    _MK_ADDR_CONST(0x14118)
#define GPIO_G_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_G_INTERRUPT_STATUS_G6_0_DUAL                       0x0
#define GPIO_G_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_G_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_G_INTERRUPT_STATUS_G6_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G6_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_G_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G6_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_G_INTERRUPT_STATUS_G6_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_G_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_G_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_G_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_G_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_G_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_G_INTERRUPT_STATUS_G7_0
#define GPIO_G_INTERRUPT_STATUS_G7_0                    _MK_ADDR_CONST(0x1411c)
#define GPIO_G_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_G_INTERRUPT_STATUS_G7_0_DUAL                       0x0
#define GPIO_G_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_G_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_G_INTERRUPT_STATUS_G7_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G7_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_G_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G7_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_G_INTERRUPT_STATUS_G7_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_G_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_G_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_G_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_G_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_G_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Reserved address 0x14120

// Reserved address 0x14124

// Reserved address 0x14128

// Reserved address 0x1412c

// Reserved address 0x14130

// Reserved address 0x14134

// Reserved address 0x14138

// Reserved address 0x1413c

// Reserved address 0x14140

// Reserved address 0x14144

// Reserved address 0x14148

// Reserved address 0x1414c

// Reserved address 0x14150

// Reserved address 0x14154

// Reserved address 0x14158

// Reserved address 0x1415c

// Reserved address 0x14160

// Reserved address 0x14164

// Reserved address 0x14168

// Reserved address 0x1416c

// Reserved address 0x14170

// Reserved address 0x14174

// Reserved address 0x14178

// Reserved address 0x1417c

// Reserved address 0x14180

// Reserved address 0x14184

// Reserved address 0x14188

// Reserved address 0x1418c

// Reserved address 0x14190

// Reserved address 0x14194

// Reserved address 0x14198

// Reserved address 0x1419c

// Reserved address 0x141a0

// Reserved address 0x141a4

// Reserved address 0x141a8

// Reserved address 0x141ac

// Reserved address 0x141b0

// Reserved address 0x141b4

// Reserved address 0x141b8

// Reserved address 0x141bc

// Reserved address 0x141c0

// Reserved address 0x141c4

// Reserved address 0x141c8

// Reserved address 0x141cc

// Reserved address 0x141d0

// Reserved address 0x141d4

// Reserved address 0x141d8

// Reserved address 0x141dc

// Reserved address 0x141e0

// Reserved address 0x141e4

// Reserved address 0x141e8

// Reserved address 0x141ec

// Reserved address 0x141f0

// Reserved address 0x141f4

// Reserved address 0x141f8

// Reserved address 0x141fc

// Register GPIO_H_ENABLE_CONFIG_00_0
#define GPIO_H_ENABLE_CONFIG_00_0                       _MK_ADDR_CONST(0x14200)
#define GPIO_H_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_H_ENABLE_CONFIG_00_0_DUAL                  0x0
#define GPIO_H_ENABLE_CONFIG_00_0_SCR                   GPIO_H_SCR_00_0
#define GPIO_H_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_H_ENABLE_CONFIG_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_00_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_H_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_H_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_H_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_H_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_H_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_H_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_H_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_H_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_00_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_00_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_H_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_H_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_H_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_H_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_H_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_H_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_H_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_H_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_H_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_H_DEBOUNCE_THRESHOLD_00_0
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0                  _MK_ADDR_CONST(0x14204)
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_H_SCR_00_0
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_H_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_H_INPUT_00_0
#define GPIO_H_INPUT_00_0                       _MK_ADDR_CONST(0x14208)
#define GPIO_H_INPUT_00_0_SECURE                        0x0
#define GPIO_H_INPUT_00_0_DUAL                  0x0
#define GPIO_H_INPUT_00_0_SCR                   GPIO_H_SCR_00_0
#define GPIO_H_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_H_INPUT_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_00_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_00_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_H_INPUT_00_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_00_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_H_INPUT_00_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_H_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_H_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_H_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_H_INPUT_00_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_00_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_H_OUTPUT_CONTROL_00_0
#define GPIO_H_OUTPUT_CONTROL_00_0                      _MK_ADDR_CONST(0x1420c)
#define GPIO_H_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_H_OUTPUT_CONTROL_00_0_DUAL                         0x0
#define GPIO_H_OUTPUT_CONTROL_00_0_SCR                  GPIO_H_SCR_00_0
#define GPIO_H_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_H_OUTPUT_CONTROL_00_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_00_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_00_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_00_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_H_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_H_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_H_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_H_OUTPUT_VALUE_00_0
#define GPIO_H_OUTPUT_VALUE_00_0                        _MK_ADDR_CONST(0x14210)
#define GPIO_H_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_H_OUTPUT_VALUE_00_0_DUAL                   0x0
#define GPIO_H_OUTPUT_VALUE_00_0_SCR                    GPIO_H_SCR_00_0
#define GPIO_H_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_H_OUTPUT_VALUE_00_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_00_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_00_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_00_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_H_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_H_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_H_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_H_INTERRUPT_CLEAR_00_0
#define GPIO_H_INTERRUPT_CLEAR_00_0                     _MK_ADDR_CONST(0x14214)
#define GPIO_H_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_H_INTERRUPT_CLEAR_00_0_DUAL                        0x0
#define GPIO_H_INTERRUPT_CLEAR_00_0_SCR                         GPIO_H_SCR_00_0
#define GPIO_H_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_H_INTERRUPT_CLEAR_00_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_00_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_00_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_00_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_H_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_H_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_H_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_H_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x14218

// Reserved address 0x1421c

// Register GPIO_H_ENABLE_CONFIG_01_0
#define GPIO_H_ENABLE_CONFIG_01_0                       _MK_ADDR_CONST(0x14220)
#define GPIO_H_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_H_ENABLE_CONFIG_01_0_DUAL                  0x0
#define GPIO_H_ENABLE_CONFIG_01_0_SCR                   GPIO_H_SCR_01_0
#define GPIO_H_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_H_ENABLE_CONFIG_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_01_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_H_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_H_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_H_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_H_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_H_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_H_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_H_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_H_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_01_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_01_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_H_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_H_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_H_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_H_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_H_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_H_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_H_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_H_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_H_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_H_DEBOUNCE_THRESHOLD_01_0
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0                  _MK_ADDR_CONST(0x14224)
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_H_SCR_01_0
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_H_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_H_INPUT_01_0
#define GPIO_H_INPUT_01_0                       _MK_ADDR_CONST(0x14228)
#define GPIO_H_INPUT_01_0_SECURE                        0x0
#define GPIO_H_INPUT_01_0_DUAL                  0x0
#define GPIO_H_INPUT_01_0_SCR                   GPIO_H_SCR_01_0
#define GPIO_H_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_H_INPUT_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_01_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_01_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_H_INPUT_01_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_01_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_H_INPUT_01_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_H_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_H_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_H_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_H_INPUT_01_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_01_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_H_OUTPUT_CONTROL_01_0
#define GPIO_H_OUTPUT_CONTROL_01_0                      _MK_ADDR_CONST(0x1422c)
#define GPIO_H_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_H_OUTPUT_CONTROL_01_0_DUAL                         0x0
#define GPIO_H_OUTPUT_CONTROL_01_0_SCR                  GPIO_H_SCR_01_0
#define GPIO_H_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_H_OUTPUT_CONTROL_01_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_01_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_01_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_01_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_H_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_H_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_H_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_H_OUTPUT_VALUE_01_0
#define GPIO_H_OUTPUT_VALUE_01_0                        _MK_ADDR_CONST(0x14230)
#define GPIO_H_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_H_OUTPUT_VALUE_01_0_DUAL                   0x0
#define GPIO_H_OUTPUT_VALUE_01_0_SCR                    GPIO_H_SCR_01_0
#define GPIO_H_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_H_OUTPUT_VALUE_01_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_01_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_01_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_01_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_H_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_H_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_H_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_H_INTERRUPT_CLEAR_01_0
#define GPIO_H_INTERRUPT_CLEAR_01_0                     _MK_ADDR_CONST(0x14234)
#define GPIO_H_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_H_INTERRUPT_CLEAR_01_0_DUAL                        0x0
#define GPIO_H_INTERRUPT_CLEAR_01_0_SCR                         GPIO_H_SCR_01_0
#define GPIO_H_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_H_INTERRUPT_CLEAR_01_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_01_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_01_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_01_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_H_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_H_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_H_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_H_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x14238

// Reserved address 0x1423c

// Register GPIO_H_ENABLE_CONFIG_02_0
#define GPIO_H_ENABLE_CONFIG_02_0                       _MK_ADDR_CONST(0x14240)
#define GPIO_H_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_H_ENABLE_CONFIG_02_0_DUAL                  0x0
#define GPIO_H_ENABLE_CONFIG_02_0_SCR                   GPIO_H_SCR_02_0
#define GPIO_H_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_H_ENABLE_CONFIG_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_02_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_H_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_H_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_H_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_H_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_H_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_H_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_H_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_H_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_02_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_02_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_H_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_H_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_H_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_H_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_H_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_H_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_H_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_H_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_H_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_H_DEBOUNCE_THRESHOLD_02_0
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0                  _MK_ADDR_CONST(0x14244)
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_H_SCR_02_0
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_H_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_H_INPUT_02_0
#define GPIO_H_INPUT_02_0                       _MK_ADDR_CONST(0x14248)
#define GPIO_H_INPUT_02_0_SECURE                        0x0
#define GPIO_H_INPUT_02_0_DUAL                  0x0
#define GPIO_H_INPUT_02_0_SCR                   GPIO_H_SCR_02_0
#define GPIO_H_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_H_INPUT_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_02_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_02_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_H_INPUT_02_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_02_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_H_INPUT_02_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_H_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_H_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_H_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_H_INPUT_02_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_02_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_H_OUTPUT_CONTROL_02_0
#define GPIO_H_OUTPUT_CONTROL_02_0                      _MK_ADDR_CONST(0x1424c)
#define GPIO_H_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_H_OUTPUT_CONTROL_02_0_DUAL                         0x0
#define GPIO_H_OUTPUT_CONTROL_02_0_SCR                  GPIO_H_SCR_02_0
#define GPIO_H_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_H_OUTPUT_CONTROL_02_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_02_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_02_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_02_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_H_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_H_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_H_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_H_OUTPUT_VALUE_02_0
#define GPIO_H_OUTPUT_VALUE_02_0                        _MK_ADDR_CONST(0x14250)
#define GPIO_H_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_H_OUTPUT_VALUE_02_0_DUAL                   0x0
#define GPIO_H_OUTPUT_VALUE_02_0_SCR                    GPIO_H_SCR_02_0
#define GPIO_H_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_H_OUTPUT_VALUE_02_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_02_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_02_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_02_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_H_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_H_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_H_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_H_INTERRUPT_CLEAR_02_0
#define GPIO_H_INTERRUPT_CLEAR_02_0                     _MK_ADDR_CONST(0x14254)
#define GPIO_H_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_H_INTERRUPT_CLEAR_02_0_DUAL                        0x0
#define GPIO_H_INTERRUPT_CLEAR_02_0_SCR                         GPIO_H_SCR_02_0
#define GPIO_H_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_H_INTERRUPT_CLEAR_02_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_02_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_02_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_02_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_H_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_H_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_H_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_H_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x14258

// Reserved address 0x1425c

// Register GPIO_H_ENABLE_CONFIG_03_0
#define GPIO_H_ENABLE_CONFIG_03_0                       _MK_ADDR_CONST(0x14260)
#define GPIO_H_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_H_ENABLE_CONFIG_03_0_DUAL                  0x0
#define GPIO_H_ENABLE_CONFIG_03_0_SCR                   GPIO_H_SCR_03_0
#define GPIO_H_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_H_ENABLE_CONFIG_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_03_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_H_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_H_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_H_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_H_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_H_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_H_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_H_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_H_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_03_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_03_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_H_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_H_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_H_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_H_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_H_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_H_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_H_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_H_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_H_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_H_DEBOUNCE_THRESHOLD_03_0
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0                  _MK_ADDR_CONST(0x14264)
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_H_SCR_03_0
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_H_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_H_INPUT_03_0
#define GPIO_H_INPUT_03_0                       _MK_ADDR_CONST(0x14268)
#define GPIO_H_INPUT_03_0_SECURE                        0x0
#define GPIO_H_INPUT_03_0_DUAL                  0x0
#define GPIO_H_INPUT_03_0_SCR                   GPIO_H_SCR_03_0
#define GPIO_H_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_H_INPUT_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_03_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_03_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_H_INPUT_03_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_03_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_H_INPUT_03_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_H_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_H_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_H_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_H_INPUT_03_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_03_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_H_OUTPUT_CONTROL_03_0
#define GPIO_H_OUTPUT_CONTROL_03_0                      _MK_ADDR_CONST(0x1426c)
#define GPIO_H_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_H_OUTPUT_CONTROL_03_0_DUAL                         0x0
#define GPIO_H_OUTPUT_CONTROL_03_0_SCR                  GPIO_H_SCR_03_0
#define GPIO_H_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_H_OUTPUT_CONTROL_03_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_03_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_03_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_03_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_H_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_H_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_H_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_H_OUTPUT_VALUE_03_0
#define GPIO_H_OUTPUT_VALUE_03_0                        _MK_ADDR_CONST(0x14270)
#define GPIO_H_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_H_OUTPUT_VALUE_03_0_DUAL                   0x0
#define GPIO_H_OUTPUT_VALUE_03_0_SCR                    GPIO_H_SCR_03_0
#define GPIO_H_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_H_OUTPUT_VALUE_03_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_03_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_03_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_03_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_H_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_H_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_H_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_H_INTERRUPT_CLEAR_03_0
#define GPIO_H_INTERRUPT_CLEAR_03_0                     _MK_ADDR_CONST(0x14274)
#define GPIO_H_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_H_INTERRUPT_CLEAR_03_0_DUAL                        0x0
#define GPIO_H_INTERRUPT_CLEAR_03_0_SCR                         GPIO_H_SCR_03_0
#define GPIO_H_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_H_INTERRUPT_CLEAR_03_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_03_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_03_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_03_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_H_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_H_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_H_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_H_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x14278

// Reserved address 0x1427c

// Register GPIO_H_ENABLE_CONFIG_04_0
#define GPIO_H_ENABLE_CONFIG_04_0                       _MK_ADDR_CONST(0x14280)
#define GPIO_H_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_H_ENABLE_CONFIG_04_0_DUAL                  0x0
#define GPIO_H_ENABLE_CONFIG_04_0_SCR                   GPIO_H_SCR_04_0
#define GPIO_H_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_H_ENABLE_CONFIG_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_04_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_H_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_H_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_H_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_H_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_H_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_H_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_H_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_H_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_04_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_04_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_H_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_H_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_H_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_H_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_H_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_H_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_H_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_H_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_H_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_H_DEBOUNCE_THRESHOLD_04_0
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0                  _MK_ADDR_CONST(0x14284)
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_DUAL                     0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_H_SCR_04_0
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_H_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_H_INPUT_04_0
#define GPIO_H_INPUT_04_0                       _MK_ADDR_CONST(0x14288)
#define GPIO_H_INPUT_04_0_SECURE                        0x0
#define GPIO_H_INPUT_04_0_DUAL                  0x0
#define GPIO_H_INPUT_04_0_SCR                   GPIO_H_SCR_04_0
#define GPIO_H_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_H_INPUT_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_04_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_04_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_H_INPUT_04_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_04_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_H_INPUT_04_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_H_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_H_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_H_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_H_INPUT_04_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_04_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_H_OUTPUT_CONTROL_04_0
#define GPIO_H_OUTPUT_CONTROL_04_0                      _MK_ADDR_CONST(0x1428c)
#define GPIO_H_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_H_OUTPUT_CONTROL_04_0_DUAL                         0x0
#define GPIO_H_OUTPUT_CONTROL_04_0_SCR                  GPIO_H_SCR_04_0
#define GPIO_H_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_H_OUTPUT_CONTROL_04_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_04_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_04_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_04_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_H_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_H_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_H_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_H_OUTPUT_VALUE_04_0
#define GPIO_H_OUTPUT_VALUE_04_0                        _MK_ADDR_CONST(0x14290)
#define GPIO_H_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_H_OUTPUT_VALUE_04_0_DUAL                   0x0
#define GPIO_H_OUTPUT_VALUE_04_0_SCR                    GPIO_H_SCR_04_0
#define GPIO_H_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_H_OUTPUT_VALUE_04_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_04_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_04_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_04_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_H_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_H_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_H_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_H_INTERRUPT_CLEAR_04_0
#define GPIO_H_INTERRUPT_CLEAR_04_0                     _MK_ADDR_CONST(0x14294)
#define GPIO_H_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_H_INTERRUPT_CLEAR_04_0_DUAL                        0x0
#define GPIO_H_INTERRUPT_CLEAR_04_0_SCR                         GPIO_H_SCR_04_0
#define GPIO_H_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_H_INTERRUPT_CLEAR_04_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_04_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_04_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_04_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_H_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_H_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_H_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_H_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x14298

// Reserved address 0x1429c

// Register GPIO_H_ENABLE_CONFIG_05_0
#define GPIO_H_ENABLE_CONFIG_05_0                       _MK_ADDR_CONST(0x142a0)
#define GPIO_H_ENABLE_CONFIG_05_0_SECURE                        0x0
#define GPIO_H_ENABLE_CONFIG_05_0_DUAL                  0x0
#define GPIO_H_ENABLE_CONFIG_05_0_SCR                   GPIO_H_SCR_05_0
#define GPIO_H_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
#define GPIO_H_ENABLE_CONFIG_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_05_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_H_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_H_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_H_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_H_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_H_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_H_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
#define GPIO_H_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
#define GPIO_H_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_05_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_05_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_H_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_H_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_H_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_H_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_H_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_H_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_H_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_H_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_H_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_H_DEBOUNCE_THRESHOLD_05_0
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0                  _MK_ADDR_CONST(0x142a4)
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_DUAL                     0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_H_SCR_05_0
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_H_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_H_INPUT_05_0
#define GPIO_H_INPUT_05_0                       _MK_ADDR_CONST(0x142a8)
#define GPIO_H_INPUT_05_0_SECURE                        0x0
#define GPIO_H_INPUT_05_0_DUAL                  0x0
#define GPIO_H_INPUT_05_0_SCR                   GPIO_H_SCR_05_0
#define GPIO_H_INPUT_05_0_WORD_COUNT                    0x1
#define GPIO_H_INPUT_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_05_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_05_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_H_INPUT_05_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_05_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_H_INPUT_05_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_H_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_H_INPUT_05_0_GPIO_IN_RANGE                 0:0
#define GPIO_H_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_H_INPUT_05_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_05_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_H_OUTPUT_CONTROL_05_0
#define GPIO_H_OUTPUT_CONTROL_05_0                      _MK_ADDR_CONST(0x142ac)
#define GPIO_H_OUTPUT_CONTROL_05_0_SECURE                       0x0
#define GPIO_H_OUTPUT_CONTROL_05_0_DUAL                         0x0
#define GPIO_H_OUTPUT_CONTROL_05_0_SCR                  GPIO_H_SCR_05_0
#define GPIO_H_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
#define GPIO_H_OUTPUT_CONTROL_05_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_05_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_05_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_05_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_H_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_H_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_H_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_H_OUTPUT_VALUE_05_0
#define GPIO_H_OUTPUT_VALUE_05_0                        _MK_ADDR_CONST(0x142b0)
#define GPIO_H_OUTPUT_VALUE_05_0_SECURE                         0x0
#define GPIO_H_OUTPUT_VALUE_05_0_DUAL                   0x0
#define GPIO_H_OUTPUT_VALUE_05_0_SCR                    GPIO_H_SCR_05_0
#define GPIO_H_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
#define GPIO_H_OUTPUT_VALUE_05_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_05_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_05_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_05_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_H_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_H_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_H_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_H_INTERRUPT_CLEAR_05_0
#define GPIO_H_INTERRUPT_CLEAR_05_0                     _MK_ADDR_CONST(0x142b4)
#define GPIO_H_INTERRUPT_CLEAR_05_0_SECURE                      0x0
#define GPIO_H_INTERRUPT_CLEAR_05_0_DUAL                        0x0
#define GPIO_H_INTERRUPT_CLEAR_05_0_SCR                         GPIO_H_SCR_05_0
#define GPIO_H_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
#define GPIO_H_INTERRUPT_CLEAR_05_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_05_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_05_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_05_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_H_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_H_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_H_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_H_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x142b8

// Reserved address 0x142bc

// Register GPIO_H_ENABLE_CONFIG_06_0
#define GPIO_H_ENABLE_CONFIG_06_0                       _MK_ADDR_CONST(0x142c0)
#define GPIO_H_ENABLE_CONFIG_06_0_SECURE                        0x0
#define GPIO_H_ENABLE_CONFIG_06_0_DUAL                  0x0
#define GPIO_H_ENABLE_CONFIG_06_0_SCR                   GPIO_H_SCR_06_0
#define GPIO_H_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
#define GPIO_H_ENABLE_CONFIG_06_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_06_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_H_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
#define GPIO_H_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_H_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_H_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_H_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
#define GPIO_H_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
#define GPIO_H_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
#define GPIO_H_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_06_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_06_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_H_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_H_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_H_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_H_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_H_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_H_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_H_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_H_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_H_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_H_DEBOUNCE_THRESHOLD_06_0
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0                  _MK_ADDR_CONST(0x142c4)
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_DUAL                     0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_H_SCR_06_0
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_H_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_H_INPUT_06_0
#define GPIO_H_INPUT_06_0                       _MK_ADDR_CONST(0x142c8)
#define GPIO_H_INPUT_06_0_SECURE                        0x0
#define GPIO_H_INPUT_06_0_DUAL                  0x0
#define GPIO_H_INPUT_06_0_SCR                   GPIO_H_SCR_06_0
#define GPIO_H_INPUT_06_0_WORD_COUNT                    0x1
#define GPIO_H_INPUT_06_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_06_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_06_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_06_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_06_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_H_INPUT_06_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_06_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_H_INPUT_06_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_H_INPUT_06_0_GPIO_IN_SHIFT)
#define GPIO_H_INPUT_06_0_GPIO_IN_RANGE                 0:0
#define GPIO_H_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_H_INPUT_06_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_06_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_06_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_06_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_H_OUTPUT_CONTROL_06_0
#define GPIO_H_OUTPUT_CONTROL_06_0                      _MK_ADDR_CONST(0x142cc)
#define GPIO_H_OUTPUT_CONTROL_06_0_SECURE                       0x0
#define GPIO_H_OUTPUT_CONTROL_06_0_DUAL                         0x0
#define GPIO_H_OUTPUT_CONTROL_06_0_SCR                  GPIO_H_SCR_06_0
#define GPIO_H_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
#define GPIO_H_OUTPUT_CONTROL_06_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_06_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_06_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_06_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_H_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_H_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_H_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_H_OUTPUT_VALUE_06_0
#define GPIO_H_OUTPUT_VALUE_06_0                        _MK_ADDR_CONST(0x142d0)
#define GPIO_H_OUTPUT_VALUE_06_0_SECURE                         0x0
#define GPIO_H_OUTPUT_VALUE_06_0_DUAL                   0x0
#define GPIO_H_OUTPUT_VALUE_06_0_SCR                    GPIO_H_SCR_06_0
#define GPIO_H_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
#define GPIO_H_OUTPUT_VALUE_06_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_06_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_06_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_06_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_H_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_H_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_H_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_H_INTERRUPT_CLEAR_06_0
#define GPIO_H_INTERRUPT_CLEAR_06_0                     _MK_ADDR_CONST(0x142d4)
#define GPIO_H_INTERRUPT_CLEAR_06_0_SECURE                      0x0
#define GPIO_H_INTERRUPT_CLEAR_06_0_DUAL                        0x0
#define GPIO_H_INTERRUPT_CLEAR_06_0_SCR                         GPIO_H_SCR_06_0
#define GPIO_H_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
#define GPIO_H_INTERRUPT_CLEAR_06_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_06_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_06_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_06_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_H_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_H_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_H_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_H_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x142d8

// Reserved address 0x142dc

// Register GPIO_H_ENABLE_CONFIG_07_0
#define GPIO_H_ENABLE_CONFIG_07_0                       _MK_ADDR_CONST(0x142e0)
#define GPIO_H_ENABLE_CONFIG_07_0_SECURE                        0x0
#define GPIO_H_ENABLE_CONFIG_07_0_DUAL                  0x0
#define GPIO_H_ENABLE_CONFIG_07_0_SCR                   GPIO_H_SCR_07_0
#define GPIO_H_ENABLE_CONFIG_07_0_WORD_COUNT                    0x1
#define GPIO_H_ENABLE_CONFIG_07_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_07_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_H_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
#define GPIO_H_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_H_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_H_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_H_ENABLE_CONFIG_07_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
#define GPIO_H_ENABLE_CONFIG_07_0_IN_OUT_RANGE                  1:1
#define GPIO_H_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                        0x0
#define GPIO_H_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_07_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_07_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_H_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_H_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_H_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_H_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_H_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_H_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_H_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_H_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_H_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_H_DEBOUNCE_THRESHOLD_07_0
#define GPIO_H_DEBOUNCE_THRESHOLD_07_0                  _MK_ADDR_CONST(0x142e4)
#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_SECURE                   0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_DUAL                     0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_SCR                      GPIO_H_SCR_07_0
#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                       0x1
#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_H_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_H_INPUT_07_0
#define GPIO_H_INPUT_07_0                       _MK_ADDR_CONST(0x142e8)
#define GPIO_H_INPUT_07_0_SECURE                        0x0
#define GPIO_H_INPUT_07_0_DUAL                  0x0
#define GPIO_H_INPUT_07_0_SCR                   GPIO_H_SCR_07_0
#define GPIO_H_INPUT_07_0_WORD_COUNT                    0x1
#define GPIO_H_INPUT_07_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_07_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_07_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_07_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_07_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_H_INPUT_07_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_07_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_H_INPUT_07_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_H_INPUT_07_0_GPIO_IN_SHIFT)
#define GPIO_H_INPUT_07_0_GPIO_IN_RANGE                 0:0
#define GPIO_H_INPUT_07_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_H_INPUT_07_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_07_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_07_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_07_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_07_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_H_OUTPUT_CONTROL_07_0
#define GPIO_H_OUTPUT_CONTROL_07_0                      _MK_ADDR_CONST(0x142ec)
#define GPIO_H_OUTPUT_CONTROL_07_0_SECURE                       0x0
#define GPIO_H_OUTPUT_CONTROL_07_0_DUAL                         0x0
#define GPIO_H_OUTPUT_CONTROL_07_0_SCR                  GPIO_H_SCR_07_0
#define GPIO_H_OUTPUT_CONTROL_07_0_WORD_COUNT                   0x1
#define GPIO_H_OUTPUT_CONTROL_07_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_07_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_07_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_07_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_H_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_H_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_H_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_H_OUTPUT_VALUE_07_0
#define GPIO_H_OUTPUT_VALUE_07_0                        _MK_ADDR_CONST(0x142f0)
#define GPIO_H_OUTPUT_VALUE_07_0_SECURE                         0x0
#define GPIO_H_OUTPUT_VALUE_07_0_DUAL                   0x0
#define GPIO_H_OUTPUT_VALUE_07_0_SCR                    GPIO_H_SCR_07_0
#define GPIO_H_OUTPUT_VALUE_07_0_WORD_COUNT                     0x1
#define GPIO_H_OUTPUT_VALUE_07_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_07_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_07_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_07_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_H_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_H_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_H_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_H_INTERRUPT_CLEAR_07_0
#define GPIO_H_INTERRUPT_CLEAR_07_0                     _MK_ADDR_CONST(0x142f4)
#define GPIO_H_INTERRUPT_CLEAR_07_0_SECURE                      0x0
#define GPIO_H_INTERRUPT_CLEAR_07_0_DUAL                        0x0
#define GPIO_H_INTERRUPT_CLEAR_07_0_SCR                         GPIO_H_SCR_07_0
#define GPIO_H_INTERRUPT_CLEAR_07_0_WORD_COUNT                  0x1
#define GPIO_H_INTERRUPT_CLEAR_07_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_07_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_07_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_07_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_H_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_H_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_H_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_H_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x142f8

// Reserved address 0x142fc

// Register GPIO_H_INTERRUPT_STATUS_G0_0
#define GPIO_H_INTERRUPT_STATUS_G0_0                    _MK_ADDR_CONST(0x14300)
#define GPIO_H_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_H_INTERRUPT_STATUS_G0_0_DUAL                       0x0
#define GPIO_H_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_H_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_H_INTERRUPT_STATUS_G0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G0_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_H_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G0_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_H_INTERRUPT_STATUS_G0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_H_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_H_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_H_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_H_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_H_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_H_INTERRUPT_STATUS_G1_0
#define GPIO_H_INTERRUPT_STATUS_G1_0                    _MK_ADDR_CONST(0x14304)
#define GPIO_H_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_H_INTERRUPT_STATUS_G1_0_DUAL                       0x0
#define GPIO_H_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_H_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_H_INTERRUPT_STATUS_G1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G1_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_H_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G1_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_H_INTERRUPT_STATUS_G1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_H_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_H_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_H_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_H_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_H_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_H_INTERRUPT_STATUS_G2_0
#define GPIO_H_INTERRUPT_STATUS_G2_0                    _MK_ADDR_CONST(0x14308)
#define GPIO_H_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_H_INTERRUPT_STATUS_G2_0_DUAL                       0x0
#define GPIO_H_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_H_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_H_INTERRUPT_STATUS_G2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G2_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_H_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G2_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_H_INTERRUPT_STATUS_G2_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_H_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_H_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_H_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_H_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_H_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_H_INTERRUPT_STATUS_G3_0
#define GPIO_H_INTERRUPT_STATUS_G3_0                    _MK_ADDR_CONST(0x1430c)
#define GPIO_H_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_H_INTERRUPT_STATUS_G3_0_DUAL                       0x0
#define GPIO_H_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_H_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_H_INTERRUPT_STATUS_G3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G3_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_H_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G3_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_H_INTERRUPT_STATUS_G3_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_H_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_H_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_H_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_H_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_H_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_H_INTERRUPT_STATUS_G4_0
#define GPIO_H_INTERRUPT_STATUS_G4_0                    _MK_ADDR_CONST(0x14310)
#define GPIO_H_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_H_INTERRUPT_STATUS_G4_0_DUAL                       0x0
#define GPIO_H_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_H_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_H_INTERRUPT_STATUS_G4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G4_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_H_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G4_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_H_INTERRUPT_STATUS_G4_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_H_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_H_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_H_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_H_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_H_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_H_INTERRUPT_STATUS_G5_0
#define GPIO_H_INTERRUPT_STATUS_G5_0                    _MK_ADDR_CONST(0x14314)
#define GPIO_H_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_H_INTERRUPT_STATUS_G5_0_DUAL                       0x0
#define GPIO_H_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_H_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_H_INTERRUPT_STATUS_G5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G5_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_H_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G5_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_H_INTERRUPT_STATUS_G5_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_H_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_H_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_H_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_H_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_H_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_H_INTERRUPT_STATUS_G6_0
#define GPIO_H_INTERRUPT_STATUS_G6_0                    _MK_ADDR_CONST(0x14318)
#define GPIO_H_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_H_INTERRUPT_STATUS_G6_0_DUAL                       0x0
#define GPIO_H_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_H_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_H_INTERRUPT_STATUS_G6_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G6_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_H_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G6_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_H_INTERRUPT_STATUS_G6_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_H_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_H_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_H_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_H_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_H_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_H_INTERRUPT_STATUS_G7_0
#define GPIO_H_INTERRUPT_STATUS_G7_0                    _MK_ADDR_CONST(0x1431c)
#define GPIO_H_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_H_INTERRUPT_STATUS_G7_0_DUAL                       0x0
#define GPIO_H_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_H_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_H_INTERRUPT_STATUS_G7_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G7_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_H_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G7_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_H_INTERRUPT_STATUS_G7_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_H_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_H_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_H_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_H_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_H_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Reserved address 0x14320

// Reserved address 0x14324

// Reserved address 0x14328

// Reserved address 0x1432c

// Reserved address 0x14330

// Reserved address 0x14334

// Reserved address 0x14338

// Reserved address 0x1433c

// Reserved address 0x14340

// Reserved address 0x14344

// Reserved address 0x14348

// Reserved address 0x1434c

// Reserved address 0x14350

// Reserved address 0x14354

// Reserved address 0x14358

// Reserved address 0x1435c

// Reserved address 0x14360

// Reserved address 0x14364

// Reserved address 0x14368

// Reserved address 0x1436c

// Reserved address 0x14370

// Reserved address 0x14374

// Reserved address 0x14378

// Reserved address 0x1437c

// Reserved address 0x14380

// Reserved address 0x14384

// Reserved address 0x14388

// Reserved address 0x1438c

// Reserved address 0x14390

// Reserved address 0x14394

// Reserved address 0x14398

// Reserved address 0x1439c

// Reserved address 0x143a0

// Reserved address 0x143a4

// Reserved address 0x143a8

// Reserved address 0x143ac

// Reserved address 0x143b0

// Reserved address 0x143b4

// Reserved address 0x143b8

// Reserved address 0x143bc

// Reserved address 0x143c0

// Reserved address 0x143c4

// Reserved address 0x143c8

// Reserved address 0x143cc

// Reserved address 0x143d0

// Reserved address 0x143d4

// Reserved address 0x143d8

// Reserved address 0x143dc

// Reserved address 0x143e0

// Reserved address 0x143e4

// Reserved address 0x143e8

// Reserved address 0x143ec

// Reserved address 0x143f0

// Reserved address 0x143f4

// Reserved address 0x143f8

// Reserved address 0x143fc

// Register GPIO_I_ENABLE_CONFIG_00_0
#define GPIO_I_ENABLE_CONFIG_00_0                       _MK_ADDR_CONST(0x14400)
#define GPIO_I_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_I_ENABLE_CONFIG_00_0_DUAL                  0x0
#define GPIO_I_ENABLE_CONFIG_00_0_SCR                   GPIO_I_SCR_00_0
#define GPIO_I_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_I_ENABLE_CONFIG_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_00_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_I_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_I_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_I_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_I_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_I_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_I_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_I_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_I_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_00_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_00_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_I_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_I_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_I_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_I_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_I_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_I_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_I_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_I_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_I_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_I_DEBOUNCE_THRESHOLD_00_0
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0                  _MK_ADDR_CONST(0x14404)
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_I_SCR_00_0
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_I_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_I_INPUT_00_0
#define GPIO_I_INPUT_00_0                       _MK_ADDR_CONST(0x14408)
#define GPIO_I_INPUT_00_0_SECURE                        0x0
#define GPIO_I_INPUT_00_0_DUAL                  0x0
#define GPIO_I_INPUT_00_0_SCR                   GPIO_I_SCR_00_0
#define GPIO_I_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_I_INPUT_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_00_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_00_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_I_INPUT_00_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_00_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_I_INPUT_00_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_I_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_I_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_I_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_I_INPUT_00_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_00_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_I_OUTPUT_CONTROL_00_0
#define GPIO_I_OUTPUT_CONTROL_00_0                      _MK_ADDR_CONST(0x1440c)
#define GPIO_I_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_I_OUTPUT_CONTROL_00_0_DUAL                         0x0
#define GPIO_I_OUTPUT_CONTROL_00_0_SCR                  GPIO_I_SCR_00_0
#define GPIO_I_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_I_OUTPUT_CONTROL_00_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_00_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_00_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_00_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_I_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_I_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_I_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_I_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_I_OUTPUT_VALUE_00_0
#define GPIO_I_OUTPUT_VALUE_00_0                        _MK_ADDR_CONST(0x14410)
#define GPIO_I_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_I_OUTPUT_VALUE_00_0_DUAL                   0x0
#define GPIO_I_OUTPUT_VALUE_00_0_SCR                    GPIO_I_SCR_00_0
#define GPIO_I_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_I_OUTPUT_VALUE_00_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_00_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_00_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_00_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_I_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_I_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_I_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_I_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_I_INTERRUPT_CLEAR_00_0
#define GPIO_I_INTERRUPT_CLEAR_00_0                     _MK_ADDR_CONST(0x14414)
#define GPIO_I_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_I_INTERRUPT_CLEAR_00_0_DUAL                        0x0
#define GPIO_I_INTERRUPT_CLEAR_00_0_SCR                         GPIO_I_SCR_00_0
#define GPIO_I_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_I_INTERRUPT_CLEAR_00_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_00_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_00_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_00_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_I_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_I_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_I_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_I_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_I_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x14418

// Reserved address 0x1441c

// Register GPIO_I_ENABLE_CONFIG_01_0
#define GPIO_I_ENABLE_CONFIG_01_0                       _MK_ADDR_CONST(0x14420)
#define GPIO_I_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_I_ENABLE_CONFIG_01_0_DUAL                  0x0
#define GPIO_I_ENABLE_CONFIG_01_0_SCR                   GPIO_I_SCR_01_0
#define GPIO_I_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_I_ENABLE_CONFIG_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_01_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_I_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_I_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_I_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_I_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_I_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_I_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_I_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_I_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_01_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_01_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_I_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_I_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_I_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_I_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_I_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_I_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_I_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_I_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_I_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_I_DEBOUNCE_THRESHOLD_01_0
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0                  _MK_ADDR_CONST(0x14424)
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_I_SCR_01_0
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_I_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_I_INPUT_01_0
#define GPIO_I_INPUT_01_0                       _MK_ADDR_CONST(0x14428)
#define GPIO_I_INPUT_01_0_SECURE                        0x0
#define GPIO_I_INPUT_01_0_DUAL                  0x0
#define GPIO_I_INPUT_01_0_SCR                   GPIO_I_SCR_01_0
#define GPIO_I_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_I_INPUT_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_01_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_01_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_I_INPUT_01_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_01_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_I_INPUT_01_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_I_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_I_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_I_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_I_INPUT_01_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_01_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_I_OUTPUT_CONTROL_01_0
#define GPIO_I_OUTPUT_CONTROL_01_0                      _MK_ADDR_CONST(0x1442c)
#define GPIO_I_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_I_OUTPUT_CONTROL_01_0_DUAL                         0x0
#define GPIO_I_OUTPUT_CONTROL_01_0_SCR                  GPIO_I_SCR_01_0
#define GPIO_I_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_I_OUTPUT_CONTROL_01_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_01_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_01_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_01_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_I_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_I_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_I_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_I_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_I_OUTPUT_VALUE_01_0
#define GPIO_I_OUTPUT_VALUE_01_0                        _MK_ADDR_CONST(0x14430)
#define GPIO_I_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_I_OUTPUT_VALUE_01_0_DUAL                   0x0
#define GPIO_I_OUTPUT_VALUE_01_0_SCR                    GPIO_I_SCR_01_0
#define GPIO_I_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_I_OUTPUT_VALUE_01_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_01_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_01_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_01_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_I_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_I_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_I_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_I_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_I_INTERRUPT_CLEAR_01_0
#define GPIO_I_INTERRUPT_CLEAR_01_0                     _MK_ADDR_CONST(0x14434)
#define GPIO_I_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_I_INTERRUPT_CLEAR_01_0_DUAL                        0x0
#define GPIO_I_INTERRUPT_CLEAR_01_0_SCR                         GPIO_I_SCR_01_0
#define GPIO_I_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_I_INTERRUPT_CLEAR_01_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_01_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_01_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_01_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_I_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_I_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_I_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_I_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_I_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x14438

// Reserved address 0x1443c

// Register GPIO_I_ENABLE_CONFIG_02_0
#define GPIO_I_ENABLE_CONFIG_02_0                       _MK_ADDR_CONST(0x14440)
#define GPIO_I_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_I_ENABLE_CONFIG_02_0_DUAL                  0x0
#define GPIO_I_ENABLE_CONFIG_02_0_SCR                   GPIO_I_SCR_02_0
#define GPIO_I_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_I_ENABLE_CONFIG_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_02_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_I_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_I_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_I_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_I_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_I_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_I_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_I_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_I_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_02_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_02_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_I_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_I_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_I_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_I_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_I_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_I_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_I_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_I_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_I_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_I_DEBOUNCE_THRESHOLD_02_0
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0                  _MK_ADDR_CONST(0x14444)
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_I_SCR_02_0
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_I_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_I_INPUT_02_0
#define GPIO_I_INPUT_02_0                       _MK_ADDR_CONST(0x14448)
#define GPIO_I_INPUT_02_0_SECURE                        0x0
#define GPIO_I_INPUT_02_0_DUAL                  0x0
#define GPIO_I_INPUT_02_0_SCR                   GPIO_I_SCR_02_0
#define GPIO_I_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_I_INPUT_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_02_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_02_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_I_INPUT_02_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_02_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_I_INPUT_02_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_I_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_I_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_I_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_I_INPUT_02_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_02_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_I_OUTPUT_CONTROL_02_0
#define GPIO_I_OUTPUT_CONTROL_02_0                      _MK_ADDR_CONST(0x1444c)
#define GPIO_I_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_I_OUTPUT_CONTROL_02_0_DUAL                         0x0
#define GPIO_I_OUTPUT_CONTROL_02_0_SCR                  GPIO_I_SCR_02_0
#define GPIO_I_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_I_OUTPUT_CONTROL_02_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_02_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_02_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_02_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_I_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_I_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_I_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_I_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_I_OUTPUT_VALUE_02_0
#define GPIO_I_OUTPUT_VALUE_02_0                        _MK_ADDR_CONST(0x14450)
#define GPIO_I_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_I_OUTPUT_VALUE_02_0_DUAL                   0x0
#define GPIO_I_OUTPUT_VALUE_02_0_SCR                    GPIO_I_SCR_02_0
#define GPIO_I_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_I_OUTPUT_VALUE_02_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_02_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_02_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_02_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_I_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_I_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_I_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_I_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_I_INTERRUPT_CLEAR_02_0
#define GPIO_I_INTERRUPT_CLEAR_02_0                     _MK_ADDR_CONST(0x14454)
#define GPIO_I_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_I_INTERRUPT_CLEAR_02_0_DUAL                        0x0
#define GPIO_I_INTERRUPT_CLEAR_02_0_SCR                         GPIO_I_SCR_02_0
#define GPIO_I_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_I_INTERRUPT_CLEAR_02_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_02_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_02_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_02_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_I_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_I_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_I_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_I_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_I_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x14458

// Reserved address 0x1445c

// Register GPIO_I_ENABLE_CONFIG_03_0
#define GPIO_I_ENABLE_CONFIG_03_0                       _MK_ADDR_CONST(0x14460)
#define GPIO_I_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_I_ENABLE_CONFIG_03_0_DUAL                  0x0
#define GPIO_I_ENABLE_CONFIG_03_0_SCR                   GPIO_I_SCR_03_0
#define GPIO_I_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_I_ENABLE_CONFIG_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_03_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_I_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_I_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_I_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_I_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_I_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_I_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_I_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_I_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_03_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_03_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_I_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_I_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_I_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_I_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_I_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_I_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_I_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_I_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_I_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_I_DEBOUNCE_THRESHOLD_03_0
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0                  _MK_ADDR_CONST(0x14464)
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_I_SCR_03_0
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_I_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_I_INPUT_03_0
#define GPIO_I_INPUT_03_0                       _MK_ADDR_CONST(0x14468)
#define GPIO_I_INPUT_03_0_SECURE                        0x0
#define GPIO_I_INPUT_03_0_DUAL                  0x0
#define GPIO_I_INPUT_03_0_SCR                   GPIO_I_SCR_03_0
#define GPIO_I_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_I_INPUT_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_03_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_03_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_I_INPUT_03_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_03_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_I_INPUT_03_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_I_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_I_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_I_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_I_INPUT_03_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_03_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_I_OUTPUT_CONTROL_03_0
#define GPIO_I_OUTPUT_CONTROL_03_0                      _MK_ADDR_CONST(0x1446c)
#define GPIO_I_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_I_OUTPUT_CONTROL_03_0_DUAL                         0x0
#define GPIO_I_OUTPUT_CONTROL_03_0_SCR                  GPIO_I_SCR_03_0
#define GPIO_I_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_I_OUTPUT_CONTROL_03_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_03_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_03_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_03_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_I_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_I_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_I_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_I_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_I_OUTPUT_VALUE_03_0
#define GPIO_I_OUTPUT_VALUE_03_0                        _MK_ADDR_CONST(0x14470)
#define GPIO_I_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_I_OUTPUT_VALUE_03_0_DUAL                   0x0
#define GPIO_I_OUTPUT_VALUE_03_0_SCR                    GPIO_I_SCR_03_0
#define GPIO_I_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_I_OUTPUT_VALUE_03_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_03_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_03_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_03_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_I_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_I_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_I_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_I_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_I_INTERRUPT_CLEAR_03_0
#define GPIO_I_INTERRUPT_CLEAR_03_0                     _MK_ADDR_CONST(0x14474)
#define GPIO_I_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_I_INTERRUPT_CLEAR_03_0_DUAL                        0x0
#define GPIO_I_INTERRUPT_CLEAR_03_0_SCR                         GPIO_I_SCR_03_0
#define GPIO_I_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_I_INTERRUPT_CLEAR_03_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_03_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_03_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_03_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_I_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_I_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_I_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_I_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_I_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x14478

// Reserved address 0x1447c

// Register GPIO_I_ENABLE_CONFIG_04_0
#define GPIO_I_ENABLE_CONFIG_04_0                       _MK_ADDR_CONST(0x14480)
#define GPIO_I_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_I_ENABLE_CONFIG_04_0_DUAL                  0x0
#define GPIO_I_ENABLE_CONFIG_04_0_SCR                   GPIO_I_SCR_04_0
#define GPIO_I_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_I_ENABLE_CONFIG_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_04_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_I_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_I_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_I_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_I_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_I_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_I_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_I_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_I_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_04_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_04_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_I_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_I_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_I_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_I_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_I_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_I_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_I_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_I_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_I_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_I_DEBOUNCE_THRESHOLD_04_0
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0                  _MK_ADDR_CONST(0x14484)
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_DUAL                     0x0
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_I_SCR_04_0
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_I_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_I_INPUT_04_0
#define GPIO_I_INPUT_04_0                       _MK_ADDR_CONST(0x14488)
#define GPIO_I_INPUT_04_0_SECURE                        0x0
#define GPIO_I_INPUT_04_0_DUAL                  0x0
#define GPIO_I_INPUT_04_0_SCR                   GPIO_I_SCR_04_0
#define GPIO_I_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_I_INPUT_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_04_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_04_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_I_INPUT_04_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_04_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_I_INPUT_04_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_I_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_I_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_I_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_I_INPUT_04_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_04_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_I_OUTPUT_CONTROL_04_0
#define GPIO_I_OUTPUT_CONTROL_04_0                      _MK_ADDR_CONST(0x1448c)
#define GPIO_I_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_I_OUTPUT_CONTROL_04_0_DUAL                         0x0
#define GPIO_I_OUTPUT_CONTROL_04_0_SCR                  GPIO_I_SCR_04_0
#define GPIO_I_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_I_OUTPUT_CONTROL_04_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_04_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_04_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_04_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_I_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_I_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_I_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_I_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_I_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_I_OUTPUT_VALUE_04_0
#define GPIO_I_OUTPUT_VALUE_04_0                        _MK_ADDR_CONST(0x14490)
#define GPIO_I_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_I_OUTPUT_VALUE_04_0_DUAL                   0x0
#define GPIO_I_OUTPUT_VALUE_04_0_SCR                    GPIO_I_SCR_04_0
#define GPIO_I_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_I_OUTPUT_VALUE_04_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_04_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_04_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_04_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_I_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_I_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_I_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_I_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_I_INTERRUPT_CLEAR_04_0
#define GPIO_I_INTERRUPT_CLEAR_04_0                     _MK_ADDR_CONST(0x14494)
#define GPIO_I_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_I_INTERRUPT_CLEAR_04_0_DUAL                        0x0
#define GPIO_I_INTERRUPT_CLEAR_04_0_SCR                         GPIO_I_SCR_04_0
#define GPIO_I_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_I_INTERRUPT_CLEAR_04_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_04_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_04_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_04_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_I_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_I_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_I_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_I_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_I_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x14498

// Reserved address 0x1449c

// Reserved address 0x144a0

// Reserved address 0x144a4

// Reserved address 0x144a8

// Reserved address 0x144ac

// Reserved address 0x144b0

// Reserved address 0x144b4

// Reserved address 0x144b8

// Reserved address 0x144bc

// Reserved address 0x144c0

// Reserved address 0x144c4

// Reserved address 0x144c8

// Reserved address 0x144cc

// Reserved address 0x144d0

// Reserved address 0x144d4

// Reserved address 0x144d8

// Reserved address 0x144dc

// Reserved address 0x144e0

// Reserved address 0x144e4

// Reserved address 0x144e8

// Reserved address 0x144ec

// Reserved address 0x144f0

// Reserved address 0x144f4

// Reserved address 0x144f8

// Reserved address 0x144fc

// Register GPIO_I_INTERRUPT_STATUS_G0_0
#define GPIO_I_INTERRUPT_STATUS_G0_0                    _MK_ADDR_CONST(0x14500)
#define GPIO_I_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_I_INTERRUPT_STATUS_G0_0_DUAL                       0x0
#define GPIO_I_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_I_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_I_INTERRUPT_STATUS_G0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G0_0_RESET_MASK                         _MK_MASK_CONST(0x1f)
#define GPIO_I_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G0_0_READ_MASK                  _MK_MASK_CONST(0x1f)
#define GPIO_I_INTERRUPT_STATUS_G0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x1f, GPIO_I_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_I_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        4:0
#define GPIO_I_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_I_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define GPIO_I_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_I_INTERRUPT_STATUS_G1_0
#define GPIO_I_INTERRUPT_STATUS_G1_0                    _MK_ADDR_CONST(0x14504)
#define GPIO_I_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_I_INTERRUPT_STATUS_G1_0_DUAL                       0x0
#define GPIO_I_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_I_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_I_INTERRUPT_STATUS_G1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G1_0_RESET_MASK                         _MK_MASK_CONST(0x1f)
#define GPIO_I_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G1_0_READ_MASK                  _MK_MASK_CONST(0x1f)
#define GPIO_I_INTERRUPT_STATUS_G1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x1f, GPIO_I_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_I_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        4:0
#define GPIO_I_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_I_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define GPIO_I_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_I_INTERRUPT_STATUS_G2_0
#define GPIO_I_INTERRUPT_STATUS_G2_0                    _MK_ADDR_CONST(0x14508)
#define GPIO_I_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_I_INTERRUPT_STATUS_G2_0_DUAL                       0x0
#define GPIO_I_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_I_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_I_INTERRUPT_STATUS_G2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G2_0_RESET_MASK                         _MK_MASK_CONST(0x1f)
#define GPIO_I_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G2_0_READ_MASK                  _MK_MASK_CONST(0x1f)
#define GPIO_I_INTERRUPT_STATUS_G2_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x1f, GPIO_I_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_I_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        4:0
#define GPIO_I_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_I_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define GPIO_I_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_I_INTERRUPT_STATUS_G3_0
#define GPIO_I_INTERRUPT_STATUS_G3_0                    _MK_ADDR_CONST(0x1450c)
#define GPIO_I_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_I_INTERRUPT_STATUS_G3_0_DUAL                       0x0
#define GPIO_I_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_I_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_I_INTERRUPT_STATUS_G3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G3_0_RESET_MASK                         _MK_MASK_CONST(0x1f)
#define GPIO_I_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G3_0_READ_MASK                  _MK_MASK_CONST(0x1f)
#define GPIO_I_INTERRUPT_STATUS_G3_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x1f, GPIO_I_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_I_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        4:0
#define GPIO_I_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_I_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define GPIO_I_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_I_INTERRUPT_STATUS_G4_0
#define GPIO_I_INTERRUPT_STATUS_G4_0                    _MK_ADDR_CONST(0x14510)
#define GPIO_I_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_I_INTERRUPT_STATUS_G4_0_DUAL                       0x0
#define GPIO_I_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_I_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_I_INTERRUPT_STATUS_G4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G4_0_RESET_MASK                         _MK_MASK_CONST(0x1f)
#define GPIO_I_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G4_0_READ_MASK                  _MK_MASK_CONST(0x1f)
#define GPIO_I_INTERRUPT_STATUS_G4_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x1f, GPIO_I_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_I_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        4:0
#define GPIO_I_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_I_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define GPIO_I_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_I_INTERRUPT_STATUS_G5_0
#define GPIO_I_INTERRUPT_STATUS_G5_0                    _MK_ADDR_CONST(0x14514)
#define GPIO_I_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_I_INTERRUPT_STATUS_G5_0_DUAL                       0x0
#define GPIO_I_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_I_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_I_INTERRUPT_STATUS_G5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G5_0_RESET_MASK                         _MK_MASK_CONST(0x1f)
#define GPIO_I_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G5_0_READ_MASK                  _MK_MASK_CONST(0x1f)
#define GPIO_I_INTERRUPT_STATUS_G5_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x1f, GPIO_I_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_I_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        4:0
#define GPIO_I_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_I_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define GPIO_I_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_I_INTERRUPT_STATUS_G6_0
#define GPIO_I_INTERRUPT_STATUS_G6_0                    _MK_ADDR_CONST(0x14518)
#define GPIO_I_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_I_INTERRUPT_STATUS_G6_0_DUAL                       0x0
#define GPIO_I_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_I_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_I_INTERRUPT_STATUS_G6_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G6_0_RESET_MASK                         _MK_MASK_CONST(0x1f)
#define GPIO_I_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G6_0_READ_MASK                  _MK_MASK_CONST(0x1f)
#define GPIO_I_INTERRUPT_STATUS_G6_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x1f, GPIO_I_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_I_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        4:0
#define GPIO_I_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_I_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define GPIO_I_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_I_INTERRUPT_STATUS_G7_0
#define GPIO_I_INTERRUPT_STATUS_G7_0                    _MK_ADDR_CONST(0x1451c)
#define GPIO_I_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_I_INTERRUPT_STATUS_G7_0_DUAL                       0x0
#define GPIO_I_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_I_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_I_INTERRUPT_STATUS_G7_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G7_0_RESET_MASK                         _MK_MASK_CONST(0x1f)
#define GPIO_I_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G7_0_READ_MASK                  _MK_MASK_CONST(0x1f)
#define GPIO_I_INTERRUPT_STATUS_G7_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x1f, GPIO_I_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_I_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        4:0
#define GPIO_I_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_I_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define GPIO_I_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Reserved address 0x14520

// Reserved address 0x14524

// Reserved address 0x14528

// Reserved address 0x1452c

// Reserved address 0x14530

// Reserved address 0x14534

// Reserved address 0x14538

// Reserved address 0x1453c

// Reserved address 0x14540

// Reserved address 0x14544

// Reserved address 0x14548

// Reserved address 0x1454c

// Reserved address 0x14550

// Reserved address 0x14554

// Reserved address 0x14558

// Reserved address 0x1455c

// Reserved address 0x14560

// Reserved address 0x14564

// Reserved address 0x14568

// Reserved address 0x1456c

// Reserved address 0x14570

// Reserved address 0x14574

// Reserved address 0x14578

// Reserved address 0x1457c

// Reserved address 0x14580

// Reserved address 0x14584

// Reserved address 0x14588

// Reserved address 0x1458c

// Reserved address 0x14590

// Reserved address 0x14594

// Reserved address 0x14598

// Reserved address 0x1459c

// Reserved address 0x145a0

// Reserved address 0x145a4

// Reserved address 0x145a8

// Reserved address 0x145ac

// Reserved address 0x145b0

// Reserved address 0x145b4

// Reserved address 0x145b8

// Reserved address 0x145bc

// Reserved address 0x145c0

// Reserved address 0x145c4

// Reserved address 0x145c8

// Reserved address 0x145cc

// Reserved address 0x145d0

// Reserved address 0x145d4

// Reserved address 0x145d8

// Reserved address 0x145dc

// Reserved address 0x145e0

// Reserved address 0x145e4

// Reserved address 0x145e8

// Reserved address 0x145ec

// Reserved address 0x145f0

// Reserved address 0x145f4

// Reserved address 0x145f8

// Reserved address 0x145fc

// Register GPIO_C_ENABLE_CONFIG_00_0
#define GPIO_C_ENABLE_CONFIG_00_0                       _MK_ADDR_CONST(0x14600)
#define GPIO_C_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_C_ENABLE_CONFIG_00_0_DUAL                  0x0
#define GPIO_C_ENABLE_CONFIG_00_0_SCR                   GPIO_C_SCR_00_0
#define GPIO_C_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_C_ENABLE_CONFIG_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_00_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_C_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_C_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_C_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_C_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_C_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_C_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_C_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_C_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_00_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_00_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_C_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_C_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_C_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_C_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_C_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_C_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_C_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_C_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_C_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_C_DEBOUNCE_THRESHOLD_00_0
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0                  _MK_ADDR_CONST(0x14604)
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_C_SCR_00_0
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_C_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_C_INPUT_00_0
#define GPIO_C_INPUT_00_0                       _MK_ADDR_CONST(0x14608)
#define GPIO_C_INPUT_00_0_SECURE                        0x0
#define GPIO_C_INPUT_00_0_DUAL                  0x0
#define GPIO_C_INPUT_00_0_SCR                   GPIO_C_SCR_00_0
#define GPIO_C_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_C_INPUT_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_00_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_00_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_C_INPUT_00_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_00_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_C_INPUT_00_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_C_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_C_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_C_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_C_INPUT_00_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_00_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_C_OUTPUT_CONTROL_00_0
#define GPIO_C_OUTPUT_CONTROL_00_0                      _MK_ADDR_CONST(0x1460c)
#define GPIO_C_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_C_OUTPUT_CONTROL_00_0_DUAL                         0x0
#define GPIO_C_OUTPUT_CONTROL_00_0_SCR                  GPIO_C_SCR_00_0
#define GPIO_C_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_C_OUTPUT_CONTROL_00_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_00_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_00_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_00_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_C_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_C_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_C_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_C_OUTPUT_VALUE_00_0
#define GPIO_C_OUTPUT_VALUE_00_0                        _MK_ADDR_CONST(0x14610)
#define GPIO_C_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_C_OUTPUT_VALUE_00_0_DUAL                   0x0
#define GPIO_C_OUTPUT_VALUE_00_0_SCR                    GPIO_C_SCR_00_0
#define GPIO_C_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_C_OUTPUT_VALUE_00_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_00_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_00_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_00_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_C_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_C_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_C_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_C_INTERRUPT_CLEAR_00_0
#define GPIO_C_INTERRUPT_CLEAR_00_0                     _MK_ADDR_CONST(0x14614)
#define GPIO_C_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_C_INTERRUPT_CLEAR_00_0_DUAL                        0x0
#define GPIO_C_INTERRUPT_CLEAR_00_0_SCR                         GPIO_C_SCR_00_0
#define GPIO_C_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_C_INTERRUPT_CLEAR_00_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_00_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_00_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_00_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_C_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_C_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_C_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_C_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x14618

// Reserved address 0x1461c

// Register GPIO_C_ENABLE_CONFIG_01_0
#define GPIO_C_ENABLE_CONFIG_01_0                       _MK_ADDR_CONST(0x14620)
#define GPIO_C_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_C_ENABLE_CONFIG_01_0_DUAL                  0x0
#define GPIO_C_ENABLE_CONFIG_01_0_SCR                   GPIO_C_SCR_01_0
#define GPIO_C_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_C_ENABLE_CONFIG_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_01_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_C_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_C_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_C_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_C_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_C_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_C_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_C_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_C_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_01_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_01_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_C_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_C_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_C_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_C_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_C_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_C_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_C_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_C_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_C_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_C_DEBOUNCE_THRESHOLD_01_0
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0                  _MK_ADDR_CONST(0x14624)
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_C_SCR_01_0
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_C_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_C_INPUT_01_0
#define GPIO_C_INPUT_01_0                       _MK_ADDR_CONST(0x14628)
#define GPIO_C_INPUT_01_0_SECURE                        0x0
#define GPIO_C_INPUT_01_0_DUAL                  0x0
#define GPIO_C_INPUT_01_0_SCR                   GPIO_C_SCR_01_0
#define GPIO_C_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_C_INPUT_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_01_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_01_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_C_INPUT_01_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_01_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_C_INPUT_01_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_C_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_C_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_C_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_C_INPUT_01_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_01_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_C_OUTPUT_CONTROL_01_0
#define GPIO_C_OUTPUT_CONTROL_01_0                      _MK_ADDR_CONST(0x1462c)
#define GPIO_C_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_C_OUTPUT_CONTROL_01_0_DUAL                         0x0
#define GPIO_C_OUTPUT_CONTROL_01_0_SCR                  GPIO_C_SCR_01_0
#define GPIO_C_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_C_OUTPUT_CONTROL_01_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_01_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_01_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_01_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_C_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_C_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_C_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_C_OUTPUT_VALUE_01_0
#define GPIO_C_OUTPUT_VALUE_01_0                        _MK_ADDR_CONST(0x14630)
#define GPIO_C_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_C_OUTPUT_VALUE_01_0_DUAL                   0x0
#define GPIO_C_OUTPUT_VALUE_01_0_SCR                    GPIO_C_SCR_01_0
#define GPIO_C_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_C_OUTPUT_VALUE_01_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_01_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_01_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_01_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_C_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_C_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_C_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_C_INTERRUPT_CLEAR_01_0
#define GPIO_C_INTERRUPT_CLEAR_01_0                     _MK_ADDR_CONST(0x14634)
#define GPIO_C_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_C_INTERRUPT_CLEAR_01_0_DUAL                        0x0
#define GPIO_C_INTERRUPT_CLEAR_01_0_SCR                         GPIO_C_SCR_01_0
#define GPIO_C_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_C_INTERRUPT_CLEAR_01_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_01_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_01_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_01_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_C_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_C_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_C_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_C_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x14638

// Reserved address 0x1463c

// Register GPIO_C_ENABLE_CONFIG_02_0
#define GPIO_C_ENABLE_CONFIG_02_0                       _MK_ADDR_CONST(0x14640)
#define GPIO_C_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_C_ENABLE_CONFIG_02_0_DUAL                  0x0
#define GPIO_C_ENABLE_CONFIG_02_0_SCR                   GPIO_C_SCR_02_0
#define GPIO_C_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_C_ENABLE_CONFIG_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_02_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_C_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_C_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_C_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_C_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_C_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_C_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_C_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_C_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_02_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_02_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_C_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_C_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_C_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_C_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_C_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_C_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_C_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_C_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_C_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_C_DEBOUNCE_THRESHOLD_02_0
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0                  _MK_ADDR_CONST(0x14644)
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_C_SCR_02_0
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_C_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_C_INPUT_02_0
#define GPIO_C_INPUT_02_0                       _MK_ADDR_CONST(0x14648)
#define GPIO_C_INPUT_02_0_SECURE                        0x0
#define GPIO_C_INPUT_02_0_DUAL                  0x0
#define GPIO_C_INPUT_02_0_SCR                   GPIO_C_SCR_02_0
#define GPIO_C_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_C_INPUT_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_02_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_02_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_C_INPUT_02_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_02_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_C_INPUT_02_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_C_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_C_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_C_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_C_INPUT_02_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_02_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_C_OUTPUT_CONTROL_02_0
#define GPIO_C_OUTPUT_CONTROL_02_0                      _MK_ADDR_CONST(0x1464c)
#define GPIO_C_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_C_OUTPUT_CONTROL_02_0_DUAL                         0x0
#define GPIO_C_OUTPUT_CONTROL_02_0_SCR                  GPIO_C_SCR_02_0
#define GPIO_C_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_C_OUTPUT_CONTROL_02_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_02_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_02_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_02_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_C_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_C_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_C_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_C_OUTPUT_VALUE_02_0
#define GPIO_C_OUTPUT_VALUE_02_0                        _MK_ADDR_CONST(0x14650)
#define GPIO_C_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_C_OUTPUT_VALUE_02_0_DUAL                   0x0
#define GPIO_C_OUTPUT_VALUE_02_0_SCR                    GPIO_C_SCR_02_0
#define GPIO_C_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_C_OUTPUT_VALUE_02_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_02_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_02_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_02_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_C_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_C_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_C_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_C_INTERRUPT_CLEAR_02_0
#define GPIO_C_INTERRUPT_CLEAR_02_0                     _MK_ADDR_CONST(0x14654)
#define GPIO_C_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_C_INTERRUPT_CLEAR_02_0_DUAL                        0x0
#define GPIO_C_INTERRUPT_CLEAR_02_0_SCR                         GPIO_C_SCR_02_0
#define GPIO_C_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_C_INTERRUPT_CLEAR_02_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_02_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_02_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_02_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_C_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_C_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_C_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_C_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x14658

// Reserved address 0x1465c

// Register GPIO_C_ENABLE_CONFIG_03_0
#define GPIO_C_ENABLE_CONFIG_03_0                       _MK_ADDR_CONST(0x14660)
#define GPIO_C_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_C_ENABLE_CONFIG_03_0_DUAL                  0x0
#define GPIO_C_ENABLE_CONFIG_03_0_SCR                   GPIO_C_SCR_03_0
#define GPIO_C_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_C_ENABLE_CONFIG_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_03_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_C_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_C_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_C_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_C_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_C_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_C_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_C_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_C_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_03_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_03_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_C_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_C_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_C_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_C_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_C_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_C_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_C_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_C_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_C_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_C_DEBOUNCE_THRESHOLD_03_0
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0                  _MK_ADDR_CONST(0x14664)
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_C_SCR_03_0
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_C_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_C_INPUT_03_0
#define GPIO_C_INPUT_03_0                       _MK_ADDR_CONST(0x14668)
#define GPIO_C_INPUT_03_0_SECURE                        0x0
#define GPIO_C_INPUT_03_0_DUAL                  0x0
#define GPIO_C_INPUT_03_0_SCR                   GPIO_C_SCR_03_0
#define GPIO_C_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_C_INPUT_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_03_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_03_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_C_INPUT_03_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_03_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_C_INPUT_03_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_C_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_C_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_C_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_C_INPUT_03_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_03_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_C_OUTPUT_CONTROL_03_0
#define GPIO_C_OUTPUT_CONTROL_03_0                      _MK_ADDR_CONST(0x1466c)
#define GPIO_C_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_C_OUTPUT_CONTROL_03_0_DUAL                         0x0
#define GPIO_C_OUTPUT_CONTROL_03_0_SCR                  GPIO_C_SCR_03_0
#define GPIO_C_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_C_OUTPUT_CONTROL_03_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_03_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_03_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_03_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_C_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_C_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_C_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_C_OUTPUT_VALUE_03_0
#define GPIO_C_OUTPUT_VALUE_03_0                        _MK_ADDR_CONST(0x14670)
#define GPIO_C_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_C_OUTPUT_VALUE_03_0_DUAL                   0x0
#define GPIO_C_OUTPUT_VALUE_03_0_SCR                    GPIO_C_SCR_03_0
#define GPIO_C_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_C_OUTPUT_VALUE_03_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_03_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_03_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_03_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_C_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_C_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_C_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_C_INTERRUPT_CLEAR_03_0
#define GPIO_C_INTERRUPT_CLEAR_03_0                     _MK_ADDR_CONST(0x14674)
#define GPIO_C_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_C_INTERRUPT_CLEAR_03_0_DUAL                        0x0
#define GPIO_C_INTERRUPT_CLEAR_03_0_SCR                         GPIO_C_SCR_03_0
#define GPIO_C_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_C_INTERRUPT_CLEAR_03_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_03_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_03_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_03_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_C_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_C_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_C_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_C_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x14678

// Reserved address 0x1467c

// Register GPIO_C_ENABLE_CONFIG_04_0
#define GPIO_C_ENABLE_CONFIG_04_0                       _MK_ADDR_CONST(0x14680)
#define GPIO_C_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_C_ENABLE_CONFIG_04_0_DUAL                  0x0
#define GPIO_C_ENABLE_CONFIG_04_0_SCR                   GPIO_C_SCR_04_0
#define GPIO_C_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_C_ENABLE_CONFIG_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_04_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_C_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_C_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_C_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_C_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_C_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_C_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_C_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_C_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_04_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_04_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_C_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_C_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_C_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_C_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_C_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_C_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_C_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_C_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_C_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_C_DEBOUNCE_THRESHOLD_04_0
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0                  _MK_ADDR_CONST(0x14684)
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_DUAL                     0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_C_SCR_04_0
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_C_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_C_INPUT_04_0
#define GPIO_C_INPUT_04_0                       _MK_ADDR_CONST(0x14688)
#define GPIO_C_INPUT_04_0_SECURE                        0x0
#define GPIO_C_INPUT_04_0_DUAL                  0x0
#define GPIO_C_INPUT_04_0_SCR                   GPIO_C_SCR_04_0
#define GPIO_C_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_C_INPUT_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_04_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_04_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_C_INPUT_04_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_04_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_C_INPUT_04_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_C_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_C_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_C_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_C_INPUT_04_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_04_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_C_OUTPUT_CONTROL_04_0
#define GPIO_C_OUTPUT_CONTROL_04_0                      _MK_ADDR_CONST(0x1468c)
#define GPIO_C_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_C_OUTPUT_CONTROL_04_0_DUAL                         0x0
#define GPIO_C_OUTPUT_CONTROL_04_0_SCR                  GPIO_C_SCR_04_0
#define GPIO_C_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_C_OUTPUT_CONTROL_04_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_04_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_04_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_04_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_C_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_C_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_C_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_C_OUTPUT_VALUE_04_0
#define GPIO_C_OUTPUT_VALUE_04_0                        _MK_ADDR_CONST(0x14690)
#define GPIO_C_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_C_OUTPUT_VALUE_04_0_DUAL                   0x0
#define GPIO_C_OUTPUT_VALUE_04_0_SCR                    GPIO_C_SCR_04_0
#define GPIO_C_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_C_OUTPUT_VALUE_04_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_04_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_04_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_04_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_C_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_C_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_C_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_C_INTERRUPT_CLEAR_04_0
#define GPIO_C_INTERRUPT_CLEAR_04_0                     _MK_ADDR_CONST(0x14694)
#define GPIO_C_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_C_INTERRUPT_CLEAR_04_0_DUAL                        0x0
#define GPIO_C_INTERRUPT_CLEAR_04_0_SCR                         GPIO_C_SCR_04_0
#define GPIO_C_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_C_INTERRUPT_CLEAR_04_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_04_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_04_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_04_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_C_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_C_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_C_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_C_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x14698

// Reserved address 0x1469c

// Register GPIO_C_ENABLE_CONFIG_05_0
#define GPIO_C_ENABLE_CONFIG_05_0                       _MK_ADDR_CONST(0x146a0)
#define GPIO_C_ENABLE_CONFIG_05_0_SECURE                        0x0
#define GPIO_C_ENABLE_CONFIG_05_0_DUAL                  0x0
#define GPIO_C_ENABLE_CONFIG_05_0_SCR                   GPIO_C_SCR_05_0
#define GPIO_C_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
#define GPIO_C_ENABLE_CONFIG_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_05_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_C_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_C_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_C_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_C_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_C_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_C_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
#define GPIO_C_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
#define GPIO_C_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_05_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_05_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_C_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_C_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_C_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_C_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_C_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_C_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_C_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_C_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_C_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_C_DEBOUNCE_THRESHOLD_05_0
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0                  _MK_ADDR_CONST(0x146a4)
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_DUAL                     0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_C_SCR_05_0
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_C_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_C_INPUT_05_0
#define GPIO_C_INPUT_05_0                       _MK_ADDR_CONST(0x146a8)
#define GPIO_C_INPUT_05_0_SECURE                        0x0
#define GPIO_C_INPUT_05_0_DUAL                  0x0
#define GPIO_C_INPUT_05_0_SCR                   GPIO_C_SCR_05_0
#define GPIO_C_INPUT_05_0_WORD_COUNT                    0x1
#define GPIO_C_INPUT_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_05_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_05_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_C_INPUT_05_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_05_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_C_INPUT_05_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_C_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_C_INPUT_05_0_GPIO_IN_RANGE                 0:0
#define GPIO_C_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_C_INPUT_05_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_05_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_C_OUTPUT_CONTROL_05_0
#define GPIO_C_OUTPUT_CONTROL_05_0                      _MK_ADDR_CONST(0x146ac)
#define GPIO_C_OUTPUT_CONTROL_05_0_SECURE                       0x0
#define GPIO_C_OUTPUT_CONTROL_05_0_DUAL                         0x0
#define GPIO_C_OUTPUT_CONTROL_05_0_SCR                  GPIO_C_SCR_05_0
#define GPIO_C_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
#define GPIO_C_OUTPUT_CONTROL_05_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_05_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_05_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_05_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_C_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_C_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_C_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_C_OUTPUT_VALUE_05_0
#define GPIO_C_OUTPUT_VALUE_05_0                        _MK_ADDR_CONST(0x146b0)
#define GPIO_C_OUTPUT_VALUE_05_0_SECURE                         0x0
#define GPIO_C_OUTPUT_VALUE_05_0_DUAL                   0x0
#define GPIO_C_OUTPUT_VALUE_05_0_SCR                    GPIO_C_SCR_05_0
#define GPIO_C_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
#define GPIO_C_OUTPUT_VALUE_05_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_05_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_05_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_05_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_C_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_C_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_C_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_C_INTERRUPT_CLEAR_05_0
#define GPIO_C_INTERRUPT_CLEAR_05_0                     _MK_ADDR_CONST(0x146b4)
#define GPIO_C_INTERRUPT_CLEAR_05_0_SECURE                      0x0
#define GPIO_C_INTERRUPT_CLEAR_05_0_DUAL                        0x0
#define GPIO_C_INTERRUPT_CLEAR_05_0_SCR                         GPIO_C_SCR_05_0
#define GPIO_C_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
#define GPIO_C_INTERRUPT_CLEAR_05_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_05_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_05_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_05_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_C_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_C_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_C_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_C_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x146b8

// Reserved address 0x146bc

// Register GPIO_C_ENABLE_CONFIG_06_0
#define GPIO_C_ENABLE_CONFIG_06_0                       _MK_ADDR_CONST(0x146c0)
#define GPIO_C_ENABLE_CONFIG_06_0_SECURE                        0x0
#define GPIO_C_ENABLE_CONFIG_06_0_DUAL                  0x0
#define GPIO_C_ENABLE_CONFIG_06_0_SCR                   GPIO_C_SCR_06_0
#define GPIO_C_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
#define GPIO_C_ENABLE_CONFIG_06_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_06_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_C_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
#define GPIO_C_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_C_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_C_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_C_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
#define GPIO_C_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
#define GPIO_C_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
#define GPIO_C_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_06_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_06_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_C_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_C_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_C_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_C_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_C_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_C_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_C_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_C_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_C_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_C_DEBOUNCE_THRESHOLD_06_0
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0                  _MK_ADDR_CONST(0x146c4)
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_DUAL                     0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_C_SCR_06_0
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_C_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_C_INPUT_06_0
#define GPIO_C_INPUT_06_0                       _MK_ADDR_CONST(0x146c8)
#define GPIO_C_INPUT_06_0_SECURE                        0x0
#define GPIO_C_INPUT_06_0_DUAL                  0x0
#define GPIO_C_INPUT_06_0_SCR                   GPIO_C_SCR_06_0
#define GPIO_C_INPUT_06_0_WORD_COUNT                    0x1
#define GPIO_C_INPUT_06_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_06_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_06_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_06_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_06_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_C_INPUT_06_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_06_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_C_INPUT_06_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_C_INPUT_06_0_GPIO_IN_SHIFT)
#define GPIO_C_INPUT_06_0_GPIO_IN_RANGE                 0:0
#define GPIO_C_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_C_INPUT_06_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_06_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_06_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_06_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_C_OUTPUT_CONTROL_06_0
#define GPIO_C_OUTPUT_CONTROL_06_0                      _MK_ADDR_CONST(0x146cc)
#define GPIO_C_OUTPUT_CONTROL_06_0_SECURE                       0x0
#define GPIO_C_OUTPUT_CONTROL_06_0_DUAL                         0x0
#define GPIO_C_OUTPUT_CONTROL_06_0_SCR                  GPIO_C_SCR_06_0
#define GPIO_C_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
#define GPIO_C_OUTPUT_CONTROL_06_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_06_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_06_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_06_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_C_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_C_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_C_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_C_OUTPUT_VALUE_06_0
#define GPIO_C_OUTPUT_VALUE_06_0                        _MK_ADDR_CONST(0x146d0)
#define GPIO_C_OUTPUT_VALUE_06_0_SECURE                         0x0
#define GPIO_C_OUTPUT_VALUE_06_0_DUAL                   0x0
#define GPIO_C_OUTPUT_VALUE_06_0_SCR                    GPIO_C_SCR_06_0
#define GPIO_C_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
#define GPIO_C_OUTPUT_VALUE_06_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_06_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_06_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_06_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_C_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_C_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_C_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_C_INTERRUPT_CLEAR_06_0
#define GPIO_C_INTERRUPT_CLEAR_06_0                     _MK_ADDR_CONST(0x146d4)
#define GPIO_C_INTERRUPT_CLEAR_06_0_SECURE                      0x0
#define GPIO_C_INTERRUPT_CLEAR_06_0_DUAL                        0x0
#define GPIO_C_INTERRUPT_CLEAR_06_0_SCR                         GPIO_C_SCR_06_0
#define GPIO_C_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
#define GPIO_C_INTERRUPT_CLEAR_06_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_06_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_06_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_06_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_C_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_C_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_C_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_C_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x146d8

// Reserved address 0x146dc

// Register GPIO_C_ENABLE_CONFIG_07_0
#define GPIO_C_ENABLE_CONFIG_07_0                       _MK_ADDR_CONST(0x146e0)
#define GPIO_C_ENABLE_CONFIG_07_0_SECURE                        0x0
#define GPIO_C_ENABLE_CONFIG_07_0_DUAL                  0x0
#define GPIO_C_ENABLE_CONFIG_07_0_SCR                   GPIO_C_SCR_07_0
#define GPIO_C_ENABLE_CONFIG_07_0_WORD_COUNT                    0x1
#define GPIO_C_ENABLE_CONFIG_07_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_07_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_C_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
#define GPIO_C_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_C_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_C_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_C_ENABLE_CONFIG_07_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
#define GPIO_C_ENABLE_CONFIG_07_0_IN_OUT_RANGE                  1:1
#define GPIO_C_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                        0x0
#define GPIO_C_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_07_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_07_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_C_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_C_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_C_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_C_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_C_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_C_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_C_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_C_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_C_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_C_DEBOUNCE_THRESHOLD_07_0
#define GPIO_C_DEBOUNCE_THRESHOLD_07_0                  _MK_ADDR_CONST(0x146e4)
#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_SECURE                   0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_DUAL                     0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_SCR                      GPIO_C_SCR_07_0
#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                       0x1
#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_C_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_C_INPUT_07_0
#define GPIO_C_INPUT_07_0                       _MK_ADDR_CONST(0x146e8)
#define GPIO_C_INPUT_07_0_SECURE                        0x0
#define GPIO_C_INPUT_07_0_DUAL                  0x0
#define GPIO_C_INPUT_07_0_SCR                   GPIO_C_SCR_07_0
#define GPIO_C_INPUT_07_0_WORD_COUNT                    0x1
#define GPIO_C_INPUT_07_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_07_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_07_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_07_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_07_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_C_INPUT_07_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_07_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_C_INPUT_07_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_C_INPUT_07_0_GPIO_IN_SHIFT)
#define GPIO_C_INPUT_07_0_GPIO_IN_RANGE                 0:0
#define GPIO_C_INPUT_07_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_C_INPUT_07_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_07_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_07_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_07_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_07_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_C_OUTPUT_CONTROL_07_0
#define GPIO_C_OUTPUT_CONTROL_07_0                      _MK_ADDR_CONST(0x146ec)
#define GPIO_C_OUTPUT_CONTROL_07_0_SECURE                       0x0
#define GPIO_C_OUTPUT_CONTROL_07_0_DUAL                         0x0
#define GPIO_C_OUTPUT_CONTROL_07_0_SCR                  GPIO_C_SCR_07_0
#define GPIO_C_OUTPUT_CONTROL_07_0_WORD_COUNT                   0x1
#define GPIO_C_OUTPUT_CONTROL_07_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_07_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_07_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_07_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_C_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_C_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_C_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_C_OUTPUT_VALUE_07_0
#define GPIO_C_OUTPUT_VALUE_07_0                        _MK_ADDR_CONST(0x146f0)
#define GPIO_C_OUTPUT_VALUE_07_0_SECURE                         0x0
#define GPIO_C_OUTPUT_VALUE_07_0_DUAL                   0x0
#define GPIO_C_OUTPUT_VALUE_07_0_SCR                    GPIO_C_SCR_07_0
#define GPIO_C_OUTPUT_VALUE_07_0_WORD_COUNT                     0x1
#define GPIO_C_OUTPUT_VALUE_07_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_07_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_07_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_07_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_C_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_C_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_C_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_C_INTERRUPT_CLEAR_07_0
#define GPIO_C_INTERRUPT_CLEAR_07_0                     _MK_ADDR_CONST(0x146f4)
#define GPIO_C_INTERRUPT_CLEAR_07_0_SECURE                      0x0
#define GPIO_C_INTERRUPT_CLEAR_07_0_DUAL                        0x0
#define GPIO_C_INTERRUPT_CLEAR_07_0_SCR                         GPIO_C_SCR_07_0
#define GPIO_C_INTERRUPT_CLEAR_07_0_WORD_COUNT                  0x1
#define GPIO_C_INTERRUPT_CLEAR_07_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_07_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_07_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_07_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_C_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_C_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_C_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_C_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x146f8

// Reserved address 0x146fc

// Register GPIO_C_INTERRUPT_STATUS_G0_0
#define GPIO_C_INTERRUPT_STATUS_G0_0                    _MK_ADDR_CONST(0x14700)
#define GPIO_C_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_C_INTERRUPT_STATUS_G0_0_DUAL                       0x0
#define GPIO_C_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_C_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_C_INTERRUPT_STATUS_G0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G0_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_C_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G0_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_C_INTERRUPT_STATUS_G0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_C_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_C_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_C_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_C_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_C_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_C_INTERRUPT_STATUS_G1_0
#define GPIO_C_INTERRUPT_STATUS_G1_0                    _MK_ADDR_CONST(0x14704)
#define GPIO_C_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_C_INTERRUPT_STATUS_G1_0_DUAL                       0x0
#define GPIO_C_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_C_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_C_INTERRUPT_STATUS_G1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G1_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_C_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G1_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_C_INTERRUPT_STATUS_G1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_C_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_C_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_C_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_C_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_C_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_C_INTERRUPT_STATUS_G2_0
#define GPIO_C_INTERRUPT_STATUS_G2_0                    _MK_ADDR_CONST(0x14708)
#define GPIO_C_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_C_INTERRUPT_STATUS_G2_0_DUAL                       0x0
#define GPIO_C_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_C_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_C_INTERRUPT_STATUS_G2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G2_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_C_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G2_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_C_INTERRUPT_STATUS_G2_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_C_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_C_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_C_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_C_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_C_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_C_INTERRUPT_STATUS_G3_0
#define GPIO_C_INTERRUPT_STATUS_G3_0                    _MK_ADDR_CONST(0x1470c)
#define GPIO_C_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_C_INTERRUPT_STATUS_G3_0_DUAL                       0x0
#define GPIO_C_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_C_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_C_INTERRUPT_STATUS_G3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G3_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_C_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G3_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_C_INTERRUPT_STATUS_G3_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_C_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_C_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_C_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_C_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_C_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_C_INTERRUPT_STATUS_G4_0
#define GPIO_C_INTERRUPT_STATUS_G4_0                    _MK_ADDR_CONST(0x14710)
#define GPIO_C_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_C_INTERRUPT_STATUS_G4_0_DUAL                       0x0
#define GPIO_C_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_C_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_C_INTERRUPT_STATUS_G4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G4_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_C_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G4_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_C_INTERRUPT_STATUS_G4_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_C_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_C_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_C_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_C_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_C_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_C_INTERRUPT_STATUS_G5_0
#define GPIO_C_INTERRUPT_STATUS_G5_0                    _MK_ADDR_CONST(0x14714)
#define GPIO_C_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_C_INTERRUPT_STATUS_G5_0_DUAL                       0x0
#define GPIO_C_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_C_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_C_INTERRUPT_STATUS_G5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G5_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_C_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G5_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_C_INTERRUPT_STATUS_G5_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_C_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_C_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_C_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_C_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_C_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_C_INTERRUPT_STATUS_G6_0
#define GPIO_C_INTERRUPT_STATUS_G6_0                    _MK_ADDR_CONST(0x14718)
#define GPIO_C_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_C_INTERRUPT_STATUS_G6_0_DUAL                       0x0
#define GPIO_C_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_C_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_C_INTERRUPT_STATUS_G6_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G6_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_C_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G6_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_C_INTERRUPT_STATUS_G6_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_C_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_C_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_C_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_C_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_C_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_C_INTERRUPT_STATUS_G7_0
#define GPIO_C_INTERRUPT_STATUS_G7_0                    _MK_ADDR_CONST(0x1471c)
#define GPIO_C_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_C_INTERRUPT_STATUS_G7_0_DUAL                       0x0
#define GPIO_C_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_C_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_C_INTERRUPT_STATUS_G7_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G7_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_C_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G7_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_C_INTERRUPT_STATUS_G7_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_C_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_C_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_C_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_C_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_C_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Reserved address 0x14720

// Reserved address 0x14724

// Reserved address 0x14728

// Reserved address 0x1472c

// Reserved address 0x14730

// Reserved address 0x14734

// Reserved address 0x14738

// Reserved address 0x1473c

// Reserved address 0x14740

// Reserved address 0x14744

// Reserved address 0x14748

// Reserved address 0x1474c

// Reserved address 0x14750

// Reserved address 0x14754

// Reserved address 0x14758

// Reserved address 0x1475c

// Reserved address 0x14760

// Reserved address 0x14764

// Reserved address 0x14768

// Reserved address 0x1476c

// Reserved address 0x14770

// Reserved address 0x14774

// Reserved address 0x14778

// Reserved address 0x1477c

// Reserved address 0x14780

// Reserved address 0x14784

// Reserved address 0x14788

// Reserved address 0x1478c

// Reserved address 0x14790

// Reserved address 0x14794

// Reserved address 0x14798

// Reserved address 0x1479c

// Reserved address 0x147a0

// Reserved address 0x147a4

// Reserved address 0x147a8

// Reserved address 0x147ac

// Reserved address 0x147b0

// Reserved address 0x147b4

// Reserved address 0x147b8

// Reserved address 0x147bc

// Reserved address 0x147c0

// Reserved address 0x147c4

// Reserved address 0x147c8

// Reserved address 0x147cc

// Reserved address 0x147d0

// Reserved address 0x147d4

// Reserved address 0x147d8

// Reserved address 0x147dc

// Reserved address 0x147e0

// Reserved address 0x147e4

// Reserved address 0x147e8

// Reserved address 0x147ec

// Reserved address 0x147f0

// Reserved address 0x147f4

// Reserved address 0x147f8

// Reserved address 0x147fc

// Register GPIO_D_ENABLE_CONFIG_00_0
#define GPIO_D_ENABLE_CONFIG_00_0                       _MK_ADDR_CONST(0x14800)
#define GPIO_D_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_D_ENABLE_CONFIG_00_0_DUAL                  0x0
#define GPIO_D_ENABLE_CONFIG_00_0_SCR                   GPIO_D_SCR_00_0
#define GPIO_D_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_D_ENABLE_CONFIG_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_D_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_D_ENABLE_CONFIG_00_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_D_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_D_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_D_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_D_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_D_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_D_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_D_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_D_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_D_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_00_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_00_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_D_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_D_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_D_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_D_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_D_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_D_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_D_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_D_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_D_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_D_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_D_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_D_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_D_DEBOUNCE_THRESHOLD_00_0
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0                  _MK_ADDR_CONST(0x14804)
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_D_SCR_00_0
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_D_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_D_INPUT_00_0
#define GPIO_D_INPUT_00_0                       _MK_ADDR_CONST(0x14808)
#define GPIO_D_INPUT_00_0_SECURE                        0x0
#define GPIO_D_INPUT_00_0_DUAL                  0x0
#define GPIO_D_INPUT_00_0_SCR                   GPIO_D_SCR_00_0
#define GPIO_D_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_D_INPUT_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_00_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_00_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_D_INPUT_00_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_00_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_D_INPUT_00_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_D_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_D_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_D_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_D_INPUT_00_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_00_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_D_OUTPUT_CONTROL_00_0
#define GPIO_D_OUTPUT_CONTROL_00_0                      _MK_ADDR_CONST(0x1480c)
#define GPIO_D_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_D_OUTPUT_CONTROL_00_0_DUAL                         0x0
#define GPIO_D_OUTPUT_CONTROL_00_0_SCR                  GPIO_D_SCR_00_0
#define GPIO_D_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_D_OUTPUT_CONTROL_00_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_00_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_00_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_00_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_D_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_D_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_D_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_D_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_D_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_D_OUTPUT_VALUE_00_0
#define GPIO_D_OUTPUT_VALUE_00_0                        _MK_ADDR_CONST(0x14810)
#define GPIO_D_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_D_OUTPUT_VALUE_00_0_DUAL                   0x0
#define GPIO_D_OUTPUT_VALUE_00_0_SCR                    GPIO_D_SCR_00_0
#define GPIO_D_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_D_OUTPUT_VALUE_00_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_00_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_00_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_00_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_D_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_D_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_D_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_D_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_D_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_D_INTERRUPT_CLEAR_00_0
#define GPIO_D_INTERRUPT_CLEAR_00_0                     _MK_ADDR_CONST(0x14814)
#define GPIO_D_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_D_INTERRUPT_CLEAR_00_0_DUAL                        0x0
#define GPIO_D_INTERRUPT_CLEAR_00_0_SCR                         GPIO_D_SCR_00_0
#define GPIO_D_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_D_INTERRUPT_CLEAR_00_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_00_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_00_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_00_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_D_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_D_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_D_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_D_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_D_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_D_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x14818

// Reserved address 0x1481c

// Register GPIO_D_ENABLE_CONFIG_01_0
#define GPIO_D_ENABLE_CONFIG_01_0                       _MK_ADDR_CONST(0x14820)
#define GPIO_D_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_D_ENABLE_CONFIG_01_0_DUAL                  0x0
#define GPIO_D_ENABLE_CONFIG_01_0_SCR                   GPIO_D_SCR_01_0
#define GPIO_D_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_D_ENABLE_CONFIG_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_D_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_D_ENABLE_CONFIG_01_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_D_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_D_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_D_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_D_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_D_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_D_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_D_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_D_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_D_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_01_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_01_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_D_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_D_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_D_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_D_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_D_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_D_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_D_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_D_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_D_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_D_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_D_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_D_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_D_DEBOUNCE_THRESHOLD_01_0
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0                  _MK_ADDR_CONST(0x14824)
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_D_SCR_01_0
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_D_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_D_INPUT_01_0
#define GPIO_D_INPUT_01_0                       _MK_ADDR_CONST(0x14828)
#define GPIO_D_INPUT_01_0_SECURE                        0x0
#define GPIO_D_INPUT_01_0_DUAL                  0x0
#define GPIO_D_INPUT_01_0_SCR                   GPIO_D_SCR_01_0
#define GPIO_D_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_D_INPUT_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_01_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_01_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_D_INPUT_01_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_01_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_D_INPUT_01_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_D_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_D_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_D_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_D_INPUT_01_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_01_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_D_OUTPUT_CONTROL_01_0
#define GPIO_D_OUTPUT_CONTROL_01_0                      _MK_ADDR_CONST(0x1482c)
#define GPIO_D_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_D_OUTPUT_CONTROL_01_0_DUAL                         0x0
#define GPIO_D_OUTPUT_CONTROL_01_0_SCR                  GPIO_D_SCR_01_0
#define GPIO_D_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_D_OUTPUT_CONTROL_01_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_01_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_01_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_01_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_D_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_D_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_D_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_D_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_D_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_D_OUTPUT_VALUE_01_0
#define GPIO_D_OUTPUT_VALUE_01_0                        _MK_ADDR_CONST(0x14830)
#define GPIO_D_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_D_OUTPUT_VALUE_01_0_DUAL                   0x0
#define GPIO_D_OUTPUT_VALUE_01_0_SCR                    GPIO_D_SCR_01_0
#define GPIO_D_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_D_OUTPUT_VALUE_01_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_01_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_01_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_01_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_D_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_D_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_D_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_D_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_D_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_D_INTERRUPT_CLEAR_01_0
#define GPIO_D_INTERRUPT_CLEAR_01_0                     _MK_ADDR_CONST(0x14834)
#define GPIO_D_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_D_INTERRUPT_CLEAR_01_0_DUAL                        0x0
#define GPIO_D_INTERRUPT_CLEAR_01_0_SCR                         GPIO_D_SCR_01_0
#define GPIO_D_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_D_INTERRUPT_CLEAR_01_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_01_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_01_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_01_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_D_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_D_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_D_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_D_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_D_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_D_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x14838

// Reserved address 0x1483c

// Register GPIO_D_ENABLE_CONFIG_02_0
#define GPIO_D_ENABLE_CONFIG_02_0                       _MK_ADDR_CONST(0x14840)
#define GPIO_D_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_D_ENABLE_CONFIG_02_0_DUAL                  0x0
#define GPIO_D_ENABLE_CONFIG_02_0_SCR                   GPIO_D_SCR_02_0
#define GPIO_D_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_D_ENABLE_CONFIG_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_D_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_D_ENABLE_CONFIG_02_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_D_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_D_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_D_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_D_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_D_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_D_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_D_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_D_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_D_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_02_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_02_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_D_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_D_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_D_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_D_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_D_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_D_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_D_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_D_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_D_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_D_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_D_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_D_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_D_DEBOUNCE_THRESHOLD_02_0
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0                  _MK_ADDR_CONST(0x14844)
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_D_SCR_02_0
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_D_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_D_INPUT_02_0
#define GPIO_D_INPUT_02_0                       _MK_ADDR_CONST(0x14848)
#define GPIO_D_INPUT_02_0_SECURE                        0x0
#define GPIO_D_INPUT_02_0_DUAL                  0x0
#define GPIO_D_INPUT_02_0_SCR                   GPIO_D_SCR_02_0
#define GPIO_D_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_D_INPUT_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_02_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_02_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_D_INPUT_02_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_02_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_D_INPUT_02_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_D_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_D_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_D_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_D_INPUT_02_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_02_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_D_OUTPUT_CONTROL_02_0
#define GPIO_D_OUTPUT_CONTROL_02_0                      _MK_ADDR_CONST(0x1484c)
#define GPIO_D_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_D_OUTPUT_CONTROL_02_0_DUAL                         0x0
#define GPIO_D_OUTPUT_CONTROL_02_0_SCR                  GPIO_D_SCR_02_0
#define GPIO_D_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_D_OUTPUT_CONTROL_02_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_02_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_02_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_02_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_D_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_D_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_D_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_D_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_D_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_D_OUTPUT_VALUE_02_0
#define GPIO_D_OUTPUT_VALUE_02_0                        _MK_ADDR_CONST(0x14850)
#define GPIO_D_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_D_OUTPUT_VALUE_02_0_DUAL                   0x0
#define GPIO_D_OUTPUT_VALUE_02_0_SCR                    GPIO_D_SCR_02_0
#define GPIO_D_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_D_OUTPUT_VALUE_02_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_02_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_02_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_02_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_D_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_D_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_D_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_D_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_D_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_D_INTERRUPT_CLEAR_02_0
#define GPIO_D_INTERRUPT_CLEAR_02_0                     _MK_ADDR_CONST(0x14854)
#define GPIO_D_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_D_INTERRUPT_CLEAR_02_0_DUAL                        0x0
#define GPIO_D_INTERRUPT_CLEAR_02_0_SCR                         GPIO_D_SCR_02_0
#define GPIO_D_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_D_INTERRUPT_CLEAR_02_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_02_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_02_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_02_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_D_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_D_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_D_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_D_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_D_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_D_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x14858

// Reserved address 0x1485c

// Register GPIO_D_ENABLE_CONFIG_03_0
#define GPIO_D_ENABLE_CONFIG_03_0                       _MK_ADDR_CONST(0x14860)
#define GPIO_D_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_D_ENABLE_CONFIG_03_0_DUAL                  0x0
#define GPIO_D_ENABLE_CONFIG_03_0_SCR                   GPIO_D_SCR_03_0
#define GPIO_D_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_D_ENABLE_CONFIG_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_D_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_D_ENABLE_CONFIG_03_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_D_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_D_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_D_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_D_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_D_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_D_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_D_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_D_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_D_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_03_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_03_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_D_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_D_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_D_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_D_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_D_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_D_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_D_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_D_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_D_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_D_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_D_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_D_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_D_DEBOUNCE_THRESHOLD_03_0
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0                  _MK_ADDR_CONST(0x14864)
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_D_SCR_03_0
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_D_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_D_INPUT_03_0
#define GPIO_D_INPUT_03_0                       _MK_ADDR_CONST(0x14868)
#define GPIO_D_INPUT_03_0_SECURE                        0x0
#define GPIO_D_INPUT_03_0_DUAL                  0x0
#define GPIO_D_INPUT_03_0_SCR                   GPIO_D_SCR_03_0
#define GPIO_D_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_D_INPUT_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_03_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_03_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_D_INPUT_03_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_03_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_D_INPUT_03_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_D_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_D_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_D_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_D_INPUT_03_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_03_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_D_OUTPUT_CONTROL_03_0
#define GPIO_D_OUTPUT_CONTROL_03_0                      _MK_ADDR_CONST(0x1486c)
#define GPIO_D_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_D_OUTPUT_CONTROL_03_0_DUAL                         0x0
#define GPIO_D_OUTPUT_CONTROL_03_0_SCR                  GPIO_D_SCR_03_0
#define GPIO_D_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_D_OUTPUT_CONTROL_03_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_03_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_03_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_03_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_D_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_D_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_D_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_D_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_D_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_D_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_D_OUTPUT_VALUE_03_0
#define GPIO_D_OUTPUT_VALUE_03_0                        _MK_ADDR_CONST(0x14870)
#define GPIO_D_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_D_OUTPUT_VALUE_03_0_DUAL                   0x0
#define GPIO_D_OUTPUT_VALUE_03_0_SCR                    GPIO_D_SCR_03_0
#define GPIO_D_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_D_OUTPUT_VALUE_03_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_03_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_03_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_03_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_D_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_D_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_D_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_D_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_D_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_D_INTERRUPT_CLEAR_03_0
#define GPIO_D_INTERRUPT_CLEAR_03_0                     _MK_ADDR_CONST(0x14874)
#define GPIO_D_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_D_INTERRUPT_CLEAR_03_0_DUAL                        0x0
#define GPIO_D_INTERRUPT_CLEAR_03_0_SCR                         GPIO_D_SCR_03_0
#define GPIO_D_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_D_INTERRUPT_CLEAR_03_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_03_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_03_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_03_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_D_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_D_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_D_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_D_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_D_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_D_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x14878

// Reserved address 0x1487c

// Reserved address 0x14880

// Reserved address 0x14884

// Reserved address 0x14888

// Reserved address 0x1488c

// Reserved address 0x14890

// Reserved address 0x14894

// Reserved address 0x14898

// Reserved address 0x1489c

// Reserved address 0x148a0

// Reserved address 0x148a4

// Reserved address 0x148a8

// Reserved address 0x148ac

// Reserved address 0x148b0

// Reserved address 0x148b4

// Reserved address 0x148b8

// Reserved address 0x148bc

// Reserved address 0x148c0

// Reserved address 0x148c4

// Reserved address 0x148c8

// Reserved address 0x148cc

// Reserved address 0x148d0

// Reserved address 0x148d4

// Reserved address 0x148d8

// Reserved address 0x148dc

// Reserved address 0x148e0

// Reserved address 0x148e4

// Reserved address 0x148e8

// Reserved address 0x148ec

// Reserved address 0x148f0

// Reserved address 0x148f4

// Reserved address 0x148f8

// Reserved address 0x148fc

// Register GPIO_D_INTERRUPT_STATUS_G0_0
#define GPIO_D_INTERRUPT_STATUS_G0_0                    _MK_ADDR_CONST(0x14900)
#define GPIO_D_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_D_INTERRUPT_STATUS_G0_0_DUAL                       0x0
#define GPIO_D_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_D_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_D_INTERRUPT_STATUS_G0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G0_0_RESET_MASK                         _MK_MASK_CONST(0xf)
#define GPIO_D_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G0_0_READ_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_D_INTERRUPT_STATUS_G0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_D_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xf, GPIO_D_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_D_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
#define GPIO_D_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_D_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define GPIO_D_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_D_INTERRUPT_STATUS_G1_0
#define GPIO_D_INTERRUPT_STATUS_G1_0                    _MK_ADDR_CONST(0x14904)
#define GPIO_D_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_D_INTERRUPT_STATUS_G1_0_DUAL                       0x0
#define GPIO_D_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_D_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_D_INTERRUPT_STATUS_G1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G1_0_RESET_MASK                         _MK_MASK_CONST(0xf)
#define GPIO_D_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G1_0_READ_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_D_INTERRUPT_STATUS_G1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_D_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xf, GPIO_D_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_D_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
#define GPIO_D_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_D_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define GPIO_D_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_D_INTERRUPT_STATUS_G2_0
#define GPIO_D_INTERRUPT_STATUS_G2_0                    _MK_ADDR_CONST(0x14908)
#define GPIO_D_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_D_INTERRUPT_STATUS_G2_0_DUAL                       0x0
#define GPIO_D_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_D_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_D_INTERRUPT_STATUS_G2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G2_0_RESET_MASK                         _MK_MASK_CONST(0xf)
#define GPIO_D_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G2_0_READ_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_D_INTERRUPT_STATUS_G2_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_D_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xf, GPIO_D_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_D_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
#define GPIO_D_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_D_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define GPIO_D_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_D_INTERRUPT_STATUS_G3_0
#define GPIO_D_INTERRUPT_STATUS_G3_0                    _MK_ADDR_CONST(0x1490c)
#define GPIO_D_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_D_INTERRUPT_STATUS_G3_0_DUAL                       0x0
#define GPIO_D_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_D_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_D_INTERRUPT_STATUS_G3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G3_0_RESET_MASK                         _MK_MASK_CONST(0xf)
#define GPIO_D_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G3_0_READ_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_D_INTERRUPT_STATUS_G3_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_D_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xf, GPIO_D_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_D_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
#define GPIO_D_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_D_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define GPIO_D_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_D_INTERRUPT_STATUS_G4_0
#define GPIO_D_INTERRUPT_STATUS_G4_0                    _MK_ADDR_CONST(0x14910)
#define GPIO_D_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_D_INTERRUPT_STATUS_G4_0_DUAL                       0x0
#define GPIO_D_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_D_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_D_INTERRUPT_STATUS_G4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G4_0_RESET_MASK                         _MK_MASK_CONST(0xf)
#define GPIO_D_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G4_0_READ_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_D_INTERRUPT_STATUS_G4_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_D_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xf, GPIO_D_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_D_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
#define GPIO_D_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_D_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define GPIO_D_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_D_INTERRUPT_STATUS_G5_0
#define GPIO_D_INTERRUPT_STATUS_G5_0                    _MK_ADDR_CONST(0x14914)
#define GPIO_D_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_D_INTERRUPT_STATUS_G5_0_DUAL                       0x0
#define GPIO_D_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_D_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_D_INTERRUPT_STATUS_G5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G5_0_RESET_MASK                         _MK_MASK_CONST(0xf)
#define GPIO_D_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G5_0_READ_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_D_INTERRUPT_STATUS_G5_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_D_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xf, GPIO_D_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_D_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
#define GPIO_D_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_D_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define GPIO_D_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_D_INTERRUPT_STATUS_G6_0
#define GPIO_D_INTERRUPT_STATUS_G6_0                    _MK_ADDR_CONST(0x14918)
#define GPIO_D_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_D_INTERRUPT_STATUS_G6_0_DUAL                       0x0
#define GPIO_D_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_D_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_D_INTERRUPT_STATUS_G6_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G6_0_RESET_MASK                         _MK_MASK_CONST(0xf)
#define GPIO_D_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G6_0_READ_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_D_INTERRUPT_STATUS_G6_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_D_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xf, GPIO_D_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_D_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
#define GPIO_D_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_D_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define GPIO_D_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_D_INTERRUPT_STATUS_G7_0
#define GPIO_D_INTERRUPT_STATUS_G7_0                    _MK_ADDR_CONST(0x1491c)
#define GPIO_D_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_D_INTERRUPT_STATUS_G7_0_DUAL                       0x0
#define GPIO_D_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_D_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_D_INTERRUPT_STATUS_G7_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G7_0_RESET_MASK                         _MK_MASK_CONST(0xf)
#define GPIO_D_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G7_0_READ_MASK                  _MK_MASK_CONST(0xf)
#define GPIO_D_INTERRUPT_STATUS_G7_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_D_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xf, GPIO_D_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_D_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
#define GPIO_D_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_D_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define GPIO_D_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Reserved address 0x14920

// Reserved address 0x14924

// Reserved address 0x14928

// Reserved address 0x1492c

// Reserved address 0x14930

// Reserved address 0x14934

// Reserved address 0x14938

// Reserved address 0x1493c

// Reserved address 0x14940

// Reserved address 0x14944

// Reserved address 0x14948

// Reserved address 0x1494c

// Reserved address 0x14950

// Reserved address 0x14954

// Reserved address 0x14958

// Reserved address 0x1495c

// Reserved address 0x14960

// Reserved address 0x14964

// Reserved address 0x14968

// Reserved address 0x1496c

// Reserved address 0x14970

// Reserved address 0x14974

// Reserved address 0x14978

// Reserved address 0x1497c

// Reserved address 0x14980

// Reserved address 0x14984

// Reserved address 0x14988

// Reserved address 0x1498c

// Reserved address 0x14990

// Reserved address 0x14994

// Reserved address 0x14998

// Reserved address 0x1499c

// Reserved address 0x149a0

// Reserved address 0x149a4

// Reserved address 0x149a8

// Reserved address 0x149ac

// Reserved address 0x149b0

// Reserved address 0x149b4

// Reserved address 0x149b8

// Reserved address 0x149bc

// Reserved address 0x149c0

// Reserved address 0x149c4

// Reserved address 0x149c8

// Reserved address 0x149cc

// Reserved address 0x149d0

// Reserved address 0x149d4

// Reserved address 0x149d8

// Reserved address 0x149dc

// Reserved address 0x149e0

// Reserved address 0x149e4

// Reserved address 0x149e8

// Reserved address 0x149ec

// Reserved address 0x149f0

// Reserved address 0x149f4

// Reserved address 0x149f8

// Reserved address 0x149fc

// Register GPIO_E_ENABLE_CONFIG_00_0
#define GPIO_E_ENABLE_CONFIG_00_0                       _MK_ADDR_CONST(0x14a00)
#define GPIO_E_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_E_ENABLE_CONFIG_00_0_DUAL                  0x0
#define GPIO_E_ENABLE_CONFIG_00_0_SCR                   GPIO_E_SCR_00_0
#define GPIO_E_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_E_ENABLE_CONFIG_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_00_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_E_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_E_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_E_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_E_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_E_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_E_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_E_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_E_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_00_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_00_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_E_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_E_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_E_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_E_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_E_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_E_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_E_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_E_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_E_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_E_DEBOUNCE_THRESHOLD_00_0
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0                  _MK_ADDR_CONST(0x14a04)
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_E_SCR_00_0
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_E_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_E_INPUT_00_0
#define GPIO_E_INPUT_00_0                       _MK_ADDR_CONST(0x14a08)
#define GPIO_E_INPUT_00_0_SECURE                        0x0
#define GPIO_E_INPUT_00_0_DUAL                  0x0
#define GPIO_E_INPUT_00_0_SCR                   GPIO_E_SCR_00_0
#define GPIO_E_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_E_INPUT_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_00_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_00_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_E_INPUT_00_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_00_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_E_INPUT_00_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_E_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_E_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_E_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_E_INPUT_00_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_00_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_E_OUTPUT_CONTROL_00_0
#define GPIO_E_OUTPUT_CONTROL_00_0                      _MK_ADDR_CONST(0x14a0c)
#define GPIO_E_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_E_OUTPUT_CONTROL_00_0_DUAL                         0x0
#define GPIO_E_OUTPUT_CONTROL_00_0_SCR                  GPIO_E_SCR_00_0
#define GPIO_E_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_E_OUTPUT_CONTROL_00_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_00_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_00_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_00_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_E_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_E_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_E_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_E_OUTPUT_VALUE_00_0
#define GPIO_E_OUTPUT_VALUE_00_0                        _MK_ADDR_CONST(0x14a10)
#define GPIO_E_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_E_OUTPUT_VALUE_00_0_DUAL                   0x0
#define GPIO_E_OUTPUT_VALUE_00_0_SCR                    GPIO_E_SCR_00_0
#define GPIO_E_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_E_OUTPUT_VALUE_00_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_00_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_00_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_00_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_E_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_E_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_E_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_E_INTERRUPT_CLEAR_00_0
#define GPIO_E_INTERRUPT_CLEAR_00_0                     _MK_ADDR_CONST(0x14a14)
#define GPIO_E_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_E_INTERRUPT_CLEAR_00_0_DUAL                        0x0
#define GPIO_E_INTERRUPT_CLEAR_00_0_SCR                         GPIO_E_SCR_00_0
#define GPIO_E_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_E_INTERRUPT_CLEAR_00_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_00_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_00_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_00_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_E_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_E_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_E_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_E_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x14a18

// Reserved address 0x14a1c

// Register GPIO_E_ENABLE_CONFIG_01_0
#define GPIO_E_ENABLE_CONFIG_01_0                       _MK_ADDR_CONST(0x14a20)
#define GPIO_E_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_E_ENABLE_CONFIG_01_0_DUAL                  0x0
#define GPIO_E_ENABLE_CONFIG_01_0_SCR                   GPIO_E_SCR_01_0
#define GPIO_E_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_E_ENABLE_CONFIG_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_01_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_E_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_E_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_E_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_E_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_E_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_E_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_E_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_E_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_01_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_01_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_E_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_E_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_E_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_E_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_E_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_E_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_E_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_E_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_E_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_E_DEBOUNCE_THRESHOLD_01_0
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0                  _MK_ADDR_CONST(0x14a24)
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_E_SCR_01_0
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_E_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_E_INPUT_01_0
#define GPIO_E_INPUT_01_0                       _MK_ADDR_CONST(0x14a28)
#define GPIO_E_INPUT_01_0_SECURE                        0x0
#define GPIO_E_INPUT_01_0_DUAL                  0x0
#define GPIO_E_INPUT_01_0_SCR                   GPIO_E_SCR_01_0
#define GPIO_E_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_E_INPUT_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_01_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_01_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_E_INPUT_01_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_01_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_E_INPUT_01_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_E_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_E_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_E_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_E_INPUT_01_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_01_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_E_OUTPUT_CONTROL_01_0
#define GPIO_E_OUTPUT_CONTROL_01_0                      _MK_ADDR_CONST(0x14a2c)
#define GPIO_E_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_E_OUTPUT_CONTROL_01_0_DUAL                         0x0
#define GPIO_E_OUTPUT_CONTROL_01_0_SCR                  GPIO_E_SCR_01_0
#define GPIO_E_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_E_OUTPUT_CONTROL_01_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_01_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_01_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_01_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_E_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_E_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_E_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_E_OUTPUT_VALUE_01_0
#define GPIO_E_OUTPUT_VALUE_01_0                        _MK_ADDR_CONST(0x14a30)
#define GPIO_E_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_E_OUTPUT_VALUE_01_0_DUAL                   0x0
#define GPIO_E_OUTPUT_VALUE_01_0_SCR                    GPIO_E_SCR_01_0
#define GPIO_E_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_E_OUTPUT_VALUE_01_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_01_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_01_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_01_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_E_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_E_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_E_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_E_INTERRUPT_CLEAR_01_0
#define GPIO_E_INTERRUPT_CLEAR_01_0                     _MK_ADDR_CONST(0x14a34)
#define GPIO_E_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_E_INTERRUPT_CLEAR_01_0_DUAL                        0x0
#define GPIO_E_INTERRUPT_CLEAR_01_0_SCR                         GPIO_E_SCR_01_0
#define GPIO_E_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_E_INTERRUPT_CLEAR_01_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_01_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_01_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_01_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_E_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_E_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_E_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_E_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x14a38

// Reserved address 0x14a3c

// Register GPIO_E_ENABLE_CONFIG_02_0
#define GPIO_E_ENABLE_CONFIG_02_0                       _MK_ADDR_CONST(0x14a40)
#define GPIO_E_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_E_ENABLE_CONFIG_02_0_DUAL                  0x0
#define GPIO_E_ENABLE_CONFIG_02_0_SCR                   GPIO_E_SCR_02_0
#define GPIO_E_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_E_ENABLE_CONFIG_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_02_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_E_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_E_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_E_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_E_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_E_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_E_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_E_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_E_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_02_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_02_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_E_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_E_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_E_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_E_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_E_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_E_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_E_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_E_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_E_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_E_DEBOUNCE_THRESHOLD_02_0
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0                  _MK_ADDR_CONST(0x14a44)
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_E_SCR_02_0
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_E_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_E_INPUT_02_0
#define GPIO_E_INPUT_02_0                       _MK_ADDR_CONST(0x14a48)
#define GPIO_E_INPUT_02_0_SECURE                        0x0
#define GPIO_E_INPUT_02_0_DUAL                  0x0
#define GPIO_E_INPUT_02_0_SCR                   GPIO_E_SCR_02_0
#define GPIO_E_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_E_INPUT_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_02_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_02_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_E_INPUT_02_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_02_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_E_INPUT_02_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_E_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_E_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_E_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_E_INPUT_02_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_02_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_E_OUTPUT_CONTROL_02_0
#define GPIO_E_OUTPUT_CONTROL_02_0                      _MK_ADDR_CONST(0x14a4c)
#define GPIO_E_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_E_OUTPUT_CONTROL_02_0_DUAL                         0x0
#define GPIO_E_OUTPUT_CONTROL_02_0_SCR                  GPIO_E_SCR_02_0
#define GPIO_E_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_E_OUTPUT_CONTROL_02_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_02_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_02_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_02_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_E_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_E_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_E_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_E_OUTPUT_VALUE_02_0
#define GPIO_E_OUTPUT_VALUE_02_0                        _MK_ADDR_CONST(0x14a50)
#define GPIO_E_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_E_OUTPUT_VALUE_02_0_DUAL                   0x0
#define GPIO_E_OUTPUT_VALUE_02_0_SCR                    GPIO_E_SCR_02_0
#define GPIO_E_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_E_OUTPUT_VALUE_02_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_02_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_02_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_02_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_E_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_E_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_E_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_E_INTERRUPT_CLEAR_02_0
#define GPIO_E_INTERRUPT_CLEAR_02_0                     _MK_ADDR_CONST(0x14a54)
#define GPIO_E_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_E_INTERRUPT_CLEAR_02_0_DUAL                        0x0
#define GPIO_E_INTERRUPT_CLEAR_02_0_SCR                         GPIO_E_SCR_02_0
#define GPIO_E_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_E_INTERRUPT_CLEAR_02_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_02_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_02_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_02_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_E_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_E_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_E_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_E_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x14a58

// Reserved address 0x14a5c

// Register GPIO_E_ENABLE_CONFIG_03_0
#define GPIO_E_ENABLE_CONFIG_03_0                       _MK_ADDR_CONST(0x14a60)
#define GPIO_E_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_E_ENABLE_CONFIG_03_0_DUAL                  0x0
#define GPIO_E_ENABLE_CONFIG_03_0_SCR                   GPIO_E_SCR_03_0
#define GPIO_E_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_E_ENABLE_CONFIG_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_03_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_E_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_E_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_E_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_E_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_E_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_E_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_E_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_E_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_03_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_03_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_E_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_E_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_E_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_E_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_E_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_E_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_E_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_E_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_E_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_E_DEBOUNCE_THRESHOLD_03_0
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0                  _MK_ADDR_CONST(0x14a64)
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_E_SCR_03_0
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_E_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_E_INPUT_03_0
#define GPIO_E_INPUT_03_0                       _MK_ADDR_CONST(0x14a68)
#define GPIO_E_INPUT_03_0_SECURE                        0x0
#define GPIO_E_INPUT_03_0_DUAL                  0x0
#define GPIO_E_INPUT_03_0_SCR                   GPIO_E_SCR_03_0
#define GPIO_E_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_E_INPUT_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_03_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_03_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_E_INPUT_03_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_03_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_E_INPUT_03_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_E_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_E_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_E_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_E_INPUT_03_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_03_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_E_OUTPUT_CONTROL_03_0
#define GPIO_E_OUTPUT_CONTROL_03_0                      _MK_ADDR_CONST(0x14a6c)
#define GPIO_E_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_E_OUTPUT_CONTROL_03_0_DUAL                         0x0
#define GPIO_E_OUTPUT_CONTROL_03_0_SCR                  GPIO_E_SCR_03_0
#define GPIO_E_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_E_OUTPUT_CONTROL_03_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_03_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_03_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_03_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_E_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_E_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_E_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_E_OUTPUT_VALUE_03_0
#define GPIO_E_OUTPUT_VALUE_03_0                        _MK_ADDR_CONST(0x14a70)
#define GPIO_E_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_E_OUTPUT_VALUE_03_0_DUAL                   0x0
#define GPIO_E_OUTPUT_VALUE_03_0_SCR                    GPIO_E_SCR_03_0
#define GPIO_E_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_E_OUTPUT_VALUE_03_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_03_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_03_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_03_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_E_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_E_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_E_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_E_INTERRUPT_CLEAR_03_0
#define GPIO_E_INTERRUPT_CLEAR_03_0                     _MK_ADDR_CONST(0x14a74)
#define GPIO_E_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_E_INTERRUPT_CLEAR_03_0_DUAL                        0x0
#define GPIO_E_INTERRUPT_CLEAR_03_0_SCR                         GPIO_E_SCR_03_0
#define GPIO_E_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_E_INTERRUPT_CLEAR_03_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_03_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_03_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_03_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_E_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_E_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_E_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_E_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x14a78

// Reserved address 0x14a7c

// Register GPIO_E_ENABLE_CONFIG_04_0
#define GPIO_E_ENABLE_CONFIG_04_0                       _MK_ADDR_CONST(0x14a80)
#define GPIO_E_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_E_ENABLE_CONFIG_04_0_DUAL                  0x0
#define GPIO_E_ENABLE_CONFIG_04_0_SCR                   GPIO_E_SCR_04_0
#define GPIO_E_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_E_ENABLE_CONFIG_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_04_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_E_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_E_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_E_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_E_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_E_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_E_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_E_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_E_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_04_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_04_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_E_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_E_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_E_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_E_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_E_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_E_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_E_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_E_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_E_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_E_DEBOUNCE_THRESHOLD_04_0
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0                  _MK_ADDR_CONST(0x14a84)
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_DUAL                     0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_E_SCR_04_0
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_E_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_E_INPUT_04_0
#define GPIO_E_INPUT_04_0                       _MK_ADDR_CONST(0x14a88)
#define GPIO_E_INPUT_04_0_SECURE                        0x0
#define GPIO_E_INPUT_04_0_DUAL                  0x0
#define GPIO_E_INPUT_04_0_SCR                   GPIO_E_SCR_04_0
#define GPIO_E_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_E_INPUT_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_04_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_04_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_E_INPUT_04_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_04_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_E_INPUT_04_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_E_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_E_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_E_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_E_INPUT_04_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_04_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_E_OUTPUT_CONTROL_04_0
#define GPIO_E_OUTPUT_CONTROL_04_0                      _MK_ADDR_CONST(0x14a8c)
#define GPIO_E_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_E_OUTPUT_CONTROL_04_0_DUAL                         0x0
#define GPIO_E_OUTPUT_CONTROL_04_0_SCR                  GPIO_E_SCR_04_0
#define GPIO_E_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_E_OUTPUT_CONTROL_04_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_04_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_04_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_04_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_E_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_E_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_E_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_E_OUTPUT_VALUE_04_0
#define GPIO_E_OUTPUT_VALUE_04_0                        _MK_ADDR_CONST(0x14a90)
#define GPIO_E_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_E_OUTPUT_VALUE_04_0_DUAL                   0x0
#define GPIO_E_OUTPUT_VALUE_04_0_SCR                    GPIO_E_SCR_04_0
#define GPIO_E_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_E_OUTPUT_VALUE_04_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_04_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_04_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_04_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_E_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_E_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_E_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_E_INTERRUPT_CLEAR_04_0
#define GPIO_E_INTERRUPT_CLEAR_04_0                     _MK_ADDR_CONST(0x14a94)
#define GPIO_E_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_E_INTERRUPT_CLEAR_04_0_DUAL                        0x0
#define GPIO_E_INTERRUPT_CLEAR_04_0_SCR                         GPIO_E_SCR_04_0
#define GPIO_E_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_E_INTERRUPT_CLEAR_04_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_04_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_04_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_04_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_E_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_E_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_E_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_E_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x14a98

// Reserved address 0x14a9c

// Register GPIO_E_ENABLE_CONFIG_05_0
#define GPIO_E_ENABLE_CONFIG_05_0                       _MK_ADDR_CONST(0x14aa0)
#define GPIO_E_ENABLE_CONFIG_05_0_SECURE                        0x0
#define GPIO_E_ENABLE_CONFIG_05_0_DUAL                  0x0
#define GPIO_E_ENABLE_CONFIG_05_0_SCR                   GPIO_E_SCR_05_0
#define GPIO_E_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
#define GPIO_E_ENABLE_CONFIG_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_05_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_E_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_E_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_E_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_E_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_E_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_E_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
#define GPIO_E_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
#define GPIO_E_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_05_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_05_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_E_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_E_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_E_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_E_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_E_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_E_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_E_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_E_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_E_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_E_DEBOUNCE_THRESHOLD_05_0
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0                  _MK_ADDR_CONST(0x14aa4)
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_DUAL                     0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_E_SCR_05_0
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_E_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_E_INPUT_05_0
#define GPIO_E_INPUT_05_0                       _MK_ADDR_CONST(0x14aa8)
#define GPIO_E_INPUT_05_0_SECURE                        0x0
#define GPIO_E_INPUT_05_0_DUAL                  0x0
#define GPIO_E_INPUT_05_0_SCR                   GPIO_E_SCR_05_0
#define GPIO_E_INPUT_05_0_WORD_COUNT                    0x1
#define GPIO_E_INPUT_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_05_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_05_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_E_INPUT_05_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_05_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_E_INPUT_05_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_E_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_E_INPUT_05_0_GPIO_IN_RANGE                 0:0
#define GPIO_E_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_E_INPUT_05_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_05_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_E_OUTPUT_CONTROL_05_0
#define GPIO_E_OUTPUT_CONTROL_05_0                      _MK_ADDR_CONST(0x14aac)
#define GPIO_E_OUTPUT_CONTROL_05_0_SECURE                       0x0
#define GPIO_E_OUTPUT_CONTROL_05_0_DUAL                         0x0
#define GPIO_E_OUTPUT_CONTROL_05_0_SCR                  GPIO_E_SCR_05_0
#define GPIO_E_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
#define GPIO_E_OUTPUT_CONTROL_05_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_05_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_05_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_05_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_E_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_E_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_E_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_E_OUTPUT_VALUE_05_0
#define GPIO_E_OUTPUT_VALUE_05_0                        _MK_ADDR_CONST(0x14ab0)
#define GPIO_E_OUTPUT_VALUE_05_0_SECURE                         0x0
#define GPIO_E_OUTPUT_VALUE_05_0_DUAL                   0x0
#define GPIO_E_OUTPUT_VALUE_05_0_SCR                    GPIO_E_SCR_05_0
#define GPIO_E_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
#define GPIO_E_OUTPUT_VALUE_05_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_05_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_05_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_05_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_E_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_E_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_E_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_E_INTERRUPT_CLEAR_05_0
#define GPIO_E_INTERRUPT_CLEAR_05_0                     _MK_ADDR_CONST(0x14ab4)
#define GPIO_E_INTERRUPT_CLEAR_05_0_SECURE                      0x0
#define GPIO_E_INTERRUPT_CLEAR_05_0_DUAL                        0x0
#define GPIO_E_INTERRUPT_CLEAR_05_0_SCR                         GPIO_E_SCR_05_0
#define GPIO_E_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
#define GPIO_E_INTERRUPT_CLEAR_05_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_05_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_05_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_05_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_E_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_E_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_E_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_E_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x14ab8

// Reserved address 0x14abc

// Register GPIO_E_ENABLE_CONFIG_06_0
#define GPIO_E_ENABLE_CONFIG_06_0                       _MK_ADDR_CONST(0x14ac0)
#define GPIO_E_ENABLE_CONFIG_06_0_SECURE                        0x0
#define GPIO_E_ENABLE_CONFIG_06_0_DUAL                  0x0
#define GPIO_E_ENABLE_CONFIG_06_0_SCR                   GPIO_E_SCR_06_0
#define GPIO_E_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
#define GPIO_E_ENABLE_CONFIG_06_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_06_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_E_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
#define GPIO_E_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_E_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_E_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_E_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
#define GPIO_E_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
#define GPIO_E_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
#define GPIO_E_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_06_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_06_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_E_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_E_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_E_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_E_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_E_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_E_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_E_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_E_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_E_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_E_DEBOUNCE_THRESHOLD_06_0
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0                  _MK_ADDR_CONST(0x14ac4)
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_DUAL                     0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_E_SCR_06_0
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_E_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_E_INPUT_06_0
#define GPIO_E_INPUT_06_0                       _MK_ADDR_CONST(0x14ac8)
#define GPIO_E_INPUT_06_0_SECURE                        0x0
#define GPIO_E_INPUT_06_0_DUAL                  0x0
#define GPIO_E_INPUT_06_0_SCR                   GPIO_E_SCR_06_0
#define GPIO_E_INPUT_06_0_WORD_COUNT                    0x1
#define GPIO_E_INPUT_06_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_06_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_06_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_06_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_06_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_E_INPUT_06_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_06_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_E_INPUT_06_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_E_INPUT_06_0_GPIO_IN_SHIFT)
#define GPIO_E_INPUT_06_0_GPIO_IN_RANGE                 0:0
#define GPIO_E_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_E_INPUT_06_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_06_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_06_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_06_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_E_OUTPUT_CONTROL_06_0
#define GPIO_E_OUTPUT_CONTROL_06_0                      _MK_ADDR_CONST(0x14acc)
#define GPIO_E_OUTPUT_CONTROL_06_0_SECURE                       0x0
#define GPIO_E_OUTPUT_CONTROL_06_0_DUAL                         0x0
#define GPIO_E_OUTPUT_CONTROL_06_0_SCR                  GPIO_E_SCR_06_0
#define GPIO_E_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
#define GPIO_E_OUTPUT_CONTROL_06_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_06_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_06_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_06_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_E_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_E_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_E_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_E_OUTPUT_VALUE_06_0
#define GPIO_E_OUTPUT_VALUE_06_0                        _MK_ADDR_CONST(0x14ad0)
#define GPIO_E_OUTPUT_VALUE_06_0_SECURE                         0x0
#define GPIO_E_OUTPUT_VALUE_06_0_DUAL                   0x0
#define GPIO_E_OUTPUT_VALUE_06_0_SCR                    GPIO_E_SCR_06_0
#define GPIO_E_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
#define GPIO_E_OUTPUT_VALUE_06_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_06_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_06_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_06_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_E_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_E_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_E_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_E_INTERRUPT_CLEAR_06_0
#define GPIO_E_INTERRUPT_CLEAR_06_0                     _MK_ADDR_CONST(0x14ad4)
#define GPIO_E_INTERRUPT_CLEAR_06_0_SECURE                      0x0
#define GPIO_E_INTERRUPT_CLEAR_06_0_DUAL                        0x0
#define GPIO_E_INTERRUPT_CLEAR_06_0_SCR                         GPIO_E_SCR_06_0
#define GPIO_E_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
#define GPIO_E_INTERRUPT_CLEAR_06_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_06_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_06_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_06_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_E_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_E_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_E_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_E_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x14ad8

// Reserved address 0x14adc

// Register GPIO_E_ENABLE_CONFIG_07_0
#define GPIO_E_ENABLE_CONFIG_07_0                       _MK_ADDR_CONST(0x14ae0)
#define GPIO_E_ENABLE_CONFIG_07_0_SECURE                        0x0
#define GPIO_E_ENABLE_CONFIG_07_0_DUAL                  0x0
#define GPIO_E_ENABLE_CONFIG_07_0_SCR                   GPIO_E_SCR_07_0
#define GPIO_E_ENABLE_CONFIG_07_0_WORD_COUNT                    0x1
#define GPIO_E_ENABLE_CONFIG_07_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_07_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_E_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
#define GPIO_E_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_E_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_E_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_E_ENABLE_CONFIG_07_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
#define GPIO_E_ENABLE_CONFIG_07_0_IN_OUT_RANGE                  1:1
#define GPIO_E_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                        0x0
#define GPIO_E_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_07_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_07_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_E_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_E_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_E_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_E_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_E_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_E_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_E_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_E_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_E_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_E_DEBOUNCE_THRESHOLD_07_0
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0                  _MK_ADDR_CONST(0x14ae4)
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_SECURE                   0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_DUAL                     0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_SCR                      GPIO_E_SCR_07_0
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                       0x1
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_E_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_E_INPUT_07_0
#define GPIO_E_INPUT_07_0                       _MK_ADDR_CONST(0x14ae8)
#define GPIO_E_INPUT_07_0_SECURE                        0x0
#define GPIO_E_INPUT_07_0_DUAL                  0x0
#define GPIO_E_INPUT_07_0_SCR                   GPIO_E_SCR_07_0
#define GPIO_E_INPUT_07_0_WORD_COUNT                    0x1
#define GPIO_E_INPUT_07_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_07_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_07_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_07_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_07_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_E_INPUT_07_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_07_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_E_INPUT_07_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_E_INPUT_07_0_GPIO_IN_SHIFT)
#define GPIO_E_INPUT_07_0_GPIO_IN_RANGE                 0:0
#define GPIO_E_INPUT_07_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_E_INPUT_07_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_07_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_07_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_07_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_07_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_E_OUTPUT_CONTROL_07_0
#define GPIO_E_OUTPUT_CONTROL_07_0                      _MK_ADDR_CONST(0x14aec)
#define GPIO_E_OUTPUT_CONTROL_07_0_SECURE                       0x0
#define GPIO_E_OUTPUT_CONTROL_07_0_DUAL                         0x0
#define GPIO_E_OUTPUT_CONTROL_07_0_SCR                  GPIO_E_SCR_07_0
#define GPIO_E_OUTPUT_CONTROL_07_0_WORD_COUNT                   0x1
#define GPIO_E_OUTPUT_CONTROL_07_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_07_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_07_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_07_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_E_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_E_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_E_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_E_OUTPUT_VALUE_07_0
#define GPIO_E_OUTPUT_VALUE_07_0                        _MK_ADDR_CONST(0x14af0)
#define GPIO_E_OUTPUT_VALUE_07_0_SECURE                         0x0
#define GPIO_E_OUTPUT_VALUE_07_0_DUAL                   0x0
#define GPIO_E_OUTPUT_VALUE_07_0_SCR                    GPIO_E_SCR_07_0
#define GPIO_E_OUTPUT_VALUE_07_0_WORD_COUNT                     0x1
#define GPIO_E_OUTPUT_VALUE_07_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_07_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_07_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_07_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_E_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_E_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_E_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_E_INTERRUPT_CLEAR_07_0
#define GPIO_E_INTERRUPT_CLEAR_07_0                     _MK_ADDR_CONST(0x14af4)
#define GPIO_E_INTERRUPT_CLEAR_07_0_SECURE                      0x0
#define GPIO_E_INTERRUPT_CLEAR_07_0_DUAL                        0x0
#define GPIO_E_INTERRUPT_CLEAR_07_0_SCR                         GPIO_E_SCR_07_0
#define GPIO_E_INTERRUPT_CLEAR_07_0_WORD_COUNT                  0x1
#define GPIO_E_INTERRUPT_CLEAR_07_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_07_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_07_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_07_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_E_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_E_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_E_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_E_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x14af8

// Reserved address 0x14afc

// Register GPIO_E_INTERRUPT_STATUS_G0_0
#define GPIO_E_INTERRUPT_STATUS_G0_0                    _MK_ADDR_CONST(0x14b00)
#define GPIO_E_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_E_INTERRUPT_STATUS_G0_0_DUAL                       0x0
#define GPIO_E_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_E_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_E_INTERRUPT_STATUS_G0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G0_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G0_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_E_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_E_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_E_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_E_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_E_INTERRUPT_STATUS_G1_0
#define GPIO_E_INTERRUPT_STATUS_G1_0                    _MK_ADDR_CONST(0x14b04)
#define GPIO_E_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_E_INTERRUPT_STATUS_G1_0_DUAL                       0x0
#define GPIO_E_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_E_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_E_INTERRUPT_STATUS_G1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G1_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G1_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_E_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_E_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_E_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_E_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_E_INTERRUPT_STATUS_G2_0
#define GPIO_E_INTERRUPT_STATUS_G2_0                    _MK_ADDR_CONST(0x14b08)
#define GPIO_E_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_E_INTERRUPT_STATUS_G2_0_DUAL                       0x0
#define GPIO_E_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_E_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_E_INTERRUPT_STATUS_G2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G2_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G2_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G2_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_E_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_E_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_E_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_E_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_E_INTERRUPT_STATUS_G3_0
#define GPIO_E_INTERRUPT_STATUS_G3_0                    _MK_ADDR_CONST(0x14b0c)
#define GPIO_E_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_E_INTERRUPT_STATUS_G3_0_DUAL                       0x0
#define GPIO_E_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_E_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_E_INTERRUPT_STATUS_G3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G3_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G3_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G3_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_E_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_E_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_E_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_E_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_E_INTERRUPT_STATUS_G4_0
#define GPIO_E_INTERRUPT_STATUS_G4_0                    _MK_ADDR_CONST(0x14b10)
#define GPIO_E_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_E_INTERRUPT_STATUS_G4_0_DUAL                       0x0
#define GPIO_E_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_E_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_E_INTERRUPT_STATUS_G4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G4_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G4_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G4_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_E_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_E_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_E_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_E_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_E_INTERRUPT_STATUS_G5_0
#define GPIO_E_INTERRUPT_STATUS_G5_0                    _MK_ADDR_CONST(0x14b14)
#define GPIO_E_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_E_INTERRUPT_STATUS_G5_0_DUAL                       0x0
#define GPIO_E_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_E_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_E_INTERRUPT_STATUS_G5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G5_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G5_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G5_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_E_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_E_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_E_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_E_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_E_INTERRUPT_STATUS_G6_0
#define GPIO_E_INTERRUPT_STATUS_G6_0                    _MK_ADDR_CONST(0x14b18)
#define GPIO_E_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_E_INTERRUPT_STATUS_G6_0_DUAL                       0x0
#define GPIO_E_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_E_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_E_INTERRUPT_STATUS_G6_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G6_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G6_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G6_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_E_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_E_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_E_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_E_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_E_INTERRUPT_STATUS_G7_0
#define GPIO_E_INTERRUPT_STATUS_G7_0                    _MK_ADDR_CONST(0x14b1c)
#define GPIO_E_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_E_INTERRUPT_STATUS_G7_0_DUAL                       0x0
#define GPIO_E_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_E_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_E_INTERRUPT_STATUS_G7_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G7_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G7_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G7_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0xff, GPIO_E_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_E_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_E_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_E_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Reserved address 0x14b20

// Reserved address 0x14b24

// Reserved address 0x14b28

// Reserved address 0x14b2c

// Reserved address 0x14b30

// Reserved address 0x14b34

// Reserved address 0x14b38

// Reserved address 0x14b3c

// Reserved address 0x14b40

// Reserved address 0x14b44

// Reserved address 0x14b48

// Reserved address 0x14b4c

// Reserved address 0x14b50

// Reserved address 0x14b54

// Reserved address 0x14b58

// Reserved address 0x14b5c

// Reserved address 0x14b60

// Reserved address 0x14b64

// Reserved address 0x14b68

// Reserved address 0x14b6c

// Reserved address 0x14b70

// Reserved address 0x14b74

// Reserved address 0x14b78

// Reserved address 0x14b7c

// Reserved address 0x14b80

// Reserved address 0x14b84

// Reserved address 0x14b88

// Reserved address 0x14b8c

// Reserved address 0x14b90

// Reserved address 0x14b94

// Reserved address 0x14b98

// Reserved address 0x14b9c

// Reserved address 0x14ba0

// Reserved address 0x14ba4

// Reserved address 0x14ba8

// Reserved address 0x14bac

// Reserved address 0x14bb0

// Reserved address 0x14bb4

// Reserved address 0x14bb8

// Reserved address 0x14bbc

// Reserved address 0x14bc0

// Reserved address 0x14bc4

// Reserved address 0x14bc8

// Reserved address 0x14bcc

// Reserved address 0x14bd0

// Reserved address 0x14bd4

// Reserved address 0x14bd8

// Reserved address 0x14bdc

// Reserved address 0x14be0

// Reserved address 0x14be4

// Reserved address 0x14be8

// Reserved address 0x14bec

// Reserved address 0x14bf0

// Reserved address 0x14bf4

// Reserved address 0x14bf8

// Reserved address 0x14bfc

// Register GPIO_F_ENABLE_CONFIG_00_0
#define GPIO_F_ENABLE_CONFIG_00_0                       _MK_ADDR_CONST(0x14c00)
#define GPIO_F_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_F_ENABLE_CONFIG_00_0_DUAL                  0x0
#define GPIO_F_ENABLE_CONFIG_00_0_SCR                   GPIO_F_SCR_00_0
#define GPIO_F_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_F_ENABLE_CONFIG_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_F_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_F_ENABLE_CONFIG_00_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_F_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_F_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_F_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_F_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_F_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_F_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_F_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_F_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_F_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_00_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_00_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_F_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_F_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_F_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_F_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_F_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_F_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_F_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_F_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_F_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_F_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_F_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_F_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_F_DEBOUNCE_THRESHOLD_00_0
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0                  _MK_ADDR_CONST(0x14c04)
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_F_SCR_00_0
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_F_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_F_INPUT_00_0
#define GPIO_F_INPUT_00_0                       _MK_ADDR_CONST(0x14c08)
#define GPIO_F_INPUT_00_0_SECURE                        0x0
#define GPIO_F_INPUT_00_0_DUAL                  0x0
#define GPIO_F_INPUT_00_0_SCR                   GPIO_F_SCR_00_0
#define GPIO_F_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_F_INPUT_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_00_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_00_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_F_INPUT_00_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_00_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_F_INPUT_00_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_F_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_F_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_F_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_F_INPUT_00_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_00_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_F_OUTPUT_CONTROL_00_0
#define GPIO_F_OUTPUT_CONTROL_00_0                      _MK_ADDR_CONST(0x14c0c)
#define GPIO_F_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_F_OUTPUT_CONTROL_00_0_DUAL                         0x0
#define GPIO_F_OUTPUT_CONTROL_00_0_SCR                  GPIO_F_SCR_00_0
#define GPIO_F_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_F_OUTPUT_CONTROL_00_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_00_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_00_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_00_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_F_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_F_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_F_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_F_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_F_OUTPUT_VALUE_00_0
#define GPIO_F_OUTPUT_VALUE_00_0                        _MK_ADDR_CONST(0x14c10)
#define GPIO_F_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_F_OUTPUT_VALUE_00_0_DUAL                   0x0
#define GPIO_F_OUTPUT_VALUE_00_0_SCR                    GPIO_F_SCR_00_0
#define GPIO_F_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_F_OUTPUT_VALUE_00_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_00_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_00_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_00_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_F_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_F_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_F_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_F_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_F_INTERRUPT_CLEAR_00_0
#define GPIO_F_INTERRUPT_CLEAR_00_0                     _MK_ADDR_CONST(0x14c14)
#define GPIO_F_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_F_INTERRUPT_CLEAR_00_0_DUAL                        0x0
#define GPIO_F_INTERRUPT_CLEAR_00_0_SCR                         GPIO_F_SCR_00_0
#define GPIO_F_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_F_INTERRUPT_CLEAR_00_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_00_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_00_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_00_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_F_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_F_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_F_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_F_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_F_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x14c18

// Reserved address 0x14c1c

// Register GPIO_F_ENABLE_CONFIG_01_0
#define GPIO_F_ENABLE_CONFIG_01_0                       _MK_ADDR_CONST(0x14c20)
#define GPIO_F_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_F_ENABLE_CONFIG_01_0_DUAL                  0x0
#define GPIO_F_ENABLE_CONFIG_01_0_SCR                   GPIO_F_SCR_01_0
#define GPIO_F_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_F_ENABLE_CONFIG_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_F_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_F_ENABLE_CONFIG_01_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_F_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_F_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_F_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_F_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_F_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_F_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_F_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_F_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_F_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_01_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_01_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_F_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_F_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_F_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_F_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_F_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_F_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_F_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_F_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_F_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_F_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_F_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_F_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_F_DEBOUNCE_THRESHOLD_01_0
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0                  _MK_ADDR_CONST(0x14c24)
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_F_SCR_01_0
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_F_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_F_INPUT_01_0
#define GPIO_F_INPUT_01_0                       _MK_ADDR_CONST(0x14c28)
#define GPIO_F_INPUT_01_0_SECURE                        0x0
#define GPIO_F_INPUT_01_0_DUAL                  0x0
#define GPIO_F_INPUT_01_0_SCR                   GPIO_F_SCR_01_0
#define GPIO_F_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_F_INPUT_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_01_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_01_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_F_INPUT_01_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_01_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_F_INPUT_01_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_F_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_F_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_F_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_F_INPUT_01_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_01_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_F_OUTPUT_CONTROL_01_0
#define GPIO_F_OUTPUT_CONTROL_01_0                      _MK_ADDR_CONST(0x14c2c)
#define GPIO_F_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_F_OUTPUT_CONTROL_01_0_DUAL                         0x0
#define GPIO_F_OUTPUT_CONTROL_01_0_SCR                  GPIO_F_SCR_01_0
#define GPIO_F_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_F_OUTPUT_CONTROL_01_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_01_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_01_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_01_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_F_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_F_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_F_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_F_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_F_OUTPUT_VALUE_01_0
#define GPIO_F_OUTPUT_VALUE_01_0                        _MK_ADDR_CONST(0x14c30)
#define GPIO_F_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_F_OUTPUT_VALUE_01_0_DUAL                   0x0
#define GPIO_F_OUTPUT_VALUE_01_0_SCR                    GPIO_F_SCR_01_0
#define GPIO_F_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_F_OUTPUT_VALUE_01_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_01_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_01_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_01_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_F_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_F_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_F_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_F_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_F_INTERRUPT_CLEAR_01_0
#define GPIO_F_INTERRUPT_CLEAR_01_0                     _MK_ADDR_CONST(0x14c34)
#define GPIO_F_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_F_INTERRUPT_CLEAR_01_0_DUAL                        0x0
#define GPIO_F_INTERRUPT_CLEAR_01_0_SCR                         GPIO_F_SCR_01_0
#define GPIO_F_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_F_INTERRUPT_CLEAR_01_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_01_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_01_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_01_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_F_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_F_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_F_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_F_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_F_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x14c38

// Reserved address 0x14c3c

// Register GPIO_F_ENABLE_CONFIG_02_0
#define GPIO_F_ENABLE_CONFIG_02_0                       _MK_ADDR_CONST(0x14c40)
#define GPIO_F_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_F_ENABLE_CONFIG_02_0_DUAL                  0x0
#define GPIO_F_ENABLE_CONFIG_02_0_SCR                   GPIO_F_SCR_02_0
#define GPIO_F_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_F_ENABLE_CONFIG_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_F_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_F_ENABLE_CONFIG_02_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_F_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_F_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_F_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_F_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_F_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_F_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_F_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_F_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_F_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_02_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_02_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_F_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_F_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_F_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_F_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_F_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_F_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_F_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_F_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_F_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_F_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_F_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_F_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_F_DEBOUNCE_THRESHOLD_02_0
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0                  _MK_ADDR_CONST(0x14c44)
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_F_SCR_02_0
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_F_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_F_INPUT_02_0
#define GPIO_F_INPUT_02_0                       _MK_ADDR_CONST(0x14c48)
#define GPIO_F_INPUT_02_0_SECURE                        0x0
#define GPIO_F_INPUT_02_0_DUAL                  0x0
#define GPIO_F_INPUT_02_0_SCR                   GPIO_F_SCR_02_0
#define GPIO_F_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_F_INPUT_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_02_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_02_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_F_INPUT_02_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_02_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_F_INPUT_02_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_F_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_F_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_F_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_F_INPUT_02_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_02_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_F_OUTPUT_CONTROL_02_0
#define GPIO_F_OUTPUT_CONTROL_02_0                      _MK_ADDR_CONST(0x14c4c)
#define GPIO_F_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_F_OUTPUT_CONTROL_02_0_DUAL                         0x0
#define GPIO_F_OUTPUT_CONTROL_02_0_SCR                  GPIO_F_SCR_02_0
#define GPIO_F_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_F_OUTPUT_CONTROL_02_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_02_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_02_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_02_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_F_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_F_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_F_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_F_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_F_OUTPUT_VALUE_02_0
#define GPIO_F_OUTPUT_VALUE_02_0                        _MK_ADDR_CONST(0x14c50)
#define GPIO_F_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_F_OUTPUT_VALUE_02_0_DUAL                   0x0
#define GPIO_F_OUTPUT_VALUE_02_0_SCR                    GPIO_F_SCR_02_0
#define GPIO_F_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_F_OUTPUT_VALUE_02_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_02_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_02_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_02_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_F_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_F_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_F_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_F_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_F_INTERRUPT_CLEAR_02_0
#define GPIO_F_INTERRUPT_CLEAR_02_0                     _MK_ADDR_CONST(0x14c54)
#define GPIO_F_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_F_INTERRUPT_CLEAR_02_0_DUAL                        0x0
#define GPIO_F_INTERRUPT_CLEAR_02_0_SCR                         GPIO_F_SCR_02_0
#define GPIO_F_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_F_INTERRUPT_CLEAR_02_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_02_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_02_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_02_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_F_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_F_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_F_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_F_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_F_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x14c58

// Reserved address 0x14c5c

// Register GPIO_F_ENABLE_CONFIG_03_0
#define GPIO_F_ENABLE_CONFIG_03_0                       _MK_ADDR_CONST(0x14c60)
#define GPIO_F_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_F_ENABLE_CONFIG_03_0_DUAL                  0x0
#define GPIO_F_ENABLE_CONFIG_03_0_SCR                   GPIO_F_SCR_03_0
#define GPIO_F_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_F_ENABLE_CONFIG_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_F_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_F_ENABLE_CONFIG_03_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_F_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_F_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_F_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_F_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_F_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_F_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_F_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_F_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_F_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_03_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_03_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_F_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_F_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_F_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_F_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_F_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_F_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_F_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_F_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_F_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_F_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_F_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_F_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_F_DEBOUNCE_THRESHOLD_03_0
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0                  _MK_ADDR_CONST(0x14c64)
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_F_SCR_03_0
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_F_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_F_INPUT_03_0
#define GPIO_F_INPUT_03_0                       _MK_ADDR_CONST(0x14c68)
#define GPIO_F_INPUT_03_0_SECURE                        0x0
#define GPIO_F_INPUT_03_0_DUAL                  0x0
#define GPIO_F_INPUT_03_0_SCR                   GPIO_F_SCR_03_0
#define GPIO_F_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_F_INPUT_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_03_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_03_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_F_INPUT_03_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_03_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_F_INPUT_03_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_F_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_F_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_F_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_F_INPUT_03_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_03_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_F_OUTPUT_CONTROL_03_0
#define GPIO_F_OUTPUT_CONTROL_03_0                      _MK_ADDR_CONST(0x14c6c)
#define GPIO_F_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_F_OUTPUT_CONTROL_03_0_DUAL                         0x0
#define GPIO_F_OUTPUT_CONTROL_03_0_SCR                  GPIO_F_SCR_03_0
#define GPIO_F_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_F_OUTPUT_CONTROL_03_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_03_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_03_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_03_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_F_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_F_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_F_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_F_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_F_OUTPUT_VALUE_03_0
#define GPIO_F_OUTPUT_VALUE_03_0                        _MK_ADDR_CONST(0x14c70)
#define GPIO_F_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_F_OUTPUT_VALUE_03_0_DUAL                   0x0
#define GPIO_F_OUTPUT_VALUE_03_0_SCR                    GPIO_F_SCR_03_0
#define GPIO_F_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_F_OUTPUT_VALUE_03_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_03_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_03_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_03_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_F_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_F_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_F_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_F_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_F_INTERRUPT_CLEAR_03_0
#define GPIO_F_INTERRUPT_CLEAR_03_0                     _MK_ADDR_CONST(0x14c74)
#define GPIO_F_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_F_INTERRUPT_CLEAR_03_0_DUAL                        0x0
#define GPIO_F_INTERRUPT_CLEAR_03_0_SCR                         GPIO_F_SCR_03_0
#define GPIO_F_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_F_INTERRUPT_CLEAR_03_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_03_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_03_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_03_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_F_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_F_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_F_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_F_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_F_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x14c78

// Reserved address 0x14c7c

// Register GPIO_F_ENABLE_CONFIG_04_0
#define GPIO_F_ENABLE_CONFIG_04_0                       _MK_ADDR_CONST(0x14c80)
#define GPIO_F_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_F_ENABLE_CONFIG_04_0_DUAL                  0x0
#define GPIO_F_ENABLE_CONFIG_04_0_SCR                   GPIO_F_SCR_04_0
#define GPIO_F_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_F_ENABLE_CONFIG_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_F_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_F_ENABLE_CONFIG_04_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_F_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_F_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_F_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_F_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_F_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_F_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_F_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_F_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_F_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_04_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_04_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_F_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_F_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_F_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_F_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_F_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_F_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_F_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_F_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_F_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_F_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_F_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_F_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_F_DEBOUNCE_THRESHOLD_04_0
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0                  _MK_ADDR_CONST(0x14c84)
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_DUAL                     0x0
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_F_SCR_04_0
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_F_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_F_INPUT_04_0
#define GPIO_F_INPUT_04_0                       _MK_ADDR_CONST(0x14c88)
#define GPIO_F_INPUT_04_0_SECURE                        0x0
#define GPIO_F_INPUT_04_0_DUAL                  0x0
#define GPIO_F_INPUT_04_0_SCR                   GPIO_F_SCR_04_0
#define GPIO_F_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_F_INPUT_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_04_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_04_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_F_INPUT_04_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_04_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_F_INPUT_04_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_F_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_F_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_F_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_F_INPUT_04_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_04_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_F_OUTPUT_CONTROL_04_0
#define GPIO_F_OUTPUT_CONTROL_04_0                      _MK_ADDR_CONST(0x14c8c)
#define GPIO_F_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_F_OUTPUT_CONTROL_04_0_DUAL                         0x0
#define GPIO_F_OUTPUT_CONTROL_04_0_SCR                  GPIO_F_SCR_04_0
#define GPIO_F_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_F_OUTPUT_CONTROL_04_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_04_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_04_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_04_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_F_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_F_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_F_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_F_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_F_OUTPUT_VALUE_04_0
#define GPIO_F_OUTPUT_VALUE_04_0                        _MK_ADDR_CONST(0x14c90)
#define GPIO_F_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_F_OUTPUT_VALUE_04_0_DUAL                   0x0
#define GPIO_F_OUTPUT_VALUE_04_0_SCR                    GPIO_F_SCR_04_0
#define GPIO_F_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_F_OUTPUT_VALUE_04_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_04_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_04_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_04_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_F_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_F_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_F_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_F_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_F_INTERRUPT_CLEAR_04_0
#define GPIO_F_INTERRUPT_CLEAR_04_0                     _MK_ADDR_CONST(0x14c94)
#define GPIO_F_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_F_INTERRUPT_CLEAR_04_0_DUAL                        0x0
#define GPIO_F_INTERRUPT_CLEAR_04_0_SCR                         GPIO_F_SCR_04_0
#define GPIO_F_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_F_INTERRUPT_CLEAR_04_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_04_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_04_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_04_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_F_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_F_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_F_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_F_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_F_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x14c98

// Reserved address 0x14c9c

// Register GPIO_F_ENABLE_CONFIG_05_0
#define GPIO_F_ENABLE_CONFIG_05_0                       _MK_ADDR_CONST(0x14ca0)
#define GPIO_F_ENABLE_CONFIG_05_0_SECURE                        0x0
#define GPIO_F_ENABLE_CONFIG_05_0_DUAL                  0x0
#define GPIO_F_ENABLE_CONFIG_05_0_SCR                   GPIO_F_SCR_05_0
#define GPIO_F_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
#define GPIO_F_ENABLE_CONFIG_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_F_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_F_ENABLE_CONFIG_05_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_F_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_F_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_F_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_F_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_F_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_F_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_F_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
#define GPIO_F_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
#define GPIO_F_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_05_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_05_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_F_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_F_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_F_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_F_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_F_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_F_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_F_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_F_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_F_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_F_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_F_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_F_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_F_DEBOUNCE_THRESHOLD_05_0
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0                  _MK_ADDR_CONST(0x14ca4)
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_DUAL                     0x0
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_F_SCR_05_0
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_F_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_F_INPUT_05_0
#define GPIO_F_INPUT_05_0                       _MK_ADDR_CONST(0x14ca8)
#define GPIO_F_INPUT_05_0_SECURE                        0x0
#define GPIO_F_INPUT_05_0_DUAL                  0x0
#define GPIO_F_INPUT_05_0_SCR                   GPIO_F_SCR_05_0
#define GPIO_F_INPUT_05_0_WORD_COUNT                    0x1
#define GPIO_F_INPUT_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_05_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_05_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_F_INPUT_05_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_05_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_F_INPUT_05_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_F_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_F_INPUT_05_0_GPIO_IN_RANGE                 0:0
#define GPIO_F_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_F_INPUT_05_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_05_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_F_OUTPUT_CONTROL_05_0
#define GPIO_F_OUTPUT_CONTROL_05_0                      _MK_ADDR_CONST(0x14cac)
#define GPIO_F_OUTPUT_CONTROL_05_0_SECURE                       0x0
#define GPIO_F_OUTPUT_CONTROL_05_0_DUAL                         0x0
#define GPIO_F_OUTPUT_CONTROL_05_0_SCR                  GPIO_F_SCR_05_0
#define GPIO_F_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
#define GPIO_F_OUTPUT_CONTROL_05_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_05_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_05_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_05_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_F_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_F_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_F_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_F_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_F_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_F_OUTPUT_VALUE_05_0
#define GPIO_F_OUTPUT_VALUE_05_0                        _MK_ADDR_CONST(0x14cb0)
#define GPIO_F_OUTPUT_VALUE_05_0_SECURE                         0x0
#define GPIO_F_OUTPUT_VALUE_05_0_DUAL                   0x0
#define GPIO_F_OUTPUT_VALUE_05_0_SCR                    GPIO_F_SCR_05_0
#define GPIO_F_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
#define GPIO_F_OUTPUT_VALUE_05_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_05_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_05_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_05_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_F_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_F_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_F_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_F_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_F_INTERRUPT_CLEAR_05_0
#define GPIO_F_INTERRUPT_CLEAR_05_0                     _MK_ADDR_CONST(0x14cb4)
#define GPIO_F_INTERRUPT_CLEAR_05_0_SECURE                      0x0
#define GPIO_F_INTERRUPT_CLEAR_05_0_DUAL                        0x0
#define GPIO_F_INTERRUPT_CLEAR_05_0_SCR                         GPIO_F_SCR_05_0
#define GPIO_F_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
#define GPIO_F_INTERRUPT_CLEAR_05_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_05_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_05_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_05_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_F_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_F_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_F_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_F_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_F_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x14cb8

// Reserved address 0x14cbc

// Reserved address 0x14cc0

// Reserved address 0x14cc4

// Reserved address 0x14cc8

// Reserved address 0x14ccc

// Reserved address 0x14cd0

// Reserved address 0x14cd4

// Reserved address 0x14cd8

// Reserved address 0x14cdc

// Reserved address 0x14ce0

// Reserved address 0x14ce4

// Reserved address 0x14ce8

// Reserved address 0x14cec

// Reserved address 0x14cf0

// Reserved address 0x14cf4

// Reserved address 0x14cf8

// Reserved address 0x14cfc

// Register GPIO_F_INTERRUPT_STATUS_G0_0
#define GPIO_F_INTERRUPT_STATUS_G0_0                    _MK_ADDR_CONST(0x14d00)
#define GPIO_F_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_F_INTERRUPT_STATUS_G0_0_DUAL                       0x0
#define GPIO_F_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_F_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_F_INTERRUPT_STATUS_G0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G0_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G0_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_F_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_F_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_F_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_F_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_F_INTERRUPT_STATUS_G1_0
#define GPIO_F_INTERRUPT_STATUS_G1_0                    _MK_ADDR_CONST(0x14d04)
#define GPIO_F_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_F_INTERRUPT_STATUS_G1_0_DUAL                       0x0
#define GPIO_F_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_F_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_F_INTERRUPT_STATUS_G1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G1_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G1_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_F_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_F_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_F_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_F_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_F_INTERRUPT_STATUS_G2_0
#define GPIO_F_INTERRUPT_STATUS_G2_0                    _MK_ADDR_CONST(0x14d08)
#define GPIO_F_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_F_INTERRUPT_STATUS_G2_0_DUAL                       0x0
#define GPIO_F_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_F_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_F_INTERRUPT_STATUS_G2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G2_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G2_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G2_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_F_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_F_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_F_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_F_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_F_INTERRUPT_STATUS_G3_0
#define GPIO_F_INTERRUPT_STATUS_G3_0                    _MK_ADDR_CONST(0x14d0c)
#define GPIO_F_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_F_INTERRUPT_STATUS_G3_0_DUAL                       0x0
#define GPIO_F_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_F_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_F_INTERRUPT_STATUS_G3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G3_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G3_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G3_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_F_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_F_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_F_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_F_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_F_INTERRUPT_STATUS_G4_0
#define GPIO_F_INTERRUPT_STATUS_G4_0                    _MK_ADDR_CONST(0x14d10)
#define GPIO_F_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_F_INTERRUPT_STATUS_G4_0_DUAL                       0x0
#define GPIO_F_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_F_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_F_INTERRUPT_STATUS_G4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G4_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G4_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G4_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_F_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_F_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_F_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_F_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_F_INTERRUPT_STATUS_G5_0
#define GPIO_F_INTERRUPT_STATUS_G5_0                    _MK_ADDR_CONST(0x14d14)
#define GPIO_F_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_F_INTERRUPT_STATUS_G5_0_DUAL                       0x0
#define GPIO_F_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_F_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_F_INTERRUPT_STATUS_G5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G5_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G5_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G5_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_F_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_F_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_F_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_F_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_F_INTERRUPT_STATUS_G6_0
#define GPIO_F_INTERRUPT_STATUS_G6_0                    _MK_ADDR_CONST(0x14d18)
#define GPIO_F_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_F_INTERRUPT_STATUS_G6_0_DUAL                       0x0
#define GPIO_F_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_F_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_F_INTERRUPT_STATUS_G6_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G6_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G6_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G6_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_F_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_F_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_F_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_F_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_F_INTERRUPT_STATUS_G7_0
#define GPIO_F_INTERRUPT_STATUS_G7_0                    _MK_ADDR_CONST(0x14d1c)
#define GPIO_F_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_F_INTERRUPT_STATUS_G7_0_DUAL                       0x0
#define GPIO_F_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_F_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_F_INTERRUPT_STATUS_G7_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G7_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G7_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G7_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_F_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_F_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_F_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_F_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Reserved address 0x14d20

// Reserved address 0x14d24

// Reserved address 0x14d28

// Reserved address 0x14d2c

// Reserved address 0x14d30

// Reserved address 0x14d34

// Reserved address 0x14d38

// Reserved address 0x14d3c

// Reserved address 0x14d40

// Reserved address 0x14d44

// Reserved address 0x14d48

// Reserved address 0x14d4c

// Reserved address 0x14d50

// Reserved address 0x14d54

// Reserved address 0x14d58

// Reserved address 0x14d5c

// Reserved address 0x14d60

// Reserved address 0x14d64

// Reserved address 0x14d68

// Reserved address 0x14d6c

// Reserved address 0x14d70

// Reserved address 0x14d74

// Reserved address 0x14d78

// Reserved address 0x14d7c

// Reserved address 0x14d80

// Reserved address 0x14d84

// Reserved address 0x14d88

// Reserved address 0x14d8c

// Reserved address 0x14d90

// Reserved address 0x14d94

// Reserved address 0x14d98

// Reserved address 0x14d9c

// Reserved address 0x14da0

// Reserved address 0x14da4

// Reserved address 0x14da8

// Reserved address 0x14dac

// Reserved address 0x14db0

// Reserved address 0x14db4

// Reserved address 0x14db8

// Reserved address 0x14dbc

// Reserved address 0x14dc0

// Reserved address 0x14dc4

// Reserved address 0x14dc8

// Reserved address 0x14dcc

// Reserved address 0x14dd0

// Reserved address 0x14dd4

// Reserved address 0x14dd8

// Reserved address 0x14ddc

// Reserved address 0x14de0

// Reserved address 0x14de4

// Reserved address 0x14de8

// Reserved address 0x14dec

// Reserved address 0x14df0

// Reserved address 0x14df4

// Reserved address 0x14df8

// Reserved address 0x14dfc

// Register GPIO_B_ENABLE_CONFIG_00_0
#define GPIO_B_ENABLE_CONFIG_00_0                       _MK_ADDR_CONST(0x14e00)
#define GPIO_B_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_B_ENABLE_CONFIG_00_0_DUAL                  0x0
#define GPIO_B_ENABLE_CONFIG_00_0_SCR                   GPIO_B_SCR_00_0
#define GPIO_B_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_B_ENABLE_CONFIG_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_B_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_B_ENABLE_CONFIG_00_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_B_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_B_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_B_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_B_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_B_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_B_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_B_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_B_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_B_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_B_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_00_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_00_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_B_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_B_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_B_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_B_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_B_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_B_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_B_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_B_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_B_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_B_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_B_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_B_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_B_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_B_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_B_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_B_DEBOUNCE_THRESHOLD_00_0
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0                  _MK_ADDR_CONST(0x14e04)
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_B_SCR_00_0
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_B_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_B_INPUT_00_0
#define GPIO_B_INPUT_00_0                       _MK_ADDR_CONST(0x14e08)
#define GPIO_B_INPUT_00_0_SECURE                        0x0
#define GPIO_B_INPUT_00_0_DUAL                  0x0
#define GPIO_B_INPUT_00_0_SCR                   GPIO_B_SCR_00_0
#define GPIO_B_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_B_INPUT_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_00_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_00_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_B_INPUT_00_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_00_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_B_INPUT_00_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_B_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_B_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_B_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_B_INPUT_00_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_00_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_B_OUTPUT_CONTROL_00_0
#define GPIO_B_OUTPUT_CONTROL_00_0                      _MK_ADDR_CONST(0x14e0c)
#define GPIO_B_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_B_OUTPUT_CONTROL_00_0_DUAL                         0x0
#define GPIO_B_OUTPUT_CONTROL_00_0_SCR                  GPIO_B_SCR_00_0
#define GPIO_B_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_B_OUTPUT_CONTROL_00_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_00_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_CONTROL_00_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_00_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_B_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_B_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_B_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_B_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_B_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_B_OUTPUT_VALUE_00_0
#define GPIO_B_OUTPUT_VALUE_00_0                        _MK_ADDR_CONST(0x14e10)
#define GPIO_B_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_B_OUTPUT_VALUE_00_0_DUAL                   0x0
#define GPIO_B_OUTPUT_VALUE_00_0_SCR                    GPIO_B_SCR_00_0
#define GPIO_B_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_B_OUTPUT_VALUE_00_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_00_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_00_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_VALUE_00_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_B_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_B_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_B_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_B_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_B_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_B_INTERRUPT_CLEAR_00_0
#define GPIO_B_INTERRUPT_CLEAR_00_0                     _MK_ADDR_CONST(0x14e14)
#define GPIO_B_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_B_INTERRUPT_CLEAR_00_0_DUAL                        0x0
#define GPIO_B_INTERRUPT_CLEAR_00_0_SCR                         GPIO_B_SCR_00_0
#define GPIO_B_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_B_INTERRUPT_CLEAR_00_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_00_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_00_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_CLEAR_00_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_B_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_B_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_B_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_B_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_B_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_B_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x14e18

// Reserved address 0x14e1c

// Register GPIO_B_ENABLE_CONFIG_01_0
#define GPIO_B_ENABLE_CONFIG_01_0                       _MK_ADDR_CONST(0x14e20)
#define GPIO_B_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_B_ENABLE_CONFIG_01_0_DUAL                  0x0
#define GPIO_B_ENABLE_CONFIG_01_0_SCR                   GPIO_B_SCR_01_0
#define GPIO_B_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_B_ENABLE_CONFIG_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_B_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_B_ENABLE_CONFIG_01_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_B_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_B_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_B_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_B_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_B_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_B_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_B_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_B_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_B_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_B_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_01_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_01_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_B_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_B_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_B_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_B_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_B_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_B_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_B_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_B_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_B_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_B_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_B_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_B_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_B_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_B_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_B_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_B_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_B_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_B_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_B_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_B_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_B_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_B_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_B_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_B_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_B_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_B_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_B_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_B_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_B_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_B_DEBOUNCE_THRESHOLD_01_0
#define GPIO_B_DEBOUNCE_THRESHOLD_01_0                  _MK_ADDR_CONST(0x14e24)
#define GPIO_B_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_B_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
#define GPIO_B_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_B_SCR_01_0
#define GPIO_B_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_B_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_B_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_B_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_B_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_B_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_B_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_B_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_B_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_B_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_B_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_B_INPUT_01_0
#define GPIO_B_INPUT_01_0                       _MK_ADDR_CONST(0x14e28)
#define GPIO_B_INPUT_01_0_SECURE                        0x0
#define GPIO_B_INPUT_01_0_DUAL                  0x0
#define GPIO_B_INPUT_01_0_SCR                   GPIO_B_SCR_01_0
#define GPIO_B_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_B_INPUT_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_01_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_01_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_B_INPUT_01_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_01_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_B_INPUT_01_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_B_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_B_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_B_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_B_INPUT_01_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_01_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_B_OUTPUT_CONTROL_01_0
#define GPIO_B_OUTPUT_CONTROL_01_0                      _MK_ADDR_CONST(0x14e2c)
#define GPIO_B_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_B_OUTPUT_CONTROL_01_0_DUAL                         0x0
#define GPIO_B_OUTPUT_CONTROL_01_0_SCR                  GPIO_B_SCR_01_0
#define GPIO_B_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_B_OUTPUT_CONTROL_01_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_01_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_CONTROL_01_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_01_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_B_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_B_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_B_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_B_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_B_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_B_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_B_OUTPUT_VALUE_01_0
#define GPIO_B_OUTPUT_VALUE_01_0                        _MK_ADDR_CONST(0x14e30)
#define GPIO_B_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_B_OUTPUT_VALUE_01_0_DUAL                   0x0
#define GPIO_B_OUTPUT_VALUE_01_0_SCR                    GPIO_B_SCR_01_0
#define GPIO_B_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_B_OUTPUT_VALUE_01_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_01_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_01_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_VALUE_01_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_B_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_B_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_B_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_B_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_B_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_B_INTERRUPT_CLEAR_01_0
#define GPIO_B_INTERRUPT_CLEAR_01_0                     _MK_ADDR_CONST(0x14e34)
#define GPIO_B_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_B_INTERRUPT_CLEAR_01_0_DUAL                        0x0
#define GPIO_B_INTERRUPT_CLEAR_01_0_SCR                         GPIO_B_SCR_01_0
#define GPIO_B_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_B_INTERRUPT_CLEAR_01_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_01_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_01_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_CLEAR_01_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_B_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_B_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_B_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_B_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_B_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_B_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x14e38

// Reserved address 0x14e3c

// Reserved address 0x14e40

// Reserved address 0x14e44

// Reserved address 0x14e48

// Reserved address 0x14e4c

// Reserved address 0x14e50

// Reserved address 0x14e54

// Reserved address 0x14e58

// Reserved address 0x14e5c

// Reserved address 0x14e60

// Reserved address 0x14e64

// Reserved address 0x14e68

// Reserved address 0x14e6c

// Reserved address 0x14e70

// Reserved address 0x14e74

// Reserved address 0x14e78

// Reserved address 0x14e7c

// Reserved address 0x14e80

// Reserved address 0x14e84

// Reserved address 0x14e88

// Reserved address 0x14e8c

// Reserved address 0x14e90

// Reserved address 0x14e94

// Reserved address 0x14e98

// Reserved address 0x14e9c

// Reserved address 0x14ea0

// Reserved address 0x14ea4

// Reserved address 0x14ea8

// Reserved address 0x14eac

// Reserved address 0x14eb0

// Reserved address 0x14eb4

// Reserved address 0x14eb8

// Reserved address 0x14ebc

// Reserved address 0x14ec0

// Reserved address 0x14ec4

// Reserved address 0x14ec8

// Reserved address 0x14ecc

// Reserved address 0x14ed0

// Reserved address 0x14ed4

// Reserved address 0x14ed8

// Reserved address 0x14edc

// Reserved address 0x14ee0

// Reserved address 0x14ee4

// Reserved address 0x14ee8

// Reserved address 0x14eec

// Reserved address 0x14ef0

// Reserved address 0x14ef4

// Reserved address 0x14ef8

// Reserved address 0x14efc

// Register GPIO_B_INTERRUPT_STATUS_G0_0
#define GPIO_B_INTERRUPT_STATUS_G0_0                    _MK_ADDR_CONST(0x14f00)
#define GPIO_B_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_B_INTERRUPT_STATUS_G0_0_DUAL                       0x0
#define GPIO_B_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_B_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_B_INTERRUPT_STATUS_G0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G0_0_RESET_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_B_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G0_0_READ_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_B_INTERRUPT_STATUS_G0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_B_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_B_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        1:0
#define GPIO_B_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_B_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_B_INTERRUPT_STATUS_G1_0
#define GPIO_B_INTERRUPT_STATUS_G1_0                    _MK_ADDR_CONST(0x14f04)
#define GPIO_B_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_B_INTERRUPT_STATUS_G1_0_DUAL                       0x0
#define GPIO_B_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_B_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_B_INTERRUPT_STATUS_G1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G1_0_RESET_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_B_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G1_0_READ_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_B_INTERRUPT_STATUS_G1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_B_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_B_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        1:0
#define GPIO_B_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_B_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_B_INTERRUPT_STATUS_G2_0
#define GPIO_B_INTERRUPT_STATUS_G2_0                    _MK_ADDR_CONST(0x14f08)
#define GPIO_B_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_B_INTERRUPT_STATUS_G2_0_DUAL                       0x0
#define GPIO_B_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_B_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_B_INTERRUPT_STATUS_G2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G2_0_RESET_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_B_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G2_0_READ_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_B_INTERRUPT_STATUS_G2_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_B_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_B_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        1:0
#define GPIO_B_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_B_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_B_INTERRUPT_STATUS_G3_0
#define GPIO_B_INTERRUPT_STATUS_G3_0                    _MK_ADDR_CONST(0x14f0c)
#define GPIO_B_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_B_INTERRUPT_STATUS_G3_0_DUAL                       0x0
#define GPIO_B_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_B_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_B_INTERRUPT_STATUS_G3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G3_0_RESET_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_B_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G3_0_READ_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_B_INTERRUPT_STATUS_G3_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_B_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_B_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        1:0
#define GPIO_B_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_B_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_B_INTERRUPT_STATUS_G4_0
#define GPIO_B_INTERRUPT_STATUS_G4_0                    _MK_ADDR_CONST(0x14f10)
#define GPIO_B_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_B_INTERRUPT_STATUS_G4_0_DUAL                       0x0
#define GPIO_B_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_B_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_B_INTERRUPT_STATUS_G4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G4_0_RESET_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_B_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G4_0_READ_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_B_INTERRUPT_STATUS_G4_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_B_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_B_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        1:0
#define GPIO_B_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_B_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_B_INTERRUPT_STATUS_G5_0
#define GPIO_B_INTERRUPT_STATUS_G5_0                    _MK_ADDR_CONST(0x14f14)
#define GPIO_B_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_B_INTERRUPT_STATUS_G5_0_DUAL                       0x0
#define GPIO_B_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_B_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_B_INTERRUPT_STATUS_G5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G5_0_RESET_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_B_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G5_0_READ_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_B_INTERRUPT_STATUS_G5_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_B_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_B_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        1:0
#define GPIO_B_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_B_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_B_INTERRUPT_STATUS_G6_0
#define GPIO_B_INTERRUPT_STATUS_G6_0                    _MK_ADDR_CONST(0x14f18)
#define GPIO_B_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_B_INTERRUPT_STATUS_G6_0_DUAL                       0x0
#define GPIO_B_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_B_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_B_INTERRUPT_STATUS_G6_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G6_0_RESET_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_B_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G6_0_READ_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_B_INTERRUPT_STATUS_G6_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_B_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_B_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        1:0
#define GPIO_B_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_B_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_B_INTERRUPT_STATUS_G7_0
#define GPIO_B_INTERRUPT_STATUS_G7_0                    _MK_ADDR_CONST(0x14f1c)
#define GPIO_B_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_B_INTERRUPT_STATUS_G7_0_DUAL                       0x0
#define GPIO_B_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_B_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_B_INTERRUPT_STATUS_G7_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G7_0_RESET_MASK                         _MK_MASK_CONST(0x3)
#define GPIO_B_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G7_0_READ_MASK                  _MK_MASK_CONST(0x3)
#define GPIO_B_INTERRUPT_STATUS_G7_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_B_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3, GPIO_B_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_B_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        1:0
#define GPIO_B_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_B_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define GPIO_B_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Reserved address 0x14f20

// Reserved address 0x14f24

// Reserved address 0x14f28

// Reserved address 0x14f2c

// Reserved address 0x14f30

// Reserved address 0x14f34

// Reserved address 0x14f38

// Reserved address 0x14f3c

// Reserved address 0x14f40

// Reserved address 0x14f44

// Reserved address 0x14f48

// Reserved address 0x14f4c

// Reserved address 0x14f50

// Reserved address 0x14f54

// Reserved address 0x14f58

// Reserved address 0x14f5c

// Reserved address 0x14f60

// Reserved address 0x14f64

// Reserved address 0x14f68

// Reserved address 0x14f6c

// Reserved address 0x14f70

// Reserved address 0x14f74

// Reserved address 0x14f78

// Reserved address 0x14f7c

// Reserved address 0x14f80

// Reserved address 0x14f84

// Reserved address 0x14f88

// Reserved address 0x14f8c

// Reserved address 0x14f90

// Reserved address 0x14f94

// Reserved address 0x14f98

// Reserved address 0x14f9c

// Reserved address 0x14fa0

// Reserved address 0x14fa4

// Reserved address 0x14fa8

// Reserved address 0x14fac

// Reserved address 0x14fb0

// Reserved address 0x14fb4

// Reserved address 0x14fb8

// Reserved address 0x14fbc

// Reserved address 0x14fc0

// Reserved address 0x14fc4

// Reserved address 0x14fc8

// Reserved address 0x14fcc

// Reserved address 0x14fd0

// Reserved address 0x14fd4

// Reserved address 0x14fd8

// Reserved address 0x14fdc

// Reserved address 0x14fe0

// Reserved address 0x14fe4

// Reserved address 0x14fe8

// Reserved address 0x14fec

// Reserved address 0x14ff0

// Reserved address 0x14ff4

// Reserved address 0x14ff8

// Reserved address 0x14ffc

// Register GPIO_O_ENABLE_CONFIG_00_0
#define GPIO_O_ENABLE_CONFIG_00_0                       _MK_ADDR_CONST(0x15000)
#define GPIO_O_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_O_ENABLE_CONFIG_00_0_DUAL                  0x0
#define GPIO_O_ENABLE_CONFIG_00_0_SCR                   GPIO_O_SCR_00_0
#define GPIO_O_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_O_ENABLE_CONFIG_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_O_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_O_ENABLE_CONFIG_00_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_O_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_O_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_O_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_O_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_O_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_O_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_O_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_O_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_O_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_O_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_00_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_00_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_O_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_O_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_O_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_O_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_O_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_O_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_O_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_O_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_O_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_O_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_O_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_O_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_O_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_O_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_O_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_O_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_O_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_O_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_O_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_O_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_O_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_O_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_O_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_O_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_O_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_O_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_O_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_O_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_O_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_O_DEBOUNCE_THRESHOLD_00_0
#define GPIO_O_DEBOUNCE_THRESHOLD_00_0                  _MK_ADDR_CONST(0x15004)
#define GPIO_O_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_O_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
#define GPIO_O_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_O_SCR_00_0
#define GPIO_O_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_O_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_O_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_O_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_O_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_O_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_O_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_O_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_O_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_O_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_O_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_O_INPUT_00_0
#define GPIO_O_INPUT_00_0                       _MK_ADDR_CONST(0x15008)
#define GPIO_O_INPUT_00_0_SECURE                        0x0
#define GPIO_O_INPUT_00_0_DUAL                  0x0
#define GPIO_O_INPUT_00_0_SCR                   GPIO_O_SCR_00_0
#define GPIO_O_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_O_INPUT_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_00_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_00_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_O_INPUT_00_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_00_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_O_INPUT_00_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_O_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_O_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_O_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_O_INPUT_00_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_00_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_O_OUTPUT_CONTROL_00_0
#define GPIO_O_OUTPUT_CONTROL_00_0                      _MK_ADDR_CONST(0x1500c)
#define GPIO_O_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_O_OUTPUT_CONTROL_00_0_DUAL                         0x0
#define GPIO_O_OUTPUT_CONTROL_00_0_SCR                  GPIO_O_SCR_00_0
#define GPIO_O_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_O_OUTPUT_CONTROL_00_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_00_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_CONTROL_00_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_00_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_O_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_O_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_O_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_O_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_O_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_O_OUTPUT_VALUE_00_0
#define GPIO_O_OUTPUT_VALUE_00_0                        _MK_ADDR_CONST(0x15010)
#define GPIO_O_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_O_OUTPUT_VALUE_00_0_DUAL                   0x0
#define GPIO_O_OUTPUT_VALUE_00_0_SCR                    GPIO_O_SCR_00_0
#define GPIO_O_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_O_OUTPUT_VALUE_00_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_00_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_00_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_VALUE_00_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_O_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_O_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_O_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_O_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_O_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_O_INTERRUPT_CLEAR_00_0
#define GPIO_O_INTERRUPT_CLEAR_00_0                     _MK_ADDR_CONST(0x15014)
#define GPIO_O_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_O_INTERRUPT_CLEAR_00_0_DUAL                        0x0
#define GPIO_O_INTERRUPT_CLEAR_00_0_SCR                         GPIO_O_SCR_00_0
#define GPIO_O_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_O_INTERRUPT_CLEAR_00_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_00_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_O_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_00_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_O_INTERRUPT_CLEAR_00_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_O_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_O_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_O_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_O_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_O_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_O_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_O_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_O_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_O_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x15018

// Reserved address 0x1501c

// Register GPIO_O_ENABLE_CONFIG_01_0
#define GPIO_O_ENABLE_CONFIG_01_0                       _MK_ADDR_CONST(0x15020)
#define GPIO_O_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_O_ENABLE_CONFIG_01_0_DUAL                  0x0
#define GPIO_O_ENABLE_CONFIG_01_0_SCR                   GPIO_O_SCR_01_0
#define GPIO_O_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_O_ENABLE_CONFIG_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_O_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_O_ENABLE_CONFIG_01_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_O_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_O_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_O_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_O_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_O_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_O_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_O_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_O_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_O_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_O_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_01_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_01_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_O_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_O_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_O_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_O_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_O_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_O_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_O_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_O_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_O_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_O_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_O_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_O_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_O_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_O_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_O_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_O_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_O_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_O_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_O_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_O_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_O_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_O_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_O_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_O_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_O_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_O_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_O_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_O_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_O_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_O_DEBOUNCE_THRESHOLD_01_0
#define GPIO_O_DEBOUNCE_THRESHOLD_01_0                  _MK_ADDR_CONST(0x15024)
#define GPIO_O_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_O_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
#define GPIO_O_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_O_SCR_01_0
#define GPIO_O_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_O_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_O_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_O_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_O_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_O_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_O_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_O_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_O_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_O_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_O_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_O_INPUT_01_0
#define GPIO_O_INPUT_01_0                       _MK_ADDR_CONST(0x15028)
#define GPIO_O_INPUT_01_0_SECURE                        0x0
#define GPIO_O_INPUT_01_0_DUAL                  0x0
#define GPIO_O_INPUT_01_0_SCR                   GPIO_O_SCR_01_0
#define GPIO_O_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_O_INPUT_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_01_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_01_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_O_INPUT_01_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_01_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_O_INPUT_01_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_O_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_O_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_O_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_O_INPUT_01_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_01_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_O_OUTPUT_CONTROL_01_0
#define GPIO_O_OUTPUT_CONTROL_01_0                      _MK_ADDR_CONST(0x1502c)
#define GPIO_O_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_O_OUTPUT_CONTROL_01_0_DUAL                         0x0
#define GPIO_O_OUTPUT_CONTROL_01_0_SCR                  GPIO_O_SCR_01_0
#define GPIO_O_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_O_OUTPUT_CONTROL_01_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_01_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_CONTROL_01_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_01_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_O_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_O_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_O_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_O_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_O_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_O_OUTPUT_VALUE_01_0
#define GPIO_O_OUTPUT_VALUE_01_0                        _MK_ADDR_CONST(0x15030)
#define GPIO_O_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_O_OUTPUT_VALUE_01_0_DUAL                   0x0
#define GPIO_O_OUTPUT_VALUE_01_0_SCR                    GPIO_O_SCR_01_0
#define GPIO_O_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_O_OUTPUT_VALUE_01_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_01_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_01_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_VALUE_01_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_O_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_O_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_O_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_O_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_O_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_O_INTERRUPT_CLEAR_01_0
#define GPIO_O_INTERRUPT_CLEAR_01_0                     _MK_ADDR_CONST(0x15034)
#define GPIO_O_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_O_INTERRUPT_CLEAR_01_0_DUAL                        0x0
#define GPIO_O_INTERRUPT_CLEAR_01_0_SCR                         GPIO_O_SCR_01_0
#define GPIO_O_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_O_INTERRUPT_CLEAR_01_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_01_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_O_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_01_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_O_INTERRUPT_CLEAR_01_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_O_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_O_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_O_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_O_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_O_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_O_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_O_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_O_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_O_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x15038

// Reserved address 0x1503c

// Register GPIO_O_ENABLE_CONFIG_02_0
#define GPIO_O_ENABLE_CONFIG_02_0                       _MK_ADDR_CONST(0x15040)
#define GPIO_O_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_O_ENABLE_CONFIG_02_0_DUAL                  0x0
#define GPIO_O_ENABLE_CONFIG_02_0_SCR                   GPIO_O_SCR_02_0
#define GPIO_O_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_O_ENABLE_CONFIG_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_O_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_O_ENABLE_CONFIG_02_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_O_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_O_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_O_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_O_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_O_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_O_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_O_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_O_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_O_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_O_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_02_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_02_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_O_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_O_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_O_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_O_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_O_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_O_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_O_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_O_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_O_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_O_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_O_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_O_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_O_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_O_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_O_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_O_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_O_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_O_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_O_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_O_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_O_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_O_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_O_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_O_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_O_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_O_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_O_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_O_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_O_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_O_DEBOUNCE_THRESHOLD_02_0
#define GPIO_O_DEBOUNCE_THRESHOLD_02_0                  _MK_ADDR_CONST(0x15044)
#define GPIO_O_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_O_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
#define GPIO_O_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_O_SCR_02_0
#define GPIO_O_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_O_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_O_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_O_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_O_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_O_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_O_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_O_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_O_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_O_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_O_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_O_INPUT_02_0
#define GPIO_O_INPUT_02_0                       _MK_ADDR_CONST(0x15048)
#define GPIO_O_INPUT_02_0_SECURE                        0x0
#define GPIO_O_INPUT_02_0_DUAL                  0x0
#define GPIO_O_INPUT_02_0_SCR                   GPIO_O_SCR_02_0
#define GPIO_O_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_O_INPUT_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_02_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_02_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_O_INPUT_02_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_02_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_O_INPUT_02_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_O_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_O_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_O_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_O_INPUT_02_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_02_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_O_OUTPUT_CONTROL_02_0
#define GPIO_O_OUTPUT_CONTROL_02_0                      _MK_ADDR_CONST(0x1504c)
#define GPIO_O_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_O_OUTPUT_CONTROL_02_0_DUAL                         0x0
#define GPIO_O_OUTPUT_CONTROL_02_0_SCR                  GPIO_O_SCR_02_0
#define GPIO_O_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_O_OUTPUT_CONTROL_02_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_02_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_CONTROL_02_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_02_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_O_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_O_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_O_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_O_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_O_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_O_OUTPUT_VALUE_02_0
#define GPIO_O_OUTPUT_VALUE_02_0                        _MK_ADDR_CONST(0x15050)
#define GPIO_O_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_O_OUTPUT_VALUE_02_0_DUAL                   0x0
#define GPIO_O_OUTPUT_VALUE_02_0_SCR                    GPIO_O_SCR_02_0
#define GPIO_O_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_O_OUTPUT_VALUE_02_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_02_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_02_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_VALUE_02_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_O_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_O_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_O_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_O_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_O_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_O_INTERRUPT_CLEAR_02_0
#define GPIO_O_INTERRUPT_CLEAR_02_0                     _MK_ADDR_CONST(0x15054)
#define GPIO_O_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_O_INTERRUPT_CLEAR_02_0_DUAL                        0x0
#define GPIO_O_INTERRUPT_CLEAR_02_0_SCR                         GPIO_O_SCR_02_0
#define GPIO_O_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_O_INTERRUPT_CLEAR_02_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_02_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_O_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_02_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_O_INTERRUPT_CLEAR_02_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_O_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_O_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_O_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_O_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_O_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_O_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_O_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_O_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_O_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x15058

// Reserved address 0x1505c

// Register GPIO_O_ENABLE_CONFIG_03_0
#define GPIO_O_ENABLE_CONFIG_03_0                       _MK_ADDR_CONST(0x15060)
#define GPIO_O_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_O_ENABLE_CONFIG_03_0_DUAL                  0x0
#define GPIO_O_ENABLE_CONFIG_03_0_SCR                   GPIO_O_SCR_03_0
#define GPIO_O_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_O_ENABLE_CONFIG_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_O_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_O_ENABLE_CONFIG_03_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_O_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_O_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_O_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_O_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_O_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_O_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_O_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_O_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_O_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_O_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_03_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_03_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_O_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_O_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_O_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_O_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_O_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_O_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_O_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_O_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_O_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_O_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_O_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_O_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_O_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_O_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_O_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_O_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_O_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_O_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_O_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_O_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_O_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_O_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_O_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_O_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_O_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_O_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_O_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_O_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_O_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_O_DEBOUNCE_THRESHOLD_03_0
#define GPIO_O_DEBOUNCE_THRESHOLD_03_0                  _MK_ADDR_CONST(0x15064)
#define GPIO_O_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_O_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
#define GPIO_O_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_O_SCR_03_0
#define GPIO_O_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_O_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_O_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_O_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_O_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_O_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_O_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_O_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_O_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_O_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_O_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_O_INPUT_03_0
#define GPIO_O_INPUT_03_0                       _MK_ADDR_CONST(0x15068)
#define GPIO_O_INPUT_03_0_SECURE                        0x0
#define GPIO_O_INPUT_03_0_DUAL                  0x0
#define GPIO_O_INPUT_03_0_SCR                   GPIO_O_SCR_03_0
#define GPIO_O_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_O_INPUT_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_03_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_03_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_O_INPUT_03_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_03_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_O_INPUT_03_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_O_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_O_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_O_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_O_INPUT_03_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_03_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_O_OUTPUT_CONTROL_03_0
#define GPIO_O_OUTPUT_CONTROL_03_0                      _MK_ADDR_CONST(0x1506c)
#define GPIO_O_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_O_OUTPUT_CONTROL_03_0_DUAL                         0x0
#define GPIO_O_OUTPUT_CONTROL_03_0_SCR                  GPIO_O_SCR_03_0
#define GPIO_O_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_O_OUTPUT_CONTROL_03_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_03_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_CONTROL_03_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_03_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_O_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_O_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_O_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_O_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_O_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_O_OUTPUT_VALUE_03_0
#define GPIO_O_OUTPUT_VALUE_03_0                        _MK_ADDR_CONST(0x15070)
#define GPIO_O_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_O_OUTPUT_VALUE_03_0_DUAL                   0x0
#define GPIO_O_OUTPUT_VALUE_03_0_SCR                    GPIO_O_SCR_03_0
#define GPIO_O_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_O_OUTPUT_VALUE_03_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_03_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_03_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_VALUE_03_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_O_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_O_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_O_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_O_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_O_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_O_INTERRUPT_CLEAR_03_0
#define GPIO_O_INTERRUPT_CLEAR_03_0                     _MK_ADDR_CONST(0x15074)
#define GPIO_O_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_O_INTERRUPT_CLEAR_03_0_DUAL                        0x0
#define GPIO_O_INTERRUPT_CLEAR_03_0_SCR                         GPIO_O_SCR_03_0
#define GPIO_O_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_O_INTERRUPT_CLEAR_03_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_03_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_O_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_03_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_O_INTERRUPT_CLEAR_03_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_O_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_O_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_O_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_O_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_O_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_O_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_O_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_O_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_O_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x15078

// Reserved address 0x1507c

// Register GPIO_O_ENABLE_CONFIG_04_0
#define GPIO_O_ENABLE_CONFIG_04_0                       _MK_ADDR_CONST(0x15080)
#define GPIO_O_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_O_ENABLE_CONFIG_04_0_DUAL                  0x0
#define GPIO_O_ENABLE_CONFIG_04_0_SCR                   GPIO_O_SCR_04_0
#define GPIO_O_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_O_ENABLE_CONFIG_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_04_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_O_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_04_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_O_ENABLE_CONFIG_04_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_O_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_O_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_O_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_O_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_O_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_O_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_O_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_O_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_O_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_O_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_04_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_04_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_O_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_O_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_O_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_O_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_O_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_O_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_O_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_O_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_O_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_O_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_O_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_O_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_O_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_O_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_O_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_O_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_O_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_O_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_O_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_O_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_O_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_O_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_O_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_O_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_O_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_O_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_O_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_O_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_O_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_O_DEBOUNCE_THRESHOLD_04_0
#define GPIO_O_DEBOUNCE_THRESHOLD_04_0                  _MK_ADDR_CONST(0x15084)
#define GPIO_O_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_O_DEBOUNCE_THRESHOLD_04_0_DUAL                     0x0
#define GPIO_O_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_O_SCR_04_0
#define GPIO_O_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_O_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_O_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_O_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_O_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_O_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_O_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_O_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_O_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_O_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_O_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_O_INPUT_04_0
#define GPIO_O_INPUT_04_0                       _MK_ADDR_CONST(0x15088)
#define GPIO_O_INPUT_04_0_SECURE                        0x0
#define GPIO_O_INPUT_04_0_DUAL                  0x0
#define GPIO_O_INPUT_04_0_SCR                   GPIO_O_SCR_04_0
#define GPIO_O_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_O_INPUT_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_04_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_04_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_O_INPUT_04_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_04_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_O_INPUT_04_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_O_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_O_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_O_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_O_INPUT_04_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_04_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_O_OUTPUT_CONTROL_04_0
#define GPIO_O_OUTPUT_CONTROL_04_0                      _MK_ADDR_CONST(0x1508c)
#define GPIO_O_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_O_OUTPUT_CONTROL_04_0_DUAL                         0x0
#define GPIO_O_OUTPUT_CONTROL_04_0_SCR                  GPIO_O_SCR_04_0
#define GPIO_O_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_O_OUTPUT_CONTROL_04_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_04_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_CONTROL_04_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_04_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_O_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_O_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_O_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_O_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_O_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_O_OUTPUT_VALUE_04_0
#define GPIO_O_OUTPUT_VALUE_04_0                        _MK_ADDR_CONST(0x15090)
#define GPIO_O_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_O_OUTPUT_VALUE_04_0_DUAL                   0x0
#define GPIO_O_OUTPUT_VALUE_04_0_SCR                    GPIO_O_SCR_04_0
#define GPIO_O_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_O_OUTPUT_VALUE_04_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_04_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_04_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_VALUE_04_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_O_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_O_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_O_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_O_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_O_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_O_INTERRUPT_CLEAR_04_0
#define GPIO_O_INTERRUPT_CLEAR_04_0                     _MK_ADDR_CONST(0x15094)
#define GPIO_O_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_O_INTERRUPT_CLEAR_04_0_DUAL                        0x0
#define GPIO_O_INTERRUPT_CLEAR_04_0_SCR                         GPIO_O_SCR_04_0
#define GPIO_O_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_O_INTERRUPT_CLEAR_04_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_04_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_O_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_04_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_O_INTERRUPT_CLEAR_04_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_O_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_O_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_O_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_O_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_O_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_O_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_O_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_O_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_O_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x15098

// Reserved address 0x1509c

// Register GPIO_O_ENABLE_CONFIG_05_0
#define GPIO_O_ENABLE_CONFIG_05_0                       _MK_ADDR_CONST(0x150a0)
#define GPIO_O_ENABLE_CONFIG_05_0_SECURE                        0x0
#define GPIO_O_ENABLE_CONFIG_05_0_DUAL                  0x0
#define GPIO_O_ENABLE_CONFIG_05_0_SCR                   GPIO_O_SCR_05_0
#define GPIO_O_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
#define GPIO_O_ENABLE_CONFIG_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_05_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_O_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_05_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_O_ENABLE_CONFIG_05_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_O_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_O_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_O_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_O_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_O_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_O_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_O_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_O_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
#define GPIO_O_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
#define GPIO_O_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_05_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_05_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_O_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_O_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_O_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_O_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_O_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_O_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_O_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_O_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_O_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_O_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_O_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_O_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_O_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_O_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_O_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_O_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_O_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_O_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_O_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_O_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_O_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_O_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_O_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_O_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_O_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_O_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_O_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_O_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_O_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_O_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_O_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_O_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_O_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_O_DEBOUNCE_THRESHOLD_05_0
#define GPIO_O_DEBOUNCE_THRESHOLD_05_0                  _MK_ADDR_CONST(0x150a4)
#define GPIO_O_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
#define GPIO_O_DEBOUNCE_THRESHOLD_05_0_DUAL                     0x0
#define GPIO_O_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_O_SCR_05_0
#define GPIO_O_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
#define GPIO_O_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_O_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_O_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_O_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_O_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_O_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_O_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_O_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_O_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_O_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_O_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_O_INPUT_05_0
#define GPIO_O_INPUT_05_0                       _MK_ADDR_CONST(0x150a8)
#define GPIO_O_INPUT_05_0_SECURE                        0x0
#define GPIO_O_INPUT_05_0_DUAL                  0x0
#define GPIO_O_INPUT_05_0_SCR                   GPIO_O_SCR_05_0
#define GPIO_O_INPUT_05_0_WORD_COUNT                    0x1
#define GPIO_O_INPUT_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_05_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_05_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_O_INPUT_05_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_05_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_O_INPUT_05_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_O_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_O_INPUT_05_0_GPIO_IN_RANGE                 0:0
#define GPIO_O_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_O_INPUT_05_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_05_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_O_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_O_OUTPUT_CONTROL_05_0
#define GPIO_O_OUTPUT_CONTROL_05_0                      _MK_ADDR_CONST(0x150ac)
#define GPIO_O_OUTPUT_CONTROL_05_0_SECURE                       0x0
#define GPIO_O_OUTPUT_CONTROL_05_0_DUAL                         0x0
#define GPIO_O_OUTPUT_CONTROL_05_0_SCR                  GPIO_O_SCR_05_0
#define GPIO_O_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
#define GPIO_O_OUTPUT_CONTROL_05_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_05_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_CONTROL_05_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_05_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_O_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_O_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_O_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_O_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_O_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_O_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_O_OUTPUT_VALUE_05_0
#define GPIO_O_OUTPUT_VALUE_05_0                        _MK_ADDR_CONST(0x150b0)
#define GPIO_O_OUTPUT_VALUE_05_0_SECURE                         0x0
#define GPIO_O_OUTPUT_VALUE_05_0_DUAL                   0x0
#define GPIO_O_OUTPUT_VALUE_05_0_SCR                    GPIO_O_SCR_05_0
#define GPIO_O_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
#define GPIO_O_OUTPUT_VALUE_05_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_05_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_05_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_VALUE_05_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_O_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_O_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_O_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_O_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_O_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_O_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_O_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_O_INTERRUPT_CLEAR_05_0
#define GPIO_O_INTERRUPT_CLEAR_05_0                     _MK_ADDR_CONST(0x150b4)
#define GPIO_O_INTERRUPT_CLEAR_05_0_SECURE                      0x0
#define GPIO_O_INTERRUPT_CLEAR_05_0_DUAL                        0x0
#define GPIO_O_INTERRUPT_CLEAR_05_0_SCR                         GPIO_O_SCR_05_0
#define GPIO_O_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
#define GPIO_O_INTERRUPT_CLEAR_05_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_05_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_O_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_05_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_O_INTERRUPT_CLEAR_05_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_O_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_O_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_O_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_O_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_O_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_O_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_O_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_O_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_O_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x150b8

// Reserved address 0x150bc

// Reserved address 0x150c0

// Reserved address 0x150c4

// Reserved address 0x150c8

// Reserved address 0x150cc

// Reserved address 0x150d0

// Reserved address 0x150d4

// Reserved address 0x150d8

// Reserved address 0x150dc

// Reserved address 0x150e0

// Reserved address 0x150e4

// Reserved address 0x150e8

// Reserved address 0x150ec

// Reserved address 0x150f0

// Reserved address 0x150f4

// Reserved address 0x150f8

// Reserved address 0x150fc

// Register GPIO_O_INTERRUPT_STATUS_G0_0
#define GPIO_O_INTERRUPT_STATUS_G0_0                    _MK_ADDR_CONST(0x15100)
#define GPIO_O_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_O_INTERRUPT_STATUS_G0_0_DUAL                       0x0
#define GPIO_O_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_O_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_O_INTERRUPT_STATUS_G0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G0_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_O_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G0_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_O_INTERRUPT_STATUS_G0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_O_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_O_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_O_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_O_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_O_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_O_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_O_INTERRUPT_STATUS_G1_0
#define GPIO_O_INTERRUPT_STATUS_G1_0                    _MK_ADDR_CONST(0x15104)
#define GPIO_O_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_O_INTERRUPT_STATUS_G1_0_DUAL                       0x0
#define GPIO_O_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_O_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_O_INTERRUPT_STATUS_G1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G1_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_O_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G1_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_O_INTERRUPT_STATUS_G1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_O_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_O_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_O_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_O_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_O_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_O_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_O_INTERRUPT_STATUS_G2_0
#define GPIO_O_INTERRUPT_STATUS_G2_0                    _MK_ADDR_CONST(0x15108)
#define GPIO_O_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_O_INTERRUPT_STATUS_G2_0_DUAL                       0x0
#define GPIO_O_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_O_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_O_INTERRUPT_STATUS_G2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G2_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_O_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G2_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_O_INTERRUPT_STATUS_G2_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_O_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_O_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_O_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_O_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_O_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_O_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_O_INTERRUPT_STATUS_G3_0
#define GPIO_O_INTERRUPT_STATUS_G3_0                    _MK_ADDR_CONST(0x1510c)
#define GPIO_O_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_O_INTERRUPT_STATUS_G3_0_DUAL                       0x0
#define GPIO_O_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_O_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_O_INTERRUPT_STATUS_G3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G3_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_O_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G3_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_O_INTERRUPT_STATUS_G3_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_O_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_O_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_O_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_O_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_O_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_O_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_O_INTERRUPT_STATUS_G4_0
#define GPIO_O_INTERRUPT_STATUS_G4_0                    _MK_ADDR_CONST(0x15110)
#define GPIO_O_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_O_INTERRUPT_STATUS_G4_0_DUAL                       0x0
#define GPIO_O_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_O_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_O_INTERRUPT_STATUS_G4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G4_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_O_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G4_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_O_INTERRUPT_STATUS_G4_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_O_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_O_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_O_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_O_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_O_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_O_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_O_INTERRUPT_STATUS_G5_0
#define GPIO_O_INTERRUPT_STATUS_G5_0                    _MK_ADDR_CONST(0x15114)
#define GPIO_O_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_O_INTERRUPT_STATUS_G5_0_DUAL                       0x0
#define GPIO_O_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_O_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_O_INTERRUPT_STATUS_G5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G5_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_O_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G5_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_O_INTERRUPT_STATUS_G5_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_O_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_O_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_O_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_O_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_O_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_O_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_O_INTERRUPT_STATUS_G6_0
#define GPIO_O_INTERRUPT_STATUS_G6_0                    _MK_ADDR_CONST(0x15118)
#define GPIO_O_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_O_INTERRUPT_STATUS_G6_0_DUAL                       0x0
#define GPIO_O_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_O_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_O_INTERRUPT_STATUS_G6_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G6_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_O_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G6_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_O_INTERRUPT_STATUS_G6_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_O_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_O_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_O_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_O_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_O_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_O_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_O_INTERRUPT_STATUS_G7_0
#define GPIO_O_INTERRUPT_STATUS_G7_0                    _MK_ADDR_CONST(0x1511c)
#define GPIO_O_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_O_INTERRUPT_STATUS_G7_0_DUAL                       0x0
#define GPIO_O_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_O_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_O_INTERRUPT_STATUS_G7_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G7_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_O_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G7_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_O_INTERRUPT_STATUS_G7_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_O_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_O_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_O_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_O_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_O_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_O_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_O_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Reserved address 0x15120

// Reserved address 0x15124

// Reserved address 0x15128

// Reserved address 0x1512c

// Reserved address 0x15130

// Reserved address 0x15134

// Reserved address 0x15138

// Reserved address 0x1513c

// Reserved address 0x15140

// Reserved address 0x15144

// Reserved address 0x15148

// Reserved address 0x1514c

// Reserved address 0x15150

// Reserved address 0x15154

// Reserved address 0x15158

// Reserved address 0x1515c

// Reserved address 0x15160

// Reserved address 0x15164

// Reserved address 0x15168

// Reserved address 0x1516c

// Reserved address 0x15170

// Reserved address 0x15174

// Reserved address 0x15178

// Reserved address 0x1517c

// Reserved address 0x15180

// Reserved address 0x15184

// Reserved address 0x15188

// Reserved address 0x1518c

// Reserved address 0x15190

// Reserved address 0x15194

// Reserved address 0x15198

// Reserved address 0x1519c

// Reserved address 0x151a0

// Reserved address 0x151a4

// Reserved address 0x151a8

// Reserved address 0x151ac

// Reserved address 0x151b0

// Reserved address 0x151b4

// Reserved address 0x151b8

// Reserved address 0x151bc

// Reserved address 0x151c0

// Reserved address 0x151c4

// Reserved address 0x151c8

// Reserved address 0x151cc

// Reserved address 0x151d0

// Reserved address 0x151d4

// Reserved address 0x151d8

// Reserved address 0x151dc

// Reserved address 0x151e0

// Reserved address 0x151e4

// Reserved address 0x151e8

// Reserved address 0x151ec

// Reserved address 0x151f0

// Reserved address 0x151f4

// Reserved address 0x151f8

// Reserved address 0x151fc

// Register GPIO_J_ENABLE_CONFIG_00_0
#define GPIO_J_ENABLE_CONFIG_00_0                       _MK_ADDR_CONST(0x15200)
#define GPIO_J_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_J_ENABLE_CONFIG_00_0_DUAL                  0x0
#define GPIO_J_ENABLE_CONFIG_00_0_SCR                   GPIO_J_SCR_00_0
#define GPIO_J_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_J_ENABLE_CONFIG_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_00_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_J_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_J_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_J_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_J_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_J_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_J_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_J_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_J_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_00_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_00_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_J_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_J_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_J_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_J_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_J_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_J_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_J_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_J_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_J_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_J_DEBOUNCE_THRESHOLD_00_0
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0                  _MK_ADDR_CONST(0x15204)
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_J_SCR_00_0
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_J_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_J_INPUT_00_0
#define GPIO_J_INPUT_00_0                       _MK_ADDR_CONST(0x15208)
#define GPIO_J_INPUT_00_0_SECURE                        0x0
#define GPIO_J_INPUT_00_0_DUAL                  0x0
#define GPIO_J_INPUT_00_0_SCR                   GPIO_J_SCR_00_0
#define GPIO_J_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_J_INPUT_00_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_00_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_00_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_00_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_00_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_J_INPUT_00_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_00_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_J_INPUT_00_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_J_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_J_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_J_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_J_INPUT_00_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_00_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_J_OUTPUT_CONTROL_00_0
#define GPIO_J_OUTPUT_CONTROL_00_0                      _MK_ADDR_CONST(0x1520c)
#define GPIO_J_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_J_OUTPUT_CONTROL_00_0_DUAL                         0x0
#define GPIO_J_OUTPUT_CONTROL_00_0_SCR                  GPIO_J_SCR_00_0
#define GPIO_J_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_J_OUTPUT_CONTROL_00_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_00_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_00_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_00_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_J_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_J_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_J_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_J_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_J_OUTPUT_VALUE_00_0
#define GPIO_J_OUTPUT_VALUE_00_0                        _MK_ADDR_CONST(0x15210)
#define GPIO_J_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_J_OUTPUT_VALUE_00_0_DUAL                   0x0
#define GPIO_J_OUTPUT_VALUE_00_0_SCR                    GPIO_J_SCR_00_0
#define GPIO_J_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_J_OUTPUT_VALUE_00_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_00_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_00_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_00_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_J_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_J_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_J_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_J_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_J_INTERRUPT_CLEAR_00_0
#define GPIO_J_INTERRUPT_CLEAR_00_0                     _MK_ADDR_CONST(0x15214)
#define GPIO_J_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_J_INTERRUPT_CLEAR_00_0_DUAL                        0x0
#define GPIO_J_INTERRUPT_CLEAR_00_0_SCR                         GPIO_J_SCR_00_0
#define GPIO_J_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_J_INTERRUPT_CLEAR_00_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_00_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_00_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_00_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_J_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_J_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_J_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_J_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_J_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x15218

// Reserved address 0x1521c

// Register GPIO_J_ENABLE_CONFIG_01_0
#define GPIO_J_ENABLE_CONFIG_01_0                       _MK_ADDR_CONST(0x15220)
#define GPIO_J_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_J_ENABLE_CONFIG_01_0_DUAL                  0x0
#define GPIO_J_ENABLE_CONFIG_01_0_SCR                   GPIO_J_SCR_01_0
#define GPIO_J_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_J_ENABLE_CONFIG_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_01_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_J_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_J_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_J_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_J_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_J_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_J_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_J_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_J_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_01_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_01_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_J_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_J_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_J_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_J_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_J_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_J_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_J_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_J_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_J_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_J_DEBOUNCE_THRESHOLD_01_0
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0                  _MK_ADDR_CONST(0x15224)
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_J_SCR_01_0
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_J_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_J_INPUT_01_0
#define GPIO_J_INPUT_01_0                       _MK_ADDR_CONST(0x15228)
#define GPIO_J_INPUT_01_0_SECURE                        0x0
#define GPIO_J_INPUT_01_0_DUAL                  0x0
#define GPIO_J_INPUT_01_0_SCR                   GPIO_J_SCR_01_0
#define GPIO_J_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_J_INPUT_01_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_01_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_01_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_01_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_01_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_J_INPUT_01_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_01_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_J_INPUT_01_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_J_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_J_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_J_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_J_INPUT_01_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_01_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_J_OUTPUT_CONTROL_01_0
#define GPIO_J_OUTPUT_CONTROL_01_0                      _MK_ADDR_CONST(0x1522c)
#define GPIO_J_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_J_OUTPUT_CONTROL_01_0_DUAL                         0x0
#define GPIO_J_OUTPUT_CONTROL_01_0_SCR                  GPIO_J_SCR_01_0
#define GPIO_J_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_J_OUTPUT_CONTROL_01_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_01_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_01_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_01_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_J_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_J_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_J_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_J_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_J_OUTPUT_VALUE_01_0
#define GPIO_J_OUTPUT_VALUE_01_0                        _MK_ADDR_CONST(0x15230)
#define GPIO_J_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_J_OUTPUT_VALUE_01_0_DUAL                   0x0
#define GPIO_J_OUTPUT_VALUE_01_0_SCR                    GPIO_J_SCR_01_0
#define GPIO_J_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_J_OUTPUT_VALUE_01_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_01_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_01_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_01_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_J_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_J_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_J_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_J_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_J_INTERRUPT_CLEAR_01_0
#define GPIO_J_INTERRUPT_CLEAR_01_0                     _MK_ADDR_CONST(0x15234)
#define GPIO_J_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_J_INTERRUPT_CLEAR_01_0_DUAL                        0x0
#define GPIO_J_INTERRUPT_CLEAR_01_0_SCR                         GPIO_J_SCR_01_0
#define GPIO_J_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_J_INTERRUPT_CLEAR_01_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_01_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_01_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_01_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_J_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_J_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_J_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_J_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_J_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x15238

// Reserved address 0x1523c

// Register GPIO_J_ENABLE_CONFIG_02_0
#define GPIO_J_ENABLE_CONFIG_02_0                       _MK_ADDR_CONST(0x15240)
#define GPIO_J_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_J_ENABLE_CONFIG_02_0_DUAL                  0x0
#define GPIO_J_ENABLE_CONFIG_02_0_SCR                   GPIO_J_SCR_02_0
#define GPIO_J_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_J_ENABLE_CONFIG_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_02_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_J_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_J_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_J_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_J_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_J_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_J_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_J_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_J_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_02_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_02_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_J_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_J_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_J_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_J_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_J_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_J_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_J_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_J_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_J_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_J_DEBOUNCE_THRESHOLD_02_0
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0                  _MK_ADDR_CONST(0x15244)
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_J_SCR_02_0
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_J_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_J_INPUT_02_0
#define GPIO_J_INPUT_02_0                       _MK_ADDR_CONST(0x15248)
#define GPIO_J_INPUT_02_0_SECURE                        0x0
#define GPIO_J_INPUT_02_0_DUAL                  0x0
#define GPIO_J_INPUT_02_0_SCR                   GPIO_J_SCR_02_0
#define GPIO_J_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_J_INPUT_02_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_02_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_02_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_02_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_02_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_J_INPUT_02_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_02_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_J_INPUT_02_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_J_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_J_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_J_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_J_INPUT_02_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_02_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_J_OUTPUT_CONTROL_02_0
#define GPIO_J_OUTPUT_CONTROL_02_0                      _MK_ADDR_CONST(0x1524c)
#define GPIO_J_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_J_OUTPUT_CONTROL_02_0_DUAL                         0x0
#define GPIO_J_OUTPUT_CONTROL_02_0_SCR                  GPIO_J_SCR_02_0
#define GPIO_J_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_J_OUTPUT_CONTROL_02_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_02_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_02_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_02_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_J_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_J_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_J_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_J_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_J_OUTPUT_VALUE_02_0
#define GPIO_J_OUTPUT_VALUE_02_0                        _MK_ADDR_CONST(0x15250)
#define GPIO_J_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_J_OUTPUT_VALUE_02_0_DUAL                   0x0
#define GPIO_J_OUTPUT_VALUE_02_0_SCR                    GPIO_J_SCR_02_0
#define GPIO_J_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_J_OUTPUT_VALUE_02_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_02_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_02_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_02_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_J_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_J_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_J_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_J_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_J_INTERRUPT_CLEAR_02_0
#define GPIO_J_INTERRUPT_CLEAR_02_0                     _MK_ADDR_CONST(0x15254)
#define GPIO_J_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_J_INTERRUPT_CLEAR_02_0_DUAL                        0x0
#define GPIO_J_INTERRUPT_CLEAR_02_0_SCR                         GPIO_J_SCR_02_0
#define GPIO_J_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_J_INTERRUPT_CLEAR_02_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_02_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_02_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_02_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_J_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_J_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_J_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_J_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_J_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x15258

// Reserved address 0x1525c

// Register GPIO_J_ENABLE_CONFIG_03_0
#define GPIO_J_ENABLE_CONFIG_03_0                       _MK_ADDR_CONST(0x15260)
#define GPIO_J_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_J_ENABLE_CONFIG_03_0_DUAL                  0x0
#define GPIO_J_ENABLE_CONFIG_03_0_SCR                   GPIO_J_SCR_03_0
#define GPIO_J_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_J_ENABLE_CONFIG_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_03_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_J_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_J_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_J_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_J_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_J_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_J_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_J_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_J_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_03_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_03_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_J_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_J_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_J_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_J_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_J_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_J_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_J_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_J_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_J_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_J_DEBOUNCE_THRESHOLD_03_0
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0                  _MK_ADDR_CONST(0x15264)
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_J_SCR_03_0
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_J_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_J_INPUT_03_0
#define GPIO_J_INPUT_03_0                       _MK_ADDR_CONST(0x15268)
#define GPIO_J_INPUT_03_0_SECURE                        0x0
#define GPIO_J_INPUT_03_0_DUAL                  0x0
#define GPIO_J_INPUT_03_0_SCR                   GPIO_J_SCR_03_0
#define GPIO_J_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_J_INPUT_03_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_03_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_03_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_03_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_03_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_J_INPUT_03_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_03_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_J_INPUT_03_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_J_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_J_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_J_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_J_INPUT_03_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_03_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_J_OUTPUT_CONTROL_03_0
#define GPIO_J_OUTPUT_CONTROL_03_0                      _MK_ADDR_CONST(0x1526c)
#define GPIO_J_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_J_OUTPUT_CONTROL_03_0_DUAL                         0x0
#define GPIO_J_OUTPUT_CONTROL_03_0_SCR                  GPIO_J_SCR_03_0
#define GPIO_J_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_J_OUTPUT_CONTROL_03_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_03_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_03_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_03_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_J_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_J_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_J_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_J_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_J_OUTPUT_VALUE_03_0
#define GPIO_J_OUTPUT_VALUE_03_0                        _MK_ADDR_CONST(0x15270)
#define GPIO_J_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_J_OUTPUT_VALUE_03_0_DUAL                   0x0
#define GPIO_J_OUTPUT_VALUE_03_0_SCR                    GPIO_J_SCR_03_0
#define GPIO_J_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_J_OUTPUT_VALUE_03_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_03_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_03_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_03_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_J_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_J_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_J_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_J_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_J_INTERRUPT_CLEAR_03_0
#define GPIO_J_INTERRUPT_CLEAR_03_0                     _MK_ADDR_CONST(0x15274)
#define GPIO_J_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_J_INTERRUPT_CLEAR_03_0_DUAL                        0x0
#define GPIO_J_INTERRUPT_CLEAR_03_0_SCR                         GPIO_J_SCR_03_0
#define GPIO_J_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_J_INTERRUPT_CLEAR_03_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_03_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_03_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_03_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_J_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_J_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_J_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_J_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_J_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x15278

// Reserved address 0x1527c

// Register GPIO_J_ENABLE_CONFIG_04_0
#define GPIO_J_ENABLE_CONFIG_04_0                       _MK_ADDR_CONST(0x15280)
#define GPIO_J_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_J_ENABLE_CONFIG_04_0_DUAL                  0x0
#define GPIO_J_ENABLE_CONFIG_04_0_SCR                   GPIO_J_SCR_04_0
#define GPIO_J_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_J_ENABLE_CONFIG_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_04_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_J_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_J_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_J_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_J_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_J_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_J_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_J_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_J_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_04_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_04_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_J_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_J_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_J_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_J_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_J_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_J_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_J_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_J_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_J_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_J_DEBOUNCE_THRESHOLD_04_0
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0                  _MK_ADDR_CONST(0x15284)
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_DUAL                     0x0
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_J_SCR_04_0
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_J_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_J_INPUT_04_0
#define GPIO_J_INPUT_04_0                       _MK_ADDR_CONST(0x15288)
#define GPIO_J_INPUT_04_0_SECURE                        0x0
#define GPIO_J_INPUT_04_0_DUAL                  0x0
#define GPIO_J_INPUT_04_0_SCR                   GPIO_J_SCR_04_0
#define GPIO_J_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_J_INPUT_04_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_04_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_04_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_04_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_04_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_J_INPUT_04_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_04_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_J_INPUT_04_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_J_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_J_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_J_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_J_INPUT_04_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_04_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_J_OUTPUT_CONTROL_04_0
#define GPIO_J_OUTPUT_CONTROL_04_0                      _MK_ADDR_CONST(0x1528c)
#define GPIO_J_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_J_OUTPUT_CONTROL_04_0_DUAL                         0x0
#define GPIO_J_OUTPUT_CONTROL_04_0_SCR                  GPIO_J_SCR_04_0
#define GPIO_J_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_J_OUTPUT_CONTROL_04_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_04_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_04_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_04_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_J_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_J_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_J_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_J_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_J_OUTPUT_VALUE_04_0
#define GPIO_J_OUTPUT_VALUE_04_0                        _MK_ADDR_CONST(0x15290)
#define GPIO_J_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_J_OUTPUT_VALUE_04_0_DUAL                   0x0
#define GPIO_J_OUTPUT_VALUE_04_0_SCR                    GPIO_J_SCR_04_0
#define GPIO_J_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_J_OUTPUT_VALUE_04_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_04_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_04_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_04_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_J_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_J_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_J_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_J_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_J_INTERRUPT_CLEAR_04_0
#define GPIO_J_INTERRUPT_CLEAR_04_0                     _MK_ADDR_CONST(0x15294)
#define GPIO_J_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_J_INTERRUPT_CLEAR_04_0_DUAL                        0x0
#define GPIO_J_INTERRUPT_CLEAR_04_0_SCR                         GPIO_J_SCR_04_0
#define GPIO_J_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_J_INTERRUPT_CLEAR_04_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_04_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_04_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_04_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_J_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_J_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_J_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_J_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_J_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x15298

// Reserved address 0x1529c

// Register GPIO_J_ENABLE_CONFIG_05_0
#define GPIO_J_ENABLE_CONFIG_05_0                       _MK_ADDR_CONST(0x152a0)
#define GPIO_J_ENABLE_CONFIG_05_0_SECURE                        0x0
#define GPIO_J_ENABLE_CONFIG_05_0_DUAL                  0x0
#define GPIO_J_ENABLE_CONFIG_05_0_SCR                   GPIO_J_SCR_05_0
#define GPIO_J_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
#define GPIO_J_ENABLE_CONFIG_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_05_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_J_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_J_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_J_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_J_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  _MK_SHIFT_CONST(1)
#define GPIO_J_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_J_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
#define GPIO_J_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
#define GPIO_J_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_05_0_IN_OUT_IN                     _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_05_0_IN_OUT_OUT                    _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    _MK_SHIFT_CONST(2)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    _MK_FIELD_CONST(0x3, GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    _MK_ENUM_CONST(1)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      _MK_ENUM_CONST(2)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      _MK_ENUM_CONST(3)

#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   _MK_SHIFT_CONST(4)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       _MK_SHIFT_CONST(5)
#define GPIO_J_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_J_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_J_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      _MK_SHIFT_CONST(6)
#define GPIO_J_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_J_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_J_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     _MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   _MK_SHIFT_CONST(7)
#define GPIO_J_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   _MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_J_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_J_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 _MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  _MK_ENUM_CONST(1)


// Register GPIO_J_DEBOUNCE_THRESHOLD_05_0
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0                  _MK_ADDR_CONST(0x152a4)
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_DUAL                     0x0
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_J_SCR_05_0
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 _MK_FIELD_CONST(0xff, GPIO_J_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_J_INPUT_05_0
#define GPIO_J_INPUT_05_0                       _MK_ADDR_CONST(0x152a8)
#define GPIO_J_INPUT_05_0_SECURE                        0x0
#define GPIO_J_INPUT_05_0_DUAL                  0x0
#define GPIO_J_INPUT_05_0_SCR                   GPIO_J_SCR_05_0
#define GPIO_J_INPUT_05_0_WORD_COUNT                    0x1
#define GPIO_J_INPUT_05_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_05_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_05_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_05_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_05_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_J_INPUT_05_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_05_0_GPIO_IN_SHIFT                 _MK_SHIFT_CONST(0)
#define GPIO_J_INPUT_05_0_GPIO_IN_FIELD                 _MK_FIELD_CONST(0x1, GPIO_J_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_J_INPUT_05_0_GPIO_IN_RANGE                 0:0
#define GPIO_J_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_J_INPUT_05_0_GPIO_IN_DEFAULT                       _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_05_0_GPIO_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register GPIO_J_OUTPUT_CONTROL_05_0
#define GPIO_J_OUTPUT_CONTROL_05_0                      _MK_ADDR_CONST(0x152ac)
#define GPIO_J_OUTPUT_CONTROL_05_0_SECURE                       0x0
#define GPIO_J_OUTPUT_CONTROL_05_0_DUAL                         0x0
#define GPIO_J_OUTPUT_CONTROL_05_0_SCR                  GPIO_J_SCR_05_0
#define GPIO_J_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
#define GPIO_J_OUTPUT_CONTROL_05_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_05_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_05_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_05_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       _MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       _MK_FIELD_CONST(0x1, GPIO_J_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_J_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_J_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_J_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      _MK_ENUM_CONST(0)
#define GPIO_J_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     _MK_ENUM_CONST(1)


// Register GPIO_J_OUTPUT_VALUE_05_0
#define GPIO_J_OUTPUT_VALUE_05_0                        _MK_ADDR_CONST(0x152b0)
#define GPIO_J_OUTPUT_VALUE_05_0_SECURE                         0x0
#define GPIO_J_OUTPUT_VALUE_05_0_DUAL                   0x0
#define GPIO_J_OUTPUT_VALUE_05_0_SCR                    GPIO_J_SCR_05_0
#define GPIO_J_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
#define GPIO_J_OUTPUT_VALUE_05_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_05_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_05_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_05_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     _MK_FIELD_CONST(0x1, GPIO_J_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_J_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_J_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_J_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register GPIO_J_INTERRUPT_CLEAR_05_0
#define GPIO_J_INTERRUPT_CLEAR_05_0                     _MK_ADDR_CONST(0x152b4)
#define GPIO_J_INTERRUPT_CLEAR_05_0_SECURE                      0x0
#define GPIO_J_INTERRUPT_CLEAR_05_0_DUAL                        0x0
#define GPIO_J_INTERRUPT_CLEAR_05_0_SCR                         GPIO_J_SCR_05_0
#define GPIO_J_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
#define GPIO_J_INTERRUPT_CLEAR_05_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_05_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_05_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_05_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  _MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  _MK_FIELD_CONST(0x1, GPIO_J_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_J_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_J_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_J_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      _MK_ENUM_CONST(0)
#define GPIO_J_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  _MK_ENUM_CONST(1)


// Reserved address 0x152b8

// Reserved address 0x152bc

// Reserved address 0x152c0

// Reserved address 0x152c4

// Reserved address 0x152c8

// Reserved address 0x152cc

// Reserved address 0x152d0

// Reserved address 0x152d4

// Reserved address 0x152d8

// Reserved address 0x152dc

// Reserved address 0x152e0

// Reserved address 0x152e4

// Reserved address 0x152e8

// Reserved address 0x152ec

// Reserved address 0x152f0

// Reserved address 0x152f4

// Reserved address 0x152f8

// Reserved address 0x152fc

// Register GPIO_J_INTERRUPT_STATUS_G0_0
#define GPIO_J_INTERRUPT_STATUS_G0_0                    _MK_ADDR_CONST(0x15300)
#define GPIO_J_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_J_INTERRUPT_STATUS_G0_0_DUAL                       0x0
#define GPIO_J_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_J_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_J_INTERRUPT_STATUS_G0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G0_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_J_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G0_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_J_INTERRUPT_STATUS_G0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_J_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_J_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_J_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_J_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_J_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_J_INTERRUPT_STATUS_G1_0
#define GPIO_J_INTERRUPT_STATUS_G1_0                    _MK_ADDR_CONST(0x15304)
#define GPIO_J_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_J_INTERRUPT_STATUS_G1_0_DUAL                       0x0
#define GPIO_J_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_J_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_J_INTERRUPT_STATUS_G1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G1_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_J_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G1_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_J_INTERRUPT_STATUS_G1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_J_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_J_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_J_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_J_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_J_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_J_INTERRUPT_STATUS_G2_0
#define GPIO_J_INTERRUPT_STATUS_G2_0                    _MK_ADDR_CONST(0x15308)
#define GPIO_J_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_J_INTERRUPT_STATUS_G2_0_DUAL                       0x0
#define GPIO_J_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_J_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_J_INTERRUPT_STATUS_G2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G2_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_J_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G2_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_J_INTERRUPT_STATUS_G2_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_J_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_J_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_J_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_J_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_J_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_J_INTERRUPT_STATUS_G3_0
#define GPIO_J_INTERRUPT_STATUS_G3_0                    _MK_ADDR_CONST(0x1530c)
#define GPIO_J_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_J_INTERRUPT_STATUS_G3_0_DUAL                       0x0
#define GPIO_J_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_J_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_J_INTERRUPT_STATUS_G3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G3_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_J_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G3_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_J_INTERRUPT_STATUS_G3_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_J_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_J_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_J_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_J_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_J_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_J_INTERRUPT_STATUS_G4_0
#define GPIO_J_INTERRUPT_STATUS_G4_0                    _MK_ADDR_CONST(0x15310)
#define GPIO_J_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_J_INTERRUPT_STATUS_G4_0_DUAL                       0x0
#define GPIO_J_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_J_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_J_INTERRUPT_STATUS_G4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G4_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_J_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G4_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_J_INTERRUPT_STATUS_G4_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_J_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_J_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_J_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_J_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_J_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_J_INTERRUPT_STATUS_G5_0
#define GPIO_J_INTERRUPT_STATUS_G5_0                    _MK_ADDR_CONST(0x15314)
#define GPIO_J_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_J_INTERRUPT_STATUS_G5_0_DUAL                       0x0
#define GPIO_J_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_J_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_J_INTERRUPT_STATUS_G5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G5_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_J_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G5_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_J_INTERRUPT_STATUS_G5_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_J_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_J_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_J_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_J_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_J_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_J_INTERRUPT_STATUS_G6_0
#define GPIO_J_INTERRUPT_STATUS_G6_0                    _MK_ADDR_CONST(0x15318)
#define GPIO_J_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_J_INTERRUPT_STATUS_G6_0_DUAL                       0x0
#define GPIO_J_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_J_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_J_INTERRUPT_STATUS_G6_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G6_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_J_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G6_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_J_INTERRUPT_STATUS_G6_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_J_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_J_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_J_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_J_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_J_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register GPIO_J_INTERRUPT_STATUS_G7_0
#define GPIO_J_INTERRUPT_STATUS_G7_0                    _MK_ADDR_CONST(0x1531c)
#define GPIO_J_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_J_INTERRUPT_STATUS_G7_0_DUAL                       0x0
#define GPIO_J_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_J_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_J_INTERRUPT_STATUS_G7_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G7_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define GPIO_J_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G7_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define GPIO_J_INTERRUPT_STATUS_G7_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        _MK_FIELD_CONST(0x3f, GPIO_J_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_J_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_J_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_J_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define GPIO_J_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Reserved address 0x15320

// Reserved address 0x15324

// Reserved address 0x15328

// Reserved address 0x1532c

// Reserved address 0x15330

// Reserved address 0x15334

// Reserved address 0x15338

// Reserved address 0x1533c

// Reserved address 0x15340

// Reserved address 0x15344

// Reserved address 0x15348

// Reserved address 0x1534c

// Reserved address 0x15350

// Reserved address 0x15354

// Reserved address 0x15358

// Reserved address 0x1535c

// Reserved address 0x15360

// Reserved address 0x15364

// Reserved address 0x15368

// Reserved address 0x1536c

// Reserved address 0x15370

// Reserved address 0x15374

// Reserved address 0x15378

// Reserved address 0x1537c

// Reserved address 0x15380

// Reserved address 0x15384

// Reserved address 0x15388

// Reserved address 0x1538c

// Reserved address 0x15390

// Reserved address 0x15394

// Reserved address 0x15398

// Reserved address 0x1539c

// Reserved address 0x153a0

// Reserved address 0x153a4

// Reserved address 0x153a8

// Reserved address 0x153ac

// Reserved address 0x153b0

// Reserved address 0x153b4

// Reserved address 0x153b8

// Reserved address 0x153bc

// Reserved address 0x153c0

// Reserved address 0x153c4

// Reserved address 0x153c8

// Reserved address 0x153cc

// Reserved address 0x153d0

// Reserved address 0x153d4

// Reserved address 0x153d8

// Reserved address 0x153dc

// Reserved address 0x153e0

// Reserved address 0x153e4

// Reserved address 0x153e8

// Reserved address 0x153ec

// Reserved address 0x153f0

// Reserved address 0x153f4

// Reserved address 0x153f8

// Reserved address 0x153fc

//
// REGISTER LIST
//
#define LIST_ARGPIO_REGS(_op_) \
_op_(GPIO_GG_VM_00_0) \
_op_(GPIO_GG_SCR_00_0) \
_op_(GPIO_GG_VM_01_0) \
_op_(GPIO_GG_SCR_01_0) \
_op_(GPIO_CTL0_VM_SCR_0) \
_op_(GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0) \
_op_(GPIO_CTL0_INTERRUPT_STATUS_VM_0) \
_op_(GPIO_CTL0_SCR_0) \
_op_(GPIO_CTL0_ICG_EN_OVERRIDE_0) \
_op_(GPIO_GG_INT0_ROUTE_MAPPING_0) \
_op_(GPIO_GG_INT1_ROUTE_MAPPING_0) \
_op_(GPIO_GG_INT2_ROUTE_MAPPING_0) \
_op_(GPIO_GG_INT3_ROUTE_MAPPING_0) \
_op_(GPIO_GG_INT4_ROUTE_MAPPING_0) \
_op_(GPIO_GG_INT5_ROUTE_MAPPING_0) \
_op_(GPIO_GG_INT6_ROUTE_MAPPING_0) \
_op_(GPIO_GG_INT7_ROUTE_MAPPING_0) \
_op_(GPIO_CTL0_SPARE_0) \
_op_(GPIO_V_VM_00_0) \
_op_(GPIO_V_SCR_00_0) \
_op_(GPIO_V_VM_01_0) \
_op_(GPIO_V_SCR_01_0) \
_op_(GPIO_V_VM_02_0) \
_op_(GPIO_V_SCR_02_0) \
_op_(GPIO_V_VM_03_0) \
_op_(GPIO_V_SCR_03_0) \
_op_(GPIO_V_VM_04_0) \
_op_(GPIO_V_SCR_04_0) \
_op_(GPIO_V_VM_05_0) \
_op_(GPIO_V_SCR_05_0) \
_op_(GPIO_V_VM_06_0) \
_op_(GPIO_V_SCR_06_0) \
_op_(GPIO_V_VM_07_0) \
_op_(GPIO_V_SCR_07_0) \
_op_(GPIO_W_VM_00_0) \
_op_(GPIO_W_SCR_00_0) \
_op_(GPIO_W_VM_01_0) \
_op_(GPIO_W_SCR_01_0) \
_op_(GPIO_A_VM_00_0) \
_op_(GPIO_A_SCR_00_0) \
_op_(GPIO_A_VM_01_0) \
_op_(GPIO_A_SCR_01_0) \
_op_(GPIO_A_VM_02_0) \
_op_(GPIO_A_SCR_02_0) \
_op_(GPIO_A_VM_03_0) \
_op_(GPIO_A_SCR_03_0) \
_op_(GPIO_A_VM_04_0) \
_op_(GPIO_A_SCR_04_0) \
_op_(GPIO_A_VM_05_0) \
_op_(GPIO_A_SCR_05_0) \
_op_(GPIO_A_VM_06_0) \
_op_(GPIO_A_SCR_06_0) \
_op_(GPIO_A_VM_07_0) \
_op_(GPIO_A_SCR_07_0) \
_op_(GPIO_CTL1_VM_SCR_0) \
_op_(GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0) \
_op_(GPIO_CTL1_INTERRUPT_STATUS_VM_0) \
_op_(GPIO_CTL1_SCR_0) \
_op_(GPIO_CTL1_ICG_EN_OVERRIDE_0) \
_op_(GPIO_V_INT0_ROUTE_MAPPING_0) \
_op_(GPIO_V_INT1_ROUTE_MAPPING_0) \
_op_(GPIO_V_INT2_ROUTE_MAPPING_0) \
_op_(GPIO_V_INT3_ROUTE_MAPPING_0) \
_op_(GPIO_V_INT4_ROUTE_MAPPING_0) \
_op_(GPIO_V_INT5_ROUTE_MAPPING_0) \
_op_(GPIO_V_INT6_ROUTE_MAPPING_0) \
_op_(GPIO_V_INT7_ROUTE_MAPPING_0) \
_op_(GPIO_W_INT0_ROUTE_MAPPING_0) \
_op_(GPIO_W_INT1_ROUTE_MAPPING_0) \
_op_(GPIO_W_INT2_ROUTE_MAPPING_0) \
_op_(GPIO_W_INT3_ROUTE_MAPPING_0) \
_op_(GPIO_W_INT4_ROUTE_MAPPING_0) \
_op_(GPIO_W_INT5_ROUTE_MAPPING_0) \
_op_(GPIO_W_INT6_ROUTE_MAPPING_0) \
_op_(GPIO_W_INT7_ROUTE_MAPPING_0) \
_op_(GPIO_A_INT0_ROUTE_MAPPING_0) \
_op_(GPIO_A_INT1_ROUTE_MAPPING_0) \
_op_(GPIO_A_INT2_ROUTE_MAPPING_0) \
_op_(GPIO_A_INT3_ROUTE_MAPPING_0) \
_op_(GPIO_A_INT4_ROUTE_MAPPING_0) \
_op_(GPIO_A_INT5_ROUTE_MAPPING_0) \
_op_(GPIO_A_INT6_ROUTE_MAPPING_0) \
_op_(GPIO_A_INT7_ROUTE_MAPPING_0) \
_op_(GPIO_CTL1_SPARE_0) \
_op_(GPIO_X_VM_00_0) \
_op_(GPIO_X_SCR_00_0) \
_op_(GPIO_X_VM_01_0) \
_op_(GPIO_X_SCR_01_0) \
_op_(GPIO_X_VM_02_0) \
_op_(GPIO_X_SCR_02_0) \
_op_(GPIO_X_VM_03_0) \
_op_(GPIO_X_SCR_03_0) \
_op_(GPIO_X_VM_04_0) \
_op_(GPIO_X_SCR_04_0) \
_op_(GPIO_X_VM_05_0) \
_op_(GPIO_X_SCR_05_0) \
_op_(GPIO_X_VM_06_0) \
_op_(GPIO_X_SCR_06_0) \
_op_(GPIO_X_VM_07_0) \
_op_(GPIO_X_SCR_07_0) \
_op_(GPIO_Y_VM_00_0) \
_op_(GPIO_Y_SCR_00_0) \
_op_(GPIO_Y_VM_01_0) \
_op_(GPIO_Y_SCR_01_0) \
_op_(GPIO_Y_VM_02_0) \
_op_(GPIO_Y_SCR_02_0) \
_op_(GPIO_Y_VM_03_0) \
_op_(GPIO_Y_SCR_03_0) \
_op_(GPIO_Y_VM_04_0) \
_op_(GPIO_Y_SCR_04_0) \
_op_(GPIO_Y_VM_05_0) \
_op_(GPIO_Y_SCR_05_0) \
_op_(GPIO_Y_VM_06_0) \
_op_(GPIO_Y_SCR_06_0) \
_op_(GPIO_Y_VM_07_0) \
_op_(GPIO_Y_SCR_07_0) \
_op_(GPIO_Z_VM_00_0) \
_op_(GPIO_Z_SCR_00_0) \
_op_(GPIO_Z_VM_01_0) \
_op_(GPIO_Z_SCR_01_0) \
_op_(GPIO_Z_VM_02_0) \
_op_(GPIO_Z_SCR_02_0) \
_op_(GPIO_Z_VM_03_0) \
_op_(GPIO_Z_SCR_03_0) \
_op_(GPIO_Z_VM_04_0) \
_op_(GPIO_Z_SCR_04_0) \
_op_(GPIO_Z_VM_05_0) \
_op_(GPIO_Z_SCR_05_0) \
_op_(GPIO_Z_VM_06_0) \
_op_(GPIO_Z_SCR_06_0) \
_op_(GPIO_Z_VM_07_0) \
_op_(GPIO_Z_SCR_07_0) \
_op_(GPIO_M_VM_00_0) \
_op_(GPIO_M_SCR_00_0) \
_op_(GPIO_M_VM_01_0) \
_op_(GPIO_M_SCR_01_0) \
_op_(GPIO_M_VM_02_0) \
_op_(GPIO_M_SCR_02_0) \
_op_(GPIO_M_VM_03_0) \
_op_(GPIO_M_SCR_03_0) \
_op_(GPIO_M_VM_04_0) \
_op_(GPIO_M_SCR_04_0) \
_op_(GPIO_M_VM_05_0) \
_op_(GPIO_M_SCR_05_0) \
_op_(GPIO_M_VM_06_0) \
_op_(GPIO_M_SCR_06_0) \
_op_(GPIO_M_VM_07_0) \
_op_(GPIO_M_SCR_07_0) \
_op_(GPIO_N_VM_00_0) \
_op_(GPIO_N_SCR_00_0) \
_op_(GPIO_N_VM_01_0) \
_op_(GPIO_N_SCR_01_0) \
_op_(GPIO_N_VM_02_0) \
_op_(GPIO_N_SCR_02_0) \
_op_(GPIO_P_VM_00_0) \
_op_(GPIO_P_SCR_00_0) \
_op_(GPIO_P_VM_01_0) \
_op_(GPIO_P_SCR_01_0) \
_op_(GPIO_P_VM_02_0) \
_op_(GPIO_P_SCR_02_0) \
_op_(GPIO_P_VM_03_0) \
_op_(GPIO_P_SCR_03_0) \
_op_(GPIO_P_VM_04_0) \
_op_(GPIO_P_SCR_04_0) \
_op_(GPIO_P_VM_05_0) \
_op_(GPIO_P_SCR_05_0) \
_op_(GPIO_P_VM_06_0) \
_op_(GPIO_P_SCR_06_0) \
_op_(GPIO_P_VM_07_0) \
_op_(GPIO_P_SCR_07_0) \
_op_(GPIO_Q_VM_00_0) \
_op_(GPIO_Q_SCR_00_0) \
_op_(GPIO_Q_VM_01_0) \
_op_(GPIO_Q_SCR_01_0) \
_op_(GPIO_Q_VM_02_0) \
_op_(GPIO_Q_SCR_02_0) \
_op_(GPIO_Q_VM_03_0) \
_op_(GPIO_Q_SCR_03_0) \
_op_(GPIO_Q_VM_04_0) \
_op_(GPIO_Q_SCR_04_0) \
_op_(GPIO_Q_VM_05_0) \
_op_(GPIO_Q_SCR_05_0) \
_op_(GPIO_Q_VM_06_0) \
_op_(GPIO_Q_SCR_06_0) \
_op_(GPIO_Q_VM_07_0) \
_op_(GPIO_Q_SCR_07_0) \
_op_(GPIO_R_VM_00_0) \
_op_(GPIO_R_SCR_00_0) \
_op_(GPIO_R_VM_01_0) \
_op_(GPIO_R_SCR_01_0) \
_op_(GPIO_R_VM_02_0) \
_op_(GPIO_R_SCR_02_0) \
_op_(GPIO_R_VM_03_0) \
_op_(GPIO_R_SCR_03_0) \
_op_(GPIO_R_VM_04_0) \
_op_(GPIO_R_SCR_04_0) \
_op_(GPIO_R_VM_05_0) \
_op_(GPIO_R_SCR_05_0) \
_op_(GPIO_CTL2_VM_SCR_0) \
_op_(GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0) \
_op_(GPIO_CTL2_INTERRUPT_STATUS_VM_0) \
_op_(GPIO_CTL2_SCR_0) \
_op_(GPIO_CTL2_ICG_EN_OVERRIDE_0) \
_op_(GPIO_X_INT0_ROUTE_MAPPING_0) \
_op_(GPIO_X_INT1_ROUTE_MAPPING_0) \
_op_(GPIO_X_INT2_ROUTE_MAPPING_0) \
_op_(GPIO_X_INT3_ROUTE_MAPPING_0) \
_op_(GPIO_X_INT4_ROUTE_MAPPING_0) \
_op_(GPIO_X_INT5_ROUTE_MAPPING_0) \
_op_(GPIO_X_INT6_ROUTE_MAPPING_0) \
_op_(GPIO_X_INT7_ROUTE_MAPPING_0) \
_op_(GPIO_Y_INT0_ROUTE_MAPPING_0) \
_op_(GPIO_Y_INT1_ROUTE_MAPPING_0) \
_op_(GPIO_Y_INT2_ROUTE_MAPPING_0) \
_op_(GPIO_Y_INT3_ROUTE_MAPPING_0) \
_op_(GPIO_Y_INT4_ROUTE_MAPPING_0) \
_op_(GPIO_Y_INT5_ROUTE_MAPPING_0) \
_op_(GPIO_Y_INT6_ROUTE_MAPPING_0) \
_op_(GPIO_Y_INT7_ROUTE_MAPPING_0) \
_op_(GPIO_Z_INT0_ROUTE_MAPPING_0) \
_op_(GPIO_Z_INT1_ROUTE_MAPPING_0) \
_op_(GPIO_Z_INT2_ROUTE_MAPPING_0) \
_op_(GPIO_Z_INT3_ROUTE_MAPPING_0) \
_op_(GPIO_Z_INT4_ROUTE_MAPPING_0) \
_op_(GPIO_Z_INT5_ROUTE_MAPPING_0) \
_op_(GPIO_Z_INT6_ROUTE_MAPPING_0) \
_op_(GPIO_Z_INT7_ROUTE_MAPPING_0) \
_op_(GPIO_M_INT0_ROUTE_MAPPING_0) \
_op_(GPIO_M_INT1_ROUTE_MAPPING_0) \
_op_(GPIO_M_INT2_ROUTE_MAPPING_0) \
_op_(GPIO_M_INT3_ROUTE_MAPPING_0) \
_op_(GPIO_M_INT4_ROUTE_MAPPING_0) \
_op_(GPIO_M_INT5_ROUTE_MAPPING_0) \
_op_(GPIO_M_INT6_ROUTE_MAPPING_0) \
_op_(GPIO_M_INT7_ROUTE_MAPPING_0) \
_op_(GPIO_N_INT0_ROUTE_MAPPING_0) \
_op_(GPIO_N_INT1_ROUTE_MAPPING_0) \
_op_(GPIO_N_INT2_ROUTE_MAPPING_0) \
_op_(GPIO_N_INT3_ROUTE_MAPPING_0) \
_op_(GPIO_N_INT4_ROUTE_MAPPING_0) \
_op_(GPIO_N_INT5_ROUTE_MAPPING_0) \
_op_(GPIO_N_INT6_ROUTE_MAPPING_0) \
_op_(GPIO_N_INT7_ROUTE_MAPPING_0) \
_op_(GPIO_P_INT0_ROUTE_MAPPING_0) \
_op_(GPIO_P_INT1_ROUTE_MAPPING_0) \
_op_(GPIO_P_INT2_ROUTE_MAPPING_0) \
_op_(GPIO_P_INT3_ROUTE_MAPPING_0) \
_op_(GPIO_P_INT4_ROUTE_MAPPING_0) \
_op_(GPIO_P_INT5_ROUTE_MAPPING_0) \
_op_(GPIO_P_INT6_ROUTE_MAPPING_0) \
_op_(GPIO_P_INT7_ROUTE_MAPPING_0) \
_op_(GPIO_Q_INT0_ROUTE_MAPPING_0) \
_op_(GPIO_Q_INT1_ROUTE_MAPPING_0) \
_op_(GPIO_Q_INT2_ROUTE_MAPPING_0) \
_op_(GPIO_Q_INT3_ROUTE_MAPPING_0) \
_op_(GPIO_Q_INT4_ROUTE_MAPPING_0) \
_op_(GPIO_Q_INT5_ROUTE_MAPPING_0) \
_op_(GPIO_Q_INT6_ROUTE_MAPPING_0) \
_op_(GPIO_Q_INT7_ROUTE_MAPPING_0) \
_op_(GPIO_R_INT0_ROUTE_MAPPING_0) \
_op_(GPIO_R_INT1_ROUTE_MAPPING_0) \
_op_(GPIO_R_INT2_ROUTE_MAPPING_0) \
_op_(GPIO_R_INT3_ROUTE_MAPPING_0) \
_op_(GPIO_R_INT4_ROUTE_MAPPING_0) \
_op_(GPIO_R_INT5_ROUTE_MAPPING_0) \
_op_(GPIO_R_INT6_ROUTE_MAPPING_0) \
_op_(GPIO_R_INT7_ROUTE_MAPPING_0) \
_op_(GPIO_CTL2_SPARE_0) \
_op_(GPIO_K_VM_00_0) \
_op_(GPIO_K_SCR_00_0) \
_op_(GPIO_K_VM_01_0) \
_op_(GPIO_K_SCR_01_0) \
_op_(GPIO_K_VM_02_0) \
_op_(GPIO_K_SCR_02_0) \
_op_(GPIO_K_VM_03_0) \
_op_(GPIO_K_SCR_03_0) \
_op_(GPIO_K_VM_04_0) \
_op_(GPIO_K_SCR_04_0) \
_op_(GPIO_K_VM_05_0) \
_op_(GPIO_K_SCR_05_0) \
_op_(GPIO_K_VM_06_0) \
_op_(GPIO_K_SCR_06_0) \
_op_(GPIO_K_VM_07_0) \
_op_(GPIO_K_SCR_07_0) \
_op_(GPIO_L_VM_00_0) \
_op_(GPIO_L_SCR_00_0) \
_op_(GPIO_L_VM_01_0) \
_op_(GPIO_L_SCR_01_0) \
_op_(GPIO_L_VM_02_0) \
_op_(GPIO_L_SCR_02_0) \
_op_(GPIO_L_VM_03_0) \
_op_(GPIO_L_SCR_03_0) \
_op_(GPIO_FF_VM_00_0) \
_op_(GPIO_FF_SCR_00_0) \
_op_(GPIO_FF_VM_01_0) \
_op_(GPIO_FF_SCR_01_0) \
_op_(GPIO_S_VM_00_0) \
_op_(GPIO_S_SCR_00_0) \
_op_(GPIO_S_VM_01_0) \
_op_(GPIO_S_SCR_01_0) \
_op_(GPIO_S_VM_02_0) \
_op_(GPIO_S_SCR_02_0) \
_op_(GPIO_S_VM_03_0) \
_op_(GPIO_S_SCR_03_0) \
_op_(GPIO_S_VM_04_0) \
_op_(GPIO_S_SCR_04_0) \
_op_(GPIO_S_VM_05_0) \
_op_(GPIO_S_SCR_05_0) \
_op_(GPIO_S_VM_06_0) \
_op_(GPIO_S_SCR_06_0) \
_op_(GPIO_S_VM_07_0) \
_op_(GPIO_S_SCR_07_0) \
_op_(GPIO_T_VM_00_0) \
_op_(GPIO_T_SCR_00_0) \
_op_(GPIO_T_VM_01_0) \
_op_(GPIO_T_SCR_01_0) \
_op_(GPIO_T_VM_02_0) \
_op_(GPIO_T_SCR_02_0) \
_op_(GPIO_T_VM_03_0) \
_op_(GPIO_T_SCR_03_0) \
_op_(GPIO_T_VM_04_0) \
_op_(GPIO_T_SCR_04_0) \
_op_(GPIO_T_VM_05_0) \
_op_(GPIO_T_SCR_05_0) \
_op_(GPIO_T_VM_06_0) \
_op_(GPIO_T_SCR_06_0) \
_op_(GPIO_T_VM_07_0) \
_op_(GPIO_T_SCR_07_0) \
_op_(GPIO_U_VM_00_0) \
_op_(GPIO_U_SCR_00_0) \
_op_(GPIO_CTL3_VM_SCR_0) \
_op_(GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0) \
_op_(GPIO_CTL3_INTERRUPT_STATUS_VM_0) \
_op_(GPIO_CTL3_SCR_0) \
_op_(GPIO_CTL3_ICG_EN_OVERRIDE_0) \
_op_(GPIO_K_INT0_ROUTE_MAPPING_0) \
_op_(GPIO_K_INT1_ROUTE_MAPPING_0) \
_op_(GPIO_K_INT2_ROUTE_MAPPING_0) \
_op_(GPIO_K_INT3_ROUTE_MAPPING_0) \
_op_(GPIO_K_INT4_ROUTE_MAPPING_0) \
_op_(GPIO_K_INT5_ROUTE_MAPPING_0) \
_op_(GPIO_K_INT6_ROUTE_MAPPING_0) \
_op_(GPIO_K_INT7_ROUTE_MAPPING_0) \
_op_(GPIO_L_INT0_ROUTE_MAPPING_0) \
_op_(GPIO_L_INT1_ROUTE_MAPPING_0) \
_op_(GPIO_L_INT2_ROUTE_MAPPING_0) \
_op_(GPIO_L_INT3_ROUTE_MAPPING_0) \
_op_(GPIO_L_INT4_ROUTE_MAPPING_0) \
_op_(GPIO_L_INT5_ROUTE_MAPPING_0) \
_op_(GPIO_L_INT6_ROUTE_MAPPING_0) \
_op_(GPIO_L_INT7_ROUTE_MAPPING_0) \
_op_(GPIO_FF_INT0_ROUTE_MAPPING_0) \
_op_(GPIO_FF_INT1_ROUTE_MAPPING_0) \
_op_(GPIO_FF_INT2_ROUTE_MAPPING_0) \
_op_(GPIO_FF_INT3_ROUTE_MAPPING_0) \
_op_(GPIO_FF_INT4_ROUTE_MAPPING_0) \
_op_(GPIO_FF_INT5_ROUTE_MAPPING_0) \
_op_(GPIO_FF_INT6_ROUTE_MAPPING_0) \
_op_(GPIO_FF_INT7_ROUTE_MAPPING_0) \
_op_(GPIO_S_INT0_ROUTE_MAPPING_0) \
_op_(GPIO_S_INT1_ROUTE_MAPPING_0) \
_op_(GPIO_S_INT2_ROUTE_MAPPING_0) \
_op_(GPIO_S_INT3_ROUTE_MAPPING_0) \
_op_(GPIO_S_INT4_ROUTE_MAPPING_0) \
_op_(GPIO_S_INT5_ROUTE_MAPPING_0) \
_op_(GPIO_S_INT6_ROUTE_MAPPING_0) \
_op_(GPIO_S_INT7_ROUTE_MAPPING_0) \
_op_(GPIO_T_INT0_ROUTE_MAPPING_0) \
_op_(GPIO_T_INT1_ROUTE_MAPPING_0) \
_op_(GPIO_T_INT2_ROUTE_MAPPING_0) \
_op_(GPIO_T_INT3_ROUTE_MAPPING_0) \
_op_(GPIO_T_INT4_ROUTE_MAPPING_0) \
_op_(GPIO_T_INT5_ROUTE_MAPPING_0) \
_op_(GPIO_T_INT6_ROUTE_MAPPING_0) \
_op_(GPIO_T_INT7_ROUTE_MAPPING_0) \
_op_(GPIO_U_INT0_ROUTE_MAPPING_0) \
_op_(GPIO_U_INT1_ROUTE_MAPPING_0) \
_op_(GPIO_U_INT2_ROUTE_MAPPING_0) \
_op_(GPIO_U_INT3_ROUTE_MAPPING_0) \
_op_(GPIO_U_INT4_ROUTE_MAPPING_0) \
_op_(GPIO_U_INT5_ROUTE_MAPPING_0) \
_op_(GPIO_U_INT6_ROUTE_MAPPING_0) \
_op_(GPIO_U_INT7_ROUTE_MAPPING_0) \
_op_(GPIO_CTL3_SPARE_0) \
_op_(GPIO_G_VM_00_0) \
_op_(GPIO_G_SCR_00_0) \
_op_(GPIO_G_VM_01_0) \
_op_(GPIO_G_SCR_01_0) \
_op_(GPIO_G_VM_02_0) \
_op_(GPIO_G_SCR_02_0) \
_op_(GPIO_G_VM_03_0) \
_op_(GPIO_G_SCR_03_0) \
_op_(GPIO_G_VM_04_0) \
_op_(GPIO_G_SCR_04_0) \
_op_(GPIO_G_VM_05_0) \
_op_(GPIO_G_SCR_05_0) \
_op_(GPIO_G_VM_06_0) \
_op_(GPIO_G_SCR_06_0) \
_op_(GPIO_G_VM_07_0) \
_op_(GPIO_G_SCR_07_0) \
_op_(GPIO_H_VM_00_0) \
_op_(GPIO_H_SCR_00_0) \
_op_(GPIO_H_VM_01_0) \
_op_(GPIO_H_SCR_01_0) \
_op_(GPIO_H_VM_02_0) \
_op_(GPIO_H_SCR_02_0) \
_op_(GPIO_H_VM_03_0) \
_op_(GPIO_H_SCR_03_0) \
_op_(GPIO_H_VM_04_0) \
_op_(GPIO_H_SCR_04_0) \
_op_(GPIO_H_VM_05_0) \
_op_(GPIO_H_SCR_05_0) \
_op_(GPIO_H_VM_06_0) \
_op_(GPIO_H_SCR_06_0) \
_op_(GPIO_H_VM_07_0) \
_op_(GPIO_H_SCR_07_0) \
_op_(GPIO_I_VM_00_0) \
_op_(GPIO_I_SCR_00_0) \
_op_(GPIO_I_VM_01_0) \
_op_(GPIO_I_SCR_01_0) \
_op_(GPIO_I_VM_02_0) \
_op_(GPIO_I_SCR_02_0) \
_op_(GPIO_I_VM_03_0) \
_op_(GPIO_I_SCR_03_0) \
_op_(GPIO_I_VM_04_0) \
_op_(GPIO_I_SCR_04_0) \
_op_(GPIO_C_VM_00_0) \
_op_(GPIO_C_SCR_00_0) \
_op_(GPIO_C_VM_01_0) \
_op_(GPIO_C_SCR_01_0) \
_op_(GPIO_C_VM_02_0) \
_op_(GPIO_C_SCR_02_0) \
_op_(GPIO_C_VM_03_0) \
_op_(GPIO_C_SCR_03_0) \
_op_(GPIO_C_VM_04_0) \
_op_(GPIO_C_SCR_04_0) \
_op_(GPIO_C_VM_05_0) \
_op_(GPIO_C_SCR_05_0) \
_op_(GPIO_C_VM_06_0) \
_op_(GPIO_C_SCR_06_0) \
_op_(GPIO_C_VM_07_0) \
_op_(GPIO_C_SCR_07_0) \
_op_(GPIO_D_VM_00_0) \
_op_(GPIO_D_SCR_00_0) \
_op_(GPIO_D_VM_01_0) \
_op_(GPIO_D_SCR_01_0) \
_op_(GPIO_D_VM_02_0) \
_op_(GPIO_D_SCR_02_0) \
_op_(GPIO_D_VM_03_0) \
_op_(GPIO_D_SCR_03_0) \
_op_(GPIO_E_VM_00_0) \
_op_(GPIO_E_SCR_00_0) \
_op_(GPIO_E_VM_01_0) \
_op_(GPIO_E_SCR_01_0) \
_op_(GPIO_E_VM_02_0) \
_op_(GPIO_E_SCR_02_0) \
_op_(GPIO_E_VM_03_0) \
_op_(GPIO_E_SCR_03_0) \
_op_(GPIO_E_VM_04_0) \
_op_(GPIO_E_SCR_04_0) \
_op_(GPIO_E_VM_05_0) \
_op_(GPIO_E_SCR_05_0) \
_op_(GPIO_E_VM_06_0) \
_op_(GPIO_E_SCR_06_0) \
_op_(GPIO_E_VM_07_0) \
_op_(GPIO_E_SCR_07_0) \
_op_(GPIO_F_VM_00_0) \
_op_(GPIO_F_SCR_00_0) \
_op_(GPIO_F_VM_01_0) \
_op_(GPIO_F_SCR_01_0) \
_op_(GPIO_F_VM_02_0) \
_op_(GPIO_F_SCR_02_0) \
_op_(GPIO_F_VM_03_0) \
_op_(GPIO_F_SCR_03_0) \
_op_(GPIO_F_VM_04_0) \
_op_(GPIO_F_SCR_04_0) \
_op_(GPIO_F_VM_05_0) \
_op_(GPIO_F_SCR_05_0) \
_op_(GPIO_B_VM_00_0) \
_op_(GPIO_B_SCR_00_0) \
_op_(GPIO_B_VM_01_0) \
_op_(GPIO_B_SCR_01_0) \
_op_(GPIO_CTL4_VM_SCR_0) \
_op_(GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0) \
_op_(GPIO_CTL4_INTERRUPT_STATUS_VM_0) \
_op_(GPIO_CTL4_SCR_0) \
_op_(GPIO_CTL4_ICG_EN_OVERRIDE_0) \
_op_(GPIO_G_INT0_ROUTE_MAPPING_0) \
_op_(GPIO_G_INT1_ROUTE_MAPPING_0) \
_op_(GPIO_G_INT2_ROUTE_MAPPING_0) \
_op_(GPIO_G_INT3_ROUTE_MAPPING_0) \
_op_(GPIO_G_INT4_ROUTE_MAPPING_0) \
_op_(GPIO_G_INT5_ROUTE_MAPPING_0) \
_op_(GPIO_G_INT6_ROUTE_MAPPING_0) \
_op_(GPIO_G_INT7_ROUTE_MAPPING_0) \
_op_(GPIO_H_INT0_ROUTE_MAPPING_0) \
_op_(GPIO_H_INT1_ROUTE_MAPPING_0) \
_op_(GPIO_H_INT2_ROUTE_MAPPING_0) \
_op_(GPIO_H_INT3_ROUTE_MAPPING_0) \
_op_(GPIO_H_INT4_ROUTE_MAPPING_0) \
_op_(GPIO_H_INT5_ROUTE_MAPPING_0) \
_op_(GPIO_H_INT6_ROUTE_MAPPING_0) \
_op_(GPIO_H_INT7_ROUTE_MAPPING_0) \
_op_(GPIO_I_INT0_ROUTE_MAPPING_0) \
_op_(GPIO_I_INT1_ROUTE_MAPPING_0) \
_op_(GPIO_I_INT2_ROUTE_MAPPING_0) \
_op_(GPIO_I_INT3_ROUTE_MAPPING_0) \
_op_(GPIO_I_INT4_ROUTE_MAPPING_0) \
_op_(GPIO_I_INT5_ROUTE_MAPPING_0) \
_op_(GPIO_I_INT6_ROUTE_MAPPING_0) \
_op_(GPIO_I_INT7_ROUTE_MAPPING_0) \
_op_(GPIO_C_INT0_ROUTE_MAPPING_0) \
_op_(GPIO_C_INT1_ROUTE_MAPPING_0) \
_op_(GPIO_C_INT2_ROUTE_MAPPING_0) \
_op_(GPIO_C_INT3_ROUTE_MAPPING_0) \
_op_(GPIO_C_INT4_ROUTE_MAPPING_0) \
_op_(GPIO_C_INT5_ROUTE_MAPPING_0) \
_op_(GPIO_C_INT6_ROUTE_MAPPING_0) \
_op_(GPIO_C_INT7_ROUTE_MAPPING_0) \
_op_(GPIO_D_INT0_ROUTE_MAPPING_0) \
_op_(GPIO_D_INT1_ROUTE_MAPPING_0) \
_op_(GPIO_D_INT2_ROUTE_MAPPING_0) \
_op_(GPIO_D_INT3_ROUTE_MAPPING_0) \
_op_(GPIO_D_INT4_ROUTE_MAPPING_0) \
_op_(GPIO_D_INT5_ROUTE_MAPPING_0) \
_op_(GPIO_D_INT6_ROUTE_MAPPING_0) \
_op_(GPIO_D_INT7_ROUTE_MAPPING_0) \
_op_(GPIO_E_INT0_ROUTE_MAPPING_0) \
_op_(GPIO_E_INT1_ROUTE_MAPPING_0) \
_op_(GPIO_E_INT2_ROUTE_MAPPING_0) \
_op_(GPIO_E_INT3_ROUTE_MAPPING_0) \
_op_(GPIO_E_INT4_ROUTE_MAPPING_0) \
_op_(GPIO_E_INT5_ROUTE_MAPPING_0) \
_op_(GPIO_E_INT6_ROUTE_MAPPING_0) \
_op_(GPIO_E_INT7_ROUTE_MAPPING_0) \
_op_(GPIO_F_INT0_ROUTE_MAPPING_0) \
_op_(GPIO_F_INT1_ROUTE_MAPPING_0) \
_op_(GPIO_F_INT2_ROUTE_MAPPING_0) \
_op_(GPIO_F_INT3_ROUTE_MAPPING_0) \
_op_(GPIO_F_INT4_ROUTE_MAPPING_0) \
_op_(GPIO_F_INT5_ROUTE_MAPPING_0) \
_op_(GPIO_F_INT6_ROUTE_MAPPING_0) \
_op_(GPIO_F_INT7_ROUTE_MAPPING_0) \
_op_(GPIO_B_INT0_ROUTE_MAPPING_0) \
_op_(GPIO_B_INT1_ROUTE_MAPPING_0) \
_op_(GPIO_B_INT2_ROUTE_MAPPING_0) \
_op_(GPIO_B_INT3_ROUTE_MAPPING_0) \
_op_(GPIO_B_INT4_ROUTE_MAPPING_0) \
_op_(GPIO_B_INT5_ROUTE_MAPPING_0) \
_op_(GPIO_B_INT6_ROUTE_MAPPING_0) \
_op_(GPIO_B_INT7_ROUTE_MAPPING_0) \
_op_(GPIO_CTL4_SPARE_0) \
_op_(GPIO_O_VM_00_0) \
_op_(GPIO_O_SCR_00_0) \
_op_(GPIO_O_VM_01_0) \
_op_(GPIO_O_SCR_01_0) \
_op_(GPIO_O_VM_02_0) \
_op_(GPIO_O_SCR_02_0) \
_op_(GPIO_O_VM_03_0) \
_op_(GPIO_O_SCR_03_0) \
_op_(GPIO_O_VM_04_0) \
_op_(GPIO_O_SCR_04_0) \
_op_(GPIO_O_VM_05_0) \
_op_(GPIO_O_SCR_05_0) \
_op_(GPIO_J_VM_00_0) \
_op_(GPIO_J_SCR_00_0) \
_op_(GPIO_J_VM_01_0) \
_op_(GPIO_J_SCR_01_0) \
_op_(GPIO_J_VM_02_0) \
_op_(GPIO_J_SCR_02_0) \
_op_(GPIO_J_VM_03_0) \
_op_(GPIO_J_SCR_03_0) \
_op_(GPIO_J_VM_04_0) \
_op_(GPIO_J_SCR_04_0) \
_op_(GPIO_J_VM_05_0) \
_op_(GPIO_J_SCR_05_0) \
_op_(GPIO_CTL5_VM_SCR_0) \
_op_(GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0) \
_op_(GPIO_CTL5_INTERRUPT_STATUS_VM_0) \
_op_(GPIO_CTL5_SCR_0) \
_op_(GPIO_CTL5_ICG_EN_OVERRIDE_0) \
_op_(GPIO_O_INT0_ROUTE_MAPPING_0) \
_op_(GPIO_O_INT1_ROUTE_MAPPING_0) \
_op_(GPIO_O_INT2_ROUTE_MAPPING_0) \
_op_(GPIO_O_INT3_ROUTE_MAPPING_0) \
_op_(GPIO_O_INT4_ROUTE_MAPPING_0) \
_op_(GPIO_O_INT5_ROUTE_MAPPING_0) \
_op_(GPIO_O_INT6_ROUTE_MAPPING_0) \
_op_(GPIO_O_INT7_ROUTE_MAPPING_0) \
_op_(GPIO_J_INT0_ROUTE_MAPPING_0) \
_op_(GPIO_J_INT1_ROUTE_MAPPING_0) \
_op_(GPIO_J_INT2_ROUTE_MAPPING_0) \
_op_(GPIO_J_INT3_ROUTE_MAPPING_0) \
_op_(GPIO_J_INT4_ROUTE_MAPPING_0) \
_op_(GPIO_J_INT5_ROUTE_MAPPING_0) \
_op_(GPIO_J_INT6_ROUTE_MAPPING_0) \
_op_(GPIO_J_INT7_ROUTE_MAPPING_0) \
_op_(GPIO_CTL5_SPARE_0) \
_op_(GPIO_GG_ENABLE_CONFIG_00_0) \
_op_(GPIO_GG_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_GG_INPUT_00_0) \
_op_(GPIO_GG_OUTPUT_CONTROL_00_0) \
_op_(GPIO_GG_OUTPUT_VALUE_00_0) \
_op_(GPIO_GG_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_GG_ENABLE_CONFIG_01_0) \
_op_(GPIO_GG_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_GG_INPUT_01_0) \
_op_(GPIO_GG_OUTPUT_CONTROL_01_0) \
_op_(GPIO_GG_OUTPUT_VALUE_01_0) \
_op_(GPIO_GG_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_GG_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_GG_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_GG_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_GG_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_GG_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_GG_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_GG_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_GG_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_V_ENABLE_CONFIG_00_0) \
_op_(GPIO_V_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_V_INPUT_00_0) \
_op_(GPIO_V_OUTPUT_CONTROL_00_0) \
_op_(GPIO_V_OUTPUT_VALUE_00_0) \
_op_(GPIO_V_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_V_ENABLE_CONFIG_01_0) \
_op_(GPIO_V_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_V_INPUT_01_0) \
_op_(GPIO_V_OUTPUT_CONTROL_01_0) \
_op_(GPIO_V_OUTPUT_VALUE_01_0) \
_op_(GPIO_V_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_V_ENABLE_CONFIG_02_0) \
_op_(GPIO_V_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_V_INPUT_02_0) \
_op_(GPIO_V_OUTPUT_CONTROL_02_0) \
_op_(GPIO_V_OUTPUT_VALUE_02_0) \
_op_(GPIO_V_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_V_ENABLE_CONFIG_03_0) \
_op_(GPIO_V_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_V_INPUT_03_0) \
_op_(GPIO_V_OUTPUT_CONTROL_03_0) \
_op_(GPIO_V_OUTPUT_VALUE_03_0) \
_op_(GPIO_V_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_V_ENABLE_CONFIG_04_0) \
_op_(GPIO_V_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_V_INPUT_04_0) \
_op_(GPIO_V_OUTPUT_CONTROL_04_0) \
_op_(GPIO_V_OUTPUT_VALUE_04_0) \
_op_(GPIO_V_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_V_ENABLE_CONFIG_05_0) \
_op_(GPIO_V_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_V_INPUT_05_0) \
_op_(GPIO_V_OUTPUT_CONTROL_05_0) \
_op_(GPIO_V_OUTPUT_VALUE_05_0) \
_op_(GPIO_V_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_V_ENABLE_CONFIG_06_0) \
_op_(GPIO_V_DEBOUNCE_THRESHOLD_06_0) \
_op_(GPIO_V_INPUT_06_0) \
_op_(GPIO_V_OUTPUT_CONTROL_06_0) \
_op_(GPIO_V_OUTPUT_VALUE_06_0) \
_op_(GPIO_V_INTERRUPT_CLEAR_06_0) \
_op_(GPIO_V_ENABLE_CONFIG_07_0) \
_op_(GPIO_V_DEBOUNCE_THRESHOLD_07_0) \
_op_(GPIO_V_INPUT_07_0) \
_op_(GPIO_V_OUTPUT_CONTROL_07_0) \
_op_(GPIO_V_OUTPUT_VALUE_07_0) \
_op_(GPIO_V_INTERRUPT_CLEAR_07_0) \
_op_(GPIO_V_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_V_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_V_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_V_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_V_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_V_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_V_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_V_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_W_ENABLE_CONFIG_00_0) \
_op_(GPIO_W_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_W_INPUT_00_0) \
_op_(GPIO_W_OUTPUT_CONTROL_00_0) \
_op_(GPIO_W_OUTPUT_VALUE_00_0) \
_op_(GPIO_W_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_W_ENABLE_CONFIG_01_0) \
_op_(GPIO_W_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_W_INPUT_01_0) \
_op_(GPIO_W_OUTPUT_CONTROL_01_0) \
_op_(GPIO_W_OUTPUT_VALUE_01_0) \
_op_(GPIO_W_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_W_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_W_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_W_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_W_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_W_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_W_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_W_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_W_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_A_ENABLE_CONFIG_00_0) \
_op_(GPIO_A_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_A_INPUT_00_0) \
_op_(GPIO_A_OUTPUT_CONTROL_00_0) \
_op_(GPIO_A_OUTPUT_VALUE_00_0) \
_op_(GPIO_A_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_A_ENABLE_CONFIG_01_0) \
_op_(GPIO_A_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_A_INPUT_01_0) \
_op_(GPIO_A_OUTPUT_CONTROL_01_0) \
_op_(GPIO_A_OUTPUT_VALUE_01_0) \
_op_(GPIO_A_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_A_ENABLE_CONFIG_02_0) \
_op_(GPIO_A_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_A_INPUT_02_0) \
_op_(GPIO_A_OUTPUT_CONTROL_02_0) \
_op_(GPIO_A_OUTPUT_VALUE_02_0) \
_op_(GPIO_A_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_A_ENABLE_CONFIG_03_0) \
_op_(GPIO_A_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_A_INPUT_03_0) \
_op_(GPIO_A_OUTPUT_CONTROL_03_0) \
_op_(GPIO_A_OUTPUT_VALUE_03_0) \
_op_(GPIO_A_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_A_ENABLE_CONFIG_04_0) \
_op_(GPIO_A_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_A_INPUT_04_0) \
_op_(GPIO_A_OUTPUT_CONTROL_04_0) \
_op_(GPIO_A_OUTPUT_VALUE_04_0) \
_op_(GPIO_A_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_A_ENABLE_CONFIG_05_0) \
_op_(GPIO_A_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_A_INPUT_05_0) \
_op_(GPIO_A_OUTPUT_CONTROL_05_0) \
_op_(GPIO_A_OUTPUT_VALUE_05_0) \
_op_(GPIO_A_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_A_ENABLE_CONFIG_06_0) \
_op_(GPIO_A_DEBOUNCE_THRESHOLD_06_0) \
_op_(GPIO_A_INPUT_06_0) \
_op_(GPIO_A_OUTPUT_CONTROL_06_0) \
_op_(GPIO_A_OUTPUT_VALUE_06_0) \
_op_(GPIO_A_INTERRUPT_CLEAR_06_0) \
_op_(GPIO_A_ENABLE_CONFIG_07_0) \
_op_(GPIO_A_DEBOUNCE_THRESHOLD_07_0) \
_op_(GPIO_A_INPUT_07_0) \
_op_(GPIO_A_OUTPUT_CONTROL_07_0) \
_op_(GPIO_A_OUTPUT_VALUE_07_0) \
_op_(GPIO_A_INTERRUPT_CLEAR_07_0) \
_op_(GPIO_A_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_A_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_A_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_A_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_A_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_A_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_A_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_A_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_X_ENABLE_CONFIG_00_0) \
_op_(GPIO_X_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_X_INPUT_00_0) \
_op_(GPIO_X_OUTPUT_CONTROL_00_0) \
_op_(GPIO_X_OUTPUT_VALUE_00_0) \
_op_(GPIO_X_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_X_ENABLE_CONFIG_01_0) \
_op_(GPIO_X_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_X_INPUT_01_0) \
_op_(GPIO_X_OUTPUT_CONTROL_01_0) \
_op_(GPIO_X_OUTPUT_VALUE_01_0) \
_op_(GPIO_X_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_X_ENABLE_CONFIG_02_0) \
_op_(GPIO_X_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_X_INPUT_02_0) \
_op_(GPIO_X_OUTPUT_CONTROL_02_0) \
_op_(GPIO_X_OUTPUT_VALUE_02_0) \
_op_(GPIO_X_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_X_ENABLE_CONFIG_03_0) \
_op_(GPIO_X_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_X_INPUT_03_0) \
_op_(GPIO_X_OUTPUT_CONTROL_03_0) \
_op_(GPIO_X_OUTPUT_VALUE_03_0) \
_op_(GPIO_X_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_X_ENABLE_CONFIG_04_0) \
_op_(GPIO_X_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_X_INPUT_04_0) \
_op_(GPIO_X_OUTPUT_CONTROL_04_0) \
_op_(GPIO_X_OUTPUT_VALUE_04_0) \
_op_(GPIO_X_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_X_ENABLE_CONFIG_05_0) \
_op_(GPIO_X_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_X_INPUT_05_0) \
_op_(GPIO_X_OUTPUT_CONTROL_05_0) \
_op_(GPIO_X_OUTPUT_VALUE_05_0) \
_op_(GPIO_X_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_X_ENABLE_CONFIG_06_0) \
_op_(GPIO_X_DEBOUNCE_THRESHOLD_06_0) \
_op_(GPIO_X_INPUT_06_0) \
_op_(GPIO_X_OUTPUT_CONTROL_06_0) \
_op_(GPIO_X_OUTPUT_VALUE_06_0) \
_op_(GPIO_X_INTERRUPT_CLEAR_06_0) \
_op_(GPIO_X_ENABLE_CONFIG_07_0) \
_op_(GPIO_X_DEBOUNCE_THRESHOLD_07_0) \
_op_(GPIO_X_INPUT_07_0) \
_op_(GPIO_X_OUTPUT_CONTROL_07_0) \
_op_(GPIO_X_OUTPUT_VALUE_07_0) \
_op_(GPIO_X_INTERRUPT_CLEAR_07_0) \
_op_(GPIO_X_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_X_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_X_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_X_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_X_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_X_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_X_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_X_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_Y_ENABLE_CONFIG_00_0) \
_op_(GPIO_Y_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_Y_INPUT_00_0) \
_op_(GPIO_Y_OUTPUT_CONTROL_00_0) \
_op_(GPIO_Y_OUTPUT_VALUE_00_0) \
_op_(GPIO_Y_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_Y_ENABLE_CONFIG_01_0) \
_op_(GPIO_Y_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_Y_INPUT_01_0) \
_op_(GPIO_Y_OUTPUT_CONTROL_01_0) \
_op_(GPIO_Y_OUTPUT_VALUE_01_0) \
_op_(GPIO_Y_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_Y_ENABLE_CONFIG_02_0) \
_op_(GPIO_Y_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_Y_INPUT_02_0) \
_op_(GPIO_Y_OUTPUT_CONTROL_02_0) \
_op_(GPIO_Y_OUTPUT_VALUE_02_0) \
_op_(GPIO_Y_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_Y_ENABLE_CONFIG_03_0) \
_op_(GPIO_Y_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_Y_INPUT_03_0) \
_op_(GPIO_Y_OUTPUT_CONTROL_03_0) \
_op_(GPIO_Y_OUTPUT_VALUE_03_0) \
_op_(GPIO_Y_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_Y_ENABLE_CONFIG_04_0) \
_op_(GPIO_Y_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_Y_INPUT_04_0) \
_op_(GPIO_Y_OUTPUT_CONTROL_04_0) \
_op_(GPIO_Y_OUTPUT_VALUE_04_0) \
_op_(GPIO_Y_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_Y_ENABLE_CONFIG_05_0) \
_op_(GPIO_Y_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_Y_INPUT_05_0) \
_op_(GPIO_Y_OUTPUT_CONTROL_05_0) \
_op_(GPIO_Y_OUTPUT_VALUE_05_0) \
_op_(GPIO_Y_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_Y_ENABLE_CONFIG_06_0) \
_op_(GPIO_Y_DEBOUNCE_THRESHOLD_06_0) \
_op_(GPIO_Y_INPUT_06_0) \
_op_(GPIO_Y_OUTPUT_CONTROL_06_0) \
_op_(GPIO_Y_OUTPUT_VALUE_06_0) \
_op_(GPIO_Y_INTERRUPT_CLEAR_06_0) \
_op_(GPIO_Y_ENABLE_CONFIG_07_0) \
_op_(GPIO_Y_DEBOUNCE_THRESHOLD_07_0) \
_op_(GPIO_Y_INPUT_07_0) \
_op_(GPIO_Y_OUTPUT_CONTROL_07_0) \
_op_(GPIO_Y_OUTPUT_VALUE_07_0) \
_op_(GPIO_Y_INTERRUPT_CLEAR_07_0) \
_op_(GPIO_Y_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_Y_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_Y_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_Y_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_Y_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_Y_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_Y_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_Y_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_Z_ENABLE_CONFIG_00_0) \
_op_(GPIO_Z_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_Z_INPUT_00_0) \
_op_(GPIO_Z_OUTPUT_CONTROL_00_0) \
_op_(GPIO_Z_OUTPUT_VALUE_00_0) \
_op_(GPIO_Z_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_Z_ENABLE_CONFIG_01_0) \
_op_(GPIO_Z_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_Z_INPUT_01_0) \
_op_(GPIO_Z_OUTPUT_CONTROL_01_0) \
_op_(GPIO_Z_OUTPUT_VALUE_01_0) \
_op_(GPIO_Z_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_Z_ENABLE_CONFIG_02_0) \
_op_(GPIO_Z_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_Z_INPUT_02_0) \
_op_(GPIO_Z_OUTPUT_CONTROL_02_0) \
_op_(GPIO_Z_OUTPUT_VALUE_02_0) \
_op_(GPIO_Z_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_Z_ENABLE_CONFIG_03_0) \
_op_(GPIO_Z_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_Z_INPUT_03_0) \
_op_(GPIO_Z_OUTPUT_CONTROL_03_0) \
_op_(GPIO_Z_OUTPUT_VALUE_03_0) \
_op_(GPIO_Z_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_Z_ENABLE_CONFIG_04_0) \
_op_(GPIO_Z_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_Z_INPUT_04_0) \
_op_(GPIO_Z_OUTPUT_CONTROL_04_0) \
_op_(GPIO_Z_OUTPUT_VALUE_04_0) \
_op_(GPIO_Z_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_Z_ENABLE_CONFIG_05_0) \
_op_(GPIO_Z_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_Z_INPUT_05_0) \
_op_(GPIO_Z_OUTPUT_CONTROL_05_0) \
_op_(GPIO_Z_OUTPUT_VALUE_05_0) \
_op_(GPIO_Z_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_Z_ENABLE_CONFIG_06_0) \
_op_(GPIO_Z_DEBOUNCE_THRESHOLD_06_0) \
_op_(GPIO_Z_INPUT_06_0) \
_op_(GPIO_Z_OUTPUT_CONTROL_06_0) \
_op_(GPIO_Z_OUTPUT_VALUE_06_0) \
_op_(GPIO_Z_INTERRUPT_CLEAR_06_0) \
_op_(GPIO_Z_ENABLE_CONFIG_07_0) \
_op_(GPIO_Z_DEBOUNCE_THRESHOLD_07_0) \
_op_(GPIO_Z_INPUT_07_0) \
_op_(GPIO_Z_OUTPUT_CONTROL_07_0) \
_op_(GPIO_Z_OUTPUT_VALUE_07_0) \
_op_(GPIO_Z_INTERRUPT_CLEAR_07_0) \
_op_(GPIO_Z_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_Z_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_Z_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_Z_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_Z_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_Z_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_Z_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_Z_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_M_ENABLE_CONFIG_00_0) \
_op_(GPIO_M_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_M_INPUT_00_0) \
_op_(GPIO_M_OUTPUT_CONTROL_00_0) \
_op_(GPIO_M_OUTPUT_VALUE_00_0) \
_op_(GPIO_M_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_M_ENABLE_CONFIG_01_0) \
_op_(GPIO_M_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_M_INPUT_01_0) \
_op_(GPIO_M_OUTPUT_CONTROL_01_0) \
_op_(GPIO_M_OUTPUT_VALUE_01_0) \
_op_(GPIO_M_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_M_ENABLE_CONFIG_02_0) \
_op_(GPIO_M_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_M_INPUT_02_0) \
_op_(GPIO_M_OUTPUT_CONTROL_02_0) \
_op_(GPIO_M_OUTPUT_VALUE_02_0) \
_op_(GPIO_M_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_M_ENABLE_CONFIG_03_0) \
_op_(GPIO_M_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_M_INPUT_03_0) \
_op_(GPIO_M_OUTPUT_CONTROL_03_0) \
_op_(GPIO_M_OUTPUT_VALUE_03_0) \
_op_(GPIO_M_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_M_ENABLE_CONFIG_04_0) \
_op_(GPIO_M_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_M_INPUT_04_0) \
_op_(GPIO_M_OUTPUT_CONTROL_04_0) \
_op_(GPIO_M_OUTPUT_VALUE_04_0) \
_op_(GPIO_M_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_M_ENABLE_CONFIG_05_0) \
_op_(GPIO_M_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_M_INPUT_05_0) \
_op_(GPIO_M_OUTPUT_CONTROL_05_0) \
_op_(GPIO_M_OUTPUT_VALUE_05_0) \
_op_(GPIO_M_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_M_ENABLE_CONFIG_06_0) \
_op_(GPIO_M_DEBOUNCE_THRESHOLD_06_0) \
_op_(GPIO_M_INPUT_06_0) \
_op_(GPIO_M_OUTPUT_CONTROL_06_0) \
_op_(GPIO_M_OUTPUT_VALUE_06_0) \
_op_(GPIO_M_INTERRUPT_CLEAR_06_0) \
_op_(GPIO_M_ENABLE_CONFIG_07_0) \
_op_(GPIO_M_DEBOUNCE_THRESHOLD_07_0) \
_op_(GPIO_M_INPUT_07_0) \
_op_(GPIO_M_OUTPUT_CONTROL_07_0) \
_op_(GPIO_M_OUTPUT_VALUE_07_0) \
_op_(GPIO_M_INTERRUPT_CLEAR_07_0) \
_op_(GPIO_M_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_M_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_M_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_M_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_M_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_M_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_M_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_M_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_N_ENABLE_CONFIG_00_0) \
_op_(GPIO_N_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_N_INPUT_00_0) \
_op_(GPIO_N_OUTPUT_CONTROL_00_0) \
_op_(GPIO_N_OUTPUT_VALUE_00_0) \
_op_(GPIO_N_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_N_ENABLE_CONFIG_01_0) \
_op_(GPIO_N_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_N_INPUT_01_0) \
_op_(GPIO_N_OUTPUT_CONTROL_01_0) \
_op_(GPIO_N_OUTPUT_VALUE_01_0) \
_op_(GPIO_N_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_N_ENABLE_CONFIG_02_0) \
_op_(GPIO_N_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_N_INPUT_02_0) \
_op_(GPIO_N_OUTPUT_CONTROL_02_0) \
_op_(GPIO_N_OUTPUT_VALUE_02_0) \
_op_(GPIO_N_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_N_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_N_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_N_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_N_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_N_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_N_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_N_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_N_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_P_ENABLE_CONFIG_00_0) \
_op_(GPIO_P_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_P_INPUT_00_0) \
_op_(GPIO_P_OUTPUT_CONTROL_00_0) \
_op_(GPIO_P_OUTPUT_VALUE_00_0) \
_op_(GPIO_P_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_P_ENABLE_CONFIG_01_0) \
_op_(GPIO_P_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_P_INPUT_01_0) \
_op_(GPIO_P_OUTPUT_CONTROL_01_0) \
_op_(GPIO_P_OUTPUT_VALUE_01_0) \
_op_(GPIO_P_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_P_ENABLE_CONFIG_02_0) \
_op_(GPIO_P_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_P_INPUT_02_0) \
_op_(GPIO_P_OUTPUT_CONTROL_02_0) \
_op_(GPIO_P_OUTPUT_VALUE_02_0) \
_op_(GPIO_P_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_P_ENABLE_CONFIG_03_0) \
_op_(GPIO_P_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_P_INPUT_03_0) \
_op_(GPIO_P_OUTPUT_CONTROL_03_0) \
_op_(GPIO_P_OUTPUT_VALUE_03_0) \
_op_(GPIO_P_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_P_ENABLE_CONFIG_04_0) \
_op_(GPIO_P_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_P_INPUT_04_0) \
_op_(GPIO_P_OUTPUT_CONTROL_04_0) \
_op_(GPIO_P_OUTPUT_VALUE_04_0) \
_op_(GPIO_P_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_P_ENABLE_CONFIG_05_0) \
_op_(GPIO_P_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_P_INPUT_05_0) \
_op_(GPIO_P_OUTPUT_CONTROL_05_0) \
_op_(GPIO_P_OUTPUT_VALUE_05_0) \
_op_(GPIO_P_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_P_ENABLE_CONFIG_06_0) \
_op_(GPIO_P_DEBOUNCE_THRESHOLD_06_0) \
_op_(GPIO_P_INPUT_06_0) \
_op_(GPIO_P_OUTPUT_CONTROL_06_0) \
_op_(GPIO_P_OUTPUT_VALUE_06_0) \
_op_(GPIO_P_INTERRUPT_CLEAR_06_0) \
_op_(GPIO_P_ENABLE_CONFIG_07_0) \
_op_(GPIO_P_DEBOUNCE_THRESHOLD_07_0) \
_op_(GPIO_P_INPUT_07_0) \
_op_(GPIO_P_OUTPUT_CONTROL_07_0) \
_op_(GPIO_P_OUTPUT_VALUE_07_0) \
_op_(GPIO_P_INTERRUPT_CLEAR_07_0) \
_op_(GPIO_P_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_P_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_P_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_P_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_P_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_P_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_P_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_P_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_Q_ENABLE_CONFIG_00_0) \
_op_(GPIO_Q_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_Q_INPUT_00_0) \
_op_(GPIO_Q_OUTPUT_CONTROL_00_0) \
_op_(GPIO_Q_OUTPUT_VALUE_00_0) \
_op_(GPIO_Q_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_Q_ENABLE_CONFIG_01_0) \
_op_(GPIO_Q_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_Q_INPUT_01_0) \
_op_(GPIO_Q_OUTPUT_CONTROL_01_0) \
_op_(GPIO_Q_OUTPUT_VALUE_01_0) \
_op_(GPIO_Q_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_Q_ENABLE_CONFIG_02_0) \
_op_(GPIO_Q_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_Q_INPUT_02_0) \
_op_(GPIO_Q_OUTPUT_CONTROL_02_0) \
_op_(GPIO_Q_OUTPUT_VALUE_02_0) \
_op_(GPIO_Q_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_Q_ENABLE_CONFIG_03_0) \
_op_(GPIO_Q_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_Q_INPUT_03_0) \
_op_(GPIO_Q_OUTPUT_CONTROL_03_0) \
_op_(GPIO_Q_OUTPUT_VALUE_03_0) \
_op_(GPIO_Q_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_Q_ENABLE_CONFIG_04_0) \
_op_(GPIO_Q_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_Q_INPUT_04_0) \
_op_(GPIO_Q_OUTPUT_CONTROL_04_0) \
_op_(GPIO_Q_OUTPUT_VALUE_04_0) \
_op_(GPIO_Q_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_Q_ENABLE_CONFIG_05_0) \
_op_(GPIO_Q_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_Q_INPUT_05_0) \
_op_(GPIO_Q_OUTPUT_CONTROL_05_0) \
_op_(GPIO_Q_OUTPUT_VALUE_05_0) \
_op_(GPIO_Q_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_Q_ENABLE_CONFIG_06_0) \
_op_(GPIO_Q_DEBOUNCE_THRESHOLD_06_0) \
_op_(GPIO_Q_INPUT_06_0) \
_op_(GPIO_Q_OUTPUT_CONTROL_06_0) \
_op_(GPIO_Q_OUTPUT_VALUE_06_0) \
_op_(GPIO_Q_INTERRUPT_CLEAR_06_0) \
_op_(GPIO_Q_ENABLE_CONFIG_07_0) \
_op_(GPIO_Q_DEBOUNCE_THRESHOLD_07_0) \
_op_(GPIO_Q_INPUT_07_0) \
_op_(GPIO_Q_OUTPUT_CONTROL_07_0) \
_op_(GPIO_Q_OUTPUT_VALUE_07_0) \
_op_(GPIO_Q_INTERRUPT_CLEAR_07_0) \
_op_(GPIO_Q_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_Q_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_Q_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_Q_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_Q_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_Q_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_Q_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_Q_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_R_ENABLE_CONFIG_00_0) \
_op_(GPIO_R_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_R_INPUT_00_0) \
_op_(GPIO_R_OUTPUT_CONTROL_00_0) \
_op_(GPIO_R_OUTPUT_VALUE_00_0) \
_op_(GPIO_R_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_R_ENABLE_CONFIG_01_0) \
_op_(GPIO_R_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_R_INPUT_01_0) \
_op_(GPIO_R_OUTPUT_CONTROL_01_0) \
_op_(GPIO_R_OUTPUT_VALUE_01_0) \
_op_(GPIO_R_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_R_ENABLE_CONFIG_02_0) \
_op_(GPIO_R_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_R_INPUT_02_0) \
_op_(GPIO_R_OUTPUT_CONTROL_02_0) \
_op_(GPIO_R_OUTPUT_VALUE_02_0) \
_op_(GPIO_R_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_R_ENABLE_CONFIG_03_0) \
_op_(GPIO_R_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_R_INPUT_03_0) \
_op_(GPIO_R_OUTPUT_CONTROL_03_0) \
_op_(GPIO_R_OUTPUT_VALUE_03_0) \
_op_(GPIO_R_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_R_ENABLE_CONFIG_04_0) \
_op_(GPIO_R_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_R_INPUT_04_0) \
_op_(GPIO_R_OUTPUT_CONTROL_04_0) \
_op_(GPIO_R_OUTPUT_VALUE_04_0) \
_op_(GPIO_R_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_R_ENABLE_CONFIG_05_0) \
_op_(GPIO_R_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_R_INPUT_05_0) \
_op_(GPIO_R_OUTPUT_CONTROL_05_0) \
_op_(GPIO_R_OUTPUT_VALUE_05_0) \
_op_(GPIO_R_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_R_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_R_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_R_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_R_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_R_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_R_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_R_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_R_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_K_ENABLE_CONFIG_00_0) \
_op_(GPIO_K_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_K_INPUT_00_0) \
_op_(GPIO_K_OUTPUT_CONTROL_00_0) \
_op_(GPIO_K_OUTPUT_VALUE_00_0) \
_op_(GPIO_K_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_K_ENABLE_CONFIG_01_0) \
_op_(GPIO_K_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_K_INPUT_01_0) \
_op_(GPIO_K_OUTPUT_CONTROL_01_0) \
_op_(GPIO_K_OUTPUT_VALUE_01_0) \
_op_(GPIO_K_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_K_ENABLE_CONFIG_02_0) \
_op_(GPIO_K_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_K_INPUT_02_0) \
_op_(GPIO_K_OUTPUT_CONTROL_02_0) \
_op_(GPIO_K_OUTPUT_VALUE_02_0) \
_op_(GPIO_K_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_K_ENABLE_CONFIG_03_0) \
_op_(GPIO_K_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_K_INPUT_03_0) \
_op_(GPIO_K_OUTPUT_CONTROL_03_0) \
_op_(GPIO_K_OUTPUT_VALUE_03_0) \
_op_(GPIO_K_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_K_ENABLE_CONFIG_04_0) \
_op_(GPIO_K_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_K_INPUT_04_0) \
_op_(GPIO_K_OUTPUT_CONTROL_04_0) \
_op_(GPIO_K_OUTPUT_VALUE_04_0) \
_op_(GPIO_K_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_K_ENABLE_CONFIG_05_0) \
_op_(GPIO_K_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_K_INPUT_05_0) \
_op_(GPIO_K_OUTPUT_CONTROL_05_0) \
_op_(GPIO_K_OUTPUT_VALUE_05_0) \
_op_(GPIO_K_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_K_ENABLE_CONFIG_06_0) \
_op_(GPIO_K_DEBOUNCE_THRESHOLD_06_0) \
_op_(GPIO_K_INPUT_06_0) \
_op_(GPIO_K_OUTPUT_CONTROL_06_0) \
_op_(GPIO_K_OUTPUT_VALUE_06_0) \
_op_(GPIO_K_INTERRUPT_CLEAR_06_0) \
_op_(GPIO_K_ENABLE_CONFIG_07_0) \
_op_(GPIO_K_DEBOUNCE_THRESHOLD_07_0) \
_op_(GPIO_K_INPUT_07_0) \
_op_(GPIO_K_OUTPUT_CONTROL_07_0) \
_op_(GPIO_K_OUTPUT_VALUE_07_0) \
_op_(GPIO_K_INTERRUPT_CLEAR_07_0) \
_op_(GPIO_K_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_K_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_K_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_K_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_K_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_K_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_K_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_K_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_L_ENABLE_CONFIG_00_0) \
_op_(GPIO_L_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_L_INPUT_00_0) \
_op_(GPIO_L_OUTPUT_CONTROL_00_0) \
_op_(GPIO_L_OUTPUT_VALUE_00_0) \
_op_(GPIO_L_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_L_ENABLE_CONFIG_01_0) \
_op_(GPIO_L_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_L_INPUT_01_0) \
_op_(GPIO_L_OUTPUT_CONTROL_01_0) \
_op_(GPIO_L_OUTPUT_VALUE_01_0) \
_op_(GPIO_L_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_L_ENABLE_CONFIG_02_0) \
_op_(GPIO_L_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_L_INPUT_02_0) \
_op_(GPIO_L_OUTPUT_CONTROL_02_0) \
_op_(GPIO_L_OUTPUT_VALUE_02_0) \
_op_(GPIO_L_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_L_ENABLE_CONFIG_03_0) \
_op_(GPIO_L_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_L_INPUT_03_0) \
_op_(GPIO_L_OUTPUT_CONTROL_03_0) \
_op_(GPIO_L_OUTPUT_VALUE_03_0) \
_op_(GPIO_L_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_L_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_L_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_L_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_L_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_L_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_L_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_L_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_L_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_FF_ENABLE_CONFIG_00_0) \
_op_(GPIO_FF_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_FF_INPUT_00_0) \
_op_(GPIO_FF_OUTPUT_CONTROL_00_0) \
_op_(GPIO_FF_OUTPUT_VALUE_00_0) \
_op_(GPIO_FF_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_FF_ENABLE_CONFIG_01_0) \
_op_(GPIO_FF_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_FF_INPUT_01_0) \
_op_(GPIO_FF_OUTPUT_CONTROL_01_0) \
_op_(GPIO_FF_OUTPUT_VALUE_01_0) \
_op_(GPIO_FF_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_FF_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_FF_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_FF_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_FF_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_FF_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_FF_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_FF_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_FF_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_S_ENABLE_CONFIG_00_0) \
_op_(GPIO_S_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_S_INPUT_00_0) \
_op_(GPIO_S_OUTPUT_CONTROL_00_0) \
_op_(GPIO_S_OUTPUT_VALUE_00_0) \
_op_(GPIO_S_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_S_ENABLE_CONFIG_01_0) \
_op_(GPIO_S_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_S_INPUT_01_0) \
_op_(GPIO_S_OUTPUT_CONTROL_01_0) \
_op_(GPIO_S_OUTPUT_VALUE_01_0) \
_op_(GPIO_S_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_S_ENABLE_CONFIG_02_0) \
_op_(GPIO_S_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_S_INPUT_02_0) \
_op_(GPIO_S_OUTPUT_CONTROL_02_0) \
_op_(GPIO_S_OUTPUT_VALUE_02_0) \
_op_(GPIO_S_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_S_ENABLE_CONFIG_03_0) \
_op_(GPIO_S_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_S_INPUT_03_0) \
_op_(GPIO_S_OUTPUT_CONTROL_03_0) \
_op_(GPIO_S_OUTPUT_VALUE_03_0) \
_op_(GPIO_S_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_S_ENABLE_CONFIG_04_0) \
_op_(GPIO_S_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_S_INPUT_04_0) \
_op_(GPIO_S_OUTPUT_CONTROL_04_0) \
_op_(GPIO_S_OUTPUT_VALUE_04_0) \
_op_(GPIO_S_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_S_ENABLE_CONFIG_05_0) \
_op_(GPIO_S_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_S_INPUT_05_0) \
_op_(GPIO_S_OUTPUT_CONTROL_05_0) \
_op_(GPIO_S_OUTPUT_VALUE_05_0) \
_op_(GPIO_S_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_S_ENABLE_CONFIG_06_0) \
_op_(GPIO_S_DEBOUNCE_THRESHOLD_06_0) \
_op_(GPIO_S_INPUT_06_0) \
_op_(GPIO_S_OUTPUT_CONTROL_06_0) \
_op_(GPIO_S_OUTPUT_VALUE_06_0) \
_op_(GPIO_S_INTERRUPT_CLEAR_06_0) \
_op_(GPIO_S_ENABLE_CONFIG_07_0) \
_op_(GPIO_S_DEBOUNCE_THRESHOLD_07_0) \
_op_(GPIO_S_INPUT_07_0) \
_op_(GPIO_S_OUTPUT_CONTROL_07_0) \
_op_(GPIO_S_OUTPUT_VALUE_07_0) \
_op_(GPIO_S_INTERRUPT_CLEAR_07_0) \
_op_(GPIO_S_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_S_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_S_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_S_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_S_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_S_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_S_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_S_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_T_ENABLE_CONFIG_00_0) \
_op_(GPIO_T_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_T_INPUT_00_0) \
_op_(GPIO_T_OUTPUT_CONTROL_00_0) \
_op_(GPIO_T_OUTPUT_VALUE_00_0) \
_op_(GPIO_T_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_T_ENABLE_CONFIG_01_0) \
_op_(GPIO_T_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_T_INPUT_01_0) \
_op_(GPIO_T_OUTPUT_CONTROL_01_0) \
_op_(GPIO_T_OUTPUT_VALUE_01_0) \
_op_(GPIO_T_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_T_ENABLE_CONFIG_02_0) \
_op_(GPIO_T_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_T_INPUT_02_0) \
_op_(GPIO_T_OUTPUT_CONTROL_02_0) \
_op_(GPIO_T_OUTPUT_VALUE_02_0) \
_op_(GPIO_T_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_T_ENABLE_CONFIG_03_0) \
_op_(GPIO_T_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_T_INPUT_03_0) \
_op_(GPIO_T_OUTPUT_CONTROL_03_0) \
_op_(GPIO_T_OUTPUT_VALUE_03_0) \
_op_(GPIO_T_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_T_ENABLE_CONFIG_04_0) \
_op_(GPIO_T_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_T_INPUT_04_0) \
_op_(GPIO_T_OUTPUT_CONTROL_04_0) \
_op_(GPIO_T_OUTPUT_VALUE_04_0) \
_op_(GPIO_T_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_T_ENABLE_CONFIG_05_0) \
_op_(GPIO_T_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_T_INPUT_05_0) \
_op_(GPIO_T_OUTPUT_CONTROL_05_0) \
_op_(GPIO_T_OUTPUT_VALUE_05_0) \
_op_(GPIO_T_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_T_ENABLE_CONFIG_06_0) \
_op_(GPIO_T_DEBOUNCE_THRESHOLD_06_0) \
_op_(GPIO_T_INPUT_06_0) \
_op_(GPIO_T_OUTPUT_CONTROL_06_0) \
_op_(GPIO_T_OUTPUT_VALUE_06_0) \
_op_(GPIO_T_INTERRUPT_CLEAR_06_0) \
_op_(GPIO_T_ENABLE_CONFIG_07_0) \
_op_(GPIO_T_DEBOUNCE_THRESHOLD_07_0) \
_op_(GPIO_T_INPUT_07_0) \
_op_(GPIO_T_OUTPUT_CONTROL_07_0) \
_op_(GPIO_T_OUTPUT_VALUE_07_0) \
_op_(GPIO_T_INTERRUPT_CLEAR_07_0) \
_op_(GPIO_T_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_T_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_T_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_T_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_T_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_T_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_T_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_T_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_U_ENABLE_CONFIG_00_0) \
_op_(GPIO_U_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_U_INPUT_00_0) \
_op_(GPIO_U_OUTPUT_CONTROL_00_0) \
_op_(GPIO_U_OUTPUT_VALUE_00_0) \
_op_(GPIO_U_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_U_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_U_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_U_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_U_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_U_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_U_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_U_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_U_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_G_ENABLE_CONFIG_00_0) \
_op_(GPIO_G_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_G_INPUT_00_0) \
_op_(GPIO_G_OUTPUT_CONTROL_00_0) \
_op_(GPIO_G_OUTPUT_VALUE_00_0) \
_op_(GPIO_G_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_G_ENABLE_CONFIG_01_0) \
_op_(GPIO_G_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_G_INPUT_01_0) \
_op_(GPIO_G_OUTPUT_CONTROL_01_0) \
_op_(GPIO_G_OUTPUT_VALUE_01_0) \
_op_(GPIO_G_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_G_ENABLE_CONFIG_02_0) \
_op_(GPIO_G_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_G_INPUT_02_0) \
_op_(GPIO_G_OUTPUT_CONTROL_02_0) \
_op_(GPIO_G_OUTPUT_VALUE_02_0) \
_op_(GPIO_G_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_G_ENABLE_CONFIG_03_0) \
_op_(GPIO_G_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_G_INPUT_03_0) \
_op_(GPIO_G_OUTPUT_CONTROL_03_0) \
_op_(GPIO_G_OUTPUT_VALUE_03_0) \
_op_(GPIO_G_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_G_ENABLE_CONFIG_04_0) \
_op_(GPIO_G_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_G_INPUT_04_0) \
_op_(GPIO_G_OUTPUT_CONTROL_04_0) \
_op_(GPIO_G_OUTPUT_VALUE_04_0) \
_op_(GPIO_G_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_G_ENABLE_CONFIG_05_0) \
_op_(GPIO_G_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_G_INPUT_05_0) \
_op_(GPIO_G_OUTPUT_CONTROL_05_0) \
_op_(GPIO_G_OUTPUT_VALUE_05_0) \
_op_(GPIO_G_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_G_ENABLE_CONFIG_06_0) \
_op_(GPIO_G_DEBOUNCE_THRESHOLD_06_0) \
_op_(GPIO_G_INPUT_06_0) \
_op_(GPIO_G_OUTPUT_CONTROL_06_0) \
_op_(GPIO_G_OUTPUT_VALUE_06_0) \
_op_(GPIO_G_INTERRUPT_CLEAR_06_0) \
_op_(GPIO_G_ENABLE_CONFIG_07_0) \
_op_(GPIO_G_DEBOUNCE_THRESHOLD_07_0) \
_op_(GPIO_G_INPUT_07_0) \
_op_(GPIO_G_OUTPUT_CONTROL_07_0) \
_op_(GPIO_G_OUTPUT_VALUE_07_0) \
_op_(GPIO_G_INTERRUPT_CLEAR_07_0) \
_op_(GPIO_G_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_G_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_G_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_G_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_G_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_G_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_G_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_G_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_H_ENABLE_CONFIG_00_0) \
_op_(GPIO_H_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_H_INPUT_00_0) \
_op_(GPIO_H_OUTPUT_CONTROL_00_0) \
_op_(GPIO_H_OUTPUT_VALUE_00_0) \
_op_(GPIO_H_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_H_ENABLE_CONFIG_01_0) \
_op_(GPIO_H_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_H_INPUT_01_0) \
_op_(GPIO_H_OUTPUT_CONTROL_01_0) \
_op_(GPIO_H_OUTPUT_VALUE_01_0) \
_op_(GPIO_H_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_H_ENABLE_CONFIG_02_0) \
_op_(GPIO_H_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_H_INPUT_02_0) \
_op_(GPIO_H_OUTPUT_CONTROL_02_0) \
_op_(GPIO_H_OUTPUT_VALUE_02_0) \
_op_(GPIO_H_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_H_ENABLE_CONFIG_03_0) \
_op_(GPIO_H_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_H_INPUT_03_0) \
_op_(GPIO_H_OUTPUT_CONTROL_03_0) \
_op_(GPIO_H_OUTPUT_VALUE_03_0) \
_op_(GPIO_H_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_H_ENABLE_CONFIG_04_0) \
_op_(GPIO_H_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_H_INPUT_04_0) \
_op_(GPIO_H_OUTPUT_CONTROL_04_0) \
_op_(GPIO_H_OUTPUT_VALUE_04_0) \
_op_(GPIO_H_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_H_ENABLE_CONFIG_05_0) \
_op_(GPIO_H_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_H_INPUT_05_0) \
_op_(GPIO_H_OUTPUT_CONTROL_05_0) \
_op_(GPIO_H_OUTPUT_VALUE_05_0) \
_op_(GPIO_H_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_H_ENABLE_CONFIG_06_0) \
_op_(GPIO_H_DEBOUNCE_THRESHOLD_06_0) \
_op_(GPIO_H_INPUT_06_0) \
_op_(GPIO_H_OUTPUT_CONTROL_06_0) \
_op_(GPIO_H_OUTPUT_VALUE_06_0) \
_op_(GPIO_H_INTERRUPT_CLEAR_06_0) \
_op_(GPIO_H_ENABLE_CONFIG_07_0) \
_op_(GPIO_H_DEBOUNCE_THRESHOLD_07_0) \
_op_(GPIO_H_INPUT_07_0) \
_op_(GPIO_H_OUTPUT_CONTROL_07_0) \
_op_(GPIO_H_OUTPUT_VALUE_07_0) \
_op_(GPIO_H_INTERRUPT_CLEAR_07_0) \
_op_(GPIO_H_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_H_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_H_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_H_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_H_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_H_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_H_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_H_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_I_ENABLE_CONFIG_00_0) \
_op_(GPIO_I_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_I_INPUT_00_0) \
_op_(GPIO_I_OUTPUT_CONTROL_00_0) \
_op_(GPIO_I_OUTPUT_VALUE_00_0) \
_op_(GPIO_I_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_I_ENABLE_CONFIG_01_0) \
_op_(GPIO_I_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_I_INPUT_01_0) \
_op_(GPIO_I_OUTPUT_CONTROL_01_0) \
_op_(GPIO_I_OUTPUT_VALUE_01_0) \
_op_(GPIO_I_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_I_ENABLE_CONFIG_02_0) \
_op_(GPIO_I_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_I_INPUT_02_0) \
_op_(GPIO_I_OUTPUT_CONTROL_02_0) \
_op_(GPIO_I_OUTPUT_VALUE_02_0) \
_op_(GPIO_I_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_I_ENABLE_CONFIG_03_0) \
_op_(GPIO_I_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_I_INPUT_03_0) \
_op_(GPIO_I_OUTPUT_CONTROL_03_0) \
_op_(GPIO_I_OUTPUT_VALUE_03_0) \
_op_(GPIO_I_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_I_ENABLE_CONFIG_04_0) \
_op_(GPIO_I_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_I_INPUT_04_0) \
_op_(GPIO_I_OUTPUT_CONTROL_04_0) \
_op_(GPIO_I_OUTPUT_VALUE_04_0) \
_op_(GPIO_I_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_I_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_I_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_I_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_I_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_I_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_I_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_I_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_I_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_C_ENABLE_CONFIG_00_0) \
_op_(GPIO_C_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_C_INPUT_00_0) \
_op_(GPIO_C_OUTPUT_CONTROL_00_0) \
_op_(GPIO_C_OUTPUT_VALUE_00_0) \
_op_(GPIO_C_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_C_ENABLE_CONFIG_01_0) \
_op_(GPIO_C_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_C_INPUT_01_0) \
_op_(GPIO_C_OUTPUT_CONTROL_01_0) \
_op_(GPIO_C_OUTPUT_VALUE_01_0) \
_op_(GPIO_C_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_C_ENABLE_CONFIG_02_0) \
_op_(GPIO_C_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_C_INPUT_02_0) \
_op_(GPIO_C_OUTPUT_CONTROL_02_0) \
_op_(GPIO_C_OUTPUT_VALUE_02_0) \
_op_(GPIO_C_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_C_ENABLE_CONFIG_03_0) \
_op_(GPIO_C_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_C_INPUT_03_0) \
_op_(GPIO_C_OUTPUT_CONTROL_03_0) \
_op_(GPIO_C_OUTPUT_VALUE_03_0) \
_op_(GPIO_C_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_C_ENABLE_CONFIG_04_0) \
_op_(GPIO_C_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_C_INPUT_04_0) \
_op_(GPIO_C_OUTPUT_CONTROL_04_0) \
_op_(GPIO_C_OUTPUT_VALUE_04_0) \
_op_(GPIO_C_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_C_ENABLE_CONFIG_05_0) \
_op_(GPIO_C_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_C_INPUT_05_0) \
_op_(GPIO_C_OUTPUT_CONTROL_05_0) \
_op_(GPIO_C_OUTPUT_VALUE_05_0) \
_op_(GPIO_C_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_C_ENABLE_CONFIG_06_0) \
_op_(GPIO_C_DEBOUNCE_THRESHOLD_06_0) \
_op_(GPIO_C_INPUT_06_0) \
_op_(GPIO_C_OUTPUT_CONTROL_06_0) \
_op_(GPIO_C_OUTPUT_VALUE_06_0) \
_op_(GPIO_C_INTERRUPT_CLEAR_06_0) \
_op_(GPIO_C_ENABLE_CONFIG_07_0) \
_op_(GPIO_C_DEBOUNCE_THRESHOLD_07_0) \
_op_(GPIO_C_INPUT_07_0) \
_op_(GPIO_C_OUTPUT_CONTROL_07_0) \
_op_(GPIO_C_OUTPUT_VALUE_07_0) \
_op_(GPIO_C_INTERRUPT_CLEAR_07_0) \
_op_(GPIO_C_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_C_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_C_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_C_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_C_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_C_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_C_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_C_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_D_ENABLE_CONFIG_00_0) \
_op_(GPIO_D_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_D_INPUT_00_0) \
_op_(GPIO_D_OUTPUT_CONTROL_00_0) \
_op_(GPIO_D_OUTPUT_VALUE_00_0) \
_op_(GPIO_D_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_D_ENABLE_CONFIG_01_0) \
_op_(GPIO_D_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_D_INPUT_01_0) \
_op_(GPIO_D_OUTPUT_CONTROL_01_0) \
_op_(GPIO_D_OUTPUT_VALUE_01_0) \
_op_(GPIO_D_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_D_ENABLE_CONFIG_02_0) \
_op_(GPIO_D_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_D_INPUT_02_0) \
_op_(GPIO_D_OUTPUT_CONTROL_02_0) \
_op_(GPIO_D_OUTPUT_VALUE_02_0) \
_op_(GPIO_D_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_D_ENABLE_CONFIG_03_0) \
_op_(GPIO_D_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_D_INPUT_03_0) \
_op_(GPIO_D_OUTPUT_CONTROL_03_0) \
_op_(GPIO_D_OUTPUT_VALUE_03_0) \
_op_(GPIO_D_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_D_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_D_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_D_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_D_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_D_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_D_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_D_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_D_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_E_ENABLE_CONFIG_00_0) \
_op_(GPIO_E_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_E_INPUT_00_0) \
_op_(GPIO_E_OUTPUT_CONTROL_00_0) \
_op_(GPIO_E_OUTPUT_VALUE_00_0) \
_op_(GPIO_E_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_E_ENABLE_CONFIG_01_0) \
_op_(GPIO_E_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_E_INPUT_01_0) \
_op_(GPIO_E_OUTPUT_CONTROL_01_0) \
_op_(GPIO_E_OUTPUT_VALUE_01_0) \
_op_(GPIO_E_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_E_ENABLE_CONFIG_02_0) \
_op_(GPIO_E_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_E_INPUT_02_0) \
_op_(GPIO_E_OUTPUT_CONTROL_02_0) \
_op_(GPIO_E_OUTPUT_VALUE_02_0) \
_op_(GPIO_E_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_E_ENABLE_CONFIG_03_0) \
_op_(GPIO_E_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_E_INPUT_03_0) \
_op_(GPIO_E_OUTPUT_CONTROL_03_0) \
_op_(GPIO_E_OUTPUT_VALUE_03_0) \
_op_(GPIO_E_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_E_ENABLE_CONFIG_04_0) \
_op_(GPIO_E_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_E_INPUT_04_0) \
_op_(GPIO_E_OUTPUT_CONTROL_04_0) \
_op_(GPIO_E_OUTPUT_VALUE_04_0) \
_op_(GPIO_E_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_E_ENABLE_CONFIG_05_0) \
_op_(GPIO_E_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_E_INPUT_05_0) \
_op_(GPIO_E_OUTPUT_CONTROL_05_0) \
_op_(GPIO_E_OUTPUT_VALUE_05_0) \
_op_(GPIO_E_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_E_ENABLE_CONFIG_06_0) \
_op_(GPIO_E_DEBOUNCE_THRESHOLD_06_0) \
_op_(GPIO_E_INPUT_06_0) \
_op_(GPIO_E_OUTPUT_CONTROL_06_0) \
_op_(GPIO_E_OUTPUT_VALUE_06_0) \
_op_(GPIO_E_INTERRUPT_CLEAR_06_0) \
_op_(GPIO_E_ENABLE_CONFIG_07_0) \
_op_(GPIO_E_DEBOUNCE_THRESHOLD_07_0) \
_op_(GPIO_E_INPUT_07_0) \
_op_(GPIO_E_OUTPUT_CONTROL_07_0) \
_op_(GPIO_E_OUTPUT_VALUE_07_0) \
_op_(GPIO_E_INTERRUPT_CLEAR_07_0) \
_op_(GPIO_E_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_E_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_E_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_E_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_E_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_E_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_E_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_E_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_F_ENABLE_CONFIG_00_0) \
_op_(GPIO_F_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_F_INPUT_00_0) \
_op_(GPIO_F_OUTPUT_CONTROL_00_0) \
_op_(GPIO_F_OUTPUT_VALUE_00_0) \
_op_(GPIO_F_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_F_ENABLE_CONFIG_01_0) \
_op_(GPIO_F_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_F_INPUT_01_0) \
_op_(GPIO_F_OUTPUT_CONTROL_01_0) \
_op_(GPIO_F_OUTPUT_VALUE_01_0) \
_op_(GPIO_F_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_F_ENABLE_CONFIG_02_0) \
_op_(GPIO_F_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_F_INPUT_02_0) \
_op_(GPIO_F_OUTPUT_CONTROL_02_0) \
_op_(GPIO_F_OUTPUT_VALUE_02_0) \
_op_(GPIO_F_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_F_ENABLE_CONFIG_03_0) \
_op_(GPIO_F_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_F_INPUT_03_0) \
_op_(GPIO_F_OUTPUT_CONTROL_03_0) \
_op_(GPIO_F_OUTPUT_VALUE_03_0) \
_op_(GPIO_F_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_F_ENABLE_CONFIG_04_0) \
_op_(GPIO_F_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_F_INPUT_04_0) \
_op_(GPIO_F_OUTPUT_CONTROL_04_0) \
_op_(GPIO_F_OUTPUT_VALUE_04_0) \
_op_(GPIO_F_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_F_ENABLE_CONFIG_05_0) \
_op_(GPIO_F_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_F_INPUT_05_0) \
_op_(GPIO_F_OUTPUT_CONTROL_05_0) \
_op_(GPIO_F_OUTPUT_VALUE_05_0) \
_op_(GPIO_F_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_F_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_F_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_F_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_F_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_F_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_F_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_F_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_F_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_B_ENABLE_CONFIG_00_0) \
_op_(GPIO_B_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_B_INPUT_00_0) \
_op_(GPIO_B_OUTPUT_CONTROL_00_0) \
_op_(GPIO_B_OUTPUT_VALUE_00_0) \
_op_(GPIO_B_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_B_ENABLE_CONFIG_01_0) \
_op_(GPIO_B_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_B_INPUT_01_0) \
_op_(GPIO_B_OUTPUT_CONTROL_01_0) \
_op_(GPIO_B_OUTPUT_VALUE_01_0) \
_op_(GPIO_B_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_B_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_B_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_B_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_B_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_B_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_B_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_B_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_B_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_O_ENABLE_CONFIG_00_0) \
_op_(GPIO_O_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_O_INPUT_00_0) \
_op_(GPIO_O_OUTPUT_CONTROL_00_0) \
_op_(GPIO_O_OUTPUT_VALUE_00_0) \
_op_(GPIO_O_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_O_ENABLE_CONFIG_01_0) \
_op_(GPIO_O_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_O_INPUT_01_0) \
_op_(GPIO_O_OUTPUT_CONTROL_01_0) \
_op_(GPIO_O_OUTPUT_VALUE_01_0) \
_op_(GPIO_O_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_O_ENABLE_CONFIG_02_0) \
_op_(GPIO_O_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_O_INPUT_02_0) \
_op_(GPIO_O_OUTPUT_CONTROL_02_0) \
_op_(GPIO_O_OUTPUT_VALUE_02_0) \
_op_(GPIO_O_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_O_ENABLE_CONFIG_03_0) \
_op_(GPIO_O_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_O_INPUT_03_0) \
_op_(GPIO_O_OUTPUT_CONTROL_03_0) \
_op_(GPIO_O_OUTPUT_VALUE_03_0) \
_op_(GPIO_O_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_O_ENABLE_CONFIG_04_0) \
_op_(GPIO_O_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_O_INPUT_04_0) \
_op_(GPIO_O_OUTPUT_CONTROL_04_0) \
_op_(GPIO_O_OUTPUT_VALUE_04_0) \
_op_(GPIO_O_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_O_ENABLE_CONFIG_05_0) \
_op_(GPIO_O_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_O_INPUT_05_0) \
_op_(GPIO_O_OUTPUT_CONTROL_05_0) \
_op_(GPIO_O_OUTPUT_VALUE_05_0) \
_op_(GPIO_O_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_O_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_O_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_O_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_O_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_O_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_O_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_O_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_O_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_J_ENABLE_CONFIG_00_0) \
_op_(GPIO_J_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_J_INPUT_00_0) \
_op_(GPIO_J_OUTPUT_CONTROL_00_0) \
_op_(GPIO_J_OUTPUT_VALUE_00_0) \
_op_(GPIO_J_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_J_ENABLE_CONFIG_01_0) \
_op_(GPIO_J_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_J_INPUT_01_0) \
_op_(GPIO_J_OUTPUT_CONTROL_01_0) \
_op_(GPIO_J_OUTPUT_VALUE_01_0) \
_op_(GPIO_J_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_J_ENABLE_CONFIG_02_0) \
_op_(GPIO_J_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_J_INPUT_02_0) \
_op_(GPIO_J_OUTPUT_CONTROL_02_0) \
_op_(GPIO_J_OUTPUT_VALUE_02_0) \
_op_(GPIO_J_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_J_ENABLE_CONFIG_03_0) \
_op_(GPIO_J_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_J_INPUT_03_0) \
_op_(GPIO_J_OUTPUT_CONTROL_03_0) \
_op_(GPIO_J_OUTPUT_VALUE_03_0) \
_op_(GPIO_J_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_J_ENABLE_CONFIG_04_0) \
_op_(GPIO_J_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_J_INPUT_04_0) \
_op_(GPIO_J_OUTPUT_CONTROL_04_0) \
_op_(GPIO_J_OUTPUT_VALUE_04_0) \
_op_(GPIO_J_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_J_ENABLE_CONFIG_05_0) \
_op_(GPIO_J_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_J_INPUT_05_0) \
_op_(GPIO_J_OUTPUT_CONTROL_05_0) \
_op_(GPIO_J_OUTPUT_VALUE_05_0) \
_op_(GPIO_J_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_J_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_J_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_J_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_J_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_J_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_J_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_J_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_J_INTERRUPT_STATUS_G7_0)


//
// ADDRESS SPACES
//

#define BASE_ADDRESS_GPIO       0x00000000

//
// ARGPIO REGISTER BANKS
//

#define GPIO0_FIRST_REG 0x0000 // GPIO_GG_VM_00_0
#define GPIO0_LAST_REG 0x000c // GPIO_GG_SCR_01_0
#define GPIO1_FIRST_REG 0x0800 // GPIO_CTL0_VM_SCR_0
#define GPIO1_LAST_REG 0x0834 // GPIO_CTL0_SPARE_0
#define GPIO2_FIRST_REG 0x1000 // GPIO_V_VM_00_0
#define GPIO2_LAST_REG 0x104c // GPIO_W_SCR_01_0
#define GPIO3_FIRST_REG 0x1080 // GPIO_A_VM_00_0
#define GPIO3_LAST_REG 0x10bc // GPIO_A_SCR_07_0
#define GPIO4_FIRST_REG 0x1800 // GPIO_CTL1_VM_SCR_0
#define GPIO4_LAST_REG 0x1874 // GPIO_CTL1_SPARE_0
#define GPIO5_FIRST_REG 0x2000 // GPIO_X_VM_00_0
#define GPIO5_LAST_REG 0x2114 // GPIO_N_SCR_02_0
#define GPIO6_FIRST_REG 0x2140 // GPIO_P_VM_00_0
#define GPIO6_LAST_REG 0x21ec // GPIO_R_SCR_05_0
#define GPIO7_FIRST_REG 0x2800 // GPIO_CTL2_VM_SCR_0
#define GPIO7_LAST_REG 0x2914 // GPIO_CTL2_SPARE_0
#define GPIO8_FIRST_REG 0x3000 // GPIO_K_VM_00_0
#define GPIO8_LAST_REG 0x305c // GPIO_L_SCR_03_0
#define GPIO9_FIRST_REG 0x3080 // GPIO_FF_VM_00_0
#define GPIO9_LAST_REG 0x308c // GPIO_FF_SCR_01_0
#define GPIO10_FIRST_REG 0x30c0 // GPIO_S_VM_00_0
#define GPIO10_LAST_REG 0x3144 // GPIO_U_SCR_00_0
#define GPIO11_FIRST_REG 0x3800 // GPIO_CTL3_VM_SCR_0
#define GPIO11_LAST_REG 0x38d4 // GPIO_CTL3_SPARE_0
#define GPIO12_FIRST_REG 0x4000 // GPIO_G_VM_00_0
#define GPIO12_LAST_REG 0x40a4 // GPIO_I_SCR_04_0
#define GPIO13_FIRST_REG 0x40c0 // GPIO_C_VM_00_0
#define GPIO13_LAST_REG 0x411c // GPIO_D_SCR_03_0
#define GPIO14_FIRST_REG 0x4140 // GPIO_E_VM_00_0
#define GPIO14_LAST_REG 0x41ac // GPIO_F_SCR_05_0
#define GPIO15_FIRST_REG 0x41c0 // GPIO_B_VM_00_0
#define GPIO15_LAST_REG 0x41cc // GPIO_B_SCR_01_0
#define GPIO16_FIRST_REG 0x4800 // GPIO_CTL4_VM_SCR_0
#define GPIO16_LAST_REG 0x4914 // GPIO_CTL4_SPARE_0
#define GPIO17_FIRST_REG 0x5000 // GPIO_O_VM_00_0
#define GPIO17_LAST_REG 0x502c // GPIO_O_SCR_05_0
#define GPIO18_FIRST_REG 0x5040 // GPIO_J_VM_00_0
#define GPIO18_LAST_REG 0x506c // GPIO_J_SCR_05_0
#define GPIO19_FIRST_REG 0x5800 // GPIO_CTL5_VM_SCR_0
#define GPIO19_LAST_REG 0x5854 // GPIO_CTL5_SPARE_0
#define GPIO20_FIRST_REG 0x10000 // GPIO_GG_ENABLE_CONFIG_00_0
#define GPIO20_LAST_REG 0x10014 // GPIO_GG_INTERRUPT_CLEAR_00_0
#define GPIO21_FIRST_REG 0x10020 // GPIO_GG_ENABLE_CONFIG_01_0
#define GPIO21_LAST_REG 0x10034 // GPIO_GG_INTERRUPT_CLEAR_01_0
#define GPIO22_FIRST_REG 0x10100 // GPIO_GG_INTERRUPT_STATUS_G0_0
#define GPIO22_LAST_REG 0x1011c // GPIO_GG_INTERRUPT_STATUS_G7_0
#define GPIO23_FIRST_REG 0x11000 // GPIO_V_ENABLE_CONFIG_00_0
#define GPIO23_LAST_REG 0x11014 // GPIO_V_INTERRUPT_CLEAR_00_0
#define GPIO24_FIRST_REG 0x11020 // GPIO_V_ENABLE_CONFIG_01_0
#define GPIO24_LAST_REG 0x11034 // GPIO_V_INTERRUPT_CLEAR_01_0
#define GPIO25_FIRST_REG 0x11040 // GPIO_V_ENABLE_CONFIG_02_0
#define GPIO25_LAST_REG 0x11054 // GPIO_V_INTERRUPT_CLEAR_02_0
#define GPIO26_FIRST_REG 0x11060 // GPIO_V_ENABLE_CONFIG_03_0
#define GPIO26_LAST_REG 0x11074 // GPIO_V_INTERRUPT_CLEAR_03_0
#define GPIO27_FIRST_REG 0x11080 // GPIO_V_ENABLE_CONFIG_04_0
#define GPIO27_LAST_REG 0x11094 // GPIO_V_INTERRUPT_CLEAR_04_0
#define GPIO28_FIRST_REG 0x110a0 // GPIO_V_ENABLE_CONFIG_05_0
#define GPIO28_LAST_REG 0x110b4 // GPIO_V_INTERRUPT_CLEAR_05_0
#define GPIO29_FIRST_REG 0x110c0 // GPIO_V_ENABLE_CONFIG_06_0
#define GPIO29_LAST_REG 0x110d4 // GPIO_V_INTERRUPT_CLEAR_06_0
#define GPIO30_FIRST_REG 0x110e0 // GPIO_V_ENABLE_CONFIG_07_0
#define GPIO30_LAST_REG 0x110f4 // GPIO_V_INTERRUPT_CLEAR_07_0
#define GPIO31_FIRST_REG 0x11100 // GPIO_V_INTERRUPT_STATUS_G0_0
#define GPIO31_LAST_REG 0x1111c // GPIO_V_INTERRUPT_STATUS_G7_0
#define GPIO32_FIRST_REG 0x11200 // GPIO_W_ENABLE_CONFIG_00_0
#define GPIO32_LAST_REG 0x11214 // GPIO_W_INTERRUPT_CLEAR_00_0
#define GPIO33_FIRST_REG 0x11220 // GPIO_W_ENABLE_CONFIG_01_0
#define GPIO33_LAST_REG 0x11234 // GPIO_W_INTERRUPT_CLEAR_01_0
#define GPIO34_FIRST_REG 0x11300 // GPIO_W_INTERRUPT_STATUS_G0_0
#define GPIO34_LAST_REG 0x1131c // GPIO_W_INTERRUPT_STATUS_G7_0
#define GPIO35_FIRST_REG 0x11400 // GPIO_A_ENABLE_CONFIG_00_0
#define GPIO35_LAST_REG 0x11414 // GPIO_A_INTERRUPT_CLEAR_00_0
#define GPIO36_FIRST_REG 0x11420 // GPIO_A_ENABLE_CONFIG_01_0
#define GPIO36_LAST_REG 0x11434 // GPIO_A_INTERRUPT_CLEAR_01_0
#define GPIO37_FIRST_REG 0x11440 // GPIO_A_ENABLE_CONFIG_02_0
#define GPIO37_LAST_REG 0x11454 // GPIO_A_INTERRUPT_CLEAR_02_0
#define GPIO38_FIRST_REG 0x11460 // GPIO_A_ENABLE_CONFIG_03_0
#define GPIO38_LAST_REG 0x11474 // GPIO_A_INTERRUPT_CLEAR_03_0
#define GPIO39_FIRST_REG 0x11480 // GPIO_A_ENABLE_CONFIG_04_0
#define GPIO39_LAST_REG 0x11494 // GPIO_A_INTERRUPT_CLEAR_04_0
#define GPIO40_FIRST_REG 0x114a0 // GPIO_A_ENABLE_CONFIG_05_0
#define GPIO40_LAST_REG 0x114b4 // GPIO_A_INTERRUPT_CLEAR_05_0
#define GPIO41_FIRST_REG 0x114c0 // GPIO_A_ENABLE_CONFIG_06_0
#define GPIO41_LAST_REG 0x114d4 // GPIO_A_INTERRUPT_CLEAR_06_0
#define GPIO42_FIRST_REG 0x114e0 // GPIO_A_ENABLE_CONFIG_07_0
#define GPIO42_LAST_REG 0x114f4 // GPIO_A_INTERRUPT_CLEAR_07_0
#define GPIO43_FIRST_REG 0x11500 // GPIO_A_INTERRUPT_STATUS_G0_0
#define GPIO43_LAST_REG 0x1151c // GPIO_A_INTERRUPT_STATUS_G7_0
#define GPIO44_FIRST_REG 0x12000 // GPIO_X_ENABLE_CONFIG_00_0
#define GPIO44_LAST_REG 0x12014 // GPIO_X_INTERRUPT_CLEAR_00_0
#define GPIO45_FIRST_REG 0x12020 // GPIO_X_ENABLE_CONFIG_01_0
#define GPIO45_LAST_REG 0x12034 // GPIO_X_INTERRUPT_CLEAR_01_0
#define GPIO46_FIRST_REG 0x12040 // GPIO_X_ENABLE_CONFIG_02_0
#define GPIO46_LAST_REG 0x12054 // GPIO_X_INTERRUPT_CLEAR_02_0
#define GPIO47_FIRST_REG 0x12060 // GPIO_X_ENABLE_CONFIG_03_0
#define GPIO47_LAST_REG 0x12074 // GPIO_X_INTERRUPT_CLEAR_03_0
#define GPIO48_FIRST_REG 0x12080 // GPIO_X_ENABLE_CONFIG_04_0
#define GPIO48_LAST_REG 0x12094 // GPIO_X_INTERRUPT_CLEAR_04_0
#define GPIO49_FIRST_REG 0x120a0 // GPIO_X_ENABLE_CONFIG_05_0
#define GPIO49_LAST_REG 0x120b4 // GPIO_X_INTERRUPT_CLEAR_05_0
#define GPIO50_FIRST_REG 0x120c0 // GPIO_X_ENABLE_CONFIG_06_0
#define GPIO50_LAST_REG 0x120d4 // GPIO_X_INTERRUPT_CLEAR_06_0
#define GPIO51_FIRST_REG 0x120e0 // GPIO_X_ENABLE_CONFIG_07_0
#define GPIO51_LAST_REG 0x120f4 // GPIO_X_INTERRUPT_CLEAR_07_0
#define GPIO52_FIRST_REG 0x12100 // GPIO_X_INTERRUPT_STATUS_G0_0
#define GPIO52_LAST_REG 0x1211c // GPIO_X_INTERRUPT_STATUS_G7_0
#define GPIO53_FIRST_REG 0x12200 // GPIO_Y_ENABLE_CONFIG_00_0
#define GPIO53_LAST_REG 0x12214 // GPIO_Y_INTERRUPT_CLEAR_00_0
#define GPIO54_FIRST_REG 0x12220 // GPIO_Y_ENABLE_CONFIG_01_0
#define GPIO54_LAST_REG 0x12234 // GPIO_Y_INTERRUPT_CLEAR_01_0
#define GPIO55_FIRST_REG 0x12240 // GPIO_Y_ENABLE_CONFIG_02_0
#define GPIO55_LAST_REG 0x12254 // GPIO_Y_INTERRUPT_CLEAR_02_0
#define GPIO56_FIRST_REG 0x12260 // GPIO_Y_ENABLE_CONFIG_03_0
#define GPIO56_LAST_REG 0x12274 // GPIO_Y_INTERRUPT_CLEAR_03_0
#define GPIO57_FIRST_REG 0x12280 // GPIO_Y_ENABLE_CONFIG_04_0
#define GPIO57_LAST_REG 0x12294 // GPIO_Y_INTERRUPT_CLEAR_04_0
#define GPIO58_FIRST_REG 0x122a0 // GPIO_Y_ENABLE_CONFIG_05_0
#define GPIO58_LAST_REG 0x122b4 // GPIO_Y_INTERRUPT_CLEAR_05_0
#define GPIO59_FIRST_REG 0x122c0 // GPIO_Y_ENABLE_CONFIG_06_0
#define GPIO59_LAST_REG 0x122d4 // GPIO_Y_INTERRUPT_CLEAR_06_0
#define GPIO60_FIRST_REG 0x122e0 // GPIO_Y_ENABLE_CONFIG_07_0
#define GPIO60_LAST_REG 0x122f4 // GPIO_Y_INTERRUPT_CLEAR_07_0
#define GPIO61_FIRST_REG 0x12300 // GPIO_Y_INTERRUPT_STATUS_G0_0
#define GPIO61_LAST_REG 0x1231c // GPIO_Y_INTERRUPT_STATUS_G7_0
#define GPIO62_FIRST_REG 0x12400 // GPIO_Z_ENABLE_CONFIG_00_0
#define GPIO62_LAST_REG 0x12414 // GPIO_Z_INTERRUPT_CLEAR_00_0
#define GPIO63_FIRST_REG 0x12420 // GPIO_Z_ENABLE_CONFIG_01_0
#define GPIO63_LAST_REG 0x12434 // GPIO_Z_INTERRUPT_CLEAR_01_0
#define GPIO64_FIRST_REG 0x12440 // GPIO_Z_ENABLE_CONFIG_02_0
#define GPIO64_LAST_REG 0x12454 // GPIO_Z_INTERRUPT_CLEAR_02_0
#define GPIO65_FIRST_REG 0x12460 // GPIO_Z_ENABLE_CONFIG_03_0
#define GPIO65_LAST_REG 0x12474 // GPIO_Z_INTERRUPT_CLEAR_03_0
#define GPIO66_FIRST_REG 0x12480 // GPIO_Z_ENABLE_CONFIG_04_0
#define GPIO66_LAST_REG 0x12494 // GPIO_Z_INTERRUPT_CLEAR_04_0
#define GPIO67_FIRST_REG 0x124a0 // GPIO_Z_ENABLE_CONFIG_05_0
#define GPIO67_LAST_REG 0x124b4 // GPIO_Z_INTERRUPT_CLEAR_05_0
#define GPIO68_FIRST_REG 0x124c0 // GPIO_Z_ENABLE_CONFIG_06_0
#define GPIO68_LAST_REG 0x124d4 // GPIO_Z_INTERRUPT_CLEAR_06_0
#define GPIO69_FIRST_REG 0x124e0 // GPIO_Z_ENABLE_CONFIG_07_0
#define GPIO69_LAST_REG 0x124f4 // GPIO_Z_INTERRUPT_CLEAR_07_0
#define GPIO70_FIRST_REG 0x12500 // GPIO_Z_INTERRUPT_STATUS_G0_0
#define GPIO70_LAST_REG 0x1251c // GPIO_Z_INTERRUPT_STATUS_G7_0
#define GPIO71_FIRST_REG 0x12600 // GPIO_M_ENABLE_CONFIG_00_0
#define GPIO71_LAST_REG 0x12614 // GPIO_M_INTERRUPT_CLEAR_00_0
#define GPIO72_FIRST_REG 0x12620 // GPIO_M_ENABLE_CONFIG_01_0
#define GPIO72_LAST_REG 0x12634 // GPIO_M_INTERRUPT_CLEAR_01_0
#define GPIO73_FIRST_REG 0x12640 // GPIO_M_ENABLE_CONFIG_02_0
#define GPIO73_LAST_REG 0x12654 // GPIO_M_INTERRUPT_CLEAR_02_0
#define GPIO74_FIRST_REG 0x12660 // GPIO_M_ENABLE_CONFIG_03_0
#define GPIO74_LAST_REG 0x12674 // GPIO_M_INTERRUPT_CLEAR_03_0
#define GPIO75_FIRST_REG 0x12680 // GPIO_M_ENABLE_CONFIG_04_0
#define GPIO75_LAST_REG 0x12694 // GPIO_M_INTERRUPT_CLEAR_04_0
#define GPIO76_FIRST_REG 0x126a0 // GPIO_M_ENABLE_CONFIG_05_0
#define GPIO76_LAST_REG 0x126b4 // GPIO_M_INTERRUPT_CLEAR_05_0
#define GPIO77_FIRST_REG 0x126c0 // GPIO_M_ENABLE_CONFIG_06_0
#define GPIO77_LAST_REG 0x126d4 // GPIO_M_INTERRUPT_CLEAR_06_0
#define GPIO78_FIRST_REG 0x126e0 // GPIO_M_ENABLE_CONFIG_07_0
#define GPIO78_LAST_REG 0x126f4 // GPIO_M_INTERRUPT_CLEAR_07_0
#define GPIO79_FIRST_REG 0x12700 // GPIO_M_INTERRUPT_STATUS_G0_0
#define GPIO79_LAST_REG 0x1271c // GPIO_M_INTERRUPT_STATUS_G7_0
#define GPIO80_FIRST_REG 0x12800 // GPIO_N_ENABLE_CONFIG_00_0
#define GPIO80_LAST_REG 0x12814 // GPIO_N_INTERRUPT_CLEAR_00_0
#define GPIO81_FIRST_REG 0x12820 // GPIO_N_ENABLE_CONFIG_01_0
#define GPIO81_LAST_REG 0x12834 // GPIO_N_INTERRUPT_CLEAR_01_0
#define GPIO82_FIRST_REG 0x12840 // GPIO_N_ENABLE_CONFIG_02_0
#define GPIO82_LAST_REG 0x12854 // GPIO_N_INTERRUPT_CLEAR_02_0
#define GPIO83_FIRST_REG 0x12900 // GPIO_N_INTERRUPT_STATUS_G0_0
#define GPIO83_LAST_REG 0x1291c // GPIO_N_INTERRUPT_STATUS_G7_0
#define GPIO84_FIRST_REG 0x12a00 // GPIO_P_ENABLE_CONFIG_00_0
#define GPIO84_LAST_REG 0x12a14 // GPIO_P_INTERRUPT_CLEAR_00_0
#define GPIO85_FIRST_REG 0x12a20 // GPIO_P_ENABLE_CONFIG_01_0
#define GPIO85_LAST_REG 0x12a34 // GPIO_P_INTERRUPT_CLEAR_01_0
#define GPIO86_FIRST_REG 0x12a40 // GPIO_P_ENABLE_CONFIG_02_0
#define GPIO86_LAST_REG 0x12a54 // GPIO_P_INTERRUPT_CLEAR_02_0
#define GPIO87_FIRST_REG 0x12a60 // GPIO_P_ENABLE_CONFIG_03_0
#define GPIO87_LAST_REG 0x12a74 // GPIO_P_INTERRUPT_CLEAR_03_0
#define GPIO88_FIRST_REG 0x12a80 // GPIO_P_ENABLE_CONFIG_04_0
#define GPIO88_LAST_REG 0x12a94 // GPIO_P_INTERRUPT_CLEAR_04_0
#define GPIO89_FIRST_REG 0x12aa0 // GPIO_P_ENABLE_CONFIG_05_0
#define GPIO89_LAST_REG 0x12ab4 // GPIO_P_INTERRUPT_CLEAR_05_0
#define GPIO90_FIRST_REG 0x12ac0 // GPIO_P_ENABLE_CONFIG_06_0
#define GPIO90_LAST_REG 0x12ad4 // GPIO_P_INTERRUPT_CLEAR_06_0
#define GPIO91_FIRST_REG 0x12ae0 // GPIO_P_ENABLE_CONFIG_07_0
#define GPIO91_LAST_REG 0x12af4 // GPIO_P_INTERRUPT_CLEAR_07_0
#define GPIO92_FIRST_REG 0x12b00 // GPIO_P_INTERRUPT_STATUS_G0_0
#define GPIO92_LAST_REG 0x12b1c // GPIO_P_INTERRUPT_STATUS_G7_0
#define GPIO93_FIRST_REG 0x12c00 // GPIO_Q_ENABLE_CONFIG_00_0
#define GPIO93_LAST_REG 0x12c14 // GPIO_Q_INTERRUPT_CLEAR_00_0
#define GPIO94_FIRST_REG 0x12c20 // GPIO_Q_ENABLE_CONFIG_01_0
#define GPIO94_LAST_REG 0x12c34 // GPIO_Q_INTERRUPT_CLEAR_01_0
#define GPIO95_FIRST_REG 0x12c40 // GPIO_Q_ENABLE_CONFIG_02_0
#define GPIO95_LAST_REG 0x12c54 // GPIO_Q_INTERRUPT_CLEAR_02_0
#define GPIO96_FIRST_REG 0x12c60 // GPIO_Q_ENABLE_CONFIG_03_0
#define GPIO96_LAST_REG 0x12c74 // GPIO_Q_INTERRUPT_CLEAR_03_0
#define GPIO97_FIRST_REG 0x12c80 // GPIO_Q_ENABLE_CONFIG_04_0
#define GPIO97_LAST_REG 0x12c94 // GPIO_Q_INTERRUPT_CLEAR_04_0
#define GPIO98_FIRST_REG 0x12ca0 // GPIO_Q_ENABLE_CONFIG_05_0
#define GPIO98_LAST_REG 0x12cb4 // GPIO_Q_INTERRUPT_CLEAR_05_0
#define GPIO99_FIRST_REG 0x12cc0 // GPIO_Q_ENABLE_CONFIG_06_0
#define GPIO99_LAST_REG 0x12cd4 // GPIO_Q_INTERRUPT_CLEAR_06_0
#define GPIO100_FIRST_REG 0x12ce0 // GPIO_Q_ENABLE_CONFIG_07_0
#define GPIO100_LAST_REG 0x12cf4 // GPIO_Q_INTERRUPT_CLEAR_07_0
#define GPIO101_FIRST_REG 0x12d00 // GPIO_Q_INTERRUPT_STATUS_G0_0
#define GPIO101_LAST_REG 0x12d1c // GPIO_Q_INTERRUPT_STATUS_G7_0
#define GPIO102_FIRST_REG 0x12e00 // GPIO_R_ENABLE_CONFIG_00_0
#define GPIO102_LAST_REG 0x12e14 // GPIO_R_INTERRUPT_CLEAR_00_0
#define GPIO103_FIRST_REG 0x12e20 // GPIO_R_ENABLE_CONFIG_01_0
#define GPIO103_LAST_REG 0x12e34 // GPIO_R_INTERRUPT_CLEAR_01_0
#define GPIO104_FIRST_REG 0x12e40 // GPIO_R_ENABLE_CONFIG_02_0
#define GPIO104_LAST_REG 0x12e54 // GPIO_R_INTERRUPT_CLEAR_02_0
#define GPIO105_FIRST_REG 0x12e60 // GPIO_R_ENABLE_CONFIG_03_0
#define GPIO105_LAST_REG 0x12e74 // GPIO_R_INTERRUPT_CLEAR_03_0
#define GPIO106_FIRST_REG 0x12e80 // GPIO_R_ENABLE_CONFIG_04_0
#define GPIO106_LAST_REG 0x12e94 // GPIO_R_INTERRUPT_CLEAR_04_0
#define GPIO107_FIRST_REG 0x12ea0 // GPIO_R_ENABLE_CONFIG_05_0
#define GPIO107_LAST_REG 0x12eb4 // GPIO_R_INTERRUPT_CLEAR_05_0
#define GPIO108_FIRST_REG 0x12f00 // GPIO_R_INTERRUPT_STATUS_G0_0
#define GPIO108_LAST_REG 0x12f1c // GPIO_R_INTERRUPT_STATUS_G7_0
#define GPIO109_FIRST_REG 0x13000 // GPIO_K_ENABLE_CONFIG_00_0
#define GPIO109_LAST_REG 0x13014 // GPIO_K_INTERRUPT_CLEAR_00_0
#define GPIO110_FIRST_REG 0x13020 // GPIO_K_ENABLE_CONFIG_01_0
#define GPIO110_LAST_REG 0x13034 // GPIO_K_INTERRUPT_CLEAR_01_0
#define GPIO111_FIRST_REG 0x13040 // GPIO_K_ENABLE_CONFIG_02_0
#define GPIO111_LAST_REG 0x13054 // GPIO_K_INTERRUPT_CLEAR_02_0
#define GPIO112_FIRST_REG 0x13060 // GPIO_K_ENABLE_CONFIG_03_0
#define GPIO112_LAST_REG 0x13074 // GPIO_K_INTERRUPT_CLEAR_03_0
#define GPIO113_FIRST_REG 0x13080 // GPIO_K_ENABLE_CONFIG_04_0
#define GPIO113_LAST_REG 0x13094 // GPIO_K_INTERRUPT_CLEAR_04_0
#define GPIO114_FIRST_REG 0x130a0 // GPIO_K_ENABLE_CONFIG_05_0
#define GPIO114_LAST_REG 0x130b4 // GPIO_K_INTERRUPT_CLEAR_05_0
#define GPIO115_FIRST_REG 0x130c0 // GPIO_K_ENABLE_CONFIG_06_0
#define GPIO115_LAST_REG 0x130d4 // GPIO_K_INTERRUPT_CLEAR_06_0
#define GPIO116_FIRST_REG 0x130e0 // GPIO_K_ENABLE_CONFIG_07_0
#define GPIO116_LAST_REG 0x130f4 // GPIO_K_INTERRUPT_CLEAR_07_0
#define GPIO117_FIRST_REG 0x13100 // GPIO_K_INTERRUPT_STATUS_G0_0
#define GPIO117_LAST_REG 0x1311c // GPIO_K_INTERRUPT_STATUS_G7_0
#define GPIO118_FIRST_REG 0x13200 // GPIO_L_ENABLE_CONFIG_00_0
#define GPIO118_LAST_REG 0x13214 // GPIO_L_INTERRUPT_CLEAR_00_0
#define GPIO119_FIRST_REG 0x13220 // GPIO_L_ENABLE_CONFIG_01_0
#define GPIO119_LAST_REG 0x13234 // GPIO_L_INTERRUPT_CLEAR_01_0
#define GPIO120_FIRST_REG 0x13240 // GPIO_L_ENABLE_CONFIG_02_0
#define GPIO120_LAST_REG 0x13254 // GPIO_L_INTERRUPT_CLEAR_02_0
#define GPIO121_FIRST_REG 0x13260 // GPIO_L_ENABLE_CONFIG_03_0
#define GPIO121_LAST_REG 0x13274 // GPIO_L_INTERRUPT_CLEAR_03_0
#define GPIO122_FIRST_REG 0x13300 // GPIO_L_INTERRUPT_STATUS_G0_0
#define GPIO122_LAST_REG 0x1331c // GPIO_L_INTERRUPT_STATUS_G7_0
#define GPIO123_FIRST_REG 0x13400 // GPIO_FF_ENABLE_CONFIG_00_0
#define GPIO123_LAST_REG 0x13414 // GPIO_FF_INTERRUPT_CLEAR_00_0
#define GPIO124_FIRST_REG 0x13420 // GPIO_FF_ENABLE_CONFIG_01_0
#define GPIO124_LAST_REG 0x13434 // GPIO_FF_INTERRUPT_CLEAR_01_0
#define GPIO125_FIRST_REG 0x13500 // GPIO_FF_INTERRUPT_STATUS_G0_0
#define GPIO125_LAST_REG 0x1351c // GPIO_FF_INTERRUPT_STATUS_G7_0
#define GPIO126_FIRST_REG 0x13600 // GPIO_S_ENABLE_CONFIG_00_0
#define GPIO126_LAST_REG 0x13614 // GPIO_S_INTERRUPT_CLEAR_00_0
#define GPIO127_FIRST_REG 0x13620 // GPIO_S_ENABLE_CONFIG_01_0
#define GPIO127_LAST_REG 0x13634 // GPIO_S_INTERRUPT_CLEAR_01_0
#define GPIO128_FIRST_REG 0x13640 // GPIO_S_ENABLE_CONFIG_02_0
#define GPIO128_LAST_REG 0x13654 // GPIO_S_INTERRUPT_CLEAR_02_0
#define GPIO129_FIRST_REG 0x13660 // GPIO_S_ENABLE_CONFIG_03_0
#define GPIO129_LAST_REG 0x13674 // GPIO_S_INTERRUPT_CLEAR_03_0
#define GPIO130_FIRST_REG 0x13680 // GPIO_S_ENABLE_CONFIG_04_0
#define GPIO130_LAST_REG 0x13694 // GPIO_S_INTERRUPT_CLEAR_04_0
#define GPIO131_FIRST_REG 0x136a0 // GPIO_S_ENABLE_CONFIG_05_0
#define GPIO131_LAST_REG 0x136b4 // GPIO_S_INTERRUPT_CLEAR_05_0
#define GPIO132_FIRST_REG 0x136c0 // GPIO_S_ENABLE_CONFIG_06_0
#define GPIO132_LAST_REG 0x136d4 // GPIO_S_INTERRUPT_CLEAR_06_0
#define GPIO133_FIRST_REG 0x136e0 // GPIO_S_ENABLE_CONFIG_07_0
#define GPIO133_LAST_REG 0x136f4 // GPIO_S_INTERRUPT_CLEAR_07_0
#define GPIO134_FIRST_REG 0x13700 // GPIO_S_INTERRUPT_STATUS_G0_0
#define GPIO134_LAST_REG 0x1371c // GPIO_S_INTERRUPT_STATUS_G7_0
#define GPIO135_FIRST_REG 0x13800 // GPIO_T_ENABLE_CONFIG_00_0
#define GPIO135_LAST_REG 0x13814 // GPIO_T_INTERRUPT_CLEAR_00_0
#define GPIO136_FIRST_REG 0x13820 // GPIO_T_ENABLE_CONFIG_01_0
#define GPIO136_LAST_REG 0x13834 // GPIO_T_INTERRUPT_CLEAR_01_0
#define GPIO137_FIRST_REG 0x13840 // GPIO_T_ENABLE_CONFIG_02_0
#define GPIO137_LAST_REG 0x13854 // GPIO_T_INTERRUPT_CLEAR_02_0
#define GPIO138_FIRST_REG 0x13860 // GPIO_T_ENABLE_CONFIG_03_0
#define GPIO138_LAST_REG 0x13874 // GPIO_T_INTERRUPT_CLEAR_03_0
#define GPIO139_FIRST_REG 0x13880 // GPIO_T_ENABLE_CONFIG_04_0
#define GPIO139_LAST_REG 0x13894 // GPIO_T_INTERRUPT_CLEAR_04_0
#define GPIO140_FIRST_REG 0x138a0 // GPIO_T_ENABLE_CONFIG_05_0
#define GPIO140_LAST_REG 0x138b4 // GPIO_T_INTERRUPT_CLEAR_05_0
#define GPIO141_FIRST_REG 0x138c0 // GPIO_T_ENABLE_CONFIG_06_0
#define GPIO141_LAST_REG 0x138d4 // GPIO_T_INTERRUPT_CLEAR_06_0
#define GPIO142_FIRST_REG 0x138e0 // GPIO_T_ENABLE_CONFIG_07_0
#define GPIO142_LAST_REG 0x138f4 // GPIO_T_INTERRUPT_CLEAR_07_0
#define GPIO143_FIRST_REG 0x13900 // GPIO_T_INTERRUPT_STATUS_G0_0
#define GPIO143_LAST_REG 0x1391c // GPIO_T_INTERRUPT_STATUS_G7_0
#define GPIO144_FIRST_REG 0x13a00 // GPIO_U_ENABLE_CONFIG_00_0
#define GPIO144_LAST_REG 0x13a14 // GPIO_U_INTERRUPT_CLEAR_00_0
#define GPIO145_FIRST_REG 0x13b00 // GPIO_U_INTERRUPT_STATUS_G0_0
#define GPIO145_LAST_REG 0x13b1c // GPIO_U_INTERRUPT_STATUS_G7_0
#define GPIO146_FIRST_REG 0x14000 // GPIO_G_ENABLE_CONFIG_00_0
#define GPIO146_LAST_REG 0x14014 // GPIO_G_INTERRUPT_CLEAR_00_0
#define GPIO147_FIRST_REG 0x14020 // GPIO_G_ENABLE_CONFIG_01_0
#define GPIO147_LAST_REG 0x14034 // GPIO_G_INTERRUPT_CLEAR_01_0
#define GPIO148_FIRST_REG 0x14040 // GPIO_G_ENABLE_CONFIG_02_0
#define GPIO148_LAST_REG 0x14054 // GPIO_G_INTERRUPT_CLEAR_02_0
#define GPIO149_FIRST_REG 0x14060 // GPIO_G_ENABLE_CONFIG_03_0
#define GPIO149_LAST_REG 0x14074 // GPIO_G_INTERRUPT_CLEAR_03_0
#define GPIO150_FIRST_REG 0x14080 // GPIO_G_ENABLE_CONFIG_04_0
#define GPIO150_LAST_REG 0x14094 // GPIO_G_INTERRUPT_CLEAR_04_0
#define GPIO151_FIRST_REG 0x140a0 // GPIO_G_ENABLE_CONFIG_05_0
#define GPIO151_LAST_REG 0x140b4 // GPIO_G_INTERRUPT_CLEAR_05_0
#define GPIO152_FIRST_REG 0x140c0 // GPIO_G_ENABLE_CONFIG_06_0
#define GPIO152_LAST_REG 0x140d4 // GPIO_G_INTERRUPT_CLEAR_06_0
#define GPIO153_FIRST_REG 0x140e0 // GPIO_G_ENABLE_CONFIG_07_0
#define GPIO153_LAST_REG 0x140f4 // GPIO_G_INTERRUPT_CLEAR_07_0
#define GPIO154_FIRST_REG 0x14100 // GPIO_G_INTERRUPT_STATUS_G0_0
#define GPIO154_LAST_REG 0x1411c // GPIO_G_INTERRUPT_STATUS_G7_0
#define GPIO155_FIRST_REG 0x14200 // GPIO_H_ENABLE_CONFIG_00_0
#define GPIO155_LAST_REG 0x14214 // GPIO_H_INTERRUPT_CLEAR_00_0
#define GPIO156_FIRST_REG 0x14220 // GPIO_H_ENABLE_CONFIG_01_0
#define GPIO156_LAST_REG 0x14234 // GPIO_H_INTERRUPT_CLEAR_01_0
#define GPIO157_FIRST_REG 0x14240 // GPIO_H_ENABLE_CONFIG_02_0
#define GPIO157_LAST_REG 0x14254 // GPIO_H_INTERRUPT_CLEAR_02_0
#define GPIO158_FIRST_REG 0x14260 // GPIO_H_ENABLE_CONFIG_03_0
#define GPIO158_LAST_REG 0x14274 // GPIO_H_INTERRUPT_CLEAR_03_0
#define GPIO159_FIRST_REG 0x14280 // GPIO_H_ENABLE_CONFIG_04_0
#define GPIO159_LAST_REG 0x14294 // GPIO_H_INTERRUPT_CLEAR_04_0
#define GPIO160_FIRST_REG 0x142a0 // GPIO_H_ENABLE_CONFIG_05_0
#define GPIO160_LAST_REG 0x142b4 // GPIO_H_INTERRUPT_CLEAR_05_0
#define GPIO161_FIRST_REG 0x142c0 // GPIO_H_ENABLE_CONFIG_06_0
#define GPIO161_LAST_REG 0x142d4 // GPIO_H_INTERRUPT_CLEAR_06_0
#define GPIO162_FIRST_REG 0x142e0 // GPIO_H_ENABLE_CONFIG_07_0
#define GPIO162_LAST_REG 0x142f4 // GPIO_H_INTERRUPT_CLEAR_07_0
#define GPIO163_FIRST_REG 0x14300 // GPIO_H_INTERRUPT_STATUS_G0_0
#define GPIO163_LAST_REG 0x1431c // GPIO_H_INTERRUPT_STATUS_G7_0
#define GPIO164_FIRST_REG 0x14400 // GPIO_I_ENABLE_CONFIG_00_0
#define GPIO164_LAST_REG 0x14414 // GPIO_I_INTERRUPT_CLEAR_00_0
#define GPIO165_FIRST_REG 0x14420 // GPIO_I_ENABLE_CONFIG_01_0
#define GPIO165_LAST_REG 0x14434 // GPIO_I_INTERRUPT_CLEAR_01_0
#define GPIO166_FIRST_REG 0x14440 // GPIO_I_ENABLE_CONFIG_02_0
#define GPIO166_LAST_REG 0x14454 // GPIO_I_INTERRUPT_CLEAR_02_0
#define GPIO167_FIRST_REG 0x14460 // GPIO_I_ENABLE_CONFIG_03_0
#define GPIO167_LAST_REG 0x14474 // GPIO_I_INTERRUPT_CLEAR_03_0
#define GPIO168_FIRST_REG 0x14480 // GPIO_I_ENABLE_CONFIG_04_0
#define GPIO168_LAST_REG 0x14494 // GPIO_I_INTERRUPT_CLEAR_04_0
#define GPIO169_FIRST_REG 0x14500 // GPIO_I_INTERRUPT_STATUS_G0_0
#define GPIO169_LAST_REG 0x1451c // GPIO_I_INTERRUPT_STATUS_G7_0
#define GPIO170_FIRST_REG 0x14600 // GPIO_C_ENABLE_CONFIG_00_0
#define GPIO170_LAST_REG 0x14614 // GPIO_C_INTERRUPT_CLEAR_00_0
#define GPIO171_FIRST_REG 0x14620 // GPIO_C_ENABLE_CONFIG_01_0
#define GPIO171_LAST_REG 0x14634 // GPIO_C_INTERRUPT_CLEAR_01_0
#define GPIO172_FIRST_REG 0x14640 // GPIO_C_ENABLE_CONFIG_02_0
#define GPIO172_LAST_REG 0x14654 // GPIO_C_INTERRUPT_CLEAR_02_0
#define GPIO173_FIRST_REG 0x14660 // GPIO_C_ENABLE_CONFIG_03_0
#define GPIO173_LAST_REG 0x14674 // GPIO_C_INTERRUPT_CLEAR_03_0
#define GPIO174_FIRST_REG 0x14680 // GPIO_C_ENABLE_CONFIG_04_0
#define GPIO174_LAST_REG 0x14694 // GPIO_C_INTERRUPT_CLEAR_04_0
#define GPIO175_FIRST_REG 0x146a0 // GPIO_C_ENABLE_CONFIG_05_0
#define GPIO175_LAST_REG 0x146b4 // GPIO_C_INTERRUPT_CLEAR_05_0
#define GPIO176_FIRST_REG 0x146c0 // GPIO_C_ENABLE_CONFIG_06_0
#define GPIO176_LAST_REG 0x146d4 // GPIO_C_INTERRUPT_CLEAR_06_0
#define GPIO177_FIRST_REG 0x146e0 // GPIO_C_ENABLE_CONFIG_07_0
#define GPIO177_LAST_REG 0x146f4 // GPIO_C_INTERRUPT_CLEAR_07_0
#define GPIO178_FIRST_REG 0x14700 // GPIO_C_INTERRUPT_STATUS_G0_0
#define GPIO178_LAST_REG 0x1471c // GPIO_C_INTERRUPT_STATUS_G7_0
#define GPIO179_FIRST_REG 0x14800 // GPIO_D_ENABLE_CONFIG_00_0
#define GPIO179_LAST_REG 0x14814 // GPIO_D_INTERRUPT_CLEAR_00_0
#define GPIO180_FIRST_REG 0x14820 // GPIO_D_ENABLE_CONFIG_01_0
#define GPIO180_LAST_REG 0x14834 // GPIO_D_INTERRUPT_CLEAR_01_0
#define GPIO181_FIRST_REG 0x14840 // GPIO_D_ENABLE_CONFIG_02_0
#define GPIO181_LAST_REG 0x14854 // GPIO_D_INTERRUPT_CLEAR_02_0
#define GPIO182_FIRST_REG 0x14860 // GPIO_D_ENABLE_CONFIG_03_0
#define GPIO182_LAST_REG 0x14874 // GPIO_D_INTERRUPT_CLEAR_03_0
#define GPIO183_FIRST_REG 0x14900 // GPIO_D_INTERRUPT_STATUS_G0_0
#define GPIO183_LAST_REG 0x1491c // GPIO_D_INTERRUPT_STATUS_G7_0
#define GPIO184_FIRST_REG 0x14a00 // GPIO_E_ENABLE_CONFIG_00_0
#define GPIO184_LAST_REG 0x14a14 // GPIO_E_INTERRUPT_CLEAR_00_0
#define GPIO185_FIRST_REG 0x14a20 // GPIO_E_ENABLE_CONFIG_01_0
#define GPIO185_LAST_REG 0x14a34 // GPIO_E_INTERRUPT_CLEAR_01_0
#define GPIO186_FIRST_REG 0x14a40 // GPIO_E_ENABLE_CONFIG_02_0
#define GPIO186_LAST_REG 0x14a54 // GPIO_E_INTERRUPT_CLEAR_02_0
#define GPIO187_FIRST_REG 0x14a60 // GPIO_E_ENABLE_CONFIG_03_0
#define GPIO187_LAST_REG 0x14a74 // GPIO_E_INTERRUPT_CLEAR_03_0
#define GPIO188_FIRST_REG 0x14a80 // GPIO_E_ENABLE_CONFIG_04_0
#define GPIO188_LAST_REG 0x14a94 // GPIO_E_INTERRUPT_CLEAR_04_0
#define GPIO189_FIRST_REG 0x14aa0 // GPIO_E_ENABLE_CONFIG_05_0
#define GPIO189_LAST_REG 0x14ab4 // GPIO_E_INTERRUPT_CLEAR_05_0
#define GPIO190_FIRST_REG 0x14ac0 // GPIO_E_ENABLE_CONFIG_06_0
#define GPIO190_LAST_REG 0x14ad4 // GPIO_E_INTERRUPT_CLEAR_06_0
#define GPIO191_FIRST_REG 0x14ae0 // GPIO_E_ENABLE_CONFIG_07_0
#define GPIO191_LAST_REG 0x14af4 // GPIO_E_INTERRUPT_CLEAR_07_0
#define GPIO192_FIRST_REG 0x14b00 // GPIO_E_INTERRUPT_STATUS_G0_0
#define GPIO192_LAST_REG 0x14b1c // GPIO_E_INTERRUPT_STATUS_G7_0
#define GPIO193_FIRST_REG 0x14c00 // GPIO_F_ENABLE_CONFIG_00_0
#define GPIO193_LAST_REG 0x14c14 // GPIO_F_INTERRUPT_CLEAR_00_0
#define GPIO194_FIRST_REG 0x14c20 // GPIO_F_ENABLE_CONFIG_01_0
#define GPIO194_LAST_REG 0x14c34 // GPIO_F_INTERRUPT_CLEAR_01_0
#define GPIO195_FIRST_REG 0x14c40 // GPIO_F_ENABLE_CONFIG_02_0
#define GPIO195_LAST_REG 0x14c54 // GPIO_F_INTERRUPT_CLEAR_02_0
#define GPIO196_FIRST_REG 0x14c60 // GPIO_F_ENABLE_CONFIG_03_0
#define GPIO196_LAST_REG 0x14c74 // GPIO_F_INTERRUPT_CLEAR_03_0
#define GPIO197_FIRST_REG 0x14c80 // GPIO_F_ENABLE_CONFIG_04_0
#define GPIO197_LAST_REG 0x14c94 // GPIO_F_INTERRUPT_CLEAR_04_0
#define GPIO198_FIRST_REG 0x14ca0 // GPIO_F_ENABLE_CONFIG_05_0
#define GPIO198_LAST_REG 0x14cb4 // GPIO_F_INTERRUPT_CLEAR_05_0
#define GPIO199_FIRST_REG 0x14d00 // GPIO_F_INTERRUPT_STATUS_G0_0
#define GPIO199_LAST_REG 0x14d1c // GPIO_F_INTERRUPT_STATUS_G7_0
#define GPIO200_FIRST_REG 0x14e00 // GPIO_B_ENABLE_CONFIG_00_0
#define GPIO200_LAST_REG 0x14e14 // GPIO_B_INTERRUPT_CLEAR_00_0
#define GPIO201_FIRST_REG 0x14e20 // GPIO_B_ENABLE_CONFIG_01_0
#define GPIO201_LAST_REG 0x14e34 // GPIO_B_INTERRUPT_CLEAR_01_0
#define GPIO202_FIRST_REG 0x14f00 // GPIO_B_INTERRUPT_STATUS_G0_0
#define GPIO202_LAST_REG 0x14f1c // GPIO_B_INTERRUPT_STATUS_G7_0
#define GPIO203_FIRST_REG 0x15000 // GPIO_O_ENABLE_CONFIG_00_0
#define GPIO203_LAST_REG 0x15014 // GPIO_O_INTERRUPT_CLEAR_00_0
#define GPIO204_FIRST_REG 0x15020 // GPIO_O_ENABLE_CONFIG_01_0
#define GPIO204_LAST_REG 0x15034 // GPIO_O_INTERRUPT_CLEAR_01_0
#define GPIO205_FIRST_REG 0x15040 // GPIO_O_ENABLE_CONFIG_02_0
#define GPIO205_LAST_REG 0x15054 // GPIO_O_INTERRUPT_CLEAR_02_0
#define GPIO206_FIRST_REG 0x15060 // GPIO_O_ENABLE_CONFIG_03_0
#define GPIO206_LAST_REG 0x15074 // GPIO_O_INTERRUPT_CLEAR_03_0
#define GPIO207_FIRST_REG 0x15080 // GPIO_O_ENABLE_CONFIG_04_0
#define GPIO207_LAST_REG 0x15094 // GPIO_O_INTERRUPT_CLEAR_04_0
#define GPIO208_FIRST_REG 0x150a0 // GPIO_O_ENABLE_CONFIG_05_0
#define GPIO208_LAST_REG 0x150b4 // GPIO_O_INTERRUPT_CLEAR_05_0
#define GPIO209_FIRST_REG 0x15100 // GPIO_O_INTERRUPT_STATUS_G0_0
#define GPIO209_LAST_REG 0x1511c // GPIO_O_INTERRUPT_STATUS_G7_0
#define GPIO210_FIRST_REG 0x15200 // GPIO_J_ENABLE_CONFIG_00_0
#define GPIO210_LAST_REG 0x15214 // GPIO_J_INTERRUPT_CLEAR_00_0
#define GPIO211_FIRST_REG 0x15220 // GPIO_J_ENABLE_CONFIG_01_0
#define GPIO211_LAST_REG 0x15234 // GPIO_J_INTERRUPT_CLEAR_01_0
#define GPIO212_FIRST_REG 0x15240 // GPIO_J_ENABLE_CONFIG_02_0
#define GPIO212_LAST_REG 0x15254 // GPIO_J_INTERRUPT_CLEAR_02_0
#define GPIO213_FIRST_REG 0x15260 // GPIO_J_ENABLE_CONFIG_03_0
#define GPIO213_LAST_REG 0x15274 // GPIO_J_INTERRUPT_CLEAR_03_0
#define GPIO214_FIRST_REG 0x15280 // GPIO_J_ENABLE_CONFIG_04_0
#define GPIO214_LAST_REG 0x15294 // GPIO_J_INTERRUPT_CLEAR_04_0
#define GPIO215_FIRST_REG 0x152a0 // GPIO_J_ENABLE_CONFIG_05_0
#define GPIO215_LAST_REG 0x152b4 // GPIO_J_INTERRUPT_CLEAR_05_0
#define GPIO216_FIRST_REG 0x15300 // GPIO_J_INTERRUPT_STATUS_G0_0
#define GPIO216_LAST_REG 0x1531c // GPIO_J_INTERRUPT_STATUS_G7_0

// To satisfy various compilers and platforms,
// we let users control the types and syntax of certain constants, using macros.
#ifndef _MK_SHIFT_CONST
  #define _MK_SHIFT_CONST(_constant_) _constant_
#endif
#ifndef _MK_MASK_CONST
  #define _MK_MASK_CONST(_constant_) _constant_
#endif
#ifndef _MK_ENUM_CONST
  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
#endif
#ifndef _MK_ADDR_CONST
  #define _MK_ADDR_CONST(_constant_) _constant_
#endif
#ifndef _MK_FIELD_CONST
  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
#endif

#endif // ifndef ___ARGPIO_H_INC_

